git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77
  78 #ifndef IT87_DRIVER_VERSION
  79 #define IT87_DRIVER_VERSION     "<not provided>"
  80 #endif
  81
  82 #define DRVNAME "it87"
  83
  84 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  85              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  86              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  87              it8655, it8665, it8686 };
  88
  89 static unsigned short force_id;
  90 module_param(force_id, ushort, 0);
  91 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  92
  93 static bool ignore_resource_conflict;
  94 module_param(ignore_resource_conflict, bool, 0);
  95 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
  96
  97 static bool mmio;
  98 module_param(mmio, bool, 0);
  99 MODULE_PARM_DESC(mmio, "Use MMIO if available");
 100
 101 static struct platform_device *it87_pdev[2];
 102
 103 #define REG_2E  0x2e    /* The register to read/write */
 104 #define REG_4E  0x4e    /* Secondary register to read/write */
 105
 106 #define DEV     0x07    /* Register: Logical device select */
 107 #define PME     0x04    /* The device with the fan registers in it */
 108
 109 /* The device with the IT8718F/IT8720F VID value in it */
 110 #define GPIO    0x07
 111
 112 #define DEVID   0x20    /* Register: Device ID */
 113 #define DEVREV  0x22    /* Register: Device Revision */
 114
 115 static inline void __superio_enter(int ioreg)
 116 {
 117         outb(0x87, ioreg);
 118         outb(0x01, ioreg);
 119         outb(0x55, ioreg);
 120         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 121 }
 122
 123 static inline int superio_inb(int ioreg, int reg)
 124 {
 125         int val;
 126
 127         outb(reg, ioreg);
 128         val = inb(ioreg + 1);
 129
 130         return val;
 131 }
 132
 133 static inline void superio_outb(int ioreg, int reg, int val)
 134 {
 135         outb(reg, ioreg);
 136         outb(val, ioreg + 1);
 137 }
 138
 139 static int superio_inw(int ioreg, int reg)
 140 {
 141         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 142 }
 143
 144 static inline void superio_select(int ioreg, int ldn)
 145 {
 146         outb(DEV, ioreg);
 147         outb(ldn, ioreg + 1);
 148 }
 149
 150 static inline int superio_enter(int ioreg)
 151 {
 152         /*
 153          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 154          */
 155         if (!request_muxed_region(ioreg, 2, DRVNAME))
 156                 return -EBUSY;
 157
 158         __superio_enter(ioreg);
 159         return 0;
 160 }
 161
 162 static inline void superio_exit(int ioreg, bool doexit)
 163 {
 164         if (doexit) {
 165                 outb(0x02, ioreg);
 166                 outb(0x02, ioreg + 1);
 167         }
 168         release_region(ioreg, 2);
 169 }
 170
 171 /* Logical device 4 registers */
 172 #define IT8712F_DEVID 0x8712
 173 #define IT8705F_DEVID 0x8705
 174 #define IT8716F_DEVID 0x8716
 175 #define IT8718F_DEVID 0x8718
 176 #define IT8720F_DEVID 0x8720
 177 #define IT8721F_DEVID 0x8721
 178 #define IT8726F_DEVID 0x8726
 179 #define IT8728F_DEVID 0x8728
 180 #define IT8732F_DEVID 0x8732
 181 #define IT8792E_DEVID 0x8733
 182 #define IT8771E_DEVID 0x8771
 183 #define IT8772E_DEVID 0x8772
 184 #define IT8781F_DEVID 0x8781
 185 #define IT8782F_DEVID 0x8782
 186 #define IT8783E_DEVID 0x8783
 187 #define IT8786E_DEVID 0x8786
 188 #define IT8790E_DEVID 0x8790
 189 #define IT8603E_DEVID 0x8603
 190 #define IT8607E_DEVID 0x8607
 191 #define IT8613E_DEVID 0x8613
 192 #define IT8620E_DEVID 0x8620
 193 #define IT8622E_DEVID 0x8622
 194 #define IT8623E_DEVID 0x8623
 195 #define IT8625E_DEVID 0x8625
 196 #define IT8628E_DEVID 0x8628
 197 #define IT8655E_DEVID 0x8655
 198 #define IT8665E_DEVID 0x8665
 199 #define IT8686E_DEVID 0x8686
 200
 201 /* Logical device 4 (Environmental Monitor) registers */
 202 #define IT87_ACT_REG            0x30
 203 #define IT87_BASE_REG           0x60
 204 #define IT87_SPECIAL_CFG_REG    0xf3    /* special configuration register */
 205
 206 /* Global configuration registers (IT8712F and later) */
 207 #define IT87_EC_HWM_MIO_REG     0x24    /* MMIO configuration register */
 208 #define IT87_SIO_GPIO1_REG      0x25
 209 #define IT87_SIO_GPIO2_REG      0x26
 210 #define IT87_SIO_GPIO3_REG      0x27
 211 #define IT87_SIO_GPIO4_REG      0x28
 212 #define IT87_SIO_GPIO5_REG      0x29
 213 #define IT87_SIO_GPIO9_REG      0xd3
 214 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 215 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 216 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 217
 218 /* Logical device 7 (GPIO) registers (IT8712F and later) */
 219 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 220 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 221 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 222
 223 /* Update battery voltage after every reading if true */
 224 static bool update_vbat;
 225
 226 /* Not all BIOSes properly configure the PWM registers */
 227 static bool fix_pwm_polarity;
 228
 229 /* Many IT87 constants specified below */
 230
 231 /* Length of ISA address segment */
 232 #define IT87_EXTENT 8
 233
 234 /* Length of ISA address segment for Environmental Controller */
 235 #define IT87_EC_EXTENT 2
 236
 237 /* Offset of EC registers from ISA base address */
 238 #define IT87_EC_OFFSET 5
 239
 240 /* Where are the ISA address/data registers relative to the EC base address */
 241 #define IT87_ADDR_REG_OFFSET 0
 242 #define IT87_DATA_REG_OFFSET 1
 243
 244 /*----- The IT87 registers -----*/
 245
 246 #define IT87_REG_CONFIG        0x00
 247
 248 #define IT87_REG_ALARM1        0x01
 249 #define IT87_REG_ALARM2        0x02
 250 #define IT87_REG_ALARM3        0x03
 251
 252 #define IT87_REG_BANK           0x06
 253
 254 /*
 255  * The IT8718F and IT8720F have the VID value in a different register, in
 256  * Super-I/O configuration space.
 257  */
 258 #define IT87_REG_VID           0x0a
 259 /*
 260  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 261  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 262  * mode.
 263  */
 264 #define IT87_REG_FAN_DIV       0x0b
 265 #define IT87_REG_FAN_16BIT     0x0c
 266
 267 /*
 268  * Monitors:
 269  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 270  * - up to 6 temp (1 to 6)
 271  * - up to 6 fan (1 to 6)
 272  */
 273
 274 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 275 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 276 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 277 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 278
 279 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 280 static const u8 IT87_REG_FAN_MIN_8665[] =
 281                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 282 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 283 static const u8 IT87_REG_FANX_MIN_8665[] =
 284                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 285
 286 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 287
 288 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 289
 290 #define IT87_REG_FAN_MAIN_CTRL 0x13
 291 #define IT87_REG_FAN_CTL       0x14
 292
 293 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 294 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 295
 296 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 297
 298 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 299                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 300
 301 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 302
 303 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 304 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 305
 306 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 307 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 308
 309 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 310                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 311 static const u8 IT87_REG_TEMP_LOW_8686[] =
 312                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 313
 314 #define IT87_REG_VIN_ENABLE    0x50
 315 #define IT87_REG_TEMP_ENABLE   0x51
 316 #define IT87_REG_TEMP_EXTRA    0x55
 317 #define IT87_REG_BEEP_ENABLE   0x5c
 318
 319 #define IT87_REG_CHIPID        0x58
 320
 321 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 322
 323 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 324 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 325
 326 #define IT87_REG_TEMP456_ENABLE 0x77
 327
 328 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 329 #define IT87_REG_TEMP_SRC2      0x23d
 330
 331 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 332 #define NUM_VIN_LIMIT           8
 333 #define NUM_TEMP                6
 334 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 335 #define NUM_FAN_DIV             3
 336 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 337 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 338
 339 struct it87_devices {
 340         const char *name;
 341         const char * const suffix;
 342         u32 features;
 343         u8 num_temp_limit;
 344         u8 num_temp_offset;
 345         u8 num_temp_map;        /* Number of temperature sources for pwm */
 346         u8 peci_mask;
 347         u8 old_peci_mask;
 348         u8 smbus_bitmap;        /* SMBus enable bits in extra config register */
 349         u8 ec_special_config;
 350 };
 351
 352 #define FEAT_12MV_ADC           BIT(0)
 353 #define FEAT_NEWER_AUTOPWM      BIT(1)
 354 #define FEAT_OLD_AUTOPWM        BIT(2)
 355 #define FEAT_16BIT_FANS         BIT(3)
 356 #define FEAT_TEMP_PECI          BIT(5)
 357 #define FEAT_TEMP_OLD_PECI      BIT(6)
 358 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 359 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 360 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 361 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 362 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 363 #define FEAT_10_9MV_ADC         BIT(12)
 364 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 365 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 366 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 367 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 368 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 369 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 370 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 371 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 372 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 373 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 374 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 375 #define FEAT_11MV_ADC           BIT(24)
 376 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 377 #define FEAT_MMIO               BIT(26) /* Chip supports MMIO */
 378 #define FEAT_FOUR_TEMP          BIT(27)
 379
 380 static const struct it87_devices it87_devices[] = {
 381         [it87] = {
 382                 .name = "it87",
 383                 .suffix = "F",
 384                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 385                                                 /* may need to overwrite */
 386                 .num_temp_limit = 3,
 387                 .num_temp_offset = 0,
 388                 .num_temp_map = 3,
 389         },
 390         [it8712] = {
 391                 .name = "it8712",
 392                 .suffix = "F",
 393                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 394                                                 /* may need to overwrite */
 395                 .num_temp_limit = 3,
 396                 .num_temp_offset = 0,
 397                 .num_temp_map = 3,
 398         },
 399         [it8716] = {
 400                 .name = "it8716",
 401                 .suffix = "F",
 402                 .features = FEAT_16BIT_FANS | FEAT_VID
 403                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 404                   | FEAT_FANCTL_ONOFF,
 405                 .num_temp_limit = 3,
 406                 .num_temp_offset = 3,
 407                 .num_temp_map = 3,
 408         },
 409         [it8718] = {
 410                 .name = "it8718",
 411                 .suffix = "F",
 412                 .features = FEAT_16BIT_FANS | FEAT_VID
 413                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 414                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 415                 .num_temp_limit = 3,
 416                 .num_temp_offset = 3,
 417                 .num_temp_map = 3,
 418                 .old_peci_mask = 0x4,
 419         },
 420         [it8720] = {
 421                 .name = "it8720",
 422                 .suffix = "F",
 423                 .features = FEAT_16BIT_FANS | FEAT_VID
 424                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 425                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 426                 .num_temp_limit = 3,
 427                 .num_temp_offset = 3,
 428                 .num_temp_map = 3,
 429                 .old_peci_mask = 0x4,
 430         },
 431         [it8721] = {
 432                 .name = "it8721",
 433                 .suffix = "F",
 434                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 435                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 436                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 437                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 438                 .num_temp_limit = 3,
 439                 .num_temp_offset = 3,
 440                 .num_temp_map = 3,
 441                 .peci_mask = 0x05,
 442                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 443         },
 444         [it8728] = {
 445                 .name = "it8728",
 446                 .suffix = "F",
 447                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 448                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 449                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 450                   | FEAT_FANCTL_ONOFF,
 451                 .num_temp_limit = 6,
 452                 .num_temp_offset = 3,
 453                 .num_temp_map = 3,
 454                 .peci_mask = 0x07,
 455         },
 456         [it8732] = {
 457                 .name = "it8732",
 458                 .suffix = "F",
 459                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 460                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 461                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 462                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 463                 .num_temp_limit = 3,
 464                 .num_temp_offset = 3,
 465                 .num_temp_map = 3,
 466                 .peci_mask = 0x07,
 467                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 468         },
 469         [it8771] = {
 470                 .name = "it8771",
 471                 .suffix = "E",
 472                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 473                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 474                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 475                                 /* PECI: guesswork */
 476                                 /* 12mV ADC (OHM) */
 477                                 /* 16 bit fans (OHM) */
 478                                 /* three fans, always 16 bit (guesswork) */
 479                 .num_temp_limit = 3,
 480                 .num_temp_offset = 3,
 481                 .num_temp_map = 3,
 482                 .peci_mask = 0x07,
 483         },
 484         [it8772] = {
 485                 .name = "it8772",
 486                 .suffix = "E",
 487                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 488                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 489                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 490                                 /* PECI (coreboot) */
 491                                 /* 12mV ADC (HWSensors4, OHM) */
 492                                 /* 16 bit fans (HWSensors4, OHM) */
 493                                 /* three fans, always 16 bit (datasheet) */
 494                 .num_temp_limit = 3,
 495                 .num_temp_offset = 3,
 496                 .num_temp_map = 3,
 497                 .peci_mask = 0x07,
 498         },
 499         [it8781] = {
 500                 .name = "it8781",
 501                 .suffix = "F",
 502                 .features = FEAT_16BIT_FANS
 503                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 504                   | FEAT_FANCTL_ONOFF,
 505                 .num_temp_limit = 3,
 506                 .num_temp_offset = 3,
 507                 .num_temp_map = 3,
 508                 .old_peci_mask = 0x4,
 509         },
 510         [it8782] = {
 511                 .name = "it8782",
 512                 .suffix = "F",
 513                 .features = FEAT_16BIT_FANS
 514                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 515                   | FEAT_FANCTL_ONOFF,
 516                 .num_temp_limit = 3,
 517                 .num_temp_offset = 3,
 518                 .num_temp_map = 3,
 519                 .old_peci_mask = 0x4,
 520         },
 521         [it8783] = {
 522                 .name = "it8783",
 523                 .suffix = "E/F",
 524                 .features = FEAT_16BIT_FANS
 525                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 526                   | FEAT_FANCTL_ONOFF,
 527                 .num_temp_limit = 3,
 528                 .num_temp_offset = 3,
 529                 .num_temp_map = 3,
 530                 .old_peci_mask = 0x4,
 531         },
 532         [it8786] = {
 533                 .name = "it8786",
 534                 .suffix = "E",
 535                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 536                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 537                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 538                 .num_temp_limit = 3,
 539                 .num_temp_offset = 3,
 540                 .num_temp_map = 3,
 541                 .peci_mask = 0x07,
 542         },
 543         [it8790] = {
 544                 .name = "it8790",
 545                 .suffix = "E",
 546                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 547                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 548                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 549                 .num_temp_limit = 3,
 550                 .num_temp_offset = 3,
 551                 .num_temp_map = 3,
 552                 .peci_mask = 0x07,
 553         },
 554         [it8792] = {
 555                 .name = "it8792",
 556                 .suffix = "E",
 557                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 558                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 559                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 560                 .num_temp_limit = 3,
 561                 .num_temp_offset = 3,
 562                 .num_temp_map = 3,
 563                 .peci_mask = 0x07,
 564         },
 565         [it8603] = {
 566                 .name = "it8603",
 567                 .suffix = "E",
 568                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 569                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 570                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 571                 .num_temp_limit = 3,
 572                 .num_temp_offset = 3,
 573                 .num_temp_map = 4,
 574                 .peci_mask = 0x07,
 575         },
 576         [it8607] = {
 577                 .name = "it8607",
 578                 .suffix = "E",
 579                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 580                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 581                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 582                   | FEAT_FANCTL_ONOFF,
 583                 .num_temp_limit = 3,
 584                 .num_temp_offset = 3,
 585                 .num_temp_map = 6,
 586                 .peci_mask = 0x07,
 587         },
 588         [it8613] = {
 589                 .name = "it8613",
 590                 .suffix = "E",
 591                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 592                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 593                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 594                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 595                 .num_temp_limit = 6,
 596                 .num_temp_offset = 6,
 597                 .num_temp_map = 6,
 598                 .peci_mask = 0x07,
 599         },
 600         [it8620] = {
 601                 .name = "it8620",
 602                 .suffix = "E",
 603                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 604                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 605                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 606                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 607                   | FEAT_FANCTL_ONOFF,
 608                 .num_temp_limit = 3,
 609                 .num_temp_offset = 3,
 610                 .num_temp_map = 3,
 611                 .peci_mask = 0x07,
 612         },
 613         [it8622] = {
 614                 .name = "it8622",
 615                 .suffix = "E",
 616                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 617                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
 618                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 619                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 620                 .num_temp_limit = 3,
 621                 .num_temp_offset = 3,
 622                 .num_temp_map = 4,
 623                 .peci_mask = 0x0f,
 624                 .smbus_bitmap = BIT(1) | BIT(2),
 625         },
 626         [it8625] = {
 627                 .name = "it8625",
 628                 .suffix = "E",
 629                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 630                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 631                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 632                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 633                 .num_temp_limit = 6,
 634                 .num_temp_offset = 6,
 635                 .num_temp_map = 6,
 636                 .smbus_bitmap = BIT(1) | BIT(2),
 637         },
 638         [it8628] = {
 639                 .name = "it8628",
 640                 .suffix = "E",
 641                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 642                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 643                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 644                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 645                   | FEAT_FANCTL_ONOFF,
 646                 .num_temp_limit = 6,
 647                 .num_temp_offset = 3,
 648                 .num_temp_map = 3,
 649                 .peci_mask = 0x07,
 650         },
 651         [it8655] = {
 652                 .name = "it8655",
 653                 .suffix = "E",
 654                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 655                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 656                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
 657                   | FEAT_MMIO,
 658                 .num_temp_limit = 6,
 659                 .num_temp_offset = 6,
 660                 .num_temp_map = 6,
 661                 .smbus_bitmap = BIT(2),
 662         },
 663         [it8665] = {
 664                 .name = "it8665",
 665                 .suffix = "E",
 666                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 667                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 668                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 669                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO,
 670                 .num_temp_limit = 6,
 671                 .num_temp_offset = 6,
 672                 .num_temp_map = 6,
 673                 .smbus_bitmap = BIT(2),
 674         },
 675         [it8686] = {
 676                 .name = "it8686",
 677                 .suffix = "E",
 678                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 679                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 680                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 681                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 682                 .num_temp_limit = 6,
 683                 .num_temp_offset = 6,
 684                 .num_temp_map = 7,
 685                 .smbus_bitmap = BIT(1) | BIT(2),
 686         },
 687 };
 688
 689 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 690 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 691 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 692 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 693 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 694 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 695                                  ((data)->peci_mask & BIT(nr)))
 696 #define has_temp_old_peci(data, nr) \
 697                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 698                                  ((data)->old_peci_mask & BIT(nr)))
 699 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 700 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 701                                                      FEAT_SIX_FANS))
 702 #define has_vid(data)           ((data)->features & FEAT_VID)
 703 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 704 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 705 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 706 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 707                                                      | FEAT_SIX_PWM))
 708 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 709 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 710 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 711 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 712 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 713                                                      FEAT_FIVE_FANS | \
 714                                                      FEAT_SIX_FANS))
 715 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 716                                                      FEAT_FIVE_PWM \
 717                                                      | FEAT_SIX_PWM))
 718 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 719 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 720 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 721 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 722 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 723 #define has_mmio(data)          ((data)->features & FEAT_MMIO)
 724 #define has_four_temp(data)     ((data)->features & FEAT_FOUR_TEMP)
 725
 726 struct it87_sio_data {
 727         enum chips type;
 728         u8 sioaddr;
 729         u8 doexit;
 730         /* Values read from Super-I/O config space */
 731         u8 revision;
 732         u8 vid_value;
 733         u8 beep_pin;
 734         u8 internal;    /* Internal sensors can be labeled */
 735         /* Features skipped based on config or DMI */
 736         u16 skip_in;
 737         u8 skip_vid;
 738         u8 skip_fan;
 739         u8 skip_pwm;
 740         u8 skip_temp;
 741         u8 smbus_bitmap;
 742         u8 ec_special_config;
 743 };
 744
 745 /*
 746  * For each registered chip, we need to keep some data in memory.
 747  * The structure is dynamically allocated.
 748  */
 749 struct it87_data {
 750         const struct attribute_group *groups[7];
 751         enum chips type;
 752         u32 features;
 753         u8 peci_mask;
 754         u8 old_peci_mask;
 755
 756         u8 smbus_bitmap;        /* !=0 if SMBus needs to be disabled */
 757         u8 ec_special_config;   /* EC special config register restore value */
 758         u8 sioaddr;             /* SIO port address */
 759         bool doexit;            /* true if exit from sio config is ok */
 760
 761         void __iomem *mmio;     /* Remapped MMIO address if available */
 762         int (*read)(struct it87_data *, u16);
 763         void (*write)(struct it87_data *, u16, u8);
 764
 765         const u8 *REG_FAN;
 766         const u8 *REG_FANX;
 767         const u8 *REG_FAN_MIN;
 768         const u8 *REG_FANX_MIN;
 769
 770         const u8 *REG_PWM;
 771
 772         const u8 *REG_TEMP_OFFSET;
 773         const u8 *REG_TEMP_LOW;
 774         const u8 *REG_TEMP_HIGH;
 775
 776         unsigned short addr;
 777         const char *name;
 778         struct mutex update_lock;
 779         char valid;             /* !=0 if following fields are valid */
 780         unsigned long last_updated;     /* In jiffies */
 781
 782         u16 in_scaled;          /* Internal voltage sensors are scaled */
 783         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 784         u16 has_in;             /* Bitfield, voltage sensors enabled */
 785         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 786         u8 has_fan;             /* Bitfield, fans enabled */
 787         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 788         u8 has_temp;            /* Bitfield, temp sensors enabled */
 789         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 790         u8 num_temp_limit;      /* Number of temperature limit registers */
 791         u8 num_temp_offset;     /* Number of temperature offset registers */
 792         u8 temp_src[4];         /* Up to 4 temperature source registers */
 793         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 794         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 795         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 796         bool has_vid;           /* True if VID supported */
 797         u8 vid;                 /* Register encoding, combined */
 798         u8 vrm;
 799         u32 alarms;             /* Register encoding, combined */
 800         bool has_beep;          /* true if beep supported */
 801         u8 beeps;               /* Register encoding */
 802         u8 fan_main_ctrl;       /* Register value */
 803         u8 fan_ctl;             /* Register value */
 804
 805         /*
 806          * The following 3 arrays correspond to the same registers up to
 807          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 808          * 7, and we want to preserve settings on mode changes, so we have
 809          * to track all values separately.
 810          * Starting with the IT8721F, the manual PWM duty cycles are stored
 811          * in separate registers (8-bit values), so the separate tracking
 812          * is no longer needed, but it is still done to keep the driver
 813          * simple.
 814          */
 815         u8 has_pwm;             /* Bitfield, pwm control enabled */
 816         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 817         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 818         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 819         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 820         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 821         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 822
 823         /* Automatic fan speed control registers */
 824         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 825         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 826 };
 827
 828 static int adc_lsb(const struct it87_data *data, int nr)
 829 {
 830         int lsb;
 831
 832         if (has_12mv_adc(data))
 833                 lsb = 120;
 834         else if (has_10_9mv_adc(data))
 835                 lsb = 109;
 836         else if (has_11mv_adc(data))
 837                 lsb = 110;
 838         else
 839                 lsb = 160;
 840         if (data->in_scaled & BIT(nr))
 841                 lsb <<= 1;
 842         return lsb;
 843 }
 844
 845 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 846 {
 847         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 848         return clamp_val(val, 0, 255);
 849 }
 850
 851 static int in_from_reg(const struct it87_data *data, int nr, int val)
 852 {
 853         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 854 }
 855
 856 static inline u8 FAN_TO_REG(long rpm, int div)
 857 {
 858         if (rpm == 0)
 859                 return 255;
 860         rpm = clamp_val(rpm, 1, 1000000);
 861         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 862 }
 863
 864 static inline u16 FAN16_TO_REG(long rpm)
 865 {
 866         if (rpm == 0)
 867                 return 0xffff;
 868         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 869 }
 870
 871 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 872                                 1350000 / ((val) * (div)))
 873 /* The divider is fixed to 2 in 16-bit mode */
 874 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 875                              1350000 / ((val) * 2))
 876
 877 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 878                                     ((val) + 500) / 1000), -128, 127))
 879 #define TEMP_FROM_REG(val) ((val) * 1000)
 880
 881 static u8 pwm_to_reg(const struct it87_data *data, long val)
 882 {
 883         if (has_newer_autopwm(data))
 884                 return val;
 885         else
 886                 return val >> 1;
 887 }
 888
 889 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 890 {
 891         if (has_newer_autopwm(data))
 892                 return reg;
 893         else
 894                 return (reg & 0x7f) << 1;
 895 }
 896
 897 static int DIV_TO_REG(int val)
 898 {
 899         int answer = 0;
 900
 901         while (answer < 7 && (val >>= 1))
 902                 answer++;
 903         return answer;
 904 }
 905
 906 #define DIV_FROM_REG(val) BIT(val)
 907
 908 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 909 {
 910         u8 map;
 911
 912         map  = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 913         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 914                 map = 0;
 915
 916         return map;
 917 }
 918
 919 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 920 {
 921         u8 ctrl = data->pwm_ctrl[nr];
 922
 923         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 924                (map << data->pwm_temp_map_shift);
 925 }
 926
 927 /*
 928  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 929  * depending on the chip type, to calculate the actual PWM frequency.
 930  *
 931  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 932  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 933  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 934  * sometimes just one. It is unknown if this is a datasheet error or real,
 935  * so this is ignored for now.
 936  */
 937 static const unsigned int pwm_freq[8] = {
 938         48000000,
 939         24000000,
 940         12000000,
 941         8000000,
 942         6000000,
 943         3000000,
 944         1500000,
 945         750000,
 946 };
 947
 948 static int smbus_disable(struct it87_data *data)
 949 {
 950         int err;
 951
 952         if (data->smbus_bitmap) {
 953                 err = superio_enter(data->sioaddr);
 954                 if (err)
 955                         return err;
 956                 superio_select(data->sioaddr, PME);
 957                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 958                              data->ec_special_config & ~data->smbus_bitmap);
 959                 superio_exit(data->sioaddr, data->doexit);
 960         }
 961         return 0;
 962 }
 963
 964 static int smbus_enable(struct it87_data *data)
 965 {
 966         int err;
 967
 968         if (data->smbus_bitmap) {
 969                 err = superio_enter(data->sioaddr);
 970                 if (err)
 971                         return err;
 972
 973                 superio_select(data->sioaddr, PME);
 974                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 975                              data->ec_special_config);
 976                 superio_exit(data->sioaddr, data->doexit);
 977         }
 978         return 0;
 979 }
 980
 981 static int _it87_io_read(struct it87_data *data, u16 reg)
 982 {
 983         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 984         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 985 }
 986
 987 static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
 988 {
 989         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 990         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 991 }
 992
 993 static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
 994 {
 995         u8 _bank = bank;
 996
 997         if (has_bank_sel(data)) {
 998                 u8 breg = _it87_io_read(data, IT87_REG_BANK);
 999
1000                 _bank = breg >> 5;
1001                 if (bank != _bank) {
1002                         breg &= 0x1f;
1003                         breg |= (bank << 5);
1004                         _it87_io_write(data, IT87_REG_BANK, breg);
1005                 }
1006         }
1007         return _bank;
1008 }
1009
1010 /*
1011  * Must be called with data->update_lock held, except during initialization.
1012  * Must be called with SMBus accesses disabled.
1013  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1014  * would slow down the IT87 access and should not be necessary.
1015  */
1016 static int it87_io_read(struct it87_data *data, u16 reg)
1017 {
1018         u8 bank;
1019         int val;
1020
1021         bank = it87_io_set_bank(data, reg >> 8);
1022         val = _it87_io_read(data, reg & 0xff);
1023         it87_io_set_bank(data, bank);
1024
1025         return val;
1026 }
1027
1028 /*
1029  * Must be called with data->update_lock held, except during initialization.
1030  * Must be called with SMBus accesses disabled
1031  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1032  * would slow down the IT87 access and should not be necessary.
1033  */
1034 static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1035 {
1036         u8 bank;
1037
1038         bank = it87_io_set_bank(data, reg >> 8);
1039         _it87_io_write(data, reg & 0xff, value);
1040         it87_io_set_bank(data, bank);
1041 }
1042
1043 static int it87_mmio_read(struct it87_data *data, u16 reg)
1044 {
1045         return readb(data->mmio + reg);
1046 }
1047
1048 static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1049 {
1050         writeb(value, data->mmio + reg);
1051 }
1052
1053 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1054 {
1055         u8 ctrl;
1056
1057         ctrl = data->read(data, data->REG_PWM[nr]);
1058         data->pwm_ctrl[nr] = ctrl;
1059         if (has_newer_autopwm(data)) {
1060                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1061                 data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1062         } else {
1063                 if (ctrl & 0x80)        /* Automatic mode */
1064                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1065                 else                            /* Manual mode */
1066                         data->pwm_duty[nr] = ctrl & 0x7f;
1067         }
1068
1069         if (has_old_autopwm(data)) {
1070                 int i;
1071
1072                 for (i = 0; i < 5 ; i++)
1073                         data->auto_temp[nr][i] = data->read(data,
1074                                                 IT87_REG_AUTO_TEMP(nr, i));
1075                 for (i = 0; i < 3 ; i++)
1076                         data->auto_pwm[nr][i] = data->read(data,
1077                                                 IT87_REG_AUTO_PWM(nr, i));
1078         } else if (has_newer_autopwm(data)) {
1079                 int i;
1080
1081                 /*
1082                  * 0: temperature hysteresis (base + 5)
1083                  * 1: fan off temperature (base + 0)
1084                  * 2: fan start temperature (base + 1)
1085                  * 3: fan max temperature (base + 2)
1086                  */
1087                 data->auto_temp[nr][0] =
1088                         data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1089
1090                 for (i = 0; i < 3 ; i++)
1091                         data->auto_temp[nr][i + 1] =
1092                                 data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1093                 /*
1094                  * 0: start pwm value (base + 3)
1095                  * 1: pwm slope (base + 4, 1/8th pwm)
1096                  */
1097                 data->auto_pwm[nr][0] =
1098                         data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1099                 data->auto_pwm[nr][1] =
1100                         data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1101         }
1102 }
1103
1104 static int it87_lock(struct it87_data *data)
1105 {
1106         int err;
1107
1108         mutex_lock(&data->update_lock);
1109         err = smbus_disable(data);
1110         if (err)
1111                 mutex_unlock(&data->update_lock);
1112         return err;
1113 }
1114
1115 static void it87_unlock(struct it87_data *data)
1116 {
1117         smbus_enable(data);
1118         mutex_unlock(&data->update_lock);
1119 }
1120
1121 static struct it87_data *it87_update_device(struct device *dev)
1122 {
1123         struct it87_data *data = dev_get_drvdata(dev);
1124         int err;
1125         int i;
1126
1127         err = it87_lock(data);
1128         if (err)
1129                 return ERR_PTR(err);
1130
1131         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1132             !data->valid) {
1133                 if (update_vbat) {
1134                         /*
1135                          * Cleared after each update, so reenable.  Value
1136                          * returned by this read will be previous value
1137                          */
1138                         data->write(data, IT87_REG_CONFIG,
1139                                     data->read(data, IT87_REG_CONFIG) | 0x40);
1140                 }
1141                 for (i = 0; i < NUM_VIN; i++) {
1142                         if (!(data->has_in & BIT(i)))
1143                                 continue;
1144
1145                         data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1146
1147                         /* VBAT and AVCC don't have limit registers */
1148                         if (i >= NUM_VIN_LIMIT)
1149                                 continue;
1150
1151                         data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1152                         data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1153                 }
1154
1155                 for (i = 0; i < NUM_FAN; i++) {
1156                         /* Skip disabled fans */
1157                         if (!(data->has_fan & BIT(i)))
1158                                 continue;
1159
1160                         data->fan[i][1] = data->read(data, data->REG_FAN_MIN[i]);
1161                         data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1162                         /* Add high byte if in 16-bit mode */
1163                         if (has_16bit_fans(data)) {
1164                                 data->fan[i][0] |= data->read(data,
1165                                                 data->REG_FANX[i]) << 8;
1166                                 data->fan[i][1] |= data->read(data,
1167                                                 data->REG_FANX_MIN[i]) << 8;
1168                         }
1169                 }
1170                 for (i = 0; i < NUM_TEMP; i++) {
1171                         if (!(data->has_temp & BIT(i)))
1172                                 continue;
1173                         data->temp[i][0] =
1174                                 data->read(data, IT87_REG_TEMP(i));
1175
1176                         if (i >= data->num_temp_limit)
1177                                 continue;
1178
1179                         if (i < data->num_temp_offset)
1180                                 data->temp[i][3] =
1181                                   data->read(data, data->REG_TEMP_OFFSET[i]);
1182
1183                         data->temp[i][1] =
1184                                 data->read(data, data->REG_TEMP_LOW[i]);
1185                         data->temp[i][2] =
1186                                 data->read(data, data->REG_TEMP_HIGH[i]);
1187                 }
1188
1189                 /* Newer chips don't have clock dividers */
1190                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1191                         i = data->read(data, IT87_REG_FAN_DIV);
1192                         data->fan_div[0] = i & 0x07;
1193                         data->fan_div[1] = (i >> 3) & 0x07;
1194                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1195                 }
1196
1197                 data->alarms =
1198                         data->read(data, IT87_REG_ALARM1) |
1199                         (data->read(data, IT87_REG_ALARM2) << 8) |
1200                         (data->read(data, IT87_REG_ALARM3) << 16);
1201                 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1202
1203                 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1204                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1205                 for (i = 0; i < NUM_PWM; i++) {
1206                         if (!(data->has_pwm & BIT(i)))
1207                                 continue;
1208                         it87_update_pwm_ctrl(data, i);
1209                 }
1210
1211                 data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1212                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1213                 /*
1214                  * The IT8705F does not have VID capability.
1215                  * The IT8718F and later don't use IT87_REG_VID for the
1216                  * same purpose.
1217                  */
1218                 if (data->type == it8712 || data->type == it8716) {
1219                         data->vid = data->read(data, IT87_REG_VID);
1220                         /*
1221                          * The older IT8712F revisions had only 5 VID pins,
1222                          * but we assume it is always safe to read 6 bits.
1223                          */
1224                         data->vid &= 0x3f;
1225                 }
1226                 data->last_updated = jiffies;
1227                 data->valid = 1;
1228         }
1229         it87_unlock(data);
1230         return data;
1231 }
1232
1233 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1234                        char *buf)
1235 {
1236         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1237         struct it87_data *data = it87_update_device(dev);
1238         int index = sattr->index;
1239         int nr = sattr->nr;
1240
1241         if (IS_ERR(data))
1242                 return PTR_ERR(data);
1243
1244         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1245 }
1246
1247 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1248                       const char *buf, size_t count)
1249 {
1250         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1251         struct it87_data *data = dev_get_drvdata(dev);
1252         int index = sattr->index;
1253         int nr = sattr->nr;
1254         unsigned long val;
1255         int err;
1256
1257         if (kstrtoul(buf, 10, &val) < 0)
1258                 return -EINVAL;
1259
1260         err = it87_lock(data);
1261         if (err)
1262                 return err;
1263
1264         data->in[nr][index] = in_to_reg(data, nr, val);
1265         data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1266                                      : IT87_REG_VIN_MAX(nr),
1267                     data->in[nr][index]);
1268         it87_unlock(data);
1269         return count;
1270 }
1271
1272 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1273 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1274                             0, 1);
1275 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1276                             0, 2);
1277
1278 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1279 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1280                             1, 1);
1281 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1282                             1, 2);
1283
1284 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1285 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1286                             2, 1);
1287 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1288                             2, 2);
1289
1290 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1291 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1292                             3, 1);
1293 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1294                             3, 2);
1295
1296 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1297 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1298                             4, 1);
1299 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1300                             4, 2);
1301
1302 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1303 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1304                             5, 1);
1305 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1306                             5, 2);
1307
1308 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1309 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1310                             6, 1);
1311 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1312                             6, 2);
1313
1314 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1315 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1316                             7, 1);
1317 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1318                             7, 2);
1319
1320 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1321 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1322 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1323 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1324 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1325
1326 /* Up to 6 temperatures */
1327 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1328                          char *buf)
1329 {
1330         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1331         int nr = sattr->nr;
1332         int index = sattr->index;
1333         struct it87_data *data = it87_update_device(dev);
1334
1335         if (IS_ERR(data))
1336                 return PTR_ERR(data);
1337
1338         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1339 }
1340
1341 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1342                         const char *buf, size_t count)
1343 {
1344         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1345         int nr = sattr->nr;
1346         int index = sattr->index;
1347         struct it87_data *data = dev_get_drvdata(dev);
1348         long val;
1349         u8 reg, regval;
1350         int err;
1351
1352         if (kstrtol(buf, 10, &val) < 0)
1353                 return -EINVAL;
1354
1355         err = it87_lock(data);
1356         if (err)
1357                 return err;
1358
1359         switch (index) {
1360         default:
1361         case 1:
1362                 reg = data->REG_TEMP_LOW[nr];
1363                 break;
1364         case 2:
1365                 reg = data->REG_TEMP_HIGH[nr];
1366                 break;
1367         case 3:
1368                 regval = data->read(data, IT87_REG_BEEP_ENABLE);
1369                 if (!(regval & 0x80)) {
1370                         regval |= 0x80;
1371                         data->write(data, IT87_REG_BEEP_ENABLE, regval);
1372                 }
1373                 data->valid = 0;
1374                 reg = data->REG_TEMP_OFFSET[nr];
1375                 break;
1376         }
1377
1378         data->temp[nr][index] = TEMP_TO_REG(val);
1379         data->write(data, reg, data->temp[nr][index]);
1380         it87_unlock(data);
1381         return count;
1382 }
1383
1384 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1385 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1386                             0, 1);
1387 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1388                             0, 2);
1389 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1390                             set_temp, 0, 3);
1391 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1392 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1393                             1, 1);
1394 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1395                             1, 2);
1396 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1397                             set_temp, 1, 3);
1398 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1399 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1400                             2, 1);
1401 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1402                             2, 2);
1403 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1404                             set_temp, 2, 3);
1405 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1406 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1407                             3, 1);
1408 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1409                             3, 2);
1410 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1411                             set_temp, 3, 3);
1412 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1413 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1414                             4, 1);
1415 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1416                             4, 2);
1417 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1418                             set_temp, 4, 3);
1419 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1420 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1421                             5, 1);
1422 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1423                             5, 2);
1424 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1425                             set_temp, 5, 3);
1426
1427 static const u8 temp_types_8686[NUM_TEMP][9] = {
1428         { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1429         { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1430         { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1431         { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1432         { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1433         { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1434 };
1435
1436 static int get_temp_type(struct it87_data *data, int index)
1437 {
1438         u8 reg, extra;
1439         int ttype, type = 0;
1440
1441         if (has_bank_sel(data)) {
1442                 u8 src1, src2;
1443
1444                 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1445
1446                 switch (data->type) {
1447                 case it8686:
1448                         if (src1 < 9)
1449                                 type = temp_types_8686[index][src1];
1450                         break;
1451                 case it8625:
1452                         if (index < 3)
1453                                 break;
1454                 case it8655:
1455                 case it8665:
1456                         if (src1 < 3) {
1457                                 index = src1;
1458                                 break;
1459                         }
1460                         src2 = data->temp_src[3];
1461                         switch (src1) {
1462                         case 3:
1463                                 type = (src2 & BIT(index)) ? 6 : 5;
1464                                 break;
1465                         case 4 ... 8:
1466                                 type = (src2 & BIT(index)) ? 4 : 6;
1467                                 break;
1468                         case 9:
1469                                 type = (src2 & BIT(index)) ? 5 : 0;
1470                                 break;
1471                         default:
1472                                 break;
1473                         }
1474                         return type;
1475                 default:
1476                         return 0;
1477                 }
1478         }
1479         if (type)
1480                 return type;
1481
1482         /* Dectect PECI vs. AMDTSI if possible */
1483         ttype = 6;
1484         if ((has_temp_peci(data, index)) && data->type != it8721) {
1485                 extra = data->read(data, 0x98); /* PCH/AMDTSI host status */
1486                 if (extra & BIT(6))
1487                         ttype = 5;
1488         }
1489
1490         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1491
1492         /* Per chip special detection */
1493         switch (data->type) {
1494         case it8622:
1495                 if (!(reg & 0xc0) && index == 3)
1496                         type = ttype;
1497                 break;
1498         default:
1499                 break;
1500         }
1501
1502         if (type || index >= 3)
1503                 return type;
1504
1505         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1506
1507         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1508             (has_temp_old_peci(data, index) && (extra & 0x80)))
1509                 type = ttype;           /* Intel PECI or AMDTSI */
1510         if (reg & BIT(index))
1511                 type = 3;               /* thermal diode */
1512         else if (reg & BIT(index + 3))
1513                 type = 4;               /* thermistor */
1514
1515         return type;
1516 }
1517
1518 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1519                               char *buf)
1520 {
1521         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1522         struct it87_data *data = it87_update_device(dev);
1523         int type;
1524
1525         if (IS_ERR(data))
1526                 return PTR_ERR(data);
1527
1528         type = get_temp_type(data, sensor_attr->index);
1529         return sprintf(buf, "%d\n", type);
1530 }
1531
1532 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1533                              const char *buf, size_t count)
1534 {
1535         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1536         int nr = sensor_attr->index;
1537
1538         struct it87_data *data = dev_get_drvdata(dev);
1539         long val;
1540         u8 reg, extra;
1541         int err;
1542
1543         if (kstrtol(buf, 10, &val) < 0)
1544                 return -EINVAL;
1545
1546         err = it87_lock(data);
1547         if (err)
1548                 return err;
1549
1550         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1551         reg &= ~(1 << nr);
1552         reg &= ~(8 << nr);
1553         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1554                 reg &= 0x3f;
1555         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1556         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1557                 extra &= 0x7f;
1558         if (val == 2) { /* backwards compatibility */
1559                 dev_warn(dev,
1560                          "Sensor type 2 is deprecated, please use 4 instead\n");
1561                 val = 4;
1562         }
1563         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1564         if (val == 3)
1565                 reg |= 1 << nr;
1566         else if (val == 4)
1567                 reg |= 8 << nr;
1568         else if (has_temp_peci(data, nr) && val == 6)
1569                 reg |= (nr + 1) << 6;
1570         else if (has_temp_old_peci(data, nr) && val == 6)
1571                 extra |= 0x80;
1572         else if (val != 0) {
1573                 count = -EINVAL;
1574                 goto unlock;
1575         }
1576
1577         data->sensor = reg;
1578         data->extra = extra;
1579         data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1580         if (has_temp_old_peci(data, nr))
1581                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1582         data->valid = 0;        /* Force cache refresh */
1583 unlock:
1584         it87_unlock(data);
1585         return count;
1586 }
1587
1588 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1589                           set_temp_type, 0);
1590 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1591                           set_temp_type, 1);
1592 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1593                           set_temp_type, 2);
1594 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1595                           set_temp_type, 3);
1596 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1597                           set_temp_type, 4);
1598 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1599                           set_temp_type, 5);
1600
1601 /* 6 Fans */
1602
1603 static int pwm_mode(const struct it87_data *data, int nr)
1604 {
1605         if (has_fanctl_onoff(data) && nr < 3 &&
1606             !(data->fan_main_ctrl & BIT(nr)))
1607                 return 0;                               /* Full speed */
1608         if (data->pwm_ctrl[nr] & 0x80)
1609                 return 2;                               /* Automatic mode */
1610         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1611             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1612                 return 0;                       /* Full speed */
1613
1614         return 1;                               /* Manual mode */
1615 }
1616
1617 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1618                         char *buf)
1619 {
1620         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1621         int nr = sattr->nr;
1622         int index = sattr->index;
1623         int speed;
1624         struct it87_data *data = it87_update_device(dev);
1625
1626         if (IS_ERR(data))
1627                 return PTR_ERR(data);
1628
1629         speed = has_16bit_fans(data) ?
1630                 FAN16_FROM_REG(data->fan[nr][index]) :
1631                 FAN_FROM_REG(data->fan[nr][index],
1632                              DIV_FROM_REG(data->fan_div[nr]));
1633         return sprintf(buf, "%d\n", speed);
1634 }
1635
1636 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1637                             char *buf)
1638 {
1639         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1640         struct it87_data *data = it87_update_device(dev);
1641         int nr = sensor_attr->index;
1642
1643         if (IS_ERR(data))
1644                 return PTR_ERR(data);
1645
1646         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1647 }
1648
1649 static ssize_t show_pwm_enable(struct device *dev,
1650                                struct device_attribute *attr, char *buf)
1651 {
1652         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1653         struct it87_data *data = it87_update_device(dev);
1654         int nr = sensor_attr->index;
1655
1656         if (IS_ERR(data))
1657                 return PTR_ERR(data);
1658
1659         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1660 }
1661
1662 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1663                         char *buf)
1664 {
1665         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1666         struct it87_data *data = it87_update_device(dev);
1667         int nr = sensor_attr->index;
1668
1669         if (IS_ERR(data))
1670                 return PTR_ERR(data);
1671
1672         return sprintf(buf, "%d\n",
1673                        pwm_from_reg(data, data->pwm_duty[nr]));
1674 }
1675
1676 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1677                              char *buf)
1678 {
1679         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1680         struct it87_data *data = it87_update_device(dev);
1681         int nr = sensor_attr->index;
1682         unsigned int freq;
1683         int index;
1684
1685         if (IS_ERR(data))
1686                 return PTR_ERR(data);
1687
1688         if (has_pwm_freq2(data) && nr == 1)
1689                 index = (data->extra >> 4) & 0x07;
1690         else
1691                 index = (data->fan_ctl >> 4) & 0x07;
1692
1693         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1694
1695         return sprintf(buf, "%u\n", freq);
1696 }
1697
1698 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1699                        const char *buf, size_t count)
1700 {
1701         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1702         int nr = sattr->nr;
1703         int index = sattr->index;
1704
1705         struct it87_data *data = dev_get_drvdata(dev);
1706         long val;
1707         int err;
1708         u8 reg;
1709
1710         if (kstrtol(buf, 10, &val) < 0)
1711                 return -EINVAL;
1712
1713         err = it87_lock(data);
1714         if (err)
1715                 return err;
1716
1717         if (has_16bit_fans(data)) {
1718                 data->fan[nr][index] = FAN16_TO_REG(val);
1719                 data->write(data, data->REG_FAN_MIN[nr],
1720                             data->fan[nr][index] & 0xff);
1721                 data->write(data, data->REG_FANX_MIN[nr],
1722                             data->fan[nr][index] >> 8);
1723         } else {
1724                 reg = data->read(data, IT87_REG_FAN_DIV);
1725                 switch (nr) {
1726                 case 0:
1727                         data->fan_div[nr] = reg & 0x07;
1728                         break;
1729                 case 1:
1730                         data->fan_div[nr] = (reg >> 3) & 0x07;
1731                         break;
1732                 case 2:
1733                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1734                         break;
1735                 }
1736                 data->fan[nr][index] =
1737                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1738                 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1739         }
1740         it87_unlock(data);
1741         return count;
1742 }
1743
1744 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1745                            const char *buf, size_t count)
1746 {
1747         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1748         struct it87_data *data = dev_get_drvdata(dev);
1749         int nr = sensor_attr->index;
1750         unsigned long val;
1751         int min, err;
1752         u8 old;
1753
1754         if (kstrtoul(buf, 10, &val) < 0)
1755                 return -EINVAL;
1756
1757         err = it87_lock(data);
1758         if (err)
1759                 return err;
1760
1761         old = data->read(data, IT87_REG_FAN_DIV);
1762
1763         /* Save fan min limit */
1764         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1765
1766         switch (nr) {
1767         case 0:
1768         case 1:
1769                 data->fan_div[nr] = DIV_TO_REG(val);
1770                 break;
1771         case 2:
1772                 if (val < 8)
1773                         data->fan_div[nr] = 1;
1774                 else
1775                         data->fan_div[nr] = 3;
1776         }
1777         val = old & 0x80;
1778         val |= (data->fan_div[0] & 0x07);
1779         val |= (data->fan_div[1] & 0x07) << 3;
1780         if (data->fan_div[2] == 3)
1781                 val |= 0x1 << 6;
1782         data->write(data, IT87_REG_FAN_DIV, val);
1783
1784         /* Restore fan min limit */
1785         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1786         data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1787         it87_unlock(data);
1788         return count;
1789 }
1790
1791 /* Returns 0 if OK, -EINVAL otherwise */
1792 static int check_trip_points(struct device *dev, int nr)
1793 {
1794         const struct it87_data *data = dev_get_drvdata(dev);
1795         int i, err = 0;
1796
1797         if (has_old_autopwm(data)) {
1798                 for (i = 0; i < 3; i++) {
1799                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1800                                 err = -EINVAL;
1801                 }
1802                 for (i = 0; i < 2; i++) {
1803                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1804                                 err = -EINVAL;
1805                 }
1806         } else if (has_newer_autopwm(data)) {
1807                 for (i = 1; i < 3; i++) {
1808                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1809                                 err = -EINVAL;
1810                 }
1811         }
1812
1813         if (err) {
1814                 dev_err(dev,
1815                         "Inconsistent trip points, not switching to automatic mode\n");
1816                 dev_err(dev, "Adjust the trip points and try again\n");
1817         }
1818         return err;
1819 }
1820
1821 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1822                               const char *buf, size_t count)
1823 {
1824         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1825         struct it87_data *data = dev_get_drvdata(dev);
1826         int nr = sensor_attr->index;
1827         long val;
1828         int err;
1829
1830         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1831                 return -EINVAL;
1832
1833         /* Check trip points before switching to automatic mode */
1834         if (val == 2) {
1835                 if (check_trip_points(dev, nr) < 0)
1836                         return -EINVAL;
1837         }
1838
1839         err = it87_lock(data);
1840         if (err)
1841                 return err;
1842
1843         it87_update_pwm_ctrl(data, nr);
1844
1845         if (val == 0) {
1846                 if (nr < 3 && has_fanctl_onoff(data)) {
1847                         int tmp;
1848                         /* make sure the fan is on when in on/off mode */
1849                         tmp = data->read(data, IT87_REG_FAN_CTL);
1850                         data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1851                         /* set on/off mode */
1852                         data->fan_main_ctrl &= ~BIT(nr);
1853                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1854                                     data->fan_main_ctrl);
1855                 } else {
1856                         u8 ctrl;
1857
1858                         /* No on/off mode, set maximum pwm value */
1859                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1860                         data->write(data, IT87_REG_PWM_DUTY[nr],
1861                                     data->pwm_duty[nr]);
1862                         /* and set manual mode */
1863                         if (has_newer_autopwm(data)) {
1864                                 ctrl = temp_map_to_reg(data, nr,
1865                                                        data->pwm_temp_map[nr]);
1866                                 ctrl &= 0x7f;
1867                         } else {
1868                                 ctrl = data->pwm_duty[nr];
1869                         }
1870                         data->pwm_ctrl[nr] = ctrl;
1871                         data->write(data, data->REG_PWM[nr], ctrl);
1872                 }
1873         } else {
1874                 u8 ctrl;
1875
1876                 if (has_newer_autopwm(data)) {
1877                         ctrl = temp_map_to_reg(data, nr,
1878                                                data->pwm_temp_map[nr]);
1879                         if (val == 1)
1880                                 ctrl &= 0x7f;
1881                         else
1882                                 ctrl |= 0x80;
1883                 } else {
1884                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1885                 }
1886                 data->pwm_ctrl[nr] = ctrl;
1887                 data->write(data, data->REG_PWM[nr], ctrl);
1888
1889                 if (has_fanctl_onoff(data) && nr < 3) {
1890                         /* set SmartGuardian mode */
1891                         data->fan_main_ctrl |= BIT(nr);
1892                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1893                                     data->fan_main_ctrl);
1894                 }
1895         }
1896         it87_unlock(data);
1897         return count;
1898 }
1899
1900 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1901                        const char *buf, size_t count)
1902 {
1903         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1904         struct it87_data *data = dev_get_drvdata(dev);
1905         int nr = sensor_attr->index;
1906         long val;
1907         int err;
1908
1909         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1910                 return -EINVAL;
1911
1912         err = it87_lock(data);
1913         if (err)
1914                 return err;
1915
1916         it87_update_pwm_ctrl(data, nr);
1917         if (has_newer_autopwm(data)) {
1918                 /*
1919                  * If we are in automatic mode, the PWM duty cycle register
1920                  * is read-only so we can't write the value.
1921                  */
1922                 if (data->pwm_ctrl[nr] & 0x80) {
1923                         count = -EBUSY;
1924                         goto unlock;
1925                 }
1926                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1927                 data->write(data, IT87_REG_PWM_DUTY[nr],
1928                             data->pwm_duty[nr]);
1929         } else {
1930                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1931                 /*
1932                  * If we are in manual mode, write the duty cycle immediately;
1933                  * otherwise, just store it for later use.
1934                  */
1935                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1936                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1937                         data->write(data, data->REG_PWM[nr],
1938                                     data->pwm_ctrl[nr]);
1939                 }
1940         }
1941 unlock:
1942         it87_unlock(data);
1943         return count;
1944 }
1945
1946 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1947                             const char *buf, size_t count)
1948 {
1949         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1950         struct it87_data *data = dev_get_drvdata(dev);
1951         int nr = sensor_attr->index;
1952         unsigned long val;
1953         int err;
1954         int i;
1955
1956         if (kstrtoul(buf, 10, &val) < 0)
1957                 return -EINVAL;
1958
1959         val = clamp_val(val, 0, 1000000);
1960         val *= has_newer_autopwm(data) ? 256 : 128;
1961
1962         /* Search for the nearest available frequency */
1963         for (i = 0; i < 7; i++) {
1964                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1965                         break;
1966         }
1967
1968         err = it87_lock(data);
1969         if (err)
1970                 return err;
1971
1972         if (nr == 0) {
1973                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1974                 data->fan_ctl |= i << 4;
1975                 data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
1976         } else {
1977                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1978                 data->extra |= i << 4;
1979                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1980         }
1981         it87_unlock(data);
1982         return count;
1983 }
1984
1985 static ssize_t show_pwm_temp_map(struct device *dev,
1986                                  struct device_attribute *attr, char *buf)
1987 {
1988         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1989         struct it87_data *data = it87_update_device(dev);
1990         int nr = sensor_attr->index;
1991
1992         if (IS_ERR(data))
1993                 return PTR_ERR(data);
1994
1995         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1996 }
1997
1998 static ssize_t set_pwm_temp_map(struct device *dev,
1999                                 struct device_attribute *attr, const char *buf,
2000                                 size_t count)
2001 {
2002         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2003         struct it87_data *data = dev_get_drvdata(dev);
2004         int nr = sensor_attr->index;
2005         unsigned long val;
2006         int err;
2007         u8 map;
2008
2009         if (kstrtoul(buf, 10, &val) < 0)
2010                 return -EINVAL;
2011
2012         if (!val || val > data->pwm_num_temp_map)
2013                 return -EINVAL;
2014
2015         map = val - 1;
2016
2017         err = it87_lock(data);
2018         if (err)
2019                 return err;
2020
2021         it87_update_pwm_ctrl(data, nr);
2022         data->pwm_temp_map[nr] = map;
2023         /*
2024          * If we are in automatic mode, write the temp mapping immediately;
2025          * otherwise, just store it for later use.
2026          */
2027         if (data->pwm_ctrl[nr] & 0x80) {
2028                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
2029                 data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
2030         }
2031         it87_unlock(data);
2032         return count;
2033 }
2034
2035 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
2036                              char *buf)
2037 {
2038         struct it87_data *data = it87_update_device(dev);
2039         struct sensor_device_attribute_2 *sensor_attr =
2040                         to_sensor_dev_attr_2(attr);
2041         int nr = sensor_attr->nr;
2042         int point = sensor_attr->index;
2043
2044         if (IS_ERR(data))
2045                 return PTR_ERR(data);
2046
2047         return sprintf(buf, "%d\n",
2048                        pwm_from_reg(data, data->auto_pwm[nr][point]));
2049 }
2050
2051 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2052                             const char *buf, size_t count)
2053 {
2054         struct it87_data *data = dev_get_drvdata(dev);
2055         struct sensor_device_attribute_2 *sensor_attr =
2056                         to_sensor_dev_attr_2(attr);
2057         int nr = sensor_attr->nr;
2058         int point = sensor_attr->index;
2059         int regaddr;
2060         long val;
2061         int err;
2062
2063         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2064                 return -EINVAL;
2065
2066         err = it87_lock(data);
2067         if (err)
2068                 return err;
2069
2070         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2071         if (has_newer_autopwm(data))
2072                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2073         else
2074                 regaddr = IT87_REG_AUTO_PWM(nr, point);
2075         data->write(data, regaddr, data->auto_pwm[nr][point]);
2076         it87_unlock(data);
2077         return count;
2078 }
2079
2080 static ssize_t show_auto_pwm_slope(struct device *dev,
2081                                    struct device_attribute *attr, char *buf)
2082 {
2083         struct it87_data *data = it87_update_device(dev);
2084         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2085         int nr = sensor_attr->index;
2086
2087         if (IS_ERR(data))
2088                 return PTR_ERR(data);
2089
2090         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2091 }
2092
2093 static ssize_t set_auto_pwm_slope(struct device *dev,
2094                                   struct device_attribute *attr,
2095                                   const char *buf, size_t count)
2096 {
2097         struct it87_data *data = dev_get_drvdata(dev);
2098         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2099         int nr = sensor_attr->index;
2100         unsigned long val;
2101         int err;
2102
2103         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2104                 return -EINVAL;
2105
2106         err = it87_lock(data);
2107         if (err)
2108                 return err;
2109
2110         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2111         data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2112         it87_unlock(data);
2113         return count;
2114 }
2115
2116 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2117                               char *buf)
2118 {
2119         struct it87_data *data = it87_update_device(dev);
2120         struct sensor_device_attribute_2 *sensor_attr =
2121                         to_sensor_dev_attr_2(attr);
2122         int nr = sensor_attr->nr;
2123         int point = sensor_attr->index;
2124         int reg;
2125
2126         if (IS_ERR(data))
2127                 return PTR_ERR(data);
2128
2129         if (has_old_autopwm(data) || point)
2130                 reg = data->auto_temp[nr][point];
2131         else
2132                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2133
2134         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2135 }
2136
2137 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2138                              const char *buf, size_t count)
2139 {
2140         struct it87_data *data = dev_get_drvdata(dev);
2141         struct sensor_device_attribute_2 *sensor_attr =
2142                         to_sensor_dev_attr_2(attr);
2143         int nr = sensor_attr->nr;
2144         int point = sensor_attr->index;
2145         long val;
2146         int reg;
2147         int err;
2148
2149         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2150                 return -EINVAL;
2151
2152         err = it87_lock(data);
2153         if (err)
2154                 return err;
2155
2156         if (has_newer_autopwm(data) && !point) {
2157                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2158                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2159                 data->auto_temp[nr][0] = reg;
2160                 data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2161         } else {
2162                 reg = TEMP_TO_REG(val);
2163                 data->auto_temp[nr][point] = reg;
2164                 if (has_newer_autopwm(data))
2165                         point--;
2166                 data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2167         }
2168         it87_unlock(data);
2169         return count;
2170 }
2171
2172 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
2173 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2174                             0, 1);
2175 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
2176                           set_fan_div, 0);
2177
2178 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
2179 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2180                             1, 1);
2181 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
2182                           set_fan_div, 1);
2183
2184 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
2185 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2186                             2, 1);
2187 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
2188                           set_fan_div, 2);
2189
2190 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2191 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2192                             3, 1);
2193
2194 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2195 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2196                             4, 1);
2197
2198 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2199 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2200                             5, 1);
2201
2202 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2203                           show_pwm_enable, set_pwm_enable, 0);
2204 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2205 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2206                           set_pwm_freq, 0);
2207 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2208                           show_pwm_temp_map, set_pwm_temp_map, 0);
2209 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2210                             show_auto_pwm, set_auto_pwm, 0, 0);
2211 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2212                             show_auto_pwm, set_auto_pwm, 0, 1);
2213 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2214                             show_auto_pwm, set_auto_pwm, 0, 2);
2215 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2216                             show_auto_pwm, NULL, 0, 3);
2217 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2218                             show_auto_temp, set_auto_temp, 0, 1);
2219 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2220                             show_auto_temp, set_auto_temp, 0, 0);
2221 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2222                             show_auto_temp, set_auto_temp, 0, 2);
2223 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2224                             show_auto_temp, set_auto_temp, 0, 3);
2225 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2226                             show_auto_temp, set_auto_temp, 0, 4);
2227 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2228                             show_auto_pwm, set_auto_pwm, 0, 0);
2229 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2230                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2231
2232 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2233                           show_pwm_enable, set_pwm_enable, 1);
2234 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2235 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2236 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2237                           show_pwm_temp_map, set_pwm_temp_map, 1);
2238 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2239                             show_auto_pwm, set_auto_pwm, 1, 0);
2240 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2241                             show_auto_pwm, set_auto_pwm, 1, 1);
2242 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2243                             show_auto_pwm, set_auto_pwm, 1, 2);
2244 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2245                             show_auto_pwm, NULL, 1, 3);
2246 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2247                             show_auto_temp, set_auto_temp, 1, 1);
2248 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2249                             show_auto_temp, set_auto_temp, 1, 0);
2250 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2251                             show_auto_temp, set_auto_temp, 1, 2);
2252 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2253                             show_auto_temp, set_auto_temp, 1, 3);
2254 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2255                             show_auto_temp, set_auto_temp, 1, 4);
2256 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2257                             show_auto_pwm, set_auto_pwm, 1, 0);
2258 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2259                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2260
2261 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2262                           show_pwm_enable, set_pwm_enable, 2);
2263 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2264 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2265 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2266                           show_pwm_temp_map, set_pwm_temp_map, 2);
2267 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2268                             show_auto_pwm, set_auto_pwm, 2, 0);
2269 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2270                             show_auto_pwm, set_auto_pwm, 2, 1);
2271 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2272                             show_auto_pwm, set_auto_pwm, 2, 2);
2273 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2274                             show_auto_pwm, NULL, 2, 3);
2275 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2276                             show_auto_temp, set_auto_temp, 2, 1);
2277 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2278                             show_auto_temp, set_auto_temp, 2, 0);
2279 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2280                             show_auto_temp, set_auto_temp, 2, 2);
2281 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2282                             show_auto_temp, set_auto_temp, 2, 3);
2283 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2284                             show_auto_temp, set_auto_temp, 2, 4);
2285 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2286                             show_auto_pwm, set_auto_pwm, 2, 0);
2287 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2288                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2289
2290 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2291                           show_pwm_enable, set_pwm_enable, 3);
2292 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2293 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2294 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2295                           show_pwm_temp_map, set_pwm_temp_map, 3);
2296 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2297                             show_auto_temp, set_auto_temp, 2, 1);
2298 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2299                             show_auto_temp, set_auto_temp, 2, 0);
2300 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2301                             show_auto_temp, set_auto_temp, 2, 2);
2302 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2303                             show_auto_temp, set_auto_temp, 2, 3);
2304 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2305                             show_auto_pwm, set_auto_pwm, 3, 0);
2306 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2307                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2308
2309 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2310                           show_pwm_enable, set_pwm_enable, 4);
2311 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2312 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2313 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2314                           show_pwm_temp_map, set_pwm_temp_map, 4);
2315 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2316                             show_auto_temp, set_auto_temp, 2, 1);
2317 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2318                             show_auto_temp, set_auto_temp, 2, 0);
2319 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2320                             show_auto_temp, set_auto_temp, 2, 2);
2321 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2322                             show_auto_temp, set_auto_temp, 2, 3);
2323 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2324                             show_auto_pwm, set_auto_pwm, 4, 0);
2325 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2326                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2327
2328 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2329                           show_pwm_enable, set_pwm_enable, 5);
2330 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2331 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2332 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2333                           show_pwm_temp_map, set_pwm_temp_map, 5);
2334 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2335                             show_auto_temp, set_auto_temp, 2, 1);
2336 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2337                             show_auto_temp, set_auto_temp, 2, 0);
2338 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2339                             show_auto_temp, set_auto_temp, 2, 2);
2340 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2341                             show_auto_temp, set_auto_temp, 2, 3);
2342 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2343                             show_auto_pwm, set_auto_pwm, 5, 0);
2344 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2345                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2346
2347 /* Alarms */
2348 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2349                            char *buf)
2350 {
2351         struct it87_data *data = it87_update_device(dev);
2352
2353         if (IS_ERR(data))
2354                 return PTR_ERR(data);
2355
2356         return sprintf(buf, "%u\n", data->alarms);
2357 }
2358 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2359
2360 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2361                           char *buf)
2362 {
2363         struct it87_data *data = it87_update_device(dev);
2364         int bitnr = to_sensor_dev_attr(attr)->index;
2365
2366         if (IS_ERR(data))
2367                 return PTR_ERR(data);
2368
2369         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2370 }
2371
2372 static ssize_t clear_intrusion(struct device *dev,
2373                                struct device_attribute *attr, const char *buf,
2374                                size_t count)
2375 {
2376         struct it87_data *data = dev_get_drvdata(dev);
2377         int err, config;
2378         long val;
2379
2380         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2381                 return -EINVAL;
2382
2383         err = it87_lock(data);
2384         if (err)
2385                 return err;
2386
2387         config = data->read(data, IT87_REG_CONFIG);
2388         config |= BIT(5);
2389         data->write(data, IT87_REG_CONFIG, config);
2390         /* Invalidate cache to force re-read */
2391         data->valid = 0;
2392         it87_unlock(data);
2393         return count;
2394 }
2395
2396 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2397 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2398 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2399 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2400 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2401 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2402 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2403 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2404 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2405 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2406 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2407 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2408 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2409 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2410 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2411 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2412 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2413 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2414 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2415 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2416 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2417                           show_alarm, clear_intrusion, 4);
2418
2419 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2420                          char *buf)
2421 {
2422         struct it87_data *data = it87_update_device(dev);
2423         int bitnr = to_sensor_dev_attr(attr)->index;
2424
2425         if (IS_ERR(data))
2426                 return PTR_ERR(data);
2427
2428         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2429 }
2430
2431 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2432                         const char *buf, size_t count)
2433 {
2434         int bitnr = to_sensor_dev_attr(attr)->index;
2435         struct it87_data *data = dev_get_drvdata(dev);
2436         long val;
2437         int err;
2438
2439         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2440                 return -EINVAL;
2441
2442         err = it87_lock(data);
2443         if (err)
2444                 return err;
2445
2446         data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2447         if (val)
2448                 data->beeps |= BIT(bitnr);
2449         else
2450                 data->beeps &= ~BIT(bitnr);
2451         data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2452         it87_unlock(data);
2453         return count;
2454 }
2455
2456 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2457                           show_beep, set_beep, 1);
2458 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2459 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2460 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2461 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2462 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2463 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2464 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2465 /* fanX_beep writability is set later */
2466 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2467 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2468 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2469 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2470 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2471 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2472 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2473                           show_beep, set_beep, 2);
2474 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2475 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2476 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2477 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2478 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2479
2480 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2481                             char *buf)
2482 {
2483         struct it87_data *data = dev_get_drvdata(dev);
2484
2485         return sprintf(buf, "%u\n", data->vrm);
2486 }
2487
2488 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2489                              const char *buf, size_t count)
2490 {
2491         struct it87_data *data = dev_get_drvdata(dev);
2492         unsigned long val;
2493
2494         if (kstrtoul(buf, 10, &val) < 0)
2495                 return -EINVAL;
2496
2497         data->vrm = val;
2498
2499         return count;
2500 }
2501 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2502
2503 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2504                             char *buf)
2505 {
2506         struct it87_data *data = it87_update_device(dev);
2507
2508         if (IS_ERR(data))
2509                 return PTR_ERR(data);
2510
2511         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2512 }
2513 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2514
2515 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2516                           char *buf)
2517 {
2518         static const char * const labels[] = {
2519                 "+5V",
2520                 "5VSB",
2521                 "Vbat",
2522                 "AVCC",
2523         };
2524         static const char * const labels_it8721[] = {
2525                 "+3.3V",
2526                 "3VSB",
2527                 "Vbat",
2528                 "+3.3V",
2529         };
2530         struct it87_data *data = dev_get_drvdata(dev);
2531         int nr = to_sensor_dev_attr(attr)->index;
2532         const char *label;
2533
2534         if (has_vin3_5v(data) && nr == 0)
2535                 label = labels[0];
2536         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2537                  has_11mv_adc(data))
2538                 label = labels_it8721[nr];
2539         else
2540                 label = labels[nr];
2541
2542         return sprintf(buf, "%s\n", label);
2543 }
2544 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2545 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2546 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2547 /* AVCC3 */
2548 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2549
2550 static umode_t it87_in_is_visible(struct kobject *kobj,
2551                                   struct attribute *attr, int index)
2552 {
2553         struct device *dev = container_of(kobj, struct device, kobj);
2554         struct it87_data *data = dev_get_drvdata(dev);
2555         int i = index / 5;      /* voltage index */
2556         int a = index % 5;      /* attribute index */
2557
2558         if (index >= 40) {      /* in8 and higher only have input attributes */
2559                 i = index - 40 + 8;
2560                 a = 0;
2561         }
2562
2563         if (!(data->has_in & BIT(i)))
2564                 return 0;
2565
2566         if (a == 4 && !data->has_beep)
2567                 return 0;
2568
2569         return attr->mode;
2570 }
2571
2572 static struct attribute *it87_attributes_in[] = {
2573         &sensor_dev_attr_in0_input.dev_attr.attr,
2574         &sensor_dev_attr_in0_min.dev_attr.attr,
2575         &sensor_dev_attr_in0_max.dev_attr.attr,
2576         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2577         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2578
2579         &sensor_dev_attr_in1_input.dev_attr.attr,
2580         &sensor_dev_attr_in1_min.dev_attr.attr,
2581         &sensor_dev_attr_in1_max.dev_attr.attr,
2582         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2583         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2584
2585         &sensor_dev_attr_in2_input.dev_attr.attr,
2586         &sensor_dev_attr_in2_min.dev_attr.attr,
2587         &sensor_dev_attr_in2_max.dev_attr.attr,
2588         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2589         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2590
2591         &sensor_dev_attr_in3_input.dev_attr.attr,
2592         &sensor_dev_attr_in3_min.dev_attr.attr,
2593         &sensor_dev_attr_in3_max.dev_attr.attr,
2594         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2595         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2596
2597         &sensor_dev_attr_in4_input.dev_attr.attr,
2598         &sensor_dev_attr_in4_min.dev_attr.attr,
2599         &sensor_dev_attr_in4_max.dev_attr.attr,
2600         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2601         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2602
2603         &sensor_dev_attr_in5_input.dev_attr.attr,
2604         &sensor_dev_attr_in5_min.dev_attr.attr,
2605         &sensor_dev_attr_in5_max.dev_attr.attr,
2606         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2607         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2608
2609         &sensor_dev_attr_in6_input.dev_attr.attr,
2610         &sensor_dev_attr_in6_min.dev_attr.attr,
2611         &sensor_dev_attr_in6_max.dev_attr.attr,
2612         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2613         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2614
2615         &sensor_dev_attr_in7_input.dev_attr.attr,
2616         &sensor_dev_attr_in7_min.dev_attr.attr,
2617         &sensor_dev_attr_in7_max.dev_attr.attr,
2618         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2619         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2620
2621         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2622         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2623         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2624         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2625         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2626         NULL
2627 };
2628
2629 static const struct attribute_group it87_group_in = {
2630         .attrs = it87_attributes_in,
2631         .is_visible = it87_in_is_visible,
2632 };
2633
2634 static umode_t it87_temp_is_visible(struct kobject *kobj,
2635                                     struct attribute *attr, int index)
2636 {
2637         struct device *dev = container_of(kobj, struct device, kobj);
2638         struct it87_data *data = dev_get_drvdata(dev);
2639         int i = index / 7;      /* temperature index */
2640         int a = index % 7;      /* attribute index */
2641
2642         if (!(data->has_temp & BIT(i)))
2643                 return 0;
2644
2645         if (a && i >= data->num_temp_limit)
2646                 return 0;
2647
2648         if (a == 3) {
2649                 int type = get_temp_type(data, i);
2650
2651                 if (type == 0)
2652                         return 0;
2653                 if (has_bank_sel(data))
2654                         return 0444;
2655                 return attr->mode;
2656         }
2657
2658         if (a == 5 && i >= data->num_temp_offset)
2659                 return 0;
2660
2661         if (a == 6 && !data->has_beep)
2662                 return 0;
2663
2664         return attr->mode;
2665 }
2666
2667 static struct attribute *it87_attributes_temp[] = {
2668         &sensor_dev_attr_temp1_input.dev_attr.attr,
2669         &sensor_dev_attr_temp1_max.dev_attr.attr,
2670         &sensor_dev_attr_temp1_min.dev_attr.attr,
2671         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2672         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2673         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2674         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2675
2676         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2677         &sensor_dev_attr_temp2_max.dev_attr.attr,
2678         &sensor_dev_attr_temp2_min.dev_attr.attr,
2679         &sensor_dev_attr_temp2_type.dev_attr.attr,
2680         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2681         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2682         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2683
2684         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2685         &sensor_dev_attr_temp3_max.dev_attr.attr,
2686         &sensor_dev_attr_temp3_min.dev_attr.attr,
2687         &sensor_dev_attr_temp3_type.dev_attr.attr,
2688         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2689         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2690         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2691
2692         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2693         &sensor_dev_attr_temp4_max.dev_attr.attr,
2694         &sensor_dev_attr_temp4_min.dev_attr.attr,
2695         &sensor_dev_attr_temp4_type.dev_attr.attr,
2696         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2697         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2698         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2699
2700         &sensor_dev_attr_temp5_input.dev_attr.attr,
2701         &sensor_dev_attr_temp5_max.dev_attr.attr,
2702         &sensor_dev_attr_temp5_min.dev_attr.attr,
2703         &sensor_dev_attr_temp5_type.dev_attr.attr,
2704         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2705         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2706         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2707
2708         &sensor_dev_attr_temp6_input.dev_attr.attr,
2709         &sensor_dev_attr_temp6_max.dev_attr.attr,
2710         &sensor_dev_attr_temp6_min.dev_attr.attr,
2711         &sensor_dev_attr_temp6_type.dev_attr.attr,
2712         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2713         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2714         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2715         NULL
2716 };
2717
2718 static const struct attribute_group it87_group_temp = {
2719         .attrs = it87_attributes_temp,
2720         .is_visible = it87_temp_is_visible,
2721 };
2722
2723 static umode_t it87_is_visible(struct kobject *kobj,
2724                                struct attribute *attr, int index)
2725 {
2726         struct device *dev = container_of(kobj, struct device, kobj);
2727         struct it87_data *data = dev_get_drvdata(dev);
2728
2729         if ((index == 2 || index == 3) && !data->has_vid)
2730                 return 0;
2731
2732         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2733                 return 0;
2734
2735         return attr->mode;
2736 }
2737
2738 static struct attribute *it87_attributes[] = {
2739         &dev_attr_alarms.attr,
2740         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2741         &dev_attr_vrm.attr,                             /* 2 */
2742         &dev_attr_cpu0_vid.attr,                        /* 3 */
2743         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2744         &sensor_dev_attr_in7_label.dev_attr.attr,
2745         &sensor_dev_attr_in8_label.dev_attr.attr,
2746         &sensor_dev_attr_in9_label.dev_attr.attr,
2747         NULL
2748 };
2749
2750 static const struct attribute_group it87_group = {
2751         .attrs = it87_attributes,
2752         .is_visible = it87_is_visible,
2753 };
2754
2755 static umode_t it87_fan_is_visible(struct kobject *kobj,
2756                                    struct attribute *attr, int index)
2757 {
2758         struct device *dev = container_of(kobj, struct device, kobj);
2759         struct it87_data *data = dev_get_drvdata(dev);
2760         int i = index / 5;      /* fan index */
2761         int a = index % 5;      /* attribute index */
2762
2763         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2764                 i = (index - 15) / 4 + 3;
2765                 a = (index - 15) % 4;
2766         }
2767
2768         if (!(data->has_fan & BIT(i)))
2769                 return 0;
2770
2771         if (a == 3) {                           /* beep */
2772                 if (!data->has_beep)
2773                         return 0;
2774                 /* first fan beep attribute is writable */
2775                 if (i == __ffs(data->has_fan))
2776                         return attr->mode | S_IWUSR;
2777         }
2778
2779         if (a == 4 && has_16bit_fans(data))     /* divisor */
2780                 return 0;
2781
2782         return attr->mode;
2783 }
2784
2785 static struct attribute *it87_attributes_fan[] = {
2786         &sensor_dev_attr_fan1_input.dev_attr.attr,
2787         &sensor_dev_attr_fan1_min.dev_attr.attr,
2788         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2789         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2790         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2791
2792         &sensor_dev_attr_fan2_input.dev_attr.attr,
2793         &sensor_dev_attr_fan2_min.dev_attr.attr,
2794         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2795         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2796         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2797
2798         &sensor_dev_attr_fan3_input.dev_attr.attr,
2799         &sensor_dev_attr_fan3_min.dev_attr.attr,
2800         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2801         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2802         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2803
2804         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2805         &sensor_dev_attr_fan4_min.dev_attr.attr,
2806         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2807         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2808
2809         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2810         &sensor_dev_attr_fan5_min.dev_attr.attr,
2811         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2812         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2813
2814         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2815         &sensor_dev_attr_fan6_min.dev_attr.attr,
2816         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2817         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2818         NULL
2819 };
2820
2821 static const struct attribute_group it87_group_fan = {
2822         .attrs = it87_attributes_fan,
2823         .is_visible = it87_fan_is_visible,
2824 };
2825
2826 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2827                                    struct attribute *attr, int index)
2828 {
2829         struct device *dev = container_of(kobj, struct device, kobj);
2830         struct it87_data *data = dev_get_drvdata(dev);
2831         int i = index / 4;      /* pwm index */
2832         int a = index % 4;      /* attribute index */
2833
2834         if (!(data->has_pwm & BIT(i)))
2835                 return 0;
2836
2837         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2838         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2839                 return attr->mode | S_IWUSR;
2840
2841         /* pwm2_freq is writable if there are two pwm frequency selects */
2842         if (has_pwm_freq2(data) && i == 1 && a == 2)
2843                 return attr->mode | S_IWUSR;
2844
2845         return attr->mode;
2846 }
2847
2848 static struct attribute *it87_attributes_pwm[] = {
2849         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2850         &sensor_dev_attr_pwm1.dev_attr.attr,
2851         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2852         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2853
2854         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2855         &sensor_dev_attr_pwm2.dev_attr.attr,
2856         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2857         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2858
2859         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2860         &sensor_dev_attr_pwm3.dev_attr.attr,
2861         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2862         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2863
2864         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2865         &sensor_dev_attr_pwm4.dev_attr.attr,
2866         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2867         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2868
2869         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2870         &sensor_dev_attr_pwm5.dev_attr.attr,
2871         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2872         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2873
2874         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2875         &sensor_dev_attr_pwm6.dev_attr.attr,
2876         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2877         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2878
2879         NULL
2880 };
2881
2882 static const struct attribute_group it87_group_pwm = {
2883         .attrs = it87_attributes_pwm,
2884         .is_visible = it87_pwm_is_visible,
2885 };
2886
2887 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2888                                         struct attribute *attr, int index)
2889 {
2890         struct device *dev = container_of(kobj, struct device, kobj);
2891         struct it87_data *data = dev_get_drvdata(dev);
2892         int i = index / 11;     /* pwm index */
2893         int a = index % 11;     /* attribute index */
2894
2895         if (index >= 33) {      /* pwm 4..6 */
2896                 i = (index - 33) / 6 + 3;
2897                 a = (index - 33) % 6 + 4;
2898         }
2899
2900         if (!(data->has_pwm & BIT(i)))
2901                 return 0;
2902
2903         if (has_newer_autopwm(data)) {
2904                 if (a < 4)      /* no auto point pwm */
2905                         return 0;
2906                 if (a == 8)     /* no auto_point4 */
2907                         return 0;
2908         }
2909         if (has_old_autopwm(data)) {
2910                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2911                         return 0;
2912         }
2913
2914         return attr->mode;
2915 }
2916
2917 static struct attribute *it87_attributes_auto_pwm[] = {
2918         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2919         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2920         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2921         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2922         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2923         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2924         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2925         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2926         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2927         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2928         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2929
2930         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2931         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2932         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2933         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2934         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2935         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2936         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2937         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2938         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2939         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2940         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2941
2942         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2943         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2944         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2945         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2946         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2947         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2948         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2949         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2950         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2951         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2952         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2953
2954         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2955         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2956         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2957         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2958         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2959         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2960
2961         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2962         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2963         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2964         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2965         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2966         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2967
2968         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2969         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2970         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2971         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2972         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2973         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2974
2975         NULL,
2976 };
2977
2978 static const struct attribute_group it87_group_auto_pwm = {
2979         .attrs = it87_attributes_auto_pwm,
2980         .is_visible = it87_auto_pwm_is_visible,
2981 };
2982
2983 /* SuperIO detection - will change isa_address if a chip is found */
2984 static int __init it87_find(int sioaddr, unsigned short *address,
2985                             phys_addr_t *mmio_address, struct it87_sio_data *sio_data)
2986 {
2987         const struct it87_devices *config;
2988         phys_addr_t base = 0;
2989         bool doexit = true;
2990         char mmio_str[32];
2991         u16 chip_type;
2992         int err;
2993
2994         err = superio_enter(sioaddr);
2995         if (err)
2996                 return err;
2997
2998         sio_data->sioaddr = sioaddr;
2999
3000         err = -ENODEV;
3001         chip_type = superio_inw(sioaddr, DEVID);
3002         if (chip_type == 0xffff)
3003                 goto exit;
3004
3005         if (force_id)
3006                 chip_type = force_id;
3007
3008         switch (chip_type) {
3009         case IT8705F_DEVID:
3010                 sio_data->type = it87;
3011                 break;
3012         case IT8712F_DEVID:
3013                 sio_data->type = it8712;
3014                 break;
3015         case IT8716F_DEVID:
3016         case IT8726F_DEVID:
3017                 sio_data->type = it8716;
3018                 break;
3019         case IT8718F_DEVID:
3020                 sio_data->type = it8718;
3021                 break;
3022         case IT8720F_DEVID:
3023                 sio_data->type = it8720;
3024                 break;
3025         case IT8721F_DEVID:
3026                 sio_data->type = it8721;
3027                 break;
3028         case IT8728F_DEVID:
3029                 sio_data->type = it8728;
3030                 break;
3031         case IT8732F_DEVID:
3032                 sio_data->type = it8732;
3033                 break;
3034         case IT8792E_DEVID:
3035                 sio_data->type = it8792;
3036                 /*
3037                  * Disabling configuration mode on IT8792E can result in system
3038                  * hang-ups and access failures to the Super-IO chip at the
3039                  * second SIO address. Never exit configuration mode on this
3040                  * chip to avoid the problem.
3041                  */
3042                 doexit = false;
3043                 break;
3044         case IT8771E_DEVID:
3045                 sio_data->type = it8771;
3046                 break;
3047         case IT8772E_DEVID:
3048                 sio_data->type = it8772;
3049                 break;
3050         case IT8781F_DEVID:
3051                 sio_data->type = it8781;
3052                 break;
3053         case IT8782F_DEVID:
3054                 sio_data->type = it8782;
3055                 break;
3056         case IT8783E_DEVID:
3057                 sio_data->type = it8783;
3058                 break;
3059         case IT8786E_DEVID:
3060                 sio_data->type = it8786;
3061                 break;
3062         case IT8790E_DEVID:
3063                 sio_data->type = it8790;
3064                 doexit = false;         /* See IT8792E comment above */
3065                 break;
3066         case IT8603E_DEVID:
3067         case IT8623E_DEVID:
3068                 sio_data->type = it8603;
3069                 break;
3070         case IT8607E_DEVID:
3071                 sio_data->type = it8607;
3072                 break;
3073         case IT8613E_DEVID:
3074                 sio_data->type = it8613;
3075                 break;
3076         case IT8620E_DEVID:
3077                 sio_data->type = it8620;
3078                 break;
3079         case IT8622E_DEVID:
3080                 sio_data->type = it8622;
3081                 break;
3082         case IT8625E_DEVID:
3083                 sio_data->type = it8625;
3084                 break;
3085         case IT8628E_DEVID:
3086                 sio_data->type = it8628;
3087                 break;
3088         case IT8655E_DEVID:
3089                 sio_data->type = it8655;
3090                 break;
3091         case IT8665E_DEVID:
3092                 sio_data->type = it8665;
3093                 break;
3094         case IT8686E_DEVID:
3095                 sio_data->type = it8686;
3096                 break;
3097         case 0xffff:    /* No device at all */
3098                 goto exit;
3099         default:
3100                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3101                 goto exit;
3102         }
3103
3104         superio_select(sioaddr, PME);
3105         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3106                 pr_info("Device not activated, skipping\n");
3107                 goto exit;
3108         }
3109
3110         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3111         if (*address == 0) {
3112                 pr_info("Base address not set, skipping\n");
3113                 goto exit;
3114         }
3115
3116         sio_data->doexit = doexit;
3117
3118         err = 0;
3119         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3120
3121         config = &it87_devices[sio_data->type];
3122
3123         if (has_mmio(config) && mmio) {
3124                 u8 reg;
3125
3126                 reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
3127                 if (reg & BIT(5)) {
3128                         base = 0xf0000000 + ((reg & 0x0f) << 24);
3129                         base += (reg & 0xc0) << 14;
3130                 }
3131         }
3132         *mmio_address = base;
3133
3134         mmio_str[0] = '\0';
3135         if (base)
3136                 snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
3137
3138         pr_info("Found IT%04x%s chip at 0x%x%s, revision %d\n", chip_type,
3139                 it87_devices[sio_data->type].suffix,
3140                 *address, mmio_str, sio_data->revision);
3141
3142         /* in7 (VSB or VCCH5V) is always internal on some chips */
3143         if (has_in7_internal(config))
3144                 sio_data->internal |= BIT(1);
3145
3146         /* in8 (Vbat) is always internal */
3147         sio_data->internal |= BIT(2);
3148
3149         /* in9 (AVCC3), always internal if supported */
3150         if (has_avcc3(config))
3151                 sio_data->internal |= BIT(3); /* in9 is AVCC */
3152         else
3153                 sio_data->skip_in |= BIT(9);
3154
3155         if (!has_four_pwm(config))
3156                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3157         else if (!has_five_pwm(config))
3158                 sio_data->skip_pwm |= BIT(4) | BIT(5);
3159         else if (!has_six_pwm(config))
3160                 sio_data->skip_pwm |= BIT(5);
3161
3162         if (!has_vid(config))
3163                 sio_data->skip_vid = 1;
3164
3165         /* Read GPIO config and VID value from LDN 7 (GPIO) */
3166         if (sio_data->type == it87) {
3167                 /* The IT8705F has a different LD number for GPIO */
3168                 superio_select(sioaddr, 5);
3169                 sio_data->beep_pin = superio_inb(sioaddr,
3170                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3171         } else if (sio_data->type == it8783) {
3172                 int reg25, reg27, reg2a, reg2c, regef;
3173
3174                 superio_select(sioaddr, GPIO);
3175
3176                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3177                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3178                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3179                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3180                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3181
3182                 /* Check if fan3 is there or not */
3183                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3184                         sio_data->skip_fan |= BIT(2);
3185                 if ((reg25 & BIT(4)) ||
3186                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
3187                         sio_data->skip_pwm |= BIT(2);
3188
3189                 /* Check if fan2 is there or not */
3190                 if (reg27 & BIT(7))
3191                         sio_data->skip_fan |= BIT(1);
3192                 if (reg27 & BIT(3))
3193                         sio_data->skip_pwm |= BIT(1);
3194
3195                 /* VIN5 */
3196                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3197                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3198
3199                 /* VIN6 */
3200                 if (reg27 & BIT(1))
3201                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3202
3203                 /*
3204                  * VIN7
3205                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3206                  */
3207                 if (reg27 & BIT(2)) {
3208                         /*
3209                          * The data sheet is a bit unclear regarding the
3210                          * internal voltage divider for VCCH5V. It says
3211                          * "This bit enables and switches VIN7 (pin 91) to the
3212                          * internal voltage divider for VCCH5V".
3213                          * This is different to other chips, where the internal
3214                          * voltage divider would connect VIN7 to an internal
3215                          * voltage source. Maybe that is the case here as well.
3216                          *
3217                          * Since we don't know for sure, re-route it if that is
3218                          * not the case, and ask the user to report if the
3219                          * resulting voltage is sane.
3220                          */
3221                         if (!(reg2c & BIT(1))) {
3222                                 reg2c |= BIT(1);
3223                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3224                                              reg2c);
3225                                 pr_notice("Routing internal VCCH5V to in7.\n");
3226                         }
3227                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3228                         pr_notice("Please report if it displays a reasonable voltage.\n");
3229                 }
3230
3231                 if (reg2c & BIT(0))
3232                         sio_data->internal |= BIT(0);
3233                 if (reg2c & BIT(1))
3234                         sio_data->internal |= BIT(1);
3235
3236                 sio_data->beep_pin = superio_inb(sioaddr,
3237                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3238         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3239                 int reg27, reg29;
3240
3241                 superio_select(sioaddr, GPIO);
3242
3243                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3244
3245                 /* Check if fan3 is there or not */
3246                 if (reg27 & BIT(6))
3247                         sio_data->skip_pwm |= BIT(2);
3248                 if (reg27 & BIT(7))
3249                         sio_data->skip_fan |= BIT(2);
3250
3251                 /* Check if fan2 is there or not */
3252                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3253                 if (reg29 & BIT(1))
3254                         sio_data->skip_pwm |= BIT(1);
3255                 if (reg29 & BIT(2))
3256                         sio_data->skip_fan |= BIT(1);
3257
3258                 switch (sio_data->type) {
3259                 case it8603:
3260                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3261                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3262                         break;
3263                 case it8607:
3264                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3265                         sio_data->skip_fan |= BIT(0);
3266                 default:
3267                         break;
3268                 }
3269
3270                 sio_data->beep_pin = superio_inb(sioaddr,
3271                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3272         } else if (sio_data->type == it8613) {
3273                 int reg27, reg29, reg2a;
3274
3275                 superio_select(sioaddr, GPIO);
3276
3277                 /* Check for pwm3, fan3, pwm5, fan5 */
3278                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3279                 if (reg27 & BIT(1))
3280                         sio_data->skip_fan |= BIT(4);
3281                 if (reg27 & BIT(3))
3282                         sio_data->skip_pwm |= BIT(4);
3283                 if (reg27 & BIT(6))
3284                         sio_data->skip_pwm |= BIT(2);
3285                 if (reg27 & BIT(7))
3286                         sio_data->skip_fan |= BIT(2);
3287
3288                 /* Check for pwm2, fan2 */
3289                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3290                 if (reg29 & BIT(1))
3291                         sio_data->skip_pwm |= BIT(1);
3292                 if (reg29 & BIT(2))
3293                         sio_data->skip_fan |= BIT(1);
3294
3295                 /* Check for pwm4, fan4 */
3296                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3297                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3298                         sio_data->skip_fan |= BIT(3);
3299                         sio_data->skip_pwm |= BIT(3);
3300                 }
3301
3302                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3303                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3304                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3305                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3306
3307                 sio_data->beep_pin = superio_inb(sioaddr,
3308                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3309         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3310                    sio_data->type == it8686) {
3311                 int reg;
3312
3313                 superio_select(sioaddr, GPIO);
3314
3315                 /* Check for pwm5 */
3316                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3317                 if (reg & BIT(6))
3318                         sio_data->skip_pwm |= BIT(4);
3319
3320                 /* Check for fan4, fan5 */
3321                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3322                 if (!(reg & BIT(5)))
3323                         sio_data->skip_fan |= BIT(3);
3324                 if (!(reg & BIT(4)))
3325                         sio_data->skip_fan |= BIT(4);
3326
3327                 /* Check for pwm3, fan3 */
3328                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3329                 if (reg & BIT(6))
3330                         sio_data->skip_pwm |= BIT(2);
3331                 if (reg & BIT(7))
3332                         sio_data->skip_fan |= BIT(2);
3333
3334                 /* Check for pwm4 */
3335                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3336                 if (reg & BIT(2))
3337                         sio_data->skip_pwm |= BIT(3);
3338
3339                 /* Check for pwm2, fan2 */
3340                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3341                 if (reg & BIT(1))
3342                         sio_data->skip_pwm |= BIT(1);
3343                 if (reg & BIT(2))
3344                         sio_data->skip_fan |= BIT(1);
3345                 /* Check for pwm6, fan6 */
3346                 if (!(reg & BIT(7))) {
3347                         sio_data->skip_pwm |= BIT(5);
3348                         sio_data->skip_fan |= BIT(5);
3349                 }
3350
3351                 /* Check if AVCC is on VIN3 */
3352                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3353                 if (reg & BIT(0)) {
3354                         /* For it8686, the bit just enables AVCC3 */
3355                         if (sio_data->type != it8686)
3356                                 sio_data->internal |= BIT(0);
3357                 } else {
3358                         sio_data->internal &= ~BIT(3);
3359                         sio_data->skip_in |= BIT(9);
3360                 }
3361
3362                 sio_data->beep_pin = superio_inb(sioaddr,
3363                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3364         } else if (sio_data->type == it8622) {
3365                 int reg;
3366
3367                 superio_select(sioaddr, GPIO);
3368
3369                 /* Check for pwm4, fan4 */
3370                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3371                 if (reg & BIT(6))
3372                         sio_data->skip_fan |= BIT(3);
3373                 if (reg & BIT(5))
3374                         sio_data->skip_pwm |= BIT(3);
3375
3376                 /* Check for pwm3, fan3, pwm5, fan5 */
3377                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3378                 if (reg & BIT(6))
3379                         sio_data->skip_pwm |= BIT(2);
3380                 if (reg & BIT(7))
3381                         sio_data->skip_fan |= BIT(2);
3382                 if (reg & BIT(3))
3383                         sio_data->skip_pwm |= BIT(4);
3384                 if (reg & BIT(1))
3385                         sio_data->skip_fan |= BIT(4);
3386
3387                 /* Check for pwm2, fan2 */
3388                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3389                 if (reg & BIT(1))
3390                         sio_data->skip_pwm |= BIT(1);
3391                 if (reg & BIT(2))
3392                         sio_data->skip_fan |= BIT(1);
3393
3394                 /* Check for AVCC */
3395                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3396                 if (!(reg & BIT(0)))
3397                         sio_data->skip_in |= BIT(9);
3398
3399                 sio_data->beep_pin = superio_inb(sioaddr,
3400                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3401         } else if (sio_data->type == it8732) {
3402                 int reg;
3403
3404                 superio_select(sioaddr, GPIO);
3405
3406                 /* Check for pwm2, fan2 */
3407                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3408                 if (reg & BIT(1))
3409                         sio_data->skip_pwm |= BIT(1);
3410                 if (reg & BIT(2))
3411                         sio_data->skip_fan |= BIT(1);
3412
3413                 /* Check for pwm3, fan3, fan4 */
3414                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3415                 if (reg & BIT(6))
3416                         sio_data->skip_pwm |= BIT(2);
3417                 if (reg & BIT(7))
3418                         sio_data->skip_fan |= BIT(2);
3419                 if (reg & BIT(5))
3420                         sio_data->skip_fan |= BIT(3);
3421
3422                 /* Check if AVCC is on VIN3 */
3423                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3424                 if (reg & BIT(0))
3425                         sio_data->internal |= BIT(0);
3426
3427                 sio_data->beep_pin = superio_inb(sioaddr,
3428                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3429         } else if (sio_data->type == it8655) {
3430                 int reg;
3431
3432                 superio_select(sioaddr, GPIO);
3433
3434                 /* Check for pwm2 */
3435                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3436                 if (reg & BIT(1))
3437                         sio_data->skip_pwm |= BIT(1);
3438
3439                 /* Check for fan2 */
3440                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3441                 if (reg & BIT(4))
3442                         sio_data->skip_fan |= BIT(1);
3443
3444                 /* Check for pwm3, fan3 */
3445                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3446                 if (reg & BIT(6))
3447                         sio_data->skip_pwm |= BIT(2);
3448                 if (reg & BIT(7))
3449                         sio_data->skip_fan |= BIT(2);
3450
3451                 sio_data->beep_pin = superio_inb(sioaddr,
3452                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3453         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3454                 int reg27, reg29, reg2d, regd3;
3455
3456                 superio_select(sioaddr, GPIO);
3457
3458                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3459                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3460                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3461                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3462
3463                 /* Check for pwm2, fan2 */
3464                 if (reg29 & BIT(1))
3465                         sio_data->skip_pwm |= BIT(1);
3466                 /*
3467                  * Note: Table 6-1 in datasheet claims that FAN_TAC2
3468                  * would be enabled with 29h[2]=0.
3469                  */
3470                 if (reg2d & BIT(4))
3471                         sio_data->skip_fan |= BIT(1);
3472
3473                 /* Check for pwm3, fan3 */
3474                 if (reg27 & BIT(6))
3475                         sio_data->skip_pwm |= BIT(2);
3476                 if (reg27 & BIT(7))
3477                         sio_data->skip_fan |= BIT(2);
3478
3479                 /* Check for pwm4, fan4, pwm5, fan5 */
3480                 if (sio_data->type == it8625) {
3481                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3482
3483                         if (reg25 & BIT(6))
3484                                 sio_data->skip_fan |= BIT(3);
3485                         if (reg25 & BIT(5))
3486                                 sio_data->skip_pwm |= BIT(3);
3487                         if (reg27 & BIT(3))
3488                                 sio_data->skip_pwm |= BIT(4);
3489                         if (reg27 & BIT(1))
3490                                 sio_data->skip_fan |= BIT(4);
3491                 } else {
3492                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3493
3494                         if (regd3 & BIT(2))
3495                                 sio_data->skip_pwm |= BIT(3);
3496                         if (regd3 & BIT(3))
3497                                 sio_data->skip_fan |= BIT(3);
3498                         if (reg26 & BIT(5))
3499                                 sio_data->skip_pwm |= BIT(4);
3500                         if (reg26 & BIT(4))
3501                                 sio_data->skip_fan |= BIT(4);
3502                 }
3503
3504                 /* Check for pwm6, fan6 */
3505                 if (regd3 & BIT(0))
3506                         sio_data->skip_pwm |= BIT(5);
3507                 if (regd3 & BIT(1))
3508                         sio_data->skip_fan |= BIT(5);
3509
3510                 sio_data->beep_pin = superio_inb(sioaddr,
3511                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3512         } else {
3513                 int reg;
3514                 bool uart6;
3515
3516                 superio_select(sioaddr, GPIO);
3517
3518                 /* Check for fan4, fan5 */
3519                 if (has_five_fans(config)) {
3520                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3521                         switch (sio_data->type) {
3522                         case it8718:
3523                                 if (reg & BIT(5))
3524                                         sio_data->skip_fan |= BIT(3);
3525                                 if (reg & BIT(4))
3526                                         sio_data->skip_fan |= BIT(4);
3527                                 break;
3528                         case it8720:
3529                         case it8721:
3530                         case it8728:
3531                                 if (!(reg & BIT(5)))
3532                                         sio_data->skip_fan |= BIT(3);
3533                                 if (!(reg & BIT(4)))
3534                                         sio_data->skip_fan |= BIT(4);
3535                                 break;
3536                         default:
3537                                 break;
3538                         }
3539                 }
3540
3541                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3542                 if (!sio_data->skip_vid) {
3543                         /* We need at least 4 VID pins */
3544                         if (reg & 0x0f) {
3545                                 pr_info("VID is disabled (pins used for GPIO)\n");
3546                                 sio_data->skip_vid = 1;
3547                         }
3548                 }
3549
3550                 /* Check if fan3 is there or not */
3551                 if (reg & BIT(6))
3552                         sio_data->skip_pwm |= BIT(2);
3553                 if (reg & BIT(7))
3554                         sio_data->skip_fan |= BIT(2);
3555
3556                 /* Check if fan2 is there or not */
3557                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3558                 if (reg & BIT(1))
3559                         sio_data->skip_pwm |= BIT(1);
3560                 if (reg & BIT(2))
3561                         sio_data->skip_fan |= BIT(1);
3562
3563                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3564                     !(sio_data->skip_vid))
3565                         sio_data->vid_value = superio_inb(sioaddr,
3566                                                           IT87_SIO_VID_REG);
3567
3568                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3569
3570                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3571
3572                 /*
3573                  * The IT8720F has no VIN7 pin, so VCCH should always be
3574                  * routed internally to VIN7 with an internal divider.
3575                  * Curiously, there still is a configuration bit to control
3576                  * this, which means it can be set incorrectly. And even
3577                  * more curiously, many boards out there are improperly
3578                  * configured, even though the IT8720F datasheet claims
3579                  * that the internal routing of VCCH to VIN7 is the default
3580                  * setting. So we force the internal routing in this case.
3581                  *
3582                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3583                  * If UART6 is enabled, re-route VIN7 to the internal divider
3584                  * if that is not already the case.
3585                  */
3586                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3587                         reg |= BIT(1);
3588                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3589                         pr_notice("Routing internal VCCH to in7\n");
3590                 }
3591                 if (reg & BIT(0))
3592                         sio_data->internal |= BIT(0);
3593                 if (reg & BIT(1))
3594                         sio_data->internal |= BIT(1);
3595
3596                 /*
3597                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3598                  * While VIN7 can be routed to the internal voltage divider,
3599                  * VIN5 and VIN6 are not available if UART6 is enabled.
3600                  *
3601                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3602                  * is the temperature source. Since we can not read the
3603                  * temperature source here, skip_temp is preliminary.
3604                  */
3605                 if (uart6) {
3606                         sio_data->skip_in |= BIT(5) | BIT(6);
3607                         sio_data->skip_temp |= BIT(2);
3608                 }
3609
3610                 sio_data->beep_pin = superio_inb(sioaddr,
3611                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3612         }
3613         if (sio_data->beep_pin)
3614                 pr_info("Beeping is supported\n");
3615
3616         if (config->smbus_bitmap && !base) {
3617                 u8 reg;
3618
3619                 superio_select(sioaddr, PME);
3620                 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3621                 sio_data->ec_special_config = reg;
3622                 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3623         }
3624
3625 exit:
3626         superio_exit(sioaddr, doexit);
3627         return err;
3628 }
3629
3630 static void it87_init_regs(struct platform_device *pdev)
3631 {
3632         struct it87_data *data = platform_get_drvdata(pdev);
3633
3634         /* Initialize chip specific register pointers */
3635         switch (data->type) {
3636         case it8628:
3637         case it8686:
3638                 data->REG_FAN = IT87_REG_FAN;
3639                 data->REG_FANX = IT87_REG_FANX;
3640                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3641                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3642                 data->REG_PWM = IT87_REG_PWM;
3643                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3644                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3645                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3646                 break;
3647         case it8625:
3648         case it8655:
3649         case it8665:
3650                 data->REG_FAN = IT87_REG_FAN_8665;
3651                 data->REG_FANX = IT87_REG_FANX_8665;
3652                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3653                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3654                 data->REG_PWM = IT87_REG_PWM_8665;
3655                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3656                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3657                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3658                 break;
3659         case it8622:
3660                 data->REG_FAN = IT87_REG_FAN;
3661                 data->REG_FANX = IT87_REG_FANX;
3662                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3663                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3664                 data->REG_PWM = IT87_REG_PWM_8665;
3665                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3666                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3667                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3668                 break;
3669         case it8613:
3670                 data->REG_FAN = IT87_REG_FAN;
3671                 data->REG_FANX = IT87_REG_FANX;
3672                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3673                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3674                 data->REG_PWM = IT87_REG_PWM_8665;
3675                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3676                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3677                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3678                 break;
3679         default:
3680                 data->REG_FAN = IT87_REG_FAN;
3681                 data->REG_FANX = IT87_REG_FANX;
3682                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3683                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3684                 data->REG_PWM = IT87_REG_PWM;
3685                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3686                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3687                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3688                 break;
3689         }
3690
3691         if (data->mmio) {
3692                 data->read = it87_mmio_read;
3693                 data->write = it87_mmio_write;
3694         } else if (has_bank_sel(data)) {
3695                 data->read = it87_io_read;
3696                 data->write = it87_io_write;
3697         } else {
3698                 data->read = _it87_io_read;
3699                 data->write = _it87_io_write;
3700         }
3701 }
3702
3703 /* Called when we have found a new IT87. */
3704 static void it87_init_device(struct platform_device *pdev)
3705 {
3706         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3707         struct it87_data *data = platform_get_drvdata(pdev);
3708         int tmp, i;
3709         u8 mask;
3710
3711         if (has_new_tempmap(data)) {
3712                 data->pwm_temp_map_shift = 3;
3713                 data->pwm_temp_map_mask = 0x07;
3714         } else {
3715                 data->pwm_temp_map_shift = 0;
3716                 data->pwm_temp_map_mask = 0x03;
3717         }
3718
3719         /*
3720          * For each PWM channel:
3721          * - If it is in automatic mode, setting to manual mode should set
3722          *   the fan to full speed by default.
3723          * - If it is in manual mode, we need a mapping to temperature
3724          *   channels to use when later setting to automatic mode later.
3725          *   Map to the first sensor by default (we are clueless.)
3726          * In both cases, the value can (and should) be changed by the user
3727          * prior to switching to a different mode.
3728          * Note that this is no longer needed for the IT8721F and later, as
3729          * these have separate registers for the temperature mapping and the
3730          * manual duty cycle.
3731          */
3732         for (i = 0; i < NUM_AUTO_PWM; i++) {
3733                 data->pwm_temp_map[i] = 0;
3734                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3735                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3736         }
3737
3738         /*
3739          * Some chips seem to have default value 0xff for all limit
3740          * registers. For low voltage limits it makes no sense and triggers
3741          * alarms, so change to 0 instead. For high temperature limits, it
3742          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3743          * but is still confusing, so change to 127 degrees C.
3744          */
3745         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3746                 tmp = data->read(data, IT87_REG_VIN_MIN(i));
3747                 if (tmp == 0xff)
3748                         data->write(data, IT87_REG_VIN_MIN(i), 0);
3749         }
3750         for (i = 0; i < data->num_temp_limit; i++) {
3751                 tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3752                 if (tmp == 0xff)
3753                         data->write(data, data->REG_TEMP_HIGH[i], 127);
3754         }
3755
3756         /*
3757          * Temperature channels are not forcibly enabled, as they can be
3758          * set to two different sensor types and we can't guess which one
3759          * is correct for a given system. These channels can be enabled at
3760          * run-time through the temp{1-3}_type sysfs accessors if needed.
3761          */
3762
3763         /* Check if voltage monitors are reset manually or by some reason */
3764         tmp = data->read(data, IT87_REG_VIN_ENABLE);
3765         if ((tmp & 0xff) == 0) {
3766                 /* Enable all voltage monitors */
3767                 data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3768         }
3769
3770         /* Check if tachometers are reset manually or by some reason */
3771         mask = 0x70 & ~(sio_data->skip_fan << 4);
3772         data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3773         if ((data->fan_main_ctrl & mask) == 0) {
3774                 /* Enable all fan tachometers */
3775                 data->fan_main_ctrl |= mask;
3776                 data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3777         }
3778         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3779
3780         tmp = data->read(data, IT87_REG_FAN_16BIT);
3781
3782         /* Set tachometers to 16-bit mode if needed */
3783         if (has_fan16_config(data)) {
3784                 if (~tmp & 0x07 & data->has_fan) {
3785                         dev_dbg(&pdev->dev,
3786                                 "Setting fan1-3 to 16-bit mode\n");
3787                         data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3788                 }
3789         }
3790
3791         /* Check for additional fans */
3792         if (has_four_fans(data) && (tmp & BIT(4)))
3793                 data->has_fan |= BIT(3); /* fan4 enabled */
3794         if (has_five_fans(data) && (tmp & BIT(5)))
3795                 data->has_fan |= BIT(4); /* fan5 enabled */
3796         if (has_six_fans(data)) {
3797                 switch (data->type) {
3798                 case it8620:
3799                 case it8628:
3800                 case it8686:
3801                         if (tmp & BIT(2))
3802                                 data->has_fan |= BIT(5); /* fan6 enabled */
3803                         break;
3804                 case it8625:
3805                 case it8665:
3806                         tmp = data->read(data, IT87_REG_FAN_DIV);
3807                         if (tmp & BIT(3))
3808                                 data->has_fan |= BIT(5); /* fan6 enabled */
3809                         break;
3810                 default:
3811                         break;
3812                 }
3813         }
3814
3815         /* Fan input pins may be used for alternative functions */
3816         data->has_fan &= ~sio_data->skip_fan;
3817
3818         /* Check if pwm6 is enabled */
3819         if (has_six_pwm(data)) {
3820                 switch (data->type) {
3821                 case it8620:
3822                 case it8686:
3823                         tmp = data->read(data, IT87_REG_FAN_DIV);
3824                         if (!(tmp & BIT(3)))
3825                                 sio_data->skip_pwm |= BIT(5);
3826                         break;
3827                 default:
3828                         break;
3829                 }
3830         }
3831
3832         if (has_bank_sel(data)) {
3833                 for (i = 0; i < 3; i++)
3834                         data->temp_src[i] =
3835                                 data->read(data, IT87_REG_TEMP_SRC1[i]);
3836                 data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3837         }
3838
3839         /* Start monitoring */
3840         data->write(data, IT87_REG_CONFIG,
3841                     (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3842                                         (update_vbat ? 0x41 : 0x01));
3843 }
3844
3845 /* Return 1 if and only if the PWM interface is safe to use */
3846 static int it87_check_pwm(struct device *dev)
3847 {
3848         struct it87_data *data = dev_get_drvdata(dev);
3849         /*
3850          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3851          * and polarity set to active low is sign that this is the case so we
3852          * disable pwm control to protect the user.
3853          */
3854         int tmp = data->read(data, IT87_REG_FAN_CTL);
3855
3856         if ((tmp & 0x87) == 0) {
3857                 if (fix_pwm_polarity) {
3858                         /*
3859                          * The user asks us to attempt a chip reconfiguration.
3860                          * This means switching to active high polarity and
3861                          * inverting all fan speed values.
3862                          */
3863                         int i;
3864                         u8 pwm[3];
3865
3866                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3867                                 pwm[i] = data->read(data,
3868                                                          data->REG_PWM[i]);
3869
3870                         /*
3871                          * If any fan is in automatic pwm mode, the polarity
3872                          * might be correct, as suspicious as it seems, so we
3873                          * better don't change anything (but still disable the
3874                          * PWM interface).
3875                          */
3876                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3877                                 dev_info(dev,
3878                                          "Reconfiguring PWM to active high polarity\n");
3879                                 data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3880                                 for (i = 0; i < 3; i++)
3881                                         data->write(data, data->REG_PWM[i],
3882                                                     0x7f & ~pwm[i]);
3883                                 return 1;
3884                         }
3885
3886                         dev_info(dev,
3887                                  "PWM configuration is too broken to be fixed\n");
3888                 }
3889
3890                 dev_info(dev,
3891                          "Detected broken BIOS defaults, disabling PWM interface\n");
3892                 return 0;
3893         } else if (fix_pwm_polarity) {
3894                 dev_info(dev,
3895                          "PWM configuration looks sane, won't touch\n");
3896         }
3897
3898         return 1;
3899 }
3900
3901 static int it87_probe(struct platform_device *pdev)
3902 {
3903         struct it87_data *data;
3904         struct resource *res;
3905         struct device *dev = &pdev->dev;
3906         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3907         int enable_pwm_interface;
3908         struct device *hwmon_dev;
3909         int err;
3910
3911         data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3912         if (!data)
3913                 return -ENOMEM;
3914
3915         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3916         if (res) {
3917                 if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3918                                          DRVNAME)) {
3919                         dev_err(dev, "Failed to request region %pR\n", res);
3920                         return -EBUSY;
3921                 }
3922         } else {
3923                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3924                 data->mmio = devm_ioremap_resource(dev, res);
3925                 if (IS_ERR(data->mmio))
3926                         return PTR_ERR(data->mmio);
3927         }
3928
3929         data->addr = res->start;
3930         data->type = sio_data->type;
3931         data->sioaddr = sio_data->sioaddr;
3932         data->smbus_bitmap = sio_data->smbus_bitmap;
3933         data->ec_special_config = sio_data->ec_special_config;
3934         data->doexit = sio_data->doexit;
3935         data->features = it87_devices[sio_data->type].features;
3936         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3937         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3938         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3939         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3940         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3941
3942         /*
3943          * IT8705F Datasheet 0.4.1, 3h == Version G.
3944          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3945          * These are the first revisions with 16-bit tachometer support.
3946          */
3947         switch (data->type) {
3948         case it87:
3949                 if (sio_data->revision >= 0x03) {
3950                         data->features &= ~FEAT_OLD_AUTOPWM;
3951                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3952                 }
3953                 break;
3954         case it8712:
3955                 if (sio_data->revision >= 0x08) {
3956                         data->features &= ~FEAT_OLD_AUTOPWM;
3957                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3958                                           FEAT_FIVE_FANS;
3959                 }
3960                 break;
3961         default:
3962                 break;
3963         }
3964
3965         platform_set_drvdata(pdev, data);
3966
3967         mutex_init(&data->update_lock);
3968
3969         /* Initialize register pointers */
3970         it87_init_regs(pdev);
3971
3972         err = smbus_disable(data);
3973         if (err)
3974                 return err;
3975
3976         /* Now, we do the remaining detection. */
3977         if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
3978             data->read(data, IT87_REG_CHIPID) != 0x90) {
3979                 smbus_enable(data);
3980                 return -ENODEV;
3981         }
3982
3983         /* Check PWM configuration */
3984         enable_pwm_interface = it87_check_pwm(dev);
3985
3986         /* Starting with IT8721F, we handle scaling of internal voltages */
3987         if (has_scaling(data)) {
3988                 if (sio_data->internal & BIT(0))
3989                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3990                 if (sio_data->internal & BIT(1))
3991                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3992                 if (sio_data->internal & BIT(2))
3993                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3994                 if (sio_data->internal & BIT(3))
3995                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3996         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3997                    sio_data->type == it8783) {
3998                 if (sio_data->internal & BIT(0))
3999                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
4000                 if (sio_data->internal & BIT(1))
4001                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
4002         }
4003
4004         data->has_temp = 0x07;
4005         if (sio_data->skip_temp & BIT(2)) {
4006                 if (sio_data->type == it8782 &&
4007                     !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
4008                         data->has_temp &= ~BIT(2);
4009         }
4010
4011         data->in_internal = sio_data->internal;
4012         data->has_in = 0x3ff & ~sio_data->skip_in;
4013
4014         if (has_four_temp(data)) {
4015                 data->has_temp |= BIT(3);
4016         } else if (has_six_temp(data)) {
4017                 u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
4018
4019                 /* Check for additional temperature sensors */
4020                 if ((reg & 0x03) >= 0x02)
4021                         data->has_temp |= BIT(3);
4022                 if (((reg >> 2) & 0x03) >= 0x02)
4023                         data->has_temp |= BIT(4);
4024                 if (((reg >> 4) & 0x03) >= 0x02)
4025                         data->has_temp |= BIT(5);
4026
4027                 /* Check for additional voltage sensors */
4028                 if ((reg & 0x03) == 0x01)
4029                         data->has_in |= BIT(10);
4030                 if (((reg >> 2) & 0x03) == 0x01)
4031                         data->has_in |= BIT(11);
4032                 if (((reg >> 4) & 0x03) == 0x01)
4033                         data->has_in |= BIT(12);
4034         }
4035
4036         data->has_beep = !!sio_data->beep_pin;
4037
4038         /* Initialize the IT87 chip */
4039         it87_init_device(pdev);
4040
4041         smbus_enable(data);
4042
4043         if (!sio_data->skip_vid) {
4044                 data->has_vid = true;
4045                 data->vrm = vid_which_vrm();
4046                 /* VID reading from Super-I/O config space if available */
4047                 data->vid = sio_data->vid_value;
4048         }
4049
4050         /* Prepare for sysfs hooks */
4051         data->groups[0] = &it87_group;
4052         data->groups[1] = &it87_group_in;
4053         data->groups[2] = &it87_group_temp;
4054         data->groups[3] = &it87_group_fan;
4055
4056         if (enable_pwm_interface) {
4057                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
4058                 data->has_pwm &= ~sio_data->skip_pwm;
4059
4060                 data->groups[4] = &it87_group_pwm;
4061                 if (has_old_autopwm(data) || has_newer_autopwm(data))
4062                         data->groups[5] = &it87_group_auto_pwm;
4063         }
4064
4065         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
4066                                         it87_devices[sio_data->type].name,
4067                                         data, data->groups);
4068         return PTR_ERR_OR_ZERO(hwmon_dev);
4069 }
4070
4071 static struct platform_driver it87_driver = {
4072         .driver = {
4073                 .name   = DRVNAME,
4074         },
4075         .probe  = it87_probe,
4076 };
4077
4078 static int __init it87_device_add(int index, unsigned short sio_address,
4079                                   phys_addr_t mmio_address,
4080                                   const struct it87_sio_data *sio_data)
4081 {
4082         struct platform_device *pdev;
4083         struct resource res = {
4084                 .name   = DRVNAME,
4085         };
4086         int err;
4087
4088         if (mmio_address) {
4089                 res.start = mmio_address;
4090                 res.end = mmio_address + 0x400 - 1;
4091                 res.flags = IORESOURCE_MEM;
4092         } else {
4093                 res.start = sio_address + IT87_EC_OFFSET;
4094                 res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
4095                 res.flags = IORESOURCE_IO;
4096         }
4097
4098         err = acpi_check_resource_conflict(&res);
4099         if (err) {
4100                 if (!ignore_resource_conflict)
4101                         return err;
4102         }
4103
4104         pdev = platform_device_alloc(DRVNAME, sio_address);
4105         if (!pdev)
4106                 return -ENOMEM;
4107
4108         err = platform_device_add_resources(pdev, &res, 1);
4109         if (err) {
4110                 pr_err("Device resource addition failed (%d)\n", err);
4111                 goto exit_device_put;
4112         }
4113
4114         err = platform_device_add_data(pdev, sio_data,
4115                                        sizeof(struct it87_sio_data));
4116         if (err) {
4117                 pr_err("Platform data allocation failed\n");
4118                 goto exit_device_put;
4119         }
4120
4121         err = platform_device_add(pdev);
4122         if (err) {
4123                 pr_err("Device addition failed (%d)\n", err);
4124                 goto exit_device_put;
4125         }
4126
4127         it87_pdev[index] = pdev;
4128         return 0;
4129
4130 exit_device_put:
4131         platform_device_put(pdev);
4132         return err;
4133 }
4134
4135 struct it87_dmi_data {
4136         bool sio2_force_config; /* force sio2 into configuration mode   */
4137         u8 skip_pwm;            /* pwm channels to skip for this board  */
4138 };
4139
4140 /*
4141  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4142  * (IT8792E) needs to be in configuration mode before accessing the first
4143  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4144  * This needs to be done before accessing the first Super-IO chip since
4145  * the second chip may have been accessed prior to loading this driver.
4146  *
4147  * The problem is also reported to affect IT8795E, which is used on X299 boards
4148  * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4149  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4150  * Z87X-OC.
4151  * DMI entries for those systems will be added as they become available and
4152  * as the problem is confirmed to affect those boards.
4153  */
4154 static struct it87_dmi_data gigabyte_sio2_force = {
4155         .sio2_force_config = true,
4156 };
4157
4158 /*
4159  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4160  * connected to a fan, but to something else. One user
4161  * has reported instant system power-off when changing
4162  * the PWM2 duty cycle, so we disable it.
4163  * I use the board name string as the trigger in case
4164  * the same board is ever used in other systems.
4165  */
4166 static struct it87_dmi_data nvidia_fn68pt = {
4167         .skip_pwm = BIT(1),
4168 };
4169
4170 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4171         {
4172                 .matches = {
4173                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4174                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4175                 },
4176                 .driver_data = &gigabyte_sio2_force,
4177         },
4178         {
4179                 .matches = {
4180                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4181                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4182                 },
4183                 .driver_data = &gigabyte_sio2_force,
4184         },
4185         {
4186                 .matches = {
4187                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4188                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4189                 },
4190                 .driver_data = &gigabyte_sio2_force,
4191         },
4192         {
4193                 .matches = {
4194                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4195                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4196                 },
4197                 .driver_data = &nvidia_fn68pt,
4198         },
4199         { }
4200 };
4201
4202 static int __init sm_it87_init(void)
4203 {
4204         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4205         struct it87_dmi_data *dmi_data = NULL;
4206         int sioaddr[2] = { REG_2E, REG_4E };
4207         struct it87_sio_data sio_data;
4208         unsigned short isa_address;
4209         phys_addr_t mmio_address;
4210         bool found = false;
4211         int i, err;
4212
4213         pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4214
4215         if (dmi)
4216                 dmi_data = dmi->driver_data;
4217
4218         err = platform_driver_register(&it87_driver);
4219         if (err)
4220                 return err;
4221
4222         if (dmi_data && dmi_data->sio2_force_config)
4223                 __superio_enter(REG_4E);
4224
4225         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4226                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4227                 isa_address = 0;
4228                 mmio_address = 0;
4229                 err = it87_find(sioaddr[i], &isa_address, &mmio_address,
4230                                 &sio_data);
4231                 if (err || isa_address == 0)
4232                         continue;
4233
4234                 if (dmi_data)
4235                         sio_data.skip_pwm |= dmi_data->skip_pwm;
4236                 err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4237                 if (err)
4238                         goto exit_dev_unregister;
4239                 found = true;
4240         }
4241
4242         if (!found) {
4243                 err = -ENODEV;
4244                 goto exit_unregister;
4245         }
4246         return 0;
4247
4248 exit_dev_unregister:
4249         /* NULL check handled by platform_device_unregister */
4250         platform_device_unregister(it87_pdev[0]);
4251 exit_unregister:
4252         platform_driver_unregister(&it87_driver);
4253         return err;
4254 }
4255
4256 static void __exit sm_it87_exit(void)
4257 {
4258         /* NULL check handled by platform_device_unregister */
4259         platform_device_unregister(it87_pdev[1]);
4260         platform_device_unregister(it87_pdev[0]);
4261         platform_driver_unregister(&it87_driver);
4262 }
4263
4264 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4265 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4266 module_param(update_vbat, bool, 0);
4267 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4268 module_param(fix_pwm_polarity, bool, 0);
4269 MODULE_PARM_DESC(fix_pwm_polarity,
4270                  "Force PWM polarity to active high (DANGEROUS)");
4271 MODULE_LICENSE("GPL");
4272
4273 module_init(sm_it87_init);
4274 module_exit(sm_it87_exit);