git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77 #include "version.h"
  78
  79 #define DRVNAME "it87"
  80
  81 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  82              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  83              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  84              it8655, it8665, it8686 };
  85
  86 static unsigned short force_id;
  87 module_param(force_id, ushort, 0);
  88 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  89
  90 static bool ignore_resource_conflict;
  91 module_param(ignore_resource_conflict, bool, 0);
  92 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
  93
  94 static bool mmio;
  95 module_param(mmio, bool, 0);
  96 MODULE_PARM_DESC(mmio, "Use MMIO if available");
  97
  98 static struct platform_device *it87_pdev[2];
  99
 100 #define REG_2E  0x2e    /* The register to read/write */
 101 #define REG_4E  0x4e    /* Secondary register to read/write */
 102
 103 #define DEV     0x07    /* Register: Logical device select */
 104 #define PME     0x04    /* The device with the fan registers in it */
 105
 106 /* The device with the IT8718F/IT8720F VID value in it */
 107 #define GPIO    0x07
 108
 109 #define DEVID   0x20    /* Register: Device ID */
 110 #define DEVREV  0x22    /* Register: Device Revision */
 111
 112 static inline void __superio_enter(int ioreg)
 113 {
 114         outb(0x87, ioreg);
 115         outb(0x01, ioreg);
 116         outb(0x55, ioreg);
 117         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 118 }
 119
 120 static inline int superio_inb(int ioreg, int reg)
 121 {
 122         int val;
 123
 124         outb(reg, ioreg);
 125         val = inb(ioreg + 1);
 126
 127         return val;
 128 }
 129
 130 static inline void superio_outb(int ioreg, int reg, int val)
 131 {
 132         outb(reg, ioreg);
 133         outb(val, ioreg + 1);
 134 }
 135
 136 static int superio_inw(int ioreg, int reg)
 137 {
 138         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 139 }
 140
 141 static inline void superio_select(int ioreg, int ldn)
 142 {
 143         outb(DEV, ioreg);
 144         outb(ldn, ioreg + 1);
 145 }
 146
 147 static inline int superio_enter(int ioreg)
 148 {
 149         /*
 150          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 151          */
 152         if (!request_muxed_region(ioreg, 2, DRVNAME))
 153                 return -EBUSY;
 154
 155         __superio_enter(ioreg);
 156         return 0;
 157 }
 158
 159 static inline void superio_exit(int ioreg, bool doexit)
 160 {
 161         if (doexit) {
 162                 outb(0x02, ioreg);
 163                 outb(0x02, ioreg + 1);
 164         }
 165         release_region(ioreg, 2);
 166 }
 167
 168 /* Logical device 4 registers */
 169 #define IT8712F_DEVID 0x8712
 170 #define IT8705F_DEVID 0x8705
 171 #define IT8716F_DEVID 0x8716
 172 #define IT8718F_DEVID 0x8718
 173 #define IT8720F_DEVID 0x8720
 174 #define IT8721F_DEVID 0x8721
 175 #define IT8726F_DEVID 0x8726
 176 #define IT8728F_DEVID 0x8728
 177 #define IT8732F_DEVID 0x8732
 178 #define IT8792E_DEVID 0x8733
 179 #define IT8771E_DEVID 0x8771
 180 #define IT8772E_DEVID 0x8772
 181 #define IT8781F_DEVID 0x8781
 182 #define IT8782F_DEVID 0x8782
 183 #define IT8783E_DEVID 0x8783
 184 #define IT8786E_DEVID 0x8786
 185 #define IT8790E_DEVID 0x8790
 186 #define IT8603E_DEVID 0x8603
 187 #define IT8607E_DEVID 0x8607
 188 #define IT8613E_DEVID 0x8613
 189 #define IT8620E_DEVID 0x8620
 190 #define IT8622E_DEVID 0x8622
 191 #define IT8623E_DEVID 0x8623
 192 #define IT8625E_DEVID 0x8625
 193 #define IT8628E_DEVID 0x8628
 194 #define IT8655E_DEVID 0x8655
 195 #define IT8665E_DEVID 0x8665
 196 #define IT8686E_DEVID 0x8686
 197
 198 /* Logical device 4 (Environmental Monitor) registers */
 199 #define IT87_ACT_REG            0x30
 200 #define IT87_BASE_REG           0x60
 201 #define IT87_SPECIAL_CFG_REG    0xf3    /* special configuration register */
 202
 203 /* Global configuration registers (IT8712F and later) */
 204 #define IT87_EC_HWM_MIO_REG     0x24    /* MMIO configuration register */
 205 #define IT87_SIO_GPIO1_REG      0x25
 206 #define IT87_SIO_GPIO2_REG      0x26
 207 #define IT87_SIO_GPIO3_REG      0x27
 208 #define IT87_SIO_GPIO4_REG      0x28
 209 #define IT87_SIO_GPIO5_REG      0x29
 210 #define IT87_SIO_GPIO9_REG      0xd3
 211 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 212 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 213 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 214
 215 /* Logical device 7 (GPIO) registers (IT8712F and later) */
 216 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 217 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 218 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 219
 220 /* Update battery voltage after every reading if true */
 221 static bool update_vbat;
 222
 223 /* Not all BIOSes properly configure the PWM registers */
 224 static bool fix_pwm_polarity;
 225
 226 /* Many IT87 constants specified below */
 227
 228 /* Length of ISA address segment */
 229 #define IT87_EXTENT 8
 230
 231 /* Length of ISA address segment for Environmental Controller */
 232 #define IT87_EC_EXTENT 2
 233
 234 /* Offset of EC registers from ISA base address */
 235 #define IT87_EC_OFFSET 5
 236
 237 /* Where are the ISA address/data registers relative to the EC base address */
 238 #define IT87_ADDR_REG_OFFSET 0
 239 #define IT87_DATA_REG_OFFSET 1
 240
 241 /*----- The IT87 registers -----*/
 242
 243 #define IT87_REG_CONFIG        0x00
 244
 245 #define IT87_REG_ALARM1        0x01
 246 #define IT87_REG_ALARM2        0x02
 247 #define IT87_REG_ALARM3        0x03
 248
 249 #define IT87_REG_BANK           0x06
 250
 251 /*
 252  * The IT8718F and IT8720F have the VID value in a different register, in
 253  * Super-I/O configuration space.
 254  */
 255 #define IT87_REG_VID           0x0a
 256 /*
 257  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 258  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 259  * mode.
 260  */
 261 #define IT87_REG_FAN_DIV       0x0b
 262 #define IT87_REG_FAN_16BIT     0x0c
 263
 264 /*
 265  * Monitors:
 266  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 267  * - up to 6 temp (1 to 6)
 268  * - up to 6 fan (1 to 6)
 269  */
 270
 271 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 272 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 273 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 274 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 275
 276 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 277 static const u8 IT87_REG_FAN_MIN_8665[] =
 278                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 279 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 280 static const u8 IT87_REG_FANX_MIN_8665[] =
 281                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 282
 283 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 284
 285 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 286
 287 #define IT87_REG_FAN_MAIN_CTRL 0x13
 288 #define IT87_REG_FAN_CTL       0x14
 289
 290 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 291 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 292
 293 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 294
 295 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 296                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 297
 298 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 299
 300 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 301 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 302
 303 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 304 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 305
 306 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 307                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 308 static const u8 IT87_REG_TEMP_LOW_8686[] =
 309                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 310
 311 #define IT87_REG_VIN_ENABLE    0x50
 312 #define IT87_REG_TEMP_ENABLE   0x51
 313 #define IT87_REG_TEMP_EXTRA    0x55
 314 #define IT87_REG_BEEP_ENABLE   0x5c
 315
 316 #define IT87_REG_CHIPID        0x58
 317
 318 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 319
 320 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 321 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 322
 323 #define IT87_REG_TEMP456_ENABLE 0x77
 324
 325 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 326 #define IT87_REG_TEMP_SRC2      0x23d
 327
 328 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 329 #define NUM_VIN_LIMIT           8
 330 #define NUM_TEMP                6
 331 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 332 #define NUM_FAN_DIV             3
 333 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 334 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 335
 336 struct it87_devices {
 337         const char *name;
 338         const char * const suffix;
 339         u32 features;
 340         u8 num_temp_limit;
 341         u8 num_temp_offset;
 342         u8 num_temp_map;        /* Number of temperature sources for pwm */
 343         u8 peci_mask;
 344         u8 old_peci_mask;
 345         u8 smbus_bitmap;        /* SMBus enable bits in extra config register */
 346         u8 ec_special_config;
 347 };
 348
 349 #define FEAT_12MV_ADC           BIT(0)
 350 #define FEAT_NEWER_AUTOPWM      BIT(1)
 351 #define FEAT_OLD_AUTOPWM        BIT(2)
 352 #define FEAT_16BIT_FANS         BIT(3)
 353 #define FEAT_TEMP_PECI          BIT(5)
 354 #define FEAT_TEMP_OLD_PECI      BIT(6)
 355 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 356 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 357 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 358 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 359 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 360 #define FEAT_10_9MV_ADC         BIT(12)
 361 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 362 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 363 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 364 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 365 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 366 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 367 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 368 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 369 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 370 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 371 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 372 #define FEAT_11MV_ADC           BIT(24)
 373 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 374 #define FEAT_MMIO               BIT(26) /* Chip supports MMIO */
 375
 376 static const struct it87_devices it87_devices[] = {
 377         [it87] = {
 378                 .name = "it87",
 379                 .suffix = "F",
 380                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 381                                                 /* may need to overwrite */
 382                 .num_temp_limit = 3,
 383                 .num_temp_offset = 0,
 384                 .num_temp_map = 3,
 385         },
 386         [it8712] = {
 387                 .name = "it8712",
 388                 .suffix = "F",
 389                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 390                                                 /* may need to overwrite */
 391                 .num_temp_limit = 3,
 392                 .num_temp_offset = 0,
 393                 .num_temp_map = 3,
 394         },
 395         [it8716] = {
 396                 .name = "it8716",
 397                 .suffix = "F",
 398                 .features = FEAT_16BIT_FANS | FEAT_VID
 399                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 400                   | FEAT_FANCTL_ONOFF,
 401                 .num_temp_limit = 3,
 402                 .num_temp_offset = 3,
 403                 .num_temp_map = 3,
 404         },
 405         [it8718] = {
 406                 .name = "it8718",
 407                 .suffix = "F",
 408                 .features = FEAT_16BIT_FANS | FEAT_VID
 409                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 410                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 411                 .num_temp_limit = 3,
 412                 .num_temp_offset = 3,
 413                 .num_temp_map = 3,
 414                 .old_peci_mask = 0x4,
 415         },
 416         [it8720] = {
 417                 .name = "it8720",
 418                 .suffix = "F",
 419                 .features = FEAT_16BIT_FANS | FEAT_VID
 420                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 421                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 422                 .num_temp_limit = 3,
 423                 .num_temp_offset = 3,
 424                 .num_temp_map = 3,
 425                 .old_peci_mask = 0x4,
 426         },
 427         [it8721] = {
 428                 .name = "it8721",
 429                 .suffix = "F",
 430                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 431                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 432                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 433                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 434                 .num_temp_limit = 3,
 435                 .num_temp_offset = 3,
 436                 .num_temp_map = 3,
 437                 .peci_mask = 0x05,
 438                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 439         },
 440         [it8728] = {
 441                 .name = "it8728",
 442                 .suffix = "F",
 443                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 444                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 445                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 446                   | FEAT_FANCTL_ONOFF,
 447                 .num_temp_limit = 6,
 448                 .num_temp_offset = 3,
 449                 .num_temp_map = 3,
 450                 .peci_mask = 0x07,
 451         },
 452         [it8732] = {
 453                 .name = "it8732",
 454                 .suffix = "F",
 455                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 456                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 457                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 458                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 459                 .num_temp_limit = 3,
 460                 .num_temp_offset = 3,
 461                 .num_temp_map = 3,
 462                 .peci_mask = 0x07,
 463                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 464         },
 465         [it8771] = {
 466                 .name = "it8771",
 467                 .suffix = "E",
 468                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 469                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 470                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 471                                 /* PECI: guesswork */
 472                                 /* 12mV ADC (OHM) */
 473                                 /* 16 bit fans (OHM) */
 474                                 /* three fans, always 16 bit (guesswork) */
 475                 .num_temp_limit = 3,
 476                 .num_temp_offset = 3,
 477                 .num_temp_map = 3,
 478                 .peci_mask = 0x07,
 479         },
 480         [it8772] = {
 481                 .name = "it8772",
 482                 .suffix = "E",
 483                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 484                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 485                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 486                                 /* PECI (coreboot) */
 487                                 /* 12mV ADC (HWSensors4, OHM) */
 488                                 /* 16 bit fans (HWSensors4, OHM) */
 489                                 /* three fans, always 16 bit (datasheet) */
 490                 .num_temp_limit = 3,
 491                 .num_temp_offset = 3,
 492                 .num_temp_map = 3,
 493                 .peci_mask = 0x07,
 494         },
 495         [it8781] = {
 496                 .name = "it8781",
 497                 .suffix = "F",
 498                 .features = FEAT_16BIT_FANS
 499                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 500                   | FEAT_FANCTL_ONOFF,
 501                 .num_temp_limit = 3,
 502                 .num_temp_offset = 3,
 503                 .num_temp_map = 3,
 504                 .old_peci_mask = 0x4,
 505         },
 506         [it8782] = {
 507                 .name = "it8782",
 508                 .suffix = "F",
 509                 .features = FEAT_16BIT_FANS
 510                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 511                   | FEAT_FANCTL_ONOFF,
 512                 .num_temp_limit = 3,
 513                 .num_temp_offset = 3,
 514                 .num_temp_map = 3,
 515                 .old_peci_mask = 0x4,
 516         },
 517         [it8783] = {
 518                 .name = "it8783",
 519                 .suffix = "E/F",
 520                 .features = FEAT_16BIT_FANS
 521                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 522                   | FEAT_FANCTL_ONOFF,
 523                 .num_temp_limit = 3,
 524                 .num_temp_offset = 3,
 525                 .num_temp_map = 3,
 526                 .old_peci_mask = 0x4,
 527         },
 528         [it8786] = {
 529                 .name = "it8786",
 530                 .suffix = "E",
 531                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 532                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 533                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 534                 .num_temp_limit = 3,
 535                 .num_temp_offset = 3,
 536                 .num_temp_map = 3,
 537                 .peci_mask = 0x07,
 538         },
 539         [it8790] = {
 540                 .name = "it8790",
 541                 .suffix = "E",
 542                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 543                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 544                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 545                 .num_temp_limit = 3,
 546                 .num_temp_offset = 3,
 547                 .num_temp_map = 3,
 548                 .peci_mask = 0x07,
 549         },
 550         [it8792] = {
 551                 .name = "it8792",
 552                 .suffix = "E",
 553                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 554                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 555                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 556                 .num_temp_limit = 3,
 557                 .num_temp_offset = 3,
 558                 .num_temp_map = 3,
 559                 .peci_mask = 0x07,
 560         },
 561         [it8603] = {
 562                 .name = "it8603",
 563                 .suffix = "E",
 564                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 565                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 566                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 567                 .num_temp_limit = 3,
 568                 .num_temp_offset = 3,
 569                 .num_temp_map = 4,
 570                 .peci_mask = 0x07,
 571         },
 572         [it8607] = {
 573                 .name = "it8607",
 574                 .suffix = "E",
 575                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 576                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 577                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 578                   | FEAT_FANCTL_ONOFF,
 579                 .num_temp_limit = 3,
 580                 .num_temp_offset = 3,
 581                 .num_temp_map = 6,
 582                 .peci_mask = 0x07,
 583         },
 584         [it8613] = {
 585                 .name = "it8613",
 586                 .suffix = "E",
 587                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 588                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 589                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 590                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 591                 .num_temp_limit = 6,
 592                 .num_temp_offset = 6,
 593                 .num_temp_map = 6,
 594                 .peci_mask = 0x07,
 595         },
 596         [it8620] = {
 597                 .name = "it8620",
 598                 .suffix = "E",
 599                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 600                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 601                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 602                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 603                   | FEAT_FANCTL_ONOFF,
 604                 .num_temp_limit = 3,
 605                 .num_temp_offset = 3,
 606                 .num_temp_map = 3,
 607                 .peci_mask = 0x07,
 608         },
 609         [it8622] = {
 610                 .name = "it8622",
 611                 .suffix = "E",
 612                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 613                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 614                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 615                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 616                 .num_temp_limit = 3,
 617                 .num_temp_offset = 3,
 618                 .num_temp_map = 4,
 619                 .peci_mask = 0x07,
 620         },
 621         [it8625] = {
 622                 .name = "it8625",
 623                 .suffix = "E",
 624                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 625                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 626                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 627                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 628                 .num_temp_limit = 6,
 629                 .num_temp_offset = 6,
 630                 .num_temp_map = 6,
 631                 .smbus_bitmap = BIT(1) | BIT(2),
 632         },
 633         [it8628] = {
 634                 .name = "it8628",
 635                 .suffix = "E",
 636                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 637                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 638                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 639                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 640                   | FEAT_FANCTL_ONOFF,
 641                 .num_temp_limit = 6,
 642                 .num_temp_offset = 3,
 643                 .num_temp_map = 3,
 644                 .peci_mask = 0x07,
 645         },
 646         [it8655] = {
 647                 .name = "it8655",
 648                 .suffix = "E",
 649                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 650                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 651                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 652                 .num_temp_limit = 6,
 653                 .num_temp_offset = 6,
 654                 .num_temp_map = 6,
 655                 .smbus_bitmap = BIT(2),
 656         },
 657         [it8665] = {
 658                 .name = "it8665",
 659                 .suffix = "E",
 660                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 661                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 662                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 663                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO,
 664                 .num_temp_limit = 6,
 665                 .num_temp_offset = 6,
 666                 .num_temp_map = 6,
 667                 .smbus_bitmap = BIT(2),
 668         },
 669         [it8686] = {
 670                 .name = "it8686",
 671                 .suffix = "E",
 672                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 673                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 674                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 675                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 676                 .num_temp_limit = 6,
 677                 .num_temp_offset = 6,
 678                 .num_temp_map = 7,
 679                 .smbus_bitmap = BIT(1) | BIT(2),
 680         },
 681 };
 682
 683 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 684 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 685 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 686 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 687 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 688 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 689                                  ((data)->peci_mask & BIT(nr)))
 690 #define has_temp_old_peci(data, nr) \
 691                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 692                                  ((data)->old_peci_mask & BIT(nr)))
 693 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 694 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 695                                                      FEAT_SIX_FANS))
 696 #define has_vid(data)           ((data)->features & FEAT_VID)
 697 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 698 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 699 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 700 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 701                                                      | FEAT_SIX_PWM))
 702 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 703 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 704 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 705 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 706 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 707                                                      FEAT_FIVE_FANS | \
 708                                                      FEAT_SIX_FANS))
 709 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 710                                                      FEAT_FIVE_PWM \
 711                                                      | FEAT_SIX_PWM))
 712 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 713 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 714 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 715 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 716 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 717 #define has_mmio(data)          ((data)->features & FEAT_MMIO)
 718
 719 struct it87_sio_data {
 720         enum chips type;
 721         u8 sioaddr;
 722         u8 doexit;
 723         /* Values read from Super-I/O config space */
 724         u8 revision;
 725         u8 vid_value;
 726         u8 beep_pin;
 727         u8 internal;    /* Internal sensors can be labeled */
 728         /* Features skipped based on config or DMI */
 729         u16 skip_in;
 730         u8 skip_vid;
 731         u8 skip_fan;
 732         u8 skip_pwm;
 733         u8 skip_temp;
 734         u8 smbus_bitmap;
 735         u8 ec_special_config;
 736 };
 737
 738 /*
 739  * For each registered chip, we need to keep some data in memory.
 740  * The structure is dynamically allocated.
 741  */
 742 struct it87_data {
 743         const struct attribute_group *groups[7];
 744         enum chips type;
 745         u32 features;
 746         u8 peci_mask;
 747         u8 old_peci_mask;
 748
 749         u8 smbus_bitmap;        /* !=0 if SMBus needs to be disabled */
 750         u8 ec_special_config;   /* EC special config register restore value */
 751         u8 sioaddr;             /* SIO port address */
 752         bool doexit;            /* true if exit from sio config is ok */
 753
 754         void __iomem *mmio;     /* Remapped MMIO address if available */
 755         int (*read)(struct it87_data *, u16);
 756         void (*write)(struct it87_data *, u16, u8);
 757
 758         const u8 *REG_FAN;
 759         const u8 *REG_FANX;
 760         const u8 *REG_FAN_MIN;
 761         const u8 *REG_FANX_MIN;
 762
 763         const u8 *REG_PWM;
 764
 765         const u8 *REG_TEMP_OFFSET;
 766         const u8 *REG_TEMP_LOW;
 767         const u8 *REG_TEMP_HIGH;
 768
 769         unsigned short addr;
 770         const char *name;
 771         struct mutex update_lock;
 772         char valid;             /* !=0 if following fields are valid */
 773         unsigned long last_updated;     /* In jiffies */
 774
 775         u16 in_scaled;          /* Internal voltage sensors are scaled */
 776         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 777         u16 has_in;             /* Bitfield, voltage sensors enabled */
 778         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 779         u8 has_fan;             /* Bitfield, fans enabled */
 780         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 781         u8 has_temp;            /* Bitfield, temp sensors enabled */
 782         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 783         u8 num_temp_limit;      /* Number of temperature limit registers */
 784         u8 num_temp_offset;     /* Number of temperature offset registers */
 785         u8 temp_src[4];         /* Up to 4 temperature source registers */
 786         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 787         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 788         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 789         bool has_vid;           /* True if VID supported */
 790         u8 vid;                 /* Register encoding, combined */
 791         u8 vrm;
 792         u32 alarms;             /* Register encoding, combined */
 793         bool has_beep;          /* true if beep supported */
 794         u8 beeps;               /* Register encoding */
 795         u8 fan_main_ctrl;       /* Register value */
 796         u8 fan_ctl;             /* Register value */
 797
 798         /*
 799          * The following 3 arrays correspond to the same registers up to
 800          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 801          * 7, and we want to preserve settings on mode changes, so we have
 802          * to track all values separately.
 803          * Starting with the IT8721F, the manual PWM duty cycles are stored
 804          * in separate registers (8-bit values), so the separate tracking
 805          * is no longer needed, but it is still done to keep the driver
 806          * simple.
 807          */
 808         u8 has_pwm;             /* Bitfield, pwm control enabled */
 809         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 810         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 811         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 812         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 813         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 814         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 815
 816         /* Automatic fan speed control registers */
 817         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 818         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 819 };
 820
 821 static int adc_lsb(const struct it87_data *data, int nr)
 822 {
 823         int lsb;
 824
 825         if (has_12mv_adc(data))
 826                 lsb = 120;
 827         else if (has_10_9mv_adc(data))
 828                 lsb = 109;
 829         else if (has_11mv_adc(data))
 830                 lsb = 110;
 831         else
 832                 lsb = 160;
 833         if (data->in_scaled & BIT(nr))
 834                 lsb <<= 1;
 835         return lsb;
 836 }
 837
 838 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 839 {
 840         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 841         return clamp_val(val, 0, 255);
 842 }
 843
 844 static int in_from_reg(const struct it87_data *data, int nr, int val)
 845 {
 846         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 847 }
 848
 849 static inline u8 FAN_TO_REG(long rpm, int div)
 850 {
 851         if (rpm == 0)
 852                 return 255;
 853         rpm = clamp_val(rpm, 1, 1000000);
 854         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 855 }
 856
 857 static inline u16 FAN16_TO_REG(long rpm)
 858 {
 859         if (rpm == 0)
 860                 return 0xffff;
 861         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 862 }
 863
 864 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 865                                 1350000 / ((val) * (div)))
 866 /* The divider is fixed to 2 in 16-bit mode */
 867 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 868                              1350000 / ((val) * 2))
 869
 870 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 871                                     ((val) + 500) / 1000), -128, 127))
 872 #define TEMP_FROM_REG(val) ((val) * 1000)
 873
 874 static u8 pwm_to_reg(const struct it87_data *data, long val)
 875 {
 876         if (has_newer_autopwm(data))
 877                 return val;
 878         else
 879                 return val >> 1;
 880 }
 881
 882 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 883 {
 884         if (has_newer_autopwm(data))
 885                 return reg;
 886         else
 887                 return (reg & 0x7f) << 1;
 888 }
 889
 890 static int DIV_TO_REG(int val)
 891 {
 892         int answer = 0;
 893
 894         while (answer < 7 && (val >>= 1))
 895                 answer++;
 896         return answer;
 897 }
 898
 899 #define DIV_FROM_REG(val) BIT(val)
 900
 901 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 902 {
 903         u8 map;
 904
 905         map  = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 906         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 907                 map = 0;
 908
 909         return map;
 910 }
 911
 912 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 913 {
 914         u8 ctrl = data->pwm_ctrl[nr];
 915
 916         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 917                (map << data->pwm_temp_map_shift);
 918 }
 919
 920 /*
 921  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 922  * depending on the chip type, to calculate the actual PWM frequency.
 923  *
 924  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 925  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 926  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 927  * sometimes just one. It is unknown if this is a datasheet error or real,
 928  * so this is ignored for now.
 929  */
 930 static const unsigned int pwm_freq[8] = {
 931         48000000,
 932         24000000,
 933         12000000,
 934         8000000,
 935         6000000,
 936         3000000,
 937         1500000,
 938         750000,
 939 };
 940
 941 static int smbus_disable(struct it87_data *data)
 942 {
 943         int err;
 944
 945         if (data->smbus_bitmap) {
 946                 err = superio_enter(data->sioaddr);
 947                 if (err)
 948                         return err;
 949                 superio_select(data->sioaddr, PME);
 950                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 951                              data->ec_special_config & ~data->smbus_bitmap);
 952                 superio_exit(data->sioaddr, data->doexit);
 953         }
 954         return 0;
 955 }
 956
 957 static int smbus_enable(struct it87_data *data)
 958 {
 959         int err;
 960
 961         if (data->smbus_bitmap) {
 962                 err = superio_enter(data->sioaddr);
 963                 if (err)
 964                         return err;
 965
 966                 superio_select(data->sioaddr, PME);
 967                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 968                              data->ec_special_config);
 969                 superio_exit(data->sioaddr, data->doexit);
 970         }
 971         return 0;
 972 }
 973
 974 static int _it87_io_read(struct it87_data *data, u16 reg)
 975 {
 976         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 977         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 978 }
 979
 980 static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
 981 {
 982         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 983         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 984 }
 985
 986 static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
 987 {
 988         u8 _bank = bank;
 989
 990         if (has_bank_sel(data)) {
 991                 u8 breg = _it87_io_read(data, IT87_REG_BANK);
 992
 993                 _bank = breg >> 5;
 994                 if (bank != _bank) {
 995                         breg &= 0x1f;
 996                         breg |= (bank << 5);
 997                         _it87_io_write(data, IT87_REG_BANK, breg);
 998                 }
 999         }
1000         return _bank;
1001 }
1002
1003 /*
1004  * Must be called with data->update_lock held, except during initialization.
1005  * Must be called with SMBus accesses disabled.
1006  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1007  * would slow down the IT87 access and should not be necessary.
1008  */
1009 static int it87_io_read(struct it87_data *data, u16 reg)
1010 {
1011         u8 bank;
1012         int val;
1013
1014         bank = it87_io_set_bank(data, reg >> 8);
1015         val = _it87_io_read(data, reg & 0xff);
1016         it87_io_set_bank(data, bank);
1017
1018         return val;
1019 }
1020
1021 /*
1022  * Must be called with data->update_lock held, except during initialization.
1023  * Must be called with SMBus accesses disabled
1024  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1025  * would slow down the IT87 access and should not be necessary.
1026  */
1027 static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1028 {
1029         u8 bank;
1030
1031         bank = it87_io_set_bank(data, reg >> 8);
1032         _it87_io_write(data, reg & 0xff, value);
1033         it87_io_set_bank(data, bank);
1034 }
1035
1036 static int it87_mmio_read(struct it87_data *data, u16 reg)
1037 {
1038         return readb(data->mmio + reg);
1039 }
1040
1041 static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1042 {
1043         writeb(value, data->mmio + reg);
1044 }
1045
1046 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1047 {
1048         u8 ctrl;
1049
1050         ctrl = data->read(data, data->REG_PWM[nr]);
1051         data->pwm_ctrl[nr] = ctrl;
1052         if (has_newer_autopwm(data)) {
1053                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1054                 data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1055         } else {
1056                 if (ctrl & 0x80)        /* Automatic mode */
1057                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1058                 else                            /* Manual mode */
1059                         data->pwm_duty[nr] = ctrl & 0x7f;
1060         }
1061
1062         if (has_old_autopwm(data)) {
1063                 int i;
1064
1065                 for (i = 0; i < 5 ; i++)
1066                         data->auto_temp[nr][i] = data->read(data,
1067                                                 IT87_REG_AUTO_TEMP(nr, i));
1068                 for (i = 0; i < 3 ; i++)
1069                         data->auto_pwm[nr][i] = data->read(data,
1070                                                 IT87_REG_AUTO_PWM(nr, i));
1071         } else if (has_newer_autopwm(data)) {
1072                 int i;
1073
1074                 /*
1075                  * 0: temperature hysteresis (base + 5)
1076                  * 1: fan off temperature (base + 0)
1077                  * 2: fan start temperature (base + 1)
1078                  * 3: fan max temperature (base + 2)
1079                  */
1080                 data->auto_temp[nr][0] =
1081                         data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1082
1083                 for (i = 0; i < 3 ; i++)
1084                         data->auto_temp[nr][i + 1] =
1085                                 data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1086                 /*
1087                  * 0: start pwm value (base + 3)
1088                  * 1: pwm slope (base + 4, 1/8th pwm)
1089                  */
1090                 data->auto_pwm[nr][0] =
1091                         data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1092                 data->auto_pwm[nr][1] =
1093                         data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1094         }
1095 }
1096
1097 static int it87_lock(struct it87_data *data)
1098 {
1099         int err;
1100
1101         mutex_lock(&data->update_lock);
1102         err = smbus_disable(data);
1103         if (err)
1104                 mutex_unlock(&data->update_lock);
1105         return err;
1106 }
1107
1108 static void it87_unlock(struct it87_data *data)
1109 {
1110         smbus_enable(data);
1111         mutex_unlock(&data->update_lock);
1112 }
1113
1114 static struct it87_data *it87_update_device(struct device *dev)
1115 {
1116         struct it87_data *data = dev_get_drvdata(dev);
1117         int err;
1118         int i;
1119
1120         err = it87_lock(data);
1121         if (err)
1122                 return ERR_PTR(err);
1123
1124         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1125             !data->valid) {
1126                 if (update_vbat) {
1127                         /*
1128                          * Cleared after each update, so reenable.  Value
1129                          * returned by this read will be previous value
1130                          */
1131                         data->write(data, IT87_REG_CONFIG,
1132                                     data->read(data, IT87_REG_CONFIG) | 0x40);
1133                 }
1134                 for (i = 0; i < NUM_VIN; i++) {
1135                         if (!(data->has_in & BIT(i)))
1136                                 continue;
1137
1138                         data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1139
1140                         /* VBAT and AVCC don't have limit registers */
1141                         if (i >= NUM_VIN_LIMIT)
1142                                 continue;
1143
1144                         data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1145                         data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1146                 }
1147
1148                 for (i = 0; i < NUM_FAN; i++) {
1149                         /* Skip disabled fans */
1150                         if (!(data->has_fan & BIT(i)))
1151                                 continue;
1152
1153                         data->fan[i][1] = data->read(data, data->REG_FAN_MIN[i]);
1154                         data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1155                         /* Add high byte if in 16-bit mode */
1156                         if (has_16bit_fans(data)) {
1157                                 data->fan[i][0] |= data->read(data,
1158                                                 data->REG_FANX[i]) << 8;
1159                                 data->fan[i][1] |= data->read(data,
1160                                                 data->REG_FANX_MIN[i]) << 8;
1161                         }
1162                 }
1163                 for (i = 0; i < NUM_TEMP; i++) {
1164                         if (!(data->has_temp & BIT(i)))
1165                                 continue;
1166                         data->temp[i][0] =
1167                                 data->read(data, IT87_REG_TEMP(i));
1168
1169                         if (i >= data->num_temp_limit)
1170                                 continue;
1171
1172                         if (i < data->num_temp_offset)
1173                                 data->temp[i][3] =
1174                                   data->read(data, data->REG_TEMP_OFFSET[i]);
1175
1176                         data->temp[i][1] =
1177                                 data->read(data, data->REG_TEMP_LOW[i]);
1178                         data->temp[i][2] =
1179                                 data->read(data, data->REG_TEMP_HIGH[i]);
1180                 }
1181
1182                 /* Newer chips don't have clock dividers */
1183                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1184                         i = data->read(data, IT87_REG_FAN_DIV);
1185                         data->fan_div[0] = i & 0x07;
1186                         data->fan_div[1] = (i >> 3) & 0x07;
1187                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1188                 }
1189
1190                 data->alarms =
1191                         data->read(data, IT87_REG_ALARM1) |
1192                         (data->read(data, IT87_REG_ALARM2) << 8) |
1193                         (data->read(data, IT87_REG_ALARM3) << 16);
1194                 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1195
1196                 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1197                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1198                 for (i = 0; i < NUM_PWM; i++) {
1199                         if (!(data->has_pwm & BIT(i)))
1200                                 continue;
1201                         it87_update_pwm_ctrl(data, i);
1202                 }
1203
1204                 data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1205                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1206                 /*
1207                  * The IT8705F does not have VID capability.
1208                  * The IT8718F and later don't use IT87_REG_VID for the
1209                  * same purpose.
1210                  */
1211                 if (data->type == it8712 || data->type == it8716) {
1212                         data->vid = data->read(data, IT87_REG_VID);
1213                         /*
1214                          * The older IT8712F revisions had only 5 VID pins,
1215                          * but we assume it is always safe to read 6 bits.
1216                          */
1217                         data->vid &= 0x3f;
1218                 }
1219                 data->last_updated = jiffies;
1220                 data->valid = 1;
1221         }
1222         it87_unlock(data);
1223         return data;
1224 }
1225
1226 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1227                        char *buf)
1228 {
1229         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1230         struct it87_data *data = it87_update_device(dev);
1231         int index = sattr->index;
1232         int nr = sattr->nr;
1233
1234         if (IS_ERR(data))
1235                 return PTR_ERR(data);
1236
1237         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1238 }
1239
1240 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1241                       const char *buf, size_t count)
1242 {
1243         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1244         struct it87_data *data = dev_get_drvdata(dev);
1245         int index = sattr->index;
1246         int nr = sattr->nr;
1247         unsigned long val;
1248         int err;
1249
1250         if (kstrtoul(buf, 10, &val) < 0)
1251                 return -EINVAL;
1252
1253         err = it87_lock(data);
1254         if (err)
1255                 return err;
1256
1257         data->in[nr][index] = in_to_reg(data, nr, val);
1258         data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1259                                      : IT87_REG_VIN_MAX(nr),
1260                     data->in[nr][index]);
1261         it87_unlock(data);
1262         return count;
1263 }
1264
1265 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1266 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1267                             0, 1);
1268 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1269                             0, 2);
1270
1271 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1272 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1273                             1, 1);
1274 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1275                             1, 2);
1276
1277 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1278 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1279                             2, 1);
1280 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1281                             2, 2);
1282
1283 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1284 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1285                             3, 1);
1286 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1287                             3, 2);
1288
1289 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1290 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1291                             4, 1);
1292 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1293                             4, 2);
1294
1295 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1296 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1297                             5, 1);
1298 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1299                             5, 2);
1300
1301 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1302 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1303                             6, 1);
1304 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1305                             6, 2);
1306
1307 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1308 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1309                             7, 1);
1310 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1311                             7, 2);
1312
1313 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1314 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1315 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1316 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1317 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1318
1319 /* Up to 6 temperatures */
1320 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1321                          char *buf)
1322 {
1323         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1324         int nr = sattr->nr;
1325         int index = sattr->index;
1326         struct it87_data *data = it87_update_device(dev);
1327
1328         if (IS_ERR(data))
1329                 return PTR_ERR(data);
1330
1331         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1332 }
1333
1334 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1335                         const char *buf, size_t count)
1336 {
1337         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1338         int nr = sattr->nr;
1339         int index = sattr->index;
1340         struct it87_data *data = dev_get_drvdata(dev);
1341         long val;
1342         u8 reg, regval;
1343         int err;
1344
1345         if (kstrtol(buf, 10, &val) < 0)
1346                 return -EINVAL;
1347
1348         err = it87_lock(data);
1349         if (err)
1350                 return err;
1351
1352         switch (index) {
1353         default:
1354         case 1:
1355                 reg = data->REG_TEMP_LOW[nr];
1356                 break;
1357         case 2:
1358                 reg = data->REG_TEMP_HIGH[nr];
1359                 break;
1360         case 3:
1361                 regval = data->read(data, IT87_REG_BEEP_ENABLE);
1362                 if (!(regval & 0x80)) {
1363                         regval |= 0x80;
1364                         data->write(data, IT87_REG_BEEP_ENABLE, regval);
1365                 }
1366                 data->valid = 0;
1367                 reg = data->REG_TEMP_OFFSET[nr];
1368                 break;
1369         }
1370
1371         data->temp[nr][index] = TEMP_TO_REG(val);
1372         data->write(data, reg, data->temp[nr][index]);
1373         it87_unlock(data);
1374         return count;
1375 }
1376
1377 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1378 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1379                             0, 1);
1380 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1381                             0, 2);
1382 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1383                             set_temp, 0, 3);
1384 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1385 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1386                             1, 1);
1387 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1388                             1, 2);
1389 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1390                             set_temp, 1, 3);
1391 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1392 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1393                             2, 1);
1394 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1395                             2, 2);
1396 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1397                             set_temp, 2, 3);
1398 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1399 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1400                             3, 1);
1401 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1402                             3, 2);
1403 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1404                             set_temp, 3, 3);
1405 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1406 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1407                             4, 1);
1408 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1409                             4, 2);
1410 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1411                             set_temp, 4, 3);
1412 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1413 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1414                             5, 1);
1415 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1416                             5, 2);
1417 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1418                             set_temp, 5, 3);
1419
1420 static const u8 temp_types_8686[NUM_TEMP][9] = {
1421         { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1422         { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1423         { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1424         { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1425         { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1426         { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1427 };
1428
1429 static int get_temp_type(struct it87_data *data, int index)
1430 {
1431         u8 reg, extra;
1432         int type = 0;
1433
1434         if (has_bank_sel(data)) {
1435                 u8 src1, src2;
1436
1437                 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1438
1439                 switch (data->type) {
1440                 case it8686:
1441                         if (src1 < 9)
1442                                 type = temp_types_8686[index][src1];
1443                         break;
1444                 case it8625:
1445                         if (index < 3)
1446                                 break;
1447                 case it8655:
1448                 case it8665:
1449                         if (src1 < 3) {
1450                                 index = src1;
1451                                 break;
1452                         }
1453                         src2 = data->temp_src[3];
1454                         switch(src1) {
1455                         case 3:
1456                                 type = (src2 & BIT(index)) ? 6 : 5;
1457                                 break;
1458                         case 4 ... 8:
1459                                 type = (src2 & BIT(index)) ? 4 : 6;
1460                                 break;
1461                         case 9:
1462                                 type = (src2 & BIT(index)) ? 5 : 0;
1463                                 break;
1464                         default:
1465                                 break;
1466                         }
1467                         return type;
1468                 default:
1469                         return 0;
1470                 }
1471         }
1472         if (type || index >= 3)
1473                 return type;
1474
1475         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1476         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1477
1478         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1479             (has_temp_old_peci(data, index) && (extra & 0x80)))
1480                 type = 6;               /* Intel PECI */
1481         if (reg & BIT(index))
1482                 type = 3;               /* thermal diode */
1483         else if (reg & BIT(index + 3))
1484                 type = 4;               /* thermistor */
1485
1486         return type;
1487 }
1488
1489 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1490                               char *buf)
1491 {
1492         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1493         struct it87_data *data = it87_update_device(dev);
1494         int type;
1495
1496         if (IS_ERR(data))
1497                 return PTR_ERR(data);
1498
1499         type = get_temp_type(data, sensor_attr->index);
1500         return sprintf(buf, "%d\n", type);
1501 }
1502
1503 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1504                              const char *buf, size_t count)
1505 {
1506         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1507         int nr = sensor_attr->index;
1508
1509         struct it87_data *data = dev_get_drvdata(dev);
1510         long val;
1511         u8 reg, extra;
1512         int err;
1513
1514         if (kstrtol(buf, 10, &val) < 0)
1515                 return -EINVAL;
1516
1517         err = it87_lock(data);
1518         if (err)
1519                 return err;
1520
1521         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1522         reg &= ~(1 << nr);
1523         reg &= ~(8 << nr);
1524         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1525                 reg &= 0x3f;
1526         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1527         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1528                 extra &= 0x7f;
1529         if (val == 2) { /* backwards compatibility */
1530                 dev_warn(dev,
1531                          "Sensor type 2 is deprecated, please use 4 instead\n");
1532                 val = 4;
1533         }
1534         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1535         if (val == 3)
1536                 reg |= 1 << nr;
1537         else if (val == 4)
1538                 reg |= 8 << nr;
1539         else if (has_temp_peci(data, nr) && val == 6)
1540                 reg |= (nr + 1) << 6;
1541         else if (has_temp_old_peci(data, nr) && val == 6)
1542                 extra |= 0x80;
1543         else if (val != 0) {
1544                 count = -EINVAL;
1545                 goto unlock;
1546         }
1547
1548         data->sensor = reg;
1549         data->extra = extra;
1550         data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1551         if (has_temp_old_peci(data, nr))
1552                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1553         data->valid = 0;        /* Force cache refresh */
1554 unlock:
1555         it87_unlock(data);
1556         return count;
1557 }
1558
1559 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1560                           set_temp_type, 0);
1561 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1562                           set_temp_type, 1);
1563 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1564                           set_temp_type, 2);
1565 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1566                           set_temp_type, 3);
1567 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1568                           set_temp_type, 4);
1569 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1570                           set_temp_type, 5);
1571
1572 /* 6 Fans */
1573
1574 static int pwm_mode(const struct it87_data *data, int nr)
1575 {
1576         if (has_fanctl_onoff(data) && nr < 3 &&
1577             !(data->fan_main_ctrl & BIT(nr)))
1578                 return 0;                               /* Full speed */
1579         if (data->pwm_ctrl[nr] & 0x80)
1580                 return 2;                               /* Automatic mode */
1581         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1582             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1583                 return 0;                       /* Full speed */
1584
1585         return 1;                               /* Manual mode */
1586 }
1587
1588 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1589                         char *buf)
1590 {
1591         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1592         int nr = sattr->nr;
1593         int index = sattr->index;
1594         int speed;
1595         struct it87_data *data = it87_update_device(dev);
1596
1597         if (IS_ERR(data))
1598                 return PTR_ERR(data);
1599
1600         speed = has_16bit_fans(data) ?
1601                 FAN16_FROM_REG(data->fan[nr][index]) :
1602                 FAN_FROM_REG(data->fan[nr][index],
1603                              DIV_FROM_REG(data->fan_div[nr]));
1604         return sprintf(buf, "%d\n", speed);
1605 }
1606
1607 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1608                             char *buf)
1609 {
1610         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1611         struct it87_data *data = it87_update_device(dev);
1612         int nr = sensor_attr->index;
1613
1614         if (IS_ERR(data))
1615                 return PTR_ERR(data);
1616
1617         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1618 }
1619
1620 static ssize_t show_pwm_enable(struct device *dev,
1621                                struct device_attribute *attr, char *buf)
1622 {
1623         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1624         struct it87_data *data = it87_update_device(dev);
1625         int nr = sensor_attr->index;
1626
1627         if (IS_ERR(data))
1628                 return PTR_ERR(data);
1629
1630         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1631 }
1632
1633 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1634                         char *buf)
1635 {
1636         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1637         struct it87_data *data = it87_update_device(dev);
1638         int nr = sensor_attr->index;
1639
1640         if (IS_ERR(data))
1641                 return PTR_ERR(data);
1642
1643         return sprintf(buf, "%d\n",
1644                        pwm_from_reg(data, data->pwm_duty[nr]));
1645 }
1646
1647 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1648                              char *buf)
1649 {
1650         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1651         struct it87_data *data = it87_update_device(dev);
1652         int nr = sensor_attr->index;
1653         unsigned int freq;
1654         int index;
1655
1656         if (IS_ERR(data))
1657                 return PTR_ERR(data);
1658
1659         if (has_pwm_freq2(data) && nr == 1)
1660                 index = (data->extra >> 4) & 0x07;
1661         else
1662                 index = (data->fan_ctl >> 4) & 0x07;
1663
1664         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1665
1666         return sprintf(buf, "%u\n", freq);
1667 }
1668
1669 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1670                        const char *buf, size_t count)
1671 {
1672         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1673         int nr = sattr->nr;
1674         int index = sattr->index;
1675
1676         struct it87_data *data = dev_get_drvdata(dev);
1677         long val;
1678         int err;
1679         u8 reg;
1680
1681         if (kstrtol(buf, 10, &val) < 0)
1682                 return -EINVAL;
1683
1684         err = it87_lock(data);
1685         if (err)
1686                 return err;
1687
1688         if (has_16bit_fans(data)) {
1689                 data->fan[nr][index] = FAN16_TO_REG(val);
1690                 data->write(data, data->REG_FAN_MIN[nr],
1691                             data->fan[nr][index] & 0xff);
1692                 data->write(data, data->REG_FANX_MIN[nr],
1693                             data->fan[nr][index] >> 8);
1694         } else {
1695                 reg = data->read(data, IT87_REG_FAN_DIV);
1696                 switch (nr) {
1697                 case 0:
1698                         data->fan_div[nr] = reg & 0x07;
1699                         break;
1700                 case 1:
1701                         data->fan_div[nr] = (reg >> 3) & 0x07;
1702                         break;
1703                 case 2:
1704                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1705                         break;
1706                 }
1707                 data->fan[nr][index] =
1708                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1709                 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1710         }
1711         it87_unlock(data);
1712         return count;
1713 }
1714
1715 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1716                            const char *buf, size_t count)
1717 {
1718         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1719         struct it87_data *data = dev_get_drvdata(dev);
1720         int nr = sensor_attr->index;
1721         unsigned long val;
1722         int min, err;
1723         u8 old;
1724
1725         if (kstrtoul(buf, 10, &val) < 0)
1726                 return -EINVAL;
1727
1728         err = it87_lock(data);
1729         if (err)
1730                 return err;
1731
1732         old = data->read(data, IT87_REG_FAN_DIV);
1733
1734         /* Save fan min limit */
1735         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1736
1737         switch (nr) {
1738         case 0:
1739         case 1:
1740                 data->fan_div[nr] = DIV_TO_REG(val);
1741                 break;
1742         case 2:
1743                 if (val < 8)
1744                         data->fan_div[nr] = 1;
1745                 else
1746                         data->fan_div[nr] = 3;
1747         }
1748         val = old & 0x80;
1749         val |= (data->fan_div[0] & 0x07);
1750         val |= (data->fan_div[1] & 0x07) << 3;
1751         if (data->fan_div[2] == 3)
1752                 val |= 0x1 << 6;
1753         data->write(data, IT87_REG_FAN_DIV, val);
1754
1755         /* Restore fan min limit */
1756         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1757         data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1758         it87_unlock(data);
1759         return count;
1760 }
1761
1762 /* Returns 0 if OK, -EINVAL otherwise */
1763 static int check_trip_points(struct device *dev, int nr)
1764 {
1765         const struct it87_data *data = dev_get_drvdata(dev);
1766         int i, err = 0;
1767
1768         if (has_old_autopwm(data)) {
1769                 for (i = 0; i < 3; i++) {
1770                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1771                                 err = -EINVAL;
1772                 }
1773                 for (i = 0; i < 2; i++) {
1774                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1775                                 err = -EINVAL;
1776                 }
1777         } else if (has_newer_autopwm(data)) {
1778                 for (i = 1; i < 3; i++) {
1779                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1780                                 err = -EINVAL;
1781                 }
1782         }
1783
1784         if (err) {
1785                 dev_err(dev,
1786                         "Inconsistent trip points, not switching to automatic mode\n");
1787                 dev_err(dev, "Adjust the trip points and try again\n");
1788         }
1789         return err;
1790 }
1791
1792 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1793                               const char *buf, size_t count)
1794 {
1795         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1796         struct it87_data *data = dev_get_drvdata(dev);
1797         int nr = sensor_attr->index;
1798         long val;
1799         int err;
1800
1801         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1802                 return -EINVAL;
1803
1804         /* Check trip points before switching to automatic mode */
1805         if (val == 2) {
1806                 if (check_trip_points(dev, nr) < 0)
1807                         return -EINVAL;
1808         }
1809
1810         err = it87_lock(data);
1811         if (err)
1812                 return err;;
1813
1814         it87_update_pwm_ctrl(data, nr);
1815
1816         if (val == 0) {
1817                 if (nr < 3 && has_fanctl_onoff(data)) {
1818                         int tmp;
1819                         /* make sure the fan is on when in on/off mode */
1820                         tmp = data->read(data, IT87_REG_FAN_CTL);
1821                         data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1822                         /* set on/off mode */
1823                         data->fan_main_ctrl &= ~BIT(nr);
1824                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1825                                     data->fan_main_ctrl);
1826                 } else {
1827                         u8 ctrl;
1828
1829                         /* No on/off mode, set maximum pwm value */
1830                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1831                         data->write(data, IT87_REG_PWM_DUTY[nr],
1832                                     data->pwm_duty[nr]);
1833                         /* and set manual mode */
1834                         if (has_newer_autopwm(data)) {
1835                                 ctrl = temp_map_to_reg(data, nr,
1836                                                        data->pwm_temp_map[nr]);
1837                                 ctrl &= 0x7f;
1838                         } else {
1839                                 ctrl = data->pwm_duty[nr];
1840                         }
1841                         data->pwm_ctrl[nr] = ctrl;
1842                         data->write(data, data->REG_PWM[nr], ctrl);
1843                 }
1844         } else {
1845                 u8 ctrl;
1846
1847                 if (has_newer_autopwm(data)) {
1848                         ctrl = temp_map_to_reg(data, nr,
1849                                                data->pwm_temp_map[nr]);
1850                         if (val == 1)
1851                                 ctrl &= 0x7f;
1852                         else
1853                                 ctrl |= 0x80;
1854                 } else {
1855                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1856                 }
1857                 data->pwm_ctrl[nr] = ctrl;
1858                 data->write(data, data->REG_PWM[nr], ctrl);
1859
1860                 if (has_fanctl_onoff(data) && nr < 3) {
1861                         /* set SmartGuardian mode */
1862                         data->fan_main_ctrl |= BIT(nr);
1863                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1864                                     data->fan_main_ctrl);
1865                 }
1866         }
1867         it87_unlock(data);
1868         return count;
1869 }
1870
1871 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1872                        const char *buf, size_t count)
1873 {
1874         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1875         struct it87_data *data = dev_get_drvdata(dev);
1876         int nr = sensor_attr->index;
1877         long val;
1878         int err;
1879
1880         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1881                 return -EINVAL;
1882
1883         err = it87_lock(data);
1884         if (err)
1885                 return err;
1886
1887         it87_update_pwm_ctrl(data, nr);
1888         if (has_newer_autopwm(data)) {
1889                 /*
1890                  * If we are in automatic mode, the PWM duty cycle register
1891                  * is read-only so we can't write the value.
1892                  */
1893                 if (data->pwm_ctrl[nr] & 0x80) {
1894                         count = -EBUSY;
1895                         goto unlock;
1896                 }
1897                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1898                 data->write(data, IT87_REG_PWM_DUTY[nr],
1899                             data->pwm_duty[nr]);
1900         } else {
1901                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1902                 /*
1903                  * If we are in manual mode, write the duty cycle immediately;
1904                  * otherwise, just store it for later use.
1905                  */
1906                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1907                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1908                         data->write(data, data->REG_PWM[nr],
1909                                     data->pwm_ctrl[nr]);
1910                 }
1911         }
1912 unlock:
1913         it87_unlock(data);
1914         return count;
1915 }
1916
1917 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1918                             const char *buf, size_t count)
1919 {
1920         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1921         struct it87_data *data = dev_get_drvdata(dev);
1922         int nr = sensor_attr->index;
1923         unsigned long val;
1924         int err;
1925         int i;
1926
1927         if (kstrtoul(buf, 10, &val) < 0)
1928                 return -EINVAL;
1929
1930         val = clamp_val(val, 0, 1000000);
1931         val *= has_newer_autopwm(data) ? 256 : 128;
1932
1933         /* Search for the nearest available frequency */
1934         for (i = 0; i < 7; i++) {
1935                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1936                         break;
1937         }
1938
1939         err = it87_lock(data);
1940         if (err)
1941                 return err;
1942
1943         if (nr == 0) {
1944                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1945                 data->fan_ctl |= i << 4;
1946                 data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
1947         } else {
1948                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1949                 data->extra |= i << 4;
1950                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1951         }
1952         it87_unlock(data);
1953         return count;
1954 }
1955
1956 static ssize_t show_pwm_temp_map(struct device *dev,
1957                                  struct device_attribute *attr, char *buf)
1958 {
1959         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1960         struct it87_data *data = it87_update_device(dev);
1961         int nr = sensor_attr->index;
1962
1963         if (IS_ERR(data))
1964                 return PTR_ERR(data);
1965
1966         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1967 }
1968
1969 static ssize_t set_pwm_temp_map(struct device *dev,
1970                                 struct device_attribute *attr, const char *buf,
1971                                 size_t count)
1972 {
1973         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1974         struct it87_data *data = dev_get_drvdata(dev);
1975         int nr = sensor_attr->index;
1976         unsigned long val;
1977         int err;
1978         u8 map;
1979
1980         if (kstrtoul(buf, 10, &val) < 0)
1981                 return -EINVAL;
1982
1983         if (!val || val > data->pwm_num_temp_map)
1984                 return -EINVAL;
1985
1986         map = val - 1;
1987
1988         err = it87_lock(data);
1989         if (err)
1990                 return err;
1991
1992         it87_update_pwm_ctrl(data, nr);
1993         data->pwm_temp_map[nr] = map;
1994         /*
1995          * If we are in automatic mode, write the temp mapping immediately;
1996          * otherwise, just store it for later use.
1997          */
1998         if (data->pwm_ctrl[nr] & 0x80) {
1999                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
2000                 data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
2001         }
2002         it87_unlock(data);
2003         return count;
2004 }
2005
2006 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
2007                              char *buf)
2008 {
2009         struct it87_data *data = it87_update_device(dev);
2010         struct sensor_device_attribute_2 *sensor_attr =
2011                         to_sensor_dev_attr_2(attr);
2012         int nr = sensor_attr->nr;
2013         int point = sensor_attr->index;
2014
2015         if (IS_ERR(data))
2016                 return PTR_ERR(data);
2017
2018         return sprintf(buf, "%d\n",
2019                        pwm_from_reg(data, data->auto_pwm[nr][point]));
2020 }
2021
2022 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2023                             const char *buf, size_t count)
2024 {
2025         struct it87_data *data = dev_get_drvdata(dev);
2026         struct sensor_device_attribute_2 *sensor_attr =
2027                         to_sensor_dev_attr_2(attr);
2028         int nr = sensor_attr->nr;
2029         int point = sensor_attr->index;
2030         int regaddr;
2031         long val;
2032         int err;
2033
2034         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2035                 return -EINVAL;
2036
2037         err = it87_lock(data);
2038         if (err)
2039                 return err;
2040
2041         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2042         if (has_newer_autopwm(data))
2043                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2044         else
2045                 regaddr = IT87_REG_AUTO_PWM(nr, point);
2046         data->write(data, regaddr, data->auto_pwm[nr][point]);
2047         it87_unlock(data);
2048         return count;
2049 }
2050
2051 static ssize_t show_auto_pwm_slope(struct device *dev,
2052                                    struct device_attribute *attr, char *buf)
2053 {
2054         struct it87_data *data = it87_update_device(dev);
2055         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2056         int nr = sensor_attr->index;
2057
2058         if (IS_ERR(data))
2059                 return PTR_ERR(data);
2060
2061         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2062 }
2063
2064 static ssize_t set_auto_pwm_slope(struct device *dev,
2065                                   struct device_attribute *attr,
2066                                   const char *buf, size_t count)
2067 {
2068         struct it87_data *data = dev_get_drvdata(dev);
2069         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2070         int nr = sensor_attr->index;
2071         unsigned long val;
2072         int err;
2073
2074         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2075                 return -EINVAL;
2076
2077         err = it87_lock(data);
2078         if (err)
2079                 return err;
2080
2081         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2082         data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2083         it87_unlock(data);
2084         return count;
2085 }
2086
2087 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2088                               char *buf)
2089 {
2090         struct it87_data *data = it87_update_device(dev);
2091         struct sensor_device_attribute_2 *sensor_attr =
2092                         to_sensor_dev_attr_2(attr);
2093         int nr = sensor_attr->nr;
2094         int point = sensor_attr->index;
2095         int reg;
2096
2097         if (IS_ERR(data))
2098                 return PTR_ERR(data);
2099
2100         if (has_old_autopwm(data) || point)
2101                 reg = data->auto_temp[nr][point];
2102         else
2103                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2104
2105         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2106 }
2107
2108 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2109                              const char *buf, size_t count)
2110 {
2111         struct it87_data *data = dev_get_drvdata(dev);
2112         struct sensor_device_attribute_2 *sensor_attr =
2113                         to_sensor_dev_attr_2(attr);
2114         int nr = sensor_attr->nr;
2115         int point = sensor_attr->index;
2116         long val;
2117         int reg;
2118         int err;
2119
2120         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2121                 return -EINVAL;
2122
2123         err = it87_lock(data);
2124         if (err)
2125                 return err;
2126
2127         if (has_newer_autopwm(data) && !point) {
2128                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2129                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2130                 data->auto_temp[nr][0] = reg;
2131                 data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2132         } else {
2133                 reg = TEMP_TO_REG(val);
2134                 data->auto_temp[nr][point] = reg;
2135                 if (has_newer_autopwm(data))
2136                         point--;
2137                 data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2138         }
2139         it87_unlock(data);
2140         return count;
2141 }
2142
2143 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
2144 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2145                             0, 1);
2146 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
2147                           set_fan_div, 0);
2148
2149 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
2150 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2151                             1, 1);
2152 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
2153                           set_fan_div, 1);
2154
2155 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
2156 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2157                             2, 1);
2158 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
2159                           set_fan_div, 2);
2160
2161 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2162 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2163                             3, 1);
2164
2165 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2166 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2167                             4, 1);
2168
2169 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2170 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2171                             5, 1);
2172
2173 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2174                           show_pwm_enable, set_pwm_enable, 0);
2175 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2176 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2177                           set_pwm_freq, 0);
2178 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2179                           show_pwm_temp_map, set_pwm_temp_map, 0);
2180 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2181                             show_auto_pwm, set_auto_pwm, 0, 0);
2182 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2183                             show_auto_pwm, set_auto_pwm, 0, 1);
2184 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2185                             show_auto_pwm, set_auto_pwm, 0, 2);
2186 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2187                             show_auto_pwm, NULL, 0, 3);
2188 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2189                             show_auto_temp, set_auto_temp, 0, 1);
2190 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2191                             show_auto_temp, set_auto_temp, 0, 0);
2192 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2193                             show_auto_temp, set_auto_temp, 0, 2);
2194 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2195                             show_auto_temp, set_auto_temp, 0, 3);
2196 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2197                             show_auto_temp, set_auto_temp, 0, 4);
2198 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2199                             show_auto_pwm, set_auto_pwm, 0, 0);
2200 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2201                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2202
2203 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2204                           show_pwm_enable, set_pwm_enable, 1);
2205 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2206 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2207 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2208                           show_pwm_temp_map, set_pwm_temp_map, 1);
2209 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2210                             show_auto_pwm, set_auto_pwm, 1, 0);
2211 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2212                             show_auto_pwm, set_auto_pwm, 1, 1);
2213 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2214                             show_auto_pwm, set_auto_pwm, 1, 2);
2215 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2216                             show_auto_pwm, NULL, 1, 3);
2217 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2218                             show_auto_temp, set_auto_temp, 1, 1);
2219 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2220                             show_auto_temp, set_auto_temp, 1, 0);
2221 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2222                             show_auto_temp, set_auto_temp, 1, 2);
2223 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2224                             show_auto_temp, set_auto_temp, 1, 3);
2225 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2226                             show_auto_temp, set_auto_temp, 1, 4);
2227 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2228                             show_auto_pwm, set_auto_pwm, 1, 0);
2229 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2230                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2231
2232 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2233                           show_pwm_enable, set_pwm_enable, 2);
2234 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2235 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2236 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2237                           show_pwm_temp_map, set_pwm_temp_map, 2);
2238 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2239                             show_auto_pwm, set_auto_pwm, 2, 0);
2240 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2241                             show_auto_pwm, set_auto_pwm, 2, 1);
2242 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2243                             show_auto_pwm, set_auto_pwm, 2, 2);
2244 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2245                             show_auto_pwm, NULL, 2, 3);
2246 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2247                             show_auto_temp, set_auto_temp, 2, 1);
2248 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2249                             show_auto_temp, set_auto_temp, 2, 0);
2250 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2251                             show_auto_temp, set_auto_temp, 2, 2);
2252 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2253                             show_auto_temp, set_auto_temp, 2, 3);
2254 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2255                             show_auto_temp, set_auto_temp, 2, 4);
2256 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2257                             show_auto_pwm, set_auto_pwm, 2, 0);
2258 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2259                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2260
2261 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2262                           show_pwm_enable, set_pwm_enable, 3);
2263 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2264 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2265 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2266                           show_pwm_temp_map, set_pwm_temp_map, 3);
2267 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2268                             show_auto_temp, set_auto_temp, 2, 1);
2269 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2270                             show_auto_temp, set_auto_temp, 2, 0);
2271 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2272                             show_auto_temp, set_auto_temp, 2, 2);
2273 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2274                             show_auto_temp, set_auto_temp, 2, 3);
2275 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2276                             show_auto_pwm, set_auto_pwm, 3, 0);
2277 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2278                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2279
2280 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2281                           show_pwm_enable, set_pwm_enable, 4);
2282 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2283 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2284 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2285                           show_pwm_temp_map, set_pwm_temp_map, 4);
2286 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2287                             show_auto_temp, set_auto_temp, 2, 1);
2288 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2289                             show_auto_temp, set_auto_temp, 2, 0);
2290 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2291                             show_auto_temp, set_auto_temp, 2, 2);
2292 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2293                             show_auto_temp, set_auto_temp, 2, 3);
2294 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2295                             show_auto_pwm, set_auto_pwm, 4, 0);
2296 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2297                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2298
2299 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2300                           show_pwm_enable, set_pwm_enable, 5);
2301 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2302 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2303 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2304                           show_pwm_temp_map, set_pwm_temp_map, 5);
2305 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2306                             show_auto_temp, set_auto_temp, 2, 1);
2307 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2308                             show_auto_temp, set_auto_temp, 2, 0);
2309 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2310                             show_auto_temp, set_auto_temp, 2, 2);
2311 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2312                             show_auto_temp, set_auto_temp, 2, 3);
2313 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2314                             show_auto_pwm, set_auto_pwm, 5, 0);
2315 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2316                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2317
2318 /* Alarms */
2319 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2320                            char *buf)
2321 {
2322         struct it87_data *data = it87_update_device(dev);
2323
2324         if (IS_ERR(data))
2325                 return PTR_ERR(data);
2326
2327         return sprintf(buf, "%u\n", data->alarms);
2328 }
2329 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2330
2331 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2332                           char *buf)
2333 {
2334         struct it87_data *data = it87_update_device(dev);
2335         int bitnr = to_sensor_dev_attr(attr)->index;
2336
2337         if (IS_ERR(data))
2338                 return PTR_ERR(data);
2339
2340         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2341 }
2342
2343 static ssize_t clear_intrusion(struct device *dev,
2344                                struct device_attribute *attr, const char *buf,
2345                                size_t count)
2346 {
2347         struct it87_data *data = dev_get_drvdata(dev);
2348         int err, config;
2349         long val;
2350
2351         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2352                 return -EINVAL;
2353
2354         err = it87_lock(data);
2355         if (err)
2356                 return err;
2357
2358         config = data->read(data, IT87_REG_CONFIG);
2359         config |= BIT(5);
2360         data->write(data, IT87_REG_CONFIG, config);
2361         /* Invalidate cache to force re-read */
2362         data->valid = 0;
2363         it87_unlock(data);
2364         return count;
2365 }
2366
2367 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2368 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2369 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2370 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2371 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2372 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2373 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2374 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2375 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2376 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2377 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2378 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2379 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2380 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2381 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2382 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2383 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2384 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2385 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2386 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2387 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2388                           show_alarm, clear_intrusion, 4);
2389
2390 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2391                          char *buf)
2392 {
2393         struct it87_data *data = it87_update_device(dev);
2394         int bitnr = to_sensor_dev_attr(attr)->index;
2395
2396         if (IS_ERR(data))
2397                 return PTR_ERR(data);
2398
2399         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2400 }
2401
2402 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2403                         const char *buf, size_t count)
2404 {
2405         int bitnr = to_sensor_dev_attr(attr)->index;
2406         struct it87_data *data = dev_get_drvdata(dev);
2407         long val;
2408         int err;
2409
2410         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2411                 return -EINVAL;
2412
2413         err = it87_lock(data);
2414         if (err)
2415                 return err;
2416
2417         data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2418         if (val)
2419                 data->beeps |= BIT(bitnr);
2420         else
2421                 data->beeps &= ~BIT(bitnr);
2422         data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2423         it87_unlock(data);
2424         return count;
2425 }
2426
2427 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2428                           show_beep, set_beep, 1);
2429 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2430 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2431 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2432 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2433 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2434 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2435 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2436 /* fanX_beep writability is set later */
2437 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2438 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2439 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2440 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2441 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2442 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2443 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2444                           show_beep, set_beep, 2);
2445 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2446 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2447 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2448 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2449 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2450
2451 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2452                             char *buf)
2453 {
2454         struct it87_data *data = dev_get_drvdata(dev);
2455
2456         return sprintf(buf, "%u\n", data->vrm);
2457 }
2458
2459 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2460                              const char *buf, size_t count)
2461 {
2462         struct it87_data *data = dev_get_drvdata(dev);
2463         unsigned long val;
2464
2465         if (kstrtoul(buf, 10, &val) < 0)
2466                 return -EINVAL;
2467
2468         data->vrm = val;
2469
2470         return count;
2471 }
2472 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2473
2474 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2475                             char *buf)
2476 {
2477         struct it87_data *data = it87_update_device(dev);
2478
2479         if (IS_ERR(data))
2480                 return PTR_ERR(data);
2481
2482         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2483 }
2484 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2485
2486 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2487                           char *buf)
2488 {
2489         static const char * const labels[] = {
2490                 "+5V",
2491                 "5VSB",
2492                 "Vbat",
2493                 "AVCC",
2494         };
2495         static const char * const labels_it8721[] = {
2496                 "+3.3V",
2497                 "3VSB",
2498                 "Vbat",
2499                 "+3.3V",
2500         };
2501         struct it87_data *data = dev_get_drvdata(dev);
2502         int nr = to_sensor_dev_attr(attr)->index;
2503         const char *label;
2504
2505         if (has_vin3_5v(data) && nr == 0)
2506                 label = labels[0];
2507         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2508                  has_11mv_adc(data))
2509                 label = labels_it8721[nr];
2510         else
2511                 label = labels[nr];
2512
2513         return sprintf(buf, "%s\n", label);
2514 }
2515 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2516 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2517 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2518 /* AVCC3 */
2519 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2520
2521 static umode_t it87_in_is_visible(struct kobject *kobj,
2522                                   struct attribute *attr, int index)
2523 {
2524         struct device *dev = container_of(kobj, struct device, kobj);
2525         struct it87_data *data = dev_get_drvdata(dev);
2526         int i = index / 5;      /* voltage index */
2527         int a = index % 5;      /* attribute index */
2528
2529         if (index >= 40) {      /* in8 and higher only have input attributes */
2530                 i = index - 40 + 8;
2531                 a = 0;
2532         }
2533
2534         if (!(data->has_in & BIT(i)))
2535                 return 0;
2536
2537         if (a == 4 && !data->has_beep)
2538                 return 0;
2539
2540         return attr->mode;
2541 }
2542
2543 static struct attribute *it87_attributes_in[] = {
2544         &sensor_dev_attr_in0_input.dev_attr.attr,
2545         &sensor_dev_attr_in0_min.dev_attr.attr,
2546         &sensor_dev_attr_in0_max.dev_attr.attr,
2547         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2548         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2549
2550         &sensor_dev_attr_in1_input.dev_attr.attr,
2551         &sensor_dev_attr_in1_min.dev_attr.attr,
2552         &sensor_dev_attr_in1_max.dev_attr.attr,
2553         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2554         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2555
2556         &sensor_dev_attr_in2_input.dev_attr.attr,
2557         &sensor_dev_attr_in2_min.dev_attr.attr,
2558         &sensor_dev_attr_in2_max.dev_attr.attr,
2559         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2560         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2561
2562         &sensor_dev_attr_in3_input.dev_attr.attr,
2563         &sensor_dev_attr_in3_min.dev_attr.attr,
2564         &sensor_dev_attr_in3_max.dev_attr.attr,
2565         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2566         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2567
2568         &sensor_dev_attr_in4_input.dev_attr.attr,
2569         &sensor_dev_attr_in4_min.dev_attr.attr,
2570         &sensor_dev_attr_in4_max.dev_attr.attr,
2571         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2572         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2573
2574         &sensor_dev_attr_in5_input.dev_attr.attr,
2575         &sensor_dev_attr_in5_min.dev_attr.attr,
2576         &sensor_dev_attr_in5_max.dev_attr.attr,
2577         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2578         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2579
2580         &sensor_dev_attr_in6_input.dev_attr.attr,
2581         &sensor_dev_attr_in6_min.dev_attr.attr,
2582         &sensor_dev_attr_in6_max.dev_attr.attr,
2583         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2584         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2585
2586         &sensor_dev_attr_in7_input.dev_attr.attr,
2587         &sensor_dev_attr_in7_min.dev_attr.attr,
2588         &sensor_dev_attr_in7_max.dev_attr.attr,
2589         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2590         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2591
2592         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2593         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2594         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2595         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2596         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2597         NULL
2598 };
2599
2600 static const struct attribute_group it87_group_in = {
2601         .attrs = it87_attributes_in,
2602         .is_visible = it87_in_is_visible,
2603 };
2604
2605 static umode_t it87_temp_is_visible(struct kobject *kobj,
2606                                     struct attribute *attr, int index)
2607 {
2608         struct device *dev = container_of(kobj, struct device, kobj);
2609         struct it87_data *data = dev_get_drvdata(dev);
2610         int i = index / 7;      /* temperature index */
2611         int a = index % 7;      /* attribute index */
2612
2613         if (!(data->has_temp & BIT(i)))
2614                 return 0;
2615
2616         if (a && i >= data->num_temp_limit)
2617                 return 0;
2618
2619         if (a == 3) {
2620                 int type = get_temp_type(data, i);
2621
2622                 if (type == 0)
2623                         return 0;
2624                 if (has_bank_sel(data))
2625                         return 0444;
2626                 return attr->mode;
2627         }
2628
2629         if (a == 5 && i >= data->num_temp_offset)
2630                 return 0;
2631
2632         if (a == 6 && !data->has_beep)
2633                 return 0;
2634
2635         return attr->mode;
2636 }
2637
2638 static struct attribute *it87_attributes_temp[] = {
2639         &sensor_dev_attr_temp1_input.dev_attr.attr,
2640         &sensor_dev_attr_temp1_max.dev_attr.attr,
2641         &sensor_dev_attr_temp1_min.dev_attr.attr,
2642         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2643         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2644         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2645         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2646
2647         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2648         &sensor_dev_attr_temp2_max.dev_attr.attr,
2649         &sensor_dev_attr_temp2_min.dev_attr.attr,
2650         &sensor_dev_attr_temp2_type.dev_attr.attr,
2651         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2652         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2653         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2654
2655         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2656         &sensor_dev_attr_temp3_max.dev_attr.attr,
2657         &sensor_dev_attr_temp3_min.dev_attr.attr,
2658         &sensor_dev_attr_temp3_type.dev_attr.attr,
2659         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2660         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2661         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2662
2663         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2664         &sensor_dev_attr_temp4_max.dev_attr.attr,
2665         &sensor_dev_attr_temp4_min.dev_attr.attr,
2666         &sensor_dev_attr_temp4_type.dev_attr.attr,
2667         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2668         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2669         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2670
2671         &sensor_dev_attr_temp5_input.dev_attr.attr,
2672         &sensor_dev_attr_temp5_max.dev_attr.attr,
2673         &sensor_dev_attr_temp5_min.dev_attr.attr,
2674         &sensor_dev_attr_temp5_type.dev_attr.attr,
2675         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2676         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2677         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2678
2679         &sensor_dev_attr_temp6_input.dev_attr.attr,
2680         &sensor_dev_attr_temp6_max.dev_attr.attr,
2681         &sensor_dev_attr_temp6_min.dev_attr.attr,
2682         &sensor_dev_attr_temp6_type.dev_attr.attr,
2683         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2684         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2685         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2686         NULL
2687 };
2688
2689 static const struct attribute_group it87_group_temp = {
2690         .attrs = it87_attributes_temp,
2691         .is_visible = it87_temp_is_visible,
2692 };
2693
2694 static umode_t it87_is_visible(struct kobject *kobj,
2695                                struct attribute *attr, int index)
2696 {
2697         struct device *dev = container_of(kobj, struct device, kobj);
2698         struct it87_data *data = dev_get_drvdata(dev);
2699
2700         if ((index == 2 || index == 3) && !data->has_vid)
2701                 return 0;
2702
2703         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2704                 return 0;
2705
2706         return attr->mode;
2707 }
2708
2709 static struct attribute *it87_attributes[] = {
2710         &dev_attr_alarms.attr,
2711         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2712         &dev_attr_vrm.attr,                             /* 2 */
2713         &dev_attr_cpu0_vid.attr,                        /* 3 */
2714         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2715         &sensor_dev_attr_in7_label.dev_attr.attr,
2716         &sensor_dev_attr_in8_label.dev_attr.attr,
2717         &sensor_dev_attr_in9_label.dev_attr.attr,
2718         NULL
2719 };
2720
2721 static const struct attribute_group it87_group = {
2722         .attrs = it87_attributes,
2723         .is_visible = it87_is_visible,
2724 };
2725
2726 static umode_t it87_fan_is_visible(struct kobject *kobj,
2727                                    struct attribute *attr, int index)
2728 {
2729         struct device *dev = container_of(kobj, struct device, kobj);
2730         struct it87_data *data = dev_get_drvdata(dev);
2731         int i = index / 5;      /* fan index */
2732         int a = index % 5;      /* attribute index */
2733
2734         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2735                 i = (index - 15) / 4 + 3;
2736                 a = (index - 15) % 4;
2737         }
2738
2739         if (!(data->has_fan & BIT(i)))
2740                 return 0;
2741
2742         if (a == 3) {                           /* beep */
2743                 if (!data->has_beep)
2744                         return 0;
2745                 /* first fan beep attribute is writable */
2746                 if (i == __ffs(data->has_fan))
2747                         return attr->mode | S_IWUSR;
2748         }
2749
2750         if (a == 4 && has_16bit_fans(data))     /* divisor */
2751                 return 0;
2752
2753         return attr->mode;
2754 }
2755
2756 static struct attribute *it87_attributes_fan[] = {
2757         &sensor_dev_attr_fan1_input.dev_attr.attr,
2758         &sensor_dev_attr_fan1_min.dev_attr.attr,
2759         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2760         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2761         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2762
2763         &sensor_dev_attr_fan2_input.dev_attr.attr,
2764         &sensor_dev_attr_fan2_min.dev_attr.attr,
2765         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2766         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2767         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2768
2769         &sensor_dev_attr_fan3_input.dev_attr.attr,
2770         &sensor_dev_attr_fan3_min.dev_attr.attr,
2771         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2772         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2773         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2774
2775         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2776         &sensor_dev_attr_fan4_min.dev_attr.attr,
2777         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2778         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2779
2780         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2781         &sensor_dev_attr_fan5_min.dev_attr.attr,
2782         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2783         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2784
2785         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2786         &sensor_dev_attr_fan6_min.dev_attr.attr,
2787         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2788         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2789         NULL
2790 };
2791
2792 static const struct attribute_group it87_group_fan = {
2793         .attrs = it87_attributes_fan,
2794         .is_visible = it87_fan_is_visible,
2795 };
2796
2797 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2798                                    struct attribute *attr, int index)
2799 {
2800         struct device *dev = container_of(kobj, struct device, kobj);
2801         struct it87_data *data = dev_get_drvdata(dev);
2802         int i = index / 4;      /* pwm index */
2803         int a = index % 4;      /* attribute index */
2804
2805         if (!(data->has_pwm & BIT(i)))
2806                 return 0;
2807
2808         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2809         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2810                 return attr->mode | S_IWUSR;
2811
2812         /* pwm2_freq is writable if there are two pwm frequency selects */
2813         if (has_pwm_freq2(data) && i == 1 && a == 2)
2814                 return attr->mode | S_IWUSR;
2815
2816         return attr->mode;
2817 }
2818
2819 static struct attribute *it87_attributes_pwm[] = {
2820         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2821         &sensor_dev_attr_pwm1.dev_attr.attr,
2822         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2823         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2824
2825         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2826         &sensor_dev_attr_pwm2.dev_attr.attr,
2827         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2828         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2829
2830         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2831         &sensor_dev_attr_pwm3.dev_attr.attr,
2832         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2833         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2834
2835         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2836         &sensor_dev_attr_pwm4.dev_attr.attr,
2837         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2838         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2839
2840         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2841         &sensor_dev_attr_pwm5.dev_attr.attr,
2842         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2843         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2844
2845         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2846         &sensor_dev_attr_pwm6.dev_attr.attr,
2847         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2848         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2849
2850         NULL
2851 };
2852
2853 static const struct attribute_group it87_group_pwm = {
2854         .attrs = it87_attributes_pwm,
2855         .is_visible = it87_pwm_is_visible,
2856 };
2857
2858 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2859                                         struct attribute *attr, int index)
2860 {
2861         struct device *dev = container_of(kobj, struct device, kobj);
2862         struct it87_data *data = dev_get_drvdata(dev);
2863         int i = index / 11;     /* pwm index */
2864         int a = index % 11;     /* attribute index */
2865
2866         if (index >= 33) {      /* pwm 4..6 */
2867                 i = (index - 33) / 6 + 3;
2868                 a = (index - 33) % 6 + 4;
2869         }
2870
2871         if (!(data->has_pwm & BIT(i)))
2872                 return 0;
2873
2874         if (has_newer_autopwm(data)) {
2875                 if (a < 4)      /* no auto point pwm */
2876                         return 0;
2877                 if (a == 8)     /* no auto_point4 */
2878                         return 0;
2879         }
2880         if (has_old_autopwm(data)) {
2881                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2882                         return 0;
2883         }
2884
2885         return attr->mode;
2886 }
2887
2888 static struct attribute *it87_attributes_auto_pwm[] = {
2889         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2890         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2891         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2892         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2893         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2894         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2895         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2896         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2897         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2898         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2899         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2900
2901         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2902         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2903         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2904         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2905         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2906         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2907         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2908         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2909         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2910         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2911         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2912
2913         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2914         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2915         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2916         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2917         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2918         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2919         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2920         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2921         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2922         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2923         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2924
2925         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2926         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2927         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2928         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2929         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2930         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2931
2932         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2933         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2934         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2935         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2936         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2937         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2938
2939         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2940         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2941         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2942         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2943         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2944         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2945
2946         NULL,
2947 };
2948
2949 static const struct attribute_group it87_group_auto_pwm = {
2950         .attrs = it87_attributes_auto_pwm,
2951         .is_visible = it87_auto_pwm_is_visible,
2952 };
2953
2954 /* SuperIO detection - will change isa_address if a chip is found */
2955 static int __init it87_find(int sioaddr, unsigned short *address,
2956                             phys_addr_t *mmio_address, struct it87_sio_data *sio_data)
2957 {
2958         const struct it87_devices *config;
2959         phys_addr_t base = 0;
2960         bool doexit = true;
2961         u16 chip_type;
2962         int err;
2963
2964         err = superio_enter(sioaddr);
2965         if (err)
2966                 return err;
2967
2968         sio_data->sioaddr = sioaddr;
2969
2970         err = -ENODEV;
2971         chip_type = superio_inw(sioaddr, DEVID);
2972         if (chip_type == 0xffff)
2973                 goto exit;
2974
2975         if (force_id)
2976                 chip_type = force_id;
2977
2978         switch (chip_type) {
2979         case IT8705F_DEVID:
2980                 sio_data->type = it87;
2981                 break;
2982         case IT8712F_DEVID:
2983                 sio_data->type = it8712;
2984                 break;
2985         case IT8716F_DEVID:
2986         case IT8726F_DEVID:
2987                 sio_data->type = it8716;
2988                 break;
2989         case IT8718F_DEVID:
2990                 sio_data->type = it8718;
2991                 break;
2992         case IT8720F_DEVID:
2993                 sio_data->type = it8720;
2994                 break;
2995         case IT8721F_DEVID:
2996                 sio_data->type = it8721;
2997                 break;
2998         case IT8728F_DEVID:
2999                 sio_data->type = it8728;
3000                 break;
3001         case IT8732F_DEVID:
3002                 sio_data->type = it8732;
3003                 break;
3004         case IT8792E_DEVID:
3005                 sio_data->type = it8792;
3006                 /*
3007                  * Disabling configuration mode on IT8792E can result in system
3008                  * hang-ups and access failures to the Super-IO chip at the
3009                  * second SIO address. Never exit configuration mode on this
3010                  * chip to avoid the problem.
3011                  */
3012                 doexit = false;
3013                 break;
3014         case IT8771E_DEVID:
3015                 sio_data->type = it8771;
3016                 break;
3017         case IT8772E_DEVID:
3018                 sio_data->type = it8772;
3019                 break;
3020         case IT8781F_DEVID:
3021                 sio_data->type = it8781;
3022                 break;
3023         case IT8782F_DEVID:
3024                 sio_data->type = it8782;
3025                 break;
3026         case IT8783E_DEVID:
3027                 sio_data->type = it8783;
3028                 break;
3029         case IT8786E_DEVID:
3030                 sio_data->type = it8786;
3031                 break;
3032         case IT8790E_DEVID:
3033                 sio_data->type = it8790;
3034                 doexit = false;         /* See IT8792E comment above */
3035                 break;
3036         case IT8603E_DEVID:
3037         case IT8623E_DEVID:
3038                 sio_data->type = it8603;
3039                 break;
3040         case IT8607E_DEVID:
3041                 sio_data->type = it8607;
3042                 break;
3043         case IT8613E_DEVID:
3044                 sio_data->type = it8613;
3045                 break;
3046         case IT8620E_DEVID:
3047                 sio_data->type = it8620;
3048                 break;
3049         case IT8622E_DEVID:
3050                 sio_data->type = it8622;
3051                 break;
3052         case IT8625E_DEVID:
3053                 sio_data->type = it8625;
3054                 break;
3055         case IT8628E_DEVID:
3056                 sio_data->type = it8628;
3057                 break;
3058         case IT8655E_DEVID:
3059                 sio_data->type = it8655;
3060                 break;
3061         case IT8665E_DEVID:
3062                 sio_data->type = it8665;
3063                 break;
3064         case IT8686E_DEVID:
3065                 sio_data->type = it8686;
3066                 break;
3067         case 0xffff:    /* No device at all */
3068                 goto exit;
3069         default:
3070                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3071                 goto exit;
3072         }
3073
3074         superio_select(sioaddr, PME);
3075         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3076                 pr_info("Device not activated, skipping\n");
3077                 goto exit;
3078         }
3079
3080         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3081         if (*address == 0) {
3082                 pr_info("Base address not set, skipping\n");
3083                 goto exit;
3084         }
3085
3086         sio_data->doexit = doexit;
3087
3088         err = 0;
3089         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3090         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
3091                 it87_devices[sio_data->type].suffix,
3092                 *address, sio_data->revision);
3093
3094         config = &it87_devices[sio_data->type];
3095
3096         if (has_mmio(config) && mmio) {
3097                 u8 reg;
3098
3099                 reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
3100                 if (reg & BIT(5)) {
3101                         base = 0xf0000000 + ((reg & 0x0f) << 24);
3102                         base += (reg & 0xc0) << 14;
3103                 }
3104         }
3105         *mmio_address = base;
3106
3107         /* in7 (VSB or VCCH5V) is always internal on some chips */
3108         if (has_in7_internal(config))
3109                 sio_data->internal |= BIT(1);
3110
3111         /* in8 (Vbat) is always internal */
3112         sio_data->internal |= BIT(2);
3113
3114         /* in9 (AVCC3), always internal if supported */
3115         if (has_avcc3(config))
3116                 sio_data->internal |= BIT(3); /* in9 is AVCC */
3117         else
3118                 sio_data->skip_in |= BIT(9);
3119
3120         if (!has_four_pwm(config))
3121                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3122         else if (!has_five_pwm(config))
3123                 sio_data->skip_pwm |= BIT(4) | BIT(5);
3124         else if (!has_six_pwm(config))
3125                 sio_data->skip_pwm |= BIT(5);
3126
3127         if (!has_vid(config))
3128                 sio_data->skip_vid = 1;
3129
3130         /* Read GPIO config and VID value from LDN 7 (GPIO) */
3131         if (sio_data->type == it87) {
3132                 /* The IT8705F has a different LD number for GPIO */
3133                 superio_select(sioaddr, 5);
3134                 sio_data->beep_pin = superio_inb(sioaddr,
3135                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3136         } else if (sio_data->type == it8783) {
3137                 int reg25, reg27, reg2a, reg2c, regef;
3138
3139                 superio_select(sioaddr, GPIO);
3140
3141                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3142                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3143                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3144                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3145                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3146
3147                 /* Check if fan3 is there or not */
3148                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3149                         sio_data->skip_fan |= BIT(2);
3150                 if ((reg25 & BIT(4)) ||
3151                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
3152                         sio_data->skip_pwm |= BIT(2);
3153
3154                 /* Check if fan2 is there or not */
3155                 if (reg27 & BIT(7))
3156                         sio_data->skip_fan |= BIT(1);
3157                 if (reg27 & BIT(3))
3158                         sio_data->skip_pwm |= BIT(1);
3159
3160                 /* VIN5 */
3161                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3162                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3163
3164                 /* VIN6 */
3165                 if (reg27 & BIT(1))
3166                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3167
3168                 /*
3169                  * VIN7
3170                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3171                  */
3172                 if (reg27 & BIT(2)) {
3173                         /*
3174                          * The data sheet is a bit unclear regarding the
3175                          * internal voltage divider for VCCH5V. It says
3176                          * "This bit enables and switches VIN7 (pin 91) to the
3177                          * internal voltage divider for VCCH5V".
3178                          * This is different to other chips, where the internal
3179                          * voltage divider would connect VIN7 to an internal
3180                          * voltage source. Maybe that is the case here as well.
3181                          *
3182                          * Since we don't know for sure, re-route it if that is
3183                          * not the case, and ask the user to report if the
3184                          * resulting voltage is sane.
3185                          */
3186                         if (!(reg2c & BIT(1))) {
3187                                 reg2c |= BIT(1);
3188                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3189                                              reg2c);
3190                                 pr_notice("Routing internal VCCH5V to in7.\n");
3191                         }
3192                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3193                         pr_notice("Please report if it displays a reasonable voltage.\n");
3194                 }
3195
3196                 if (reg2c & BIT(0))
3197                         sio_data->internal |= BIT(0);
3198                 if (reg2c & BIT(1))
3199                         sio_data->internal |= BIT(1);
3200
3201                 sio_data->beep_pin = superio_inb(sioaddr,
3202                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3203         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3204                 int reg27, reg29;
3205
3206                 superio_select(sioaddr, GPIO);
3207
3208                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3209
3210                 /* Check if fan3 is there or not */
3211                 if (reg27 & BIT(6))
3212                         sio_data->skip_pwm |= BIT(2);
3213                 if (reg27 & BIT(7))
3214                         sio_data->skip_fan |= BIT(2);
3215
3216                 /* Check if fan2 is there or not */
3217                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3218                 if (reg29 & BIT(1))
3219                         sio_data->skip_pwm |= BIT(1);
3220                 if (reg29 & BIT(2))
3221                         sio_data->skip_fan |= BIT(1);
3222
3223                 switch (sio_data->type) {
3224                 case it8603:
3225                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3226                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3227                         break;
3228                 case it8607:
3229                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3230                         sio_data->skip_fan |= BIT(0);
3231                 default:
3232                         break;
3233                 }
3234
3235                 sio_data->beep_pin = superio_inb(sioaddr,
3236                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3237         } else if (sio_data->type == it8613) {
3238                 int reg27, reg29, reg2a;
3239
3240                 superio_select(sioaddr, GPIO);
3241
3242                 /* Check for pwm3, fan3, pwm5, fan5 */
3243                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3244                 if (reg27 & BIT(1))
3245                         sio_data->skip_fan |= BIT(4);
3246                 if (reg27 & BIT(3))
3247                         sio_data->skip_pwm |= BIT(4);
3248                 if (reg27 & BIT(6))
3249                         sio_data->skip_pwm |= BIT(2);
3250                 if (reg27 & BIT(7))
3251                         sio_data->skip_fan |= BIT(2);
3252
3253                 /* Check for pwm2, fan2 */
3254                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3255                 if (reg29 & BIT(1))
3256                         sio_data->skip_pwm |= BIT(1);
3257                 if (reg29 & BIT(2))
3258                         sio_data->skip_fan |= BIT(1);
3259
3260                 /* Check for pwm4, fan4 */
3261                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3262                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3263                         sio_data->skip_fan |= BIT(3);
3264                         sio_data->skip_pwm |= BIT(3);
3265                 }
3266
3267                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3268                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3269                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3270                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3271
3272                 sio_data->beep_pin = superio_inb(sioaddr,
3273                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3274         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3275                    sio_data->type == it8686) {
3276                 int reg;
3277
3278                 superio_select(sioaddr, GPIO);
3279
3280                 /* Check for pwm5 */
3281                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3282                 if (reg & BIT(6))
3283                         sio_data->skip_pwm |= BIT(4);
3284
3285                 /* Check for fan4, fan5 */
3286                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3287                 if (!(reg & BIT(5)))
3288                         sio_data->skip_fan |= BIT(3);
3289                 if (!(reg & BIT(4)))
3290                         sio_data->skip_fan |= BIT(4);
3291
3292                 /* Check for pwm3, fan3 */
3293                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3294                 if (reg & BIT(6))
3295                         sio_data->skip_pwm |= BIT(2);
3296                 if (reg & BIT(7))
3297                         sio_data->skip_fan |= BIT(2);
3298
3299                 /* Check for pwm4 */
3300                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3301                 if (reg & BIT(2))
3302                         sio_data->skip_pwm |= BIT(3);
3303
3304                 /* Check for pwm2, fan2 */
3305                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3306                 if (reg & BIT(1))
3307                         sio_data->skip_pwm |= BIT(1);
3308                 if (reg & BIT(2))
3309                         sio_data->skip_fan |= BIT(1);
3310                 /* Check for pwm6, fan6 */
3311                 if (!(reg & BIT(7))) {
3312                         sio_data->skip_pwm |= BIT(5);
3313                         sio_data->skip_fan |= BIT(5);
3314                 }
3315
3316                 /* Check if AVCC is on VIN3 */
3317                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3318                 if (reg & BIT(0)) {
3319                         /* For it8686, the bit just enables AVCC3 */
3320                         if (sio_data->type != it8686)
3321                                 sio_data->internal |= BIT(0);
3322                 } else {
3323                         sio_data->internal &= ~BIT(3);
3324                         sio_data->skip_in |= BIT(9);
3325                 }
3326
3327                 sio_data->beep_pin = superio_inb(sioaddr,
3328                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3329         } else if (sio_data->type == it8622) {
3330                 int reg;
3331
3332                 superio_select(sioaddr, GPIO);
3333
3334                 /* Check for pwm4, fan4 */
3335                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3336                 if (reg & BIT(6))
3337                         sio_data->skip_fan |= BIT(3);
3338                 if (reg & BIT(5))
3339                         sio_data->skip_pwm |= BIT(3);
3340
3341                 /* Check for pwm3, fan3, pwm5, fan5 */
3342                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3343                 if (reg & BIT(6))
3344                         sio_data->skip_pwm |= BIT(2);
3345                 if (reg & BIT(7))
3346                         sio_data->skip_fan |= BIT(2);
3347                 if (reg & BIT(3))
3348                         sio_data->skip_pwm |= BIT(4);
3349                 if (reg & BIT(1))
3350                         sio_data->skip_fan |= BIT(4);
3351
3352                 /* Check for pwm2, fan2 */
3353                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3354                 if (reg & BIT(1))
3355                         sio_data->skip_pwm |= BIT(1);
3356                 if (reg & BIT(2))
3357                         sio_data->skip_fan |= BIT(1);
3358
3359                 /* Check for AVCC */
3360                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3361                 if (!(reg & BIT(0)))
3362                         sio_data->skip_in |= BIT(9);
3363
3364                 sio_data->beep_pin = superio_inb(sioaddr,
3365                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3366         } else if (sio_data->type == it8732) {
3367                 int reg;
3368
3369                 superio_select(sioaddr, GPIO);
3370
3371                 /* Check for pwm2, fan2 */
3372                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3373                 if (reg & BIT(1))
3374                         sio_data->skip_pwm |= BIT(1);
3375                 if (reg & BIT(2))
3376                         sio_data->skip_fan |= BIT(1);
3377
3378                 /* Check for pwm3, fan3, fan4 */
3379                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3380                 if (reg & BIT(6))
3381                         sio_data->skip_pwm |= BIT(2);
3382                 if (reg & BIT(7))
3383                         sio_data->skip_fan |= BIT(2);
3384                 if (reg & BIT(5))
3385                         sio_data->skip_fan |= BIT(3);
3386
3387                 /* Check if AVCC is on VIN3 */
3388                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3389                 if (reg & BIT(0))
3390                         sio_data->internal |= BIT(0);
3391
3392                 sio_data->beep_pin = superio_inb(sioaddr,
3393                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3394         } else if (sio_data->type == it8655) {
3395                 int reg;
3396
3397                 superio_select(sioaddr, GPIO);
3398
3399                 /* Check for pwm2 */
3400                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3401                 if (reg & BIT(1))
3402                         sio_data->skip_pwm |= BIT(1);
3403
3404                 /* Check for fan2 */
3405                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3406                 if (reg & BIT(4))
3407                         sio_data->skip_fan |= BIT(1);
3408
3409                 /* Check for pwm3, fan3 */
3410                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3411                 if (reg & BIT(6))
3412                         sio_data->skip_pwm |= BIT(2);
3413                 if (reg & BIT(7))
3414                         sio_data->skip_fan |= BIT(2);
3415
3416                 sio_data->beep_pin = superio_inb(sioaddr,
3417                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3418         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3419                 int reg27, reg29, reg2d, regd3;
3420
3421                 superio_select(sioaddr, GPIO);
3422
3423                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3424                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3425                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3426                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3427
3428                 /* Check for pwm2, fan2 */
3429                 if (reg29 & BIT(1))
3430                         sio_data->skip_pwm |= BIT(1);
3431                 /*
3432                  * Note: Table 6-1 in datasheet claims that FAN_TAC2
3433                  * would be enabled with 29h[2]=0.
3434                  */
3435                 if (reg2d & BIT(4))
3436                         sio_data->skip_fan |= BIT(1);
3437
3438                 /* Check for pwm3, fan3 */
3439                 if (reg27 & BIT(6))
3440                         sio_data->skip_pwm |= BIT(2);
3441                 if (reg27 & BIT(7))
3442                         sio_data->skip_fan |= BIT(2);
3443
3444                 /* Check for pwm4, fan4, pwm5, fan5 */
3445                 if (sio_data->type == it8625) {
3446                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3447
3448                         if (reg25 & BIT(6))
3449                                 sio_data->skip_fan |= BIT(3);
3450                         if (reg25 & BIT(5))
3451                                 sio_data->skip_pwm |= BIT(3);
3452                         if (reg27 & BIT(3))
3453                                 sio_data->skip_pwm |= BIT(4);
3454                         if (reg27 & BIT(1))
3455                                 sio_data->skip_fan |= BIT(4);
3456                 } else {
3457                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3458
3459                         if (regd3 & BIT(2))
3460                                 sio_data->skip_pwm |= BIT(3);
3461                         if (regd3 & BIT(3))
3462                                 sio_data->skip_fan |= BIT(3);
3463                         if (reg26 & BIT(5))
3464                                 sio_data->skip_pwm |= BIT(4);
3465                         if (reg26 & BIT(4))
3466                                 sio_data->skip_fan |= BIT(4);
3467                 }
3468
3469                 /* Check for pwm6, fan6 */
3470                 if (regd3 & BIT(0))
3471                         sio_data->skip_pwm |= BIT(5);
3472                 if (regd3 & BIT(1))
3473                         sio_data->skip_fan |= BIT(5);
3474
3475                 sio_data->beep_pin = superio_inb(sioaddr,
3476                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3477         } else {
3478                 int reg;
3479                 bool uart6;
3480
3481                 superio_select(sioaddr, GPIO);
3482
3483                 /* Check for fan4, fan5 */
3484                 if (has_five_fans(config)) {
3485                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3486                         switch (sio_data->type) {
3487                         case it8718:
3488                                 if (reg & BIT(5))
3489                                         sio_data->skip_fan |= BIT(3);
3490                                 if (reg & BIT(4))
3491                                         sio_data->skip_fan |= BIT(4);
3492                                 break;
3493                         case it8720:
3494                         case it8721:
3495                         case it8728:
3496                                 if (!(reg & BIT(5)))
3497                                         sio_data->skip_fan |= BIT(3);
3498                                 if (!(reg & BIT(4)))
3499                                         sio_data->skip_fan |= BIT(4);
3500                                 break;
3501                         default:
3502                                 break;
3503                         }
3504                 }
3505
3506                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3507                 if (!sio_data->skip_vid) {
3508                         /* We need at least 4 VID pins */
3509                         if (reg & 0x0f) {
3510                                 pr_info("VID is disabled (pins used for GPIO)\n");
3511                                 sio_data->skip_vid = 1;
3512                         }
3513                 }
3514
3515                 /* Check if fan3 is there or not */
3516                 if (reg & BIT(6))
3517                         sio_data->skip_pwm |= BIT(2);
3518                 if (reg & BIT(7))
3519                         sio_data->skip_fan |= BIT(2);
3520
3521                 /* Check if fan2 is there or not */
3522                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3523                 if (reg & BIT(1))
3524                         sio_data->skip_pwm |= BIT(1);
3525                 if (reg & BIT(2))
3526                         sio_data->skip_fan |= BIT(1);
3527
3528                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3529                     !(sio_data->skip_vid))
3530                         sio_data->vid_value = superio_inb(sioaddr,
3531                                                           IT87_SIO_VID_REG);
3532
3533                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3534
3535                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3536
3537                 /*
3538                  * The IT8720F has no VIN7 pin, so VCCH should always be
3539                  * routed internally to VIN7 with an internal divider.
3540                  * Curiously, there still is a configuration bit to control
3541                  * this, which means it can be set incorrectly. And even
3542                  * more curiously, many boards out there are improperly
3543                  * configured, even though the IT8720F datasheet claims
3544                  * that the internal routing of VCCH to VIN7 is the default
3545                  * setting. So we force the internal routing in this case.
3546                  *
3547                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3548                  * If UART6 is enabled, re-route VIN7 to the internal divider
3549                  * if that is not already the case.
3550                  */
3551                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3552                         reg |= BIT(1);
3553                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3554                         pr_notice("Routing internal VCCH to in7\n");
3555                 }
3556                 if (reg & BIT(0))
3557                         sio_data->internal |= BIT(0);
3558                 if (reg & BIT(1))
3559                         sio_data->internal |= BIT(1);
3560
3561                 /*
3562                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3563                  * While VIN7 can be routed to the internal voltage divider,
3564                  * VIN5 and VIN6 are not available if UART6 is enabled.
3565                  *
3566                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3567                  * is the temperature source. Since we can not read the
3568                  * temperature source here, skip_temp is preliminary.
3569                  */
3570                 if (uart6) {
3571                         sio_data->skip_in |= BIT(5) | BIT(6);
3572                         sio_data->skip_temp |= BIT(2);
3573                 }
3574
3575                 sio_data->beep_pin = superio_inb(sioaddr,
3576                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3577         }
3578         if (sio_data->beep_pin)
3579                 pr_info("Beeping is supported\n");
3580
3581         if (config->smbus_bitmap && !base) {
3582                 u8 reg;
3583
3584                 superio_select(sioaddr, PME);
3585                 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3586                 sio_data->ec_special_config = reg;
3587                 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3588         }
3589
3590 exit:
3591         superio_exit(sioaddr, doexit);
3592         return err;
3593 }
3594
3595 static void it87_init_regs(struct platform_device *pdev)
3596 {
3597         struct it87_data *data = platform_get_drvdata(pdev);
3598
3599         /* Initialize chip specific register pointers */
3600         switch (data->type) {
3601         case it8628:
3602         case it8686:
3603                 data->REG_FAN = IT87_REG_FAN;
3604                 data->REG_FANX = IT87_REG_FANX;
3605                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3606                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3607                 data->REG_PWM = IT87_REG_PWM;
3608                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3609                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3610                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3611                 break;
3612         case it8625:
3613         case it8655:
3614         case it8665:
3615                 data->REG_FAN = IT87_REG_FAN_8665;
3616                 data->REG_FANX = IT87_REG_FANX_8665;
3617                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3618                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3619                 data->REG_PWM = IT87_REG_PWM_8665;
3620                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3621                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3622                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3623                 break;
3624         case it8622:
3625                 data->REG_FAN = IT87_REG_FAN;
3626                 data->REG_FANX = IT87_REG_FANX;
3627                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3628                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3629                 data->REG_PWM = IT87_REG_PWM_8665;
3630                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3631                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3632                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3633                 break;
3634         case it8613:
3635                 data->REG_FAN = IT87_REG_FAN;
3636                 data->REG_FANX = IT87_REG_FANX;
3637                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3638                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3639                 data->REG_PWM = IT87_REG_PWM_8665;
3640                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3641                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3642                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3643                 break;
3644         default:
3645                 data->REG_FAN = IT87_REG_FAN;
3646                 data->REG_FANX = IT87_REG_FANX;
3647                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3648                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3649                 data->REG_PWM = IT87_REG_PWM;
3650                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3651                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3652                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3653                 break;
3654         }
3655
3656         if (data->mmio) {
3657                 data->read = it87_mmio_read;
3658                 data->write = it87_mmio_write;
3659         } else if (has_bank_sel(data)) {
3660                 data->read = it87_io_read;
3661                 data->write = it87_io_write;
3662         } else {
3663                 data->read = _it87_io_read;
3664                 data->write = _it87_io_write;
3665         }
3666 }
3667
3668 /* Called when we have found a new IT87. */
3669 static void it87_init_device(struct platform_device *pdev)
3670 {
3671         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3672         struct it87_data *data = platform_get_drvdata(pdev);
3673         int tmp, i;
3674         u8 mask;
3675
3676         if (has_new_tempmap(data)) {
3677                 data->pwm_temp_map_shift = 3;
3678                 data->pwm_temp_map_mask = 0x07;
3679         } else {
3680                 data->pwm_temp_map_shift = 0;
3681                 data->pwm_temp_map_mask = 0x03;
3682         }
3683
3684         /*
3685          * For each PWM channel:
3686          * - If it is in automatic mode, setting to manual mode should set
3687          *   the fan to full speed by default.
3688          * - If it is in manual mode, we need a mapping to temperature
3689          *   channels to use when later setting to automatic mode later.
3690          *   Map to the first sensor by default (we are clueless.)
3691          * In both cases, the value can (and should) be changed by the user
3692          * prior to switching to a different mode.
3693          * Note that this is no longer needed for the IT8721F and later, as
3694          * these have separate registers for the temperature mapping and the
3695          * manual duty cycle.
3696          */
3697         for (i = 0; i < NUM_AUTO_PWM; i++) {
3698                 data->pwm_temp_map[i] = 0;
3699                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3700                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3701         }
3702
3703         /*
3704          * Some chips seem to have default value 0xff for all limit
3705          * registers. For low voltage limits it makes no sense and triggers
3706          * alarms, so change to 0 instead. For high temperature limits, it
3707          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3708          * but is still confusing, so change to 127 degrees C.
3709          */
3710         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3711                 tmp = data->read(data, IT87_REG_VIN_MIN(i));
3712                 if (tmp == 0xff)
3713                         data->write(data, IT87_REG_VIN_MIN(i), 0);
3714         }
3715         for (i = 0; i < data->num_temp_limit; i++) {
3716                 tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3717                 if (tmp == 0xff)
3718                         data->write(data, data->REG_TEMP_HIGH[i], 127);
3719         }
3720
3721         /*
3722          * Temperature channels are not forcibly enabled, as they can be
3723          * set to two different sensor types and we can't guess which one
3724          * is correct for a given system. These channels can be enabled at
3725          * run-time through the temp{1-3}_type sysfs accessors if needed.
3726          */
3727
3728         /* Check if voltage monitors are reset manually or by some reason */
3729         tmp = data->read(data, IT87_REG_VIN_ENABLE);
3730         if ((tmp & 0xff) == 0) {
3731                 /* Enable all voltage monitors */
3732                 data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3733         }
3734
3735         /* Check if tachometers are reset manually or by some reason */
3736         mask = 0x70 & ~(sio_data->skip_fan << 4);
3737         data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3738         if ((data->fan_main_ctrl & mask) == 0) {
3739                 /* Enable all fan tachometers */
3740                 data->fan_main_ctrl |= mask;
3741                 data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3742         }
3743         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3744
3745         tmp = data->read(data, IT87_REG_FAN_16BIT);
3746
3747         /* Set tachometers to 16-bit mode if needed */
3748         if (has_fan16_config(data)) {
3749                 if (~tmp & 0x07 & data->has_fan) {
3750                         dev_dbg(&pdev->dev,
3751                                 "Setting fan1-3 to 16-bit mode\n");
3752                         data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3753                 }
3754         }
3755
3756         /* Check for additional fans */
3757         if (has_four_fans(data) && (tmp & BIT(4)))
3758                 data->has_fan |= BIT(3); /* fan4 enabled */
3759         if (has_five_fans(data) && (tmp & BIT(5)))
3760                 data->has_fan |= BIT(4); /* fan5 enabled */
3761         if (has_six_fans(data)) {
3762                 switch (data->type) {
3763                 case it8620:
3764                 case it8628:
3765                 case it8686:
3766                         if (tmp & BIT(2))
3767                                 data->has_fan |= BIT(5); /* fan6 enabled */
3768                         break;
3769                 case it8625:
3770                 case it8665:
3771                         tmp = data->read(data, IT87_REG_FAN_DIV);
3772                         if (tmp & BIT(3))
3773                                 data->has_fan |= BIT(5); /* fan6 enabled */
3774                         break;
3775                 default:
3776                         break;
3777                 }
3778         }
3779
3780         /* Fan input pins may be used for alternative functions */
3781         data->has_fan &= ~sio_data->skip_fan;
3782
3783         /* Check if pwm6 is enabled */
3784         if (has_six_pwm(data)) {
3785                 switch (data->type) {
3786                 case it8620:
3787                 case it8686:
3788                         tmp = data->read(data, IT87_REG_FAN_DIV);
3789                         if (!(tmp & BIT(3)))
3790                                 sio_data->skip_pwm |= BIT(5);
3791                         break;
3792                 default:
3793                         break;
3794                 }
3795         }
3796
3797         if (has_bank_sel(data)) {
3798                 for (i = 0; i < 3; i++)
3799                         data->temp_src[i] =
3800                                 data->read(data, IT87_REG_TEMP_SRC1[i]);
3801                 data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3802         }
3803
3804         /* Start monitoring */
3805         data->write(data, IT87_REG_CONFIG,
3806                     (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3807                                         (update_vbat ? 0x41 : 0x01));
3808 }
3809
3810 /* Return 1 if and only if the PWM interface is safe to use */
3811 static int it87_check_pwm(struct device *dev)
3812 {
3813         struct it87_data *data = dev_get_drvdata(dev);
3814         /*
3815          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3816          * and polarity set to active low is sign that this is the case so we
3817          * disable pwm control to protect the user.
3818          */
3819         int tmp = data->read(data, IT87_REG_FAN_CTL);
3820
3821         if ((tmp & 0x87) == 0) {
3822                 if (fix_pwm_polarity) {
3823                         /*
3824                          * The user asks us to attempt a chip reconfiguration.
3825                          * This means switching to active high polarity and
3826                          * inverting all fan speed values.
3827                          */
3828                         int i;
3829                         u8 pwm[3];
3830
3831                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3832                                 pwm[i] = data->read(data,
3833                                                          data->REG_PWM[i]);
3834
3835                         /*
3836                          * If any fan is in automatic pwm mode, the polarity
3837                          * might be correct, as suspicious as it seems, so we
3838                          * better don't change anything (but still disable the
3839                          * PWM interface).
3840                          */
3841                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3842                                 dev_info(dev,
3843                                          "Reconfiguring PWM to active high polarity\n");
3844                                 data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3845                                 for (i = 0; i < 3; i++)
3846                                         data->write(data, data->REG_PWM[i],
3847                                                     0x7f & ~pwm[i]);
3848                                 return 1;
3849                         }
3850
3851                         dev_info(dev,
3852                                  "PWM configuration is too broken to be fixed\n");
3853                 }
3854
3855                 dev_info(dev,
3856                          "Detected broken BIOS defaults, disabling PWM interface\n");
3857                 return 0;
3858         } else if (fix_pwm_polarity) {
3859                 dev_info(dev,
3860                          "PWM configuration looks sane, won't touch\n");
3861         }
3862
3863         return 1;
3864 }
3865
3866 static int it87_probe(struct platform_device *pdev)
3867 {
3868         struct it87_data *data;
3869         struct resource *res;
3870         struct device *dev = &pdev->dev;
3871         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3872         int enable_pwm_interface;
3873         struct device *hwmon_dev;
3874         int err;
3875
3876         data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3877         if (!data)
3878                 return -ENOMEM;
3879
3880         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3881         if (!res)
3882                 return -EINVAL;
3883         if (res->flags & IORESOURCE_IO) {
3884                 if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3885                                          DRVNAME)) {
3886                         dev_err(dev, "Failed to request region %pR\n", res);
3887                         return -EBUSY;
3888                 }
3889         } else {
3890                 data->mmio = devm_ioremap_resource(dev, res);
3891                 if (IS_ERR(data->mmio))
3892                         return PTR_ERR(data->mmio);
3893         }
3894
3895         data->addr = res->start;
3896         data->type = sio_data->type;
3897         data->sioaddr = sio_data->sioaddr;
3898         data->smbus_bitmap = sio_data->smbus_bitmap;
3899         data->ec_special_config = sio_data->ec_special_config;
3900         data->doexit = sio_data->doexit;
3901         data->features = it87_devices[sio_data->type].features;
3902         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3903         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3904         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3905         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3906         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3907
3908         /*
3909          * IT8705F Datasheet 0.4.1, 3h == Version G.
3910          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3911          * These are the first revisions with 16-bit tachometer support.
3912          */
3913         switch (data->type) {
3914         case it87:
3915                 if (sio_data->revision >= 0x03) {
3916                         data->features &= ~FEAT_OLD_AUTOPWM;
3917                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3918                 }
3919                 break;
3920         case it8712:
3921                 if (sio_data->revision >= 0x08) {
3922                         data->features &= ~FEAT_OLD_AUTOPWM;
3923                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3924                                           FEAT_FIVE_FANS;
3925                 }
3926                 break;
3927         default:
3928                 break;
3929         }
3930
3931         platform_set_drvdata(pdev, data);
3932
3933         mutex_init(&data->update_lock);
3934
3935         /* Initialize register pointers */
3936         it87_init_regs(pdev);
3937
3938         err = smbus_disable(data);
3939         if (err)
3940                 return err;
3941
3942         /* Now, we do the remaining detection. */
3943         if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
3944             data->read(data, IT87_REG_CHIPID) != 0x90) {
3945                 smbus_enable(data);
3946                 return -ENODEV;
3947         }
3948
3949         /* Check PWM configuration */
3950         enable_pwm_interface = it87_check_pwm(dev);
3951
3952         /* Starting with IT8721F, we handle scaling of internal voltages */
3953         if (has_scaling(data)) {
3954                 if (sio_data->internal & BIT(0))
3955                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3956                 if (sio_data->internal & BIT(1))
3957                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3958                 if (sio_data->internal & BIT(2))
3959                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3960                 if (sio_data->internal & BIT(3))
3961                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3962         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3963                    sio_data->type == it8783) {
3964                 if (sio_data->internal & BIT(0))
3965                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3966                 if (sio_data->internal & BIT(1))
3967                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3968         }
3969
3970         data->has_temp = 0x07;
3971         if (sio_data->skip_temp & BIT(2)) {
3972                 if (sio_data->type == it8782 &&
3973                     !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
3974                         data->has_temp &= ~BIT(2);
3975         }
3976
3977         data->in_internal = sio_data->internal;
3978         data->has_in = 0x3ff & ~sio_data->skip_in;
3979
3980         if (has_six_temp(data)) {
3981                 u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
3982
3983                 /* Check for additional temperature sensors */
3984                 if ((reg & 0x03) >= 0x02)
3985                         data->has_temp |= BIT(3);
3986                 if (((reg >> 2) & 0x03) >= 0x02)
3987                         data->has_temp |= BIT(4);
3988                 if (((reg >> 4) & 0x03) >= 0x02)
3989                         data->has_temp |= BIT(5);
3990
3991                 /* Check for additional voltage sensors */
3992                 if ((reg & 0x03) == 0x01)
3993                         data->has_in |= BIT(10);
3994                 if (((reg >> 2) & 0x03) == 0x01)
3995                         data->has_in |= BIT(11);
3996                 if (((reg >> 4) & 0x03) == 0x01)
3997                         data->has_in |= BIT(12);
3998         }
3999
4000         data->has_beep = !!sio_data->beep_pin;
4001
4002         /* Initialize the IT87 chip */
4003         it87_init_device(pdev);
4004
4005         smbus_enable(data);
4006
4007         if (!sio_data->skip_vid) {
4008                 data->has_vid = true;
4009                 data->vrm = vid_which_vrm();
4010                 /* VID reading from Super-I/O config space if available */
4011                 data->vid = sio_data->vid_value;
4012         }
4013
4014         /* Prepare for sysfs hooks */
4015         data->groups[0] = &it87_group;
4016         data->groups[1] = &it87_group_in;
4017         data->groups[2] = &it87_group_temp;
4018         data->groups[3] = &it87_group_fan;
4019
4020         if (enable_pwm_interface) {
4021                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
4022                 data->has_pwm &= ~sio_data->skip_pwm;
4023
4024                 data->groups[4] = &it87_group_pwm;
4025                 if (has_old_autopwm(data) || has_newer_autopwm(data))
4026                         data->groups[5] = &it87_group_auto_pwm;
4027         }
4028
4029         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
4030                                         it87_devices[sio_data->type].name,
4031                                         data, data->groups);
4032         return PTR_ERR_OR_ZERO(hwmon_dev);
4033 }
4034
4035 static struct platform_driver it87_driver = {
4036         .driver = {
4037                 .name   = DRVNAME,
4038         },
4039         .probe  = it87_probe,
4040 };
4041
4042 static int __init it87_device_add(int index, unsigned short sio_address,
4043                                   phys_addr_t mmio_address,
4044                                   const struct it87_sio_data *sio_data)
4045 {
4046         struct platform_device *pdev;
4047         struct resource res = {
4048                 .name   = DRVNAME,
4049         };
4050         int err;
4051
4052         if (mmio_address) {
4053                 res.start = mmio_address;
4054                 res.end = mmio_address + 0x400 - 1;
4055                 res.flags = IORESOURCE_MEM;
4056         } else {
4057                 res.start = sio_address + IT87_EC_OFFSET;
4058                 res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
4059                 res.flags = IORESOURCE_IO;
4060         }
4061
4062         err = acpi_check_resource_conflict(&res);
4063         if (err) {
4064                 if (!ignore_resource_conflict)
4065                         return err;
4066         }
4067
4068         pdev = platform_device_alloc(DRVNAME, sio_address);
4069         if (!pdev)
4070                 return -ENOMEM;
4071
4072         err = platform_device_add_resources(pdev, &res, 1);
4073         if (err) {
4074                 pr_err("Device resource addition failed (%d)\n", err);
4075                 goto exit_device_put;
4076         }
4077
4078         err = platform_device_add_data(pdev, sio_data,
4079                                        sizeof(struct it87_sio_data));
4080         if (err) {
4081                 pr_err("Platform data allocation failed\n");
4082                 goto exit_device_put;
4083         }
4084
4085         err = platform_device_add(pdev);
4086         if (err) {
4087                 pr_err("Device addition failed (%d)\n", err);
4088                 goto exit_device_put;
4089         }
4090
4091         it87_pdev[index] = pdev;
4092         return 0;
4093
4094 exit_device_put:
4095         platform_device_put(pdev);
4096         return err;
4097 }
4098
4099 struct it87_dmi_data {
4100         bool sio2_force_config; /* force sio2 into configuration mode   */
4101         u8 skip_pwm;            /* pwm channels to skip for this board  */
4102 };
4103
4104 /*
4105  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4106  * (IT8792E) needs to be in configuration mode before accessing the first
4107  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4108  * This needs to be done before accessing the first Super-IO chip since
4109  * the second chip may have been accessed prior to loading this driver.
4110  *
4111  * The problem is also reported to affect IT8795E, which is used on X299 boards
4112  * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4113  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4114  * Z87X-OC.
4115  * DMI entries for those systems will be added as they become available and
4116  * as the problem is confirmed to affect those boards.
4117  */
4118 static struct it87_dmi_data gigabyte_sio2_force = {
4119         .sio2_force_config = true,
4120 };
4121
4122 /*
4123  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4124  * connected to a fan, but to something else. One user
4125  * has reported instant system power-off when changing
4126  * the PWM2 duty cycle, so we disable it.
4127  * I use the board name string as the trigger in case
4128  * the same board is ever used in other systems.
4129  */
4130 static struct it87_dmi_data nvidia_fn68pt = {
4131         .skip_pwm = BIT(1),
4132 };
4133
4134 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4135         {
4136                 .matches = {
4137                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4138                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4139                 },
4140                 .driver_data = &gigabyte_sio2_force,
4141         },
4142         {
4143                 .matches = {
4144                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4145                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4146                 },
4147                 .driver_data = &gigabyte_sio2_force,
4148         },
4149         {
4150                 .matches = {
4151                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4152                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4153                 },
4154                 .driver_data = &gigabyte_sio2_force,
4155         },
4156         {
4157                 .matches = {
4158                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4159                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4160                 },
4161                 .driver_data = &nvidia_fn68pt,
4162         },
4163         { }
4164 };
4165
4166 static int __init sm_it87_init(void)
4167 {
4168         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4169         struct it87_dmi_data *dmi_data = NULL;
4170         int sioaddr[2] = { REG_2E, REG_4E };
4171         struct it87_sio_data sio_data;
4172         unsigned short isa_address;
4173         phys_addr_t mmio_address;
4174         bool found = false;
4175         int i, err;
4176
4177         pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4178
4179         if (dmi)
4180                 dmi_data = dmi->driver_data;
4181
4182         err = platform_driver_register(&it87_driver);
4183         if (err)
4184                 return err;
4185
4186         if (dmi_data && dmi_data->sio2_force_config)
4187                 __superio_enter(REG_4E);
4188
4189         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4190                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4191                 isa_address = 0;
4192                 mmio_address = 0;
4193                 err = it87_find(sioaddr[i], &isa_address, &mmio_address,
4194                                 &sio_data);
4195                 if (err || isa_address == 0)
4196                         continue;
4197
4198                 if (dmi_data)
4199                         sio_data.skip_pwm |= dmi_data->skip_pwm;
4200                 err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4201                 if (err)
4202                         goto exit_dev_unregister;
4203                 found = true;
4204         }
4205
4206         if (!found) {
4207                 err = -ENODEV;
4208                 goto exit_unregister;
4209         }
4210         return 0;
4211
4212 exit_dev_unregister:
4213         /* NULL check handled by platform_device_unregister */
4214         platform_device_unregister(it87_pdev[0]);
4215 exit_unregister:
4216         platform_driver_unregister(&it87_driver);
4217         return err;
4218 }
4219
4220 static void __exit sm_it87_exit(void)
4221 {
4222         /* NULL check handled by platform_device_unregister */
4223         platform_device_unregister(it87_pdev[1]);
4224         platform_device_unregister(it87_pdev[0]);
4225         platform_driver_unregister(&it87_driver);
4226 }
4227
4228 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4229 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4230 module_param(update_vbat, bool, 0);
4231 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4232 module_param(fix_pwm_polarity, bool, 0);
4233 MODULE_PARM_DESC(fix_pwm_polarity,
4234                  "Force PWM polarity to active high (DANGEROUS)");
4235 MODULE_LICENSE("GPL");
4236
4237 module_init(sm_it87_init);
4238 module_exit(sm_it87_exit);