git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77 #include "version.h"
  78
  79 #define DRVNAME "it87"
  80
  81 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  82              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  83              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  84              it8655, it8665, it8686 };
  85
  86 static unsigned short force_id;
  87 module_param(force_id, ushort, 0);
  88 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  89
  90 static bool ignore_resource_conflict;
  91 module_param(ignore_resource_conflict, bool, 0);
  92 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
  93
  94 static struct platform_device *it87_pdev[2];
  95
  96 #define REG_2E  0x2e    /* The register to read/write */
  97 #define REG_4E  0x4e    /* Secondary register to read/write */
  98
  99 #define DEV     0x07    /* Register: Logical device select */
 100 #define PME     0x04    /* The device with the fan registers in it */
 101
 102 /* The device with the IT8718F/IT8720F VID value in it */
 103 #define GPIO    0x07
 104
 105 #define DEVID   0x20    /* Register: Device ID */
 106 #define DEVREV  0x22    /* Register: Device Revision */
 107
 108 static inline void __superio_enter(int ioreg)
 109 {
 110         outb(0x87, ioreg);
 111         outb(0x01, ioreg);
 112         outb(0x55, ioreg);
 113         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 114 }
 115
 116 static inline int superio_inb(int ioreg, int reg)
 117 {
 118         int val;
 119
 120         outb(reg, ioreg);
 121         val = inb(ioreg + 1);
 122
 123         return val;
 124 }
 125
 126 static inline void superio_outb(int ioreg, int reg, int val)
 127 {
 128         outb(reg, ioreg);
 129         outb(val, ioreg + 1);
 130 }
 131
 132 static int superio_inw(int ioreg, int reg)
 133 {
 134         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 135 }
 136
 137 static inline void superio_select(int ioreg, int ldn)
 138 {
 139         outb(DEV, ioreg);
 140         outb(ldn, ioreg + 1);
 141 }
 142
 143 static inline int superio_enter(int ioreg)
 144 {
 145         /*
 146          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 147          */
 148         if (!request_muxed_region(ioreg, 2, DRVNAME))
 149                 goto error;
 150
 151         __superio_enter(ioreg);
 152         return 0;
 153
 154 error:
 155         return -EBUSY;
 156 }
 157
 158 static inline void superio_exit(int ioreg, bool doexit)
 159 {
 160         if (doexit) {
 161                 outb(0x02, ioreg);
 162                 outb(0x02, ioreg + 1);
 163         }
 164         release_region(ioreg, 2);
 165 }
 166
 167 /* Logical device 4 registers */
 168 #define IT8712F_DEVID 0x8712
 169 #define IT8705F_DEVID 0x8705
 170 #define IT8716F_DEVID 0x8716
 171 #define IT8718F_DEVID 0x8718
 172 #define IT8720F_DEVID 0x8720
 173 #define IT8721F_DEVID 0x8721
 174 #define IT8726F_DEVID 0x8726
 175 #define IT8728F_DEVID 0x8728
 176 #define IT8732F_DEVID 0x8732
 177 #define IT8792E_DEVID 0x8733
 178 #define IT8771E_DEVID 0x8771
 179 #define IT8772E_DEVID 0x8772
 180 #define IT8781F_DEVID 0x8781
 181 #define IT8782F_DEVID 0x8782
 182 #define IT8783E_DEVID 0x8783
 183 #define IT8786E_DEVID 0x8786
 184 #define IT8790E_DEVID 0x8790
 185 #define IT8603E_DEVID 0x8603
 186 #define IT8607E_DEVID 0x8607
 187 #define IT8613E_DEVID 0x8613
 188 #define IT8620E_DEVID 0x8620
 189 #define IT8622E_DEVID 0x8622
 190 #define IT8623E_DEVID 0x8623
 191 #define IT8625E_DEVID 0x8625
 192 #define IT8628E_DEVID 0x8628
 193 #define IT8655E_DEVID 0x8655
 194 #define IT8665E_DEVID 0x8665
 195 #define IT8686E_DEVID 0x8686
 196 #define IT87_ACT_REG  0x30
 197 #define IT87_BASE_REG 0x60
 198
 199 /* Logical device 7 registers (IT8712F and later) */
 200 #define IT87_SIO_GPIO1_REG      0x25
 201 #define IT87_SIO_GPIO2_REG      0x26
 202 #define IT87_SIO_GPIO3_REG      0x27
 203 #define IT87_SIO_GPIO4_REG      0x28
 204 #define IT87_SIO_GPIO5_REG      0x29
 205 #define IT87_SIO_GPIO9_REG      0xd3
 206 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 207 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 208 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 209 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 210 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 211 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 212
 213 /* Update battery voltage after every reading if true */
 214 static bool update_vbat;
 215
 216 /* Not all BIOSes properly configure the PWM registers */
 217 static bool fix_pwm_polarity;
 218
 219 /* Many IT87 constants specified below */
 220
 221 /* Length of ISA address segment */
 222 #define IT87_EXTENT 8
 223
 224 /* Length of ISA address segment for Environmental Controller */
 225 #define IT87_EC_EXTENT 2
 226
 227 /* Offset of EC registers from ISA base address */
 228 #define IT87_EC_OFFSET 5
 229
 230 /* Where are the ISA address/data registers relative to the EC base address */
 231 #define IT87_ADDR_REG_OFFSET 0
 232 #define IT87_DATA_REG_OFFSET 1
 233
 234 /*----- The IT87 registers -----*/
 235
 236 #define IT87_REG_CONFIG        0x00
 237
 238 #define IT87_REG_ALARM1        0x01
 239 #define IT87_REG_ALARM2        0x02
 240 #define IT87_REG_ALARM3        0x03
 241
 242 #define IT87_REG_BANK           0x06
 243
 244 /*
 245  * The IT8718F and IT8720F have the VID value in a different register, in
 246  * Super-I/O configuration space.
 247  */
 248 #define IT87_REG_VID           0x0a
 249 /*
 250  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 251  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 252  * mode.
 253  */
 254 #define IT87_REG_FAN_DIV       0x0b
 255 #define IT87_REG_FAN_16BIT     0x0c
 256
 257 /*
 258  * Monitors:
 259  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 260  * - up to 6 temp (1 to 6)
 261  * - up to 6 fan (1 to 6)
 262  */
 263
 264 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 265 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 266 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 267 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 268
 269 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 270 static const u8 IT87_REG_FAN_MIN_8665[] =
 271                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 272 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 273 static const u8 IT87_REG_FANX_MIN_8665[] =
 274                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 275
 276 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 277
 278 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 279
 280 #define IT87_REG_FAN_MAIN_CTRL 0x13
 281 #define IT87_REG_FAN_CTL       0x14
 282
 283 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 284 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 285
 286 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 287
 288 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 289                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 290
 291 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 292
 293 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 294 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 295
 296 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 297 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 298
 299 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 300                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 301 static const u8 IT87_REG_TEMP_LOW_8686[] =
 302                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 303
 304 #define IT87_REG_VIN_ENABLE    0x50
 305 #define IT87_REG_TEMP_ENABLE   0x51
 306 #define IT87_REG_TEMP_EXTRA    0x55
 307 #define IT87_REG_BEEP_ENABLE   0x5c
 308
 309 #define IT87_REG_CHIPID        0x58
 310
 311 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 312
 313 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 314 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 315
 316 #define IT87_REG_TEMP456_ENABLE 0x77
 317
 318 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 319 #define IT87_REG_TEMP_SRC2      0x23d
 320
 321 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 322 #define NUM_VIN_LIMIT           8
 323 #define NUM_TEMP                6
 324 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 325 #define NUM_FAN_DIV             3
 326 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 327 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 328
 329 struct it87_devices {
 330         const char *name;
 331         const char * const suffix;
 332         u32 features;
 333         u8 num_temp_limit;
 334         u8 num_temp_offset;
 335         u8 num_temp_map;        /* Number of temperature sources for pwm */
 336         u8 peci_mask;
 337         u8 old_peci_mask;
 338 };
 339
 340 #define FEAT_12MV_ADC           BIT(0)
 341 #define FEAT_NEWER_AUTOPWM      BIT(1)
 342 #define FEAT_OLD_AUTOPWM        BIT(2)
 343 #define FEAT_16BIT_FANS         BIT(3)
 344 #define FEAT_TEMP_PECI          BIT(5)
 345 #define FEAT_TEMP_OLD_PECI      BIT(6)
 346 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 347 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 348 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 349 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 350 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 351 #define FEAT_10_9MV_ADC         BIT(12)
 352 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 353 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 354 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 355 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 356 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 357 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 358 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 359 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 360 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 361 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 362 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 363 #define FEAT_11MV_ADC           BIT(24)
 364 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 365
 366 static const struct it87_devices it87_devices[] = {
 367         [it87] = {
 368                 .name = "it87",
 369                 .suffix = "F",
 370                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 371                                                 /* may need to overwrite */
 372                 .num_temp_limit = 3,
 373                 .num_temp_offset = 0,
 374                 .num_temp_map = 3,
 375         },
 376         [it8712] = {
 377                 .name = "it8712",
 378                 .suffix = "F",
 379                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 380                                                 /* may need to overwrite */
 381                 .num_temp_limit = 3,
 382                 .num_temp_offset = 0,
 383                 .num_temp_map = 3,
 384         },
 385         [it8716] = {
 386                 .name = "it8716",
 387                 .suffix = "F",
 388                 .features = FEAT_16BIT_FANS | FEAT_VID
 389                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 390                   | FEAT_FANCTL_ONOFF,
 391                 .num_temp_limit = 3,
 392                 .num_temp_offset = 3,
 393                 .num_temp_map = 3,
 394         },
 395         [it8718] = {
 396                 .name = "it8718",
 397                 .suffix = "F",
 398                 .features = FEAT_16BIT_FANS | FEAT_VID
 399                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 400                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 401                 .num_temp_limit = 3,
 402                 .num_temp_offset = 3,
 403                 .num_temp_map = 3,
 404                 .old_peci_mask = 0x4,
 405         },
 406         [it8720] = {
 407                 .name = "it8720",
 408                 .suffix = "F",
 409                 .features = FEAT_16BIT_FANS | FEAT_VID
 410                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 411                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 412                 .num_temp_limit = 3,
 413                 .num_temp_offset = 3,
 414                 .num_temp_map = 3,
 415                 .old_peci_mask = 0x4,
 416         },
 417         [it8721] = {
 418                 .name = "it8721",
 419                 .suffix = "F",
 420                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 421                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 422                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 423                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 424                 .num_temp_limit = 3,
 425                 .num_temp_offset = 3,
 426                 .num_temp_map = 3,
 427                 .peci_mask = 0x05,
 428                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 429         },
 430         [it8728] = {
 431                 .name = "it8728",
 432                 .suffix = "F",
 433                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 434                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 435                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 436                   | FEAT_FANCTL_ONOFF,
 437                 .num_temp_limit = 6,
 438                 .num_temp_offset = 3,
 439                 .num_temp_map = 3,
 440                 .peci_mask = 0x07,
 441         },
 442         [it8732] = {
 443                 .name = "it8732",
 444                 .suffix = "F",
 445                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 446                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 447                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 448                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 449                 .num_temp_limit = 3,
 450                 .num_temp_offset = 3,
 451                 .num_temp_map = 3,
 452                 .peci_mask = 0x07,
 453                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 454         },
 455         [it8771] = {
 456                 .name = "it8771",
 457                 .suffix = "E",
 458                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 459                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 460                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 461                                 /* PECI: guesswork */
 462                                 /* 12mV ADC (OHM) */
 463                                 /* 16 bit fans (OHM) */
 464                                 /* three fans, always 16 bit (guesswork) */
 465                 .num_temp_limit = 3,
 466                 .num_temp_offset = 3,
 467                 .num_temp_map = 3,
 468                 .peci_mask = 0x07,
 469         },
 470         [it8772] = {
 471                 .name = "it8772",
 472                 .suffix = "E",
 473                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 474                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 475                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 476                                 /* PECI (coreboot) */
 477                                 /* 12mV ADC (HWSensors4, OHM) */
 478                                 /* 16 bit fans (HWSensors4, OHM) */
 479                                 /* three fans, always 16 bit (datasheet) */
 480                 .num_temp_limit = 3,
 481                 .num_temp_offset = 3,
 482                 .num_temp_map = 3,
 483                 .peci_mask = 0x07,
 484         },
 485         [it8781] = {
 486                 .name = "it8781",
 487                 .suffix = "F",
 488                 .features = FEAT_16BIT_FANS
 489                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 490                   | FEAT_FANCTL_ONOFF,
 491                 .num_temp_limit = 3,
 492                 .num_temp_offset = 3,
 493                 .num_temp_map = 3,
 494                 .old_peci_mask = 0x4,
 495         },
 496         [it8782] = {
 497                 .name = "it8782",
 498                 .suffix = "F",
 499                 .features = FEAT_16BIT_FANS
 500                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 501                   | FEAT_FANCTL_ONOFF,
 502                 .num_temp_limit = 3,
 503                 .num_temp_offset = 3,
 504                 .num_temp_map = 3,
 505                 .old_peci_mask = 0x4,
 506         },
 507         [it8783] = {
 508                 .name = "it8783",
 509                 .suffix = "E/F",
 510                 .features = FEAT_16BIT_FANS
 511                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 512                   | FEAT_FANCTL_ONOFF,
 513                 .num_temp_limit = 3,
 514                 .num_temp_offset = 3,
 515                 .num_temp_map = 3,
 516                 .old_peci_mask = 0x4,
 517         },
 518         [it8786] = {
 519                 .name = "it8786",
 520                 .suffix = "E",
 521                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 522                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 523                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 524                 .num_temp_limit = 3,
 525                 .num_temp_offset = 3,
 526                 .num_temp_map = 3,
 527                 .peci_mask = 0x07,
 528         },
 529         [it8790] = {
 530                 .name = "it8790",
 531                 .suffix = "E",
 532                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 533                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 534                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 535                 .num_temp_limit = 3,
 536                 .num_temp_offset = 3,
 537                 .num_temp_map = 3,
 538                 .peci_mask = 0x07,
 539         },
 540         [it8792] = {
 541                 .name = "it8792",
 542                 .suffix = "E",
 543                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 544                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 545                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 546                 .num_temp_limit = 3,
 547                 .num_temp_offset = 3,
 548                 .num_temp_map = 3,
 549                 .peci_mask = 0x07,
 550         },
 551         [it8603] = {
 552                 .name = "it8603",
 553                 .suffix = "E",
 554                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 555                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 556                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 557                 .num_temp_limit = 3,
 558                 .num_temp_offset = 3,
 559                 .num_temp_map = 4,
 560                 .peci_mask = 0x07,
 561         },
 562         [it8607] = {
 563                 .name = "it8607",
 564                 .suffix = "E",
 565                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 566                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 567                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 568                   | FEAT_FANCTL_ONOFF,
 569                 .num_temp_limit = 3,
 570                 .num_temp_offset = 3,
 571                 .num_temp_map = 6,
 572                 .peci_mask = 0x07,
 573         },
 574         [it8613] = {
 575                 .name = "it8613",
 576                 .suffix = "E",
 577                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 578                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 579                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 580                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 581                 .num_temp_limit = 6,
 582                 .num_temp_offset = 6,
 583                 .num_temp_map = 6,
 584                 .peci_mask = 0x07,
 585         },
 586         [it8620] = {
 587                 .name = "it8620",
 588                 .suffix = "E",
 589                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 590                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 591                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 592                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 593                   | FEAT_FANCTL_ONOFF,
 594                 .num_temp_limit = 3,
 595                 .num_temp_offset = 3,
 596                 .num_temp_map = 3,
 597                 .peci_mask = 0x07,
 598         },
 599         [it8622] = {
 600                 .name = "it8622",
 601                 .suffix = "E",
 602                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 603                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 604                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 605                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 606                 .num_temp_limit = 3,
 607                 .num_temp_offset = 3,
 608                 .num_temp_map = 4,
 609                 .peci_mask = 0x07,
 610         },
 611         [it8625] = {
 612                 .name = "it8625",
 613                 .suffix = "E",
 614                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 615                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 616                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 617                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 618                 .num_temp_limit = 6,
 619                 .num_temp_offset = 6,
 620                 .num_temp_map = 6,
 621         },
 622         [it8628] = {
 623                 .name = "it8628",
 624                 .suffix = "E",
 625                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 626                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 627                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 628                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 629                   | FEAT_FANCTL_ONOFF,
 630                 .num_temp_limit = 6,
 631                 .num_temp_offset = 3,
 632                 .num_temp_map = 3,
 633                 .peci_mask = 0x07,
 634         },
 635         [it8655] = {
 636                 .name = "it8655",
 637                 .suffix = "E",
 638                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 639                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 640                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 641                 .num_temp_limit = 6,
 642                 .num_temp_offset = 6,
 643                 .num_temp_map = 6,
 644         },
 645         [it8665] = {
 646                 .name = "it8665",
 647                 .suffix = "E",
 648                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 649                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 650                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 651                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 652                 .num_temp_limit = 6,
 653                 .num_temp_offset = 6,
 654                 .num_temp_map = 6,
 655         },
 656         [it8686] = {
 657                 .name = "it8686",
 658                 .suffix = "E",
 659                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 660                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 661                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 662                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 663                 .num_temp_limit = 6,
 664                 .num_temp_offset = 6,
 665                 .num_temp_map = 7,
 666         },
 667 };
 668
 669 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 670 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 671 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 672 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 673 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 674 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 675                                  ((data)->peci_mask & BIT(nr)))
 676 #define has_temp_old_peci(data, nr) \
 677                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 678                                  ((data)->old_peci_mask & BIT(nr)))
 679 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 680 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 681                                                      FEAT_SIX_FANS))
 682 #define has_vid(data)           ((data)->features & FEAT_VID)
 683 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 684 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 685 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 686 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 687                                                      | FEAT_SIX_PWM))
 688 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 689 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 690 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 691 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 692 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 693                                                      FEAT_FIVE_FANS | \
 694                                                      FEAT_SIX_FANS))
 695 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 696                                                      FEAT_FIVE_PWM \
 697                                                      | FEAT_SIX_PWM))
 698 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 699 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 700 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 701 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 702 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 703
 704 struct it87_sio_data {
 705         enum chips type;
 706         /* Values read from Super-I/O config space */
 707         u8 revision;
 708         u8 vid_value;
 709         u8 beep_pin;
 710         u8 internal;    /* Internal sensors can be labeled */
 711         /* Features skipped based on config or DMI */
 712         u16 skip_in;
 713         u8 skip_vid;
 714         u8 skip_fan;
 715         u8 skip_pwm;
 716         u8 skip_temp;
 717 };
 718
 719 /*
 720  * For each registered chip, we need to keep some data in memory.
 721  * The structure is dynamically allocated.
 722  */
 723 struct it87_data {
 724         const struct attribute_group *groups[7];
 725         enum chips type;
 726         u32 features;
 727         u8 peci_mask;
 728         u8 old_peci_mask;
 729
 730         const u8 *REG_FAN;
 731         const u8 *REG_FANX;
 732         const u8 *REG_FAN_MIN;
 733         const u8 *REG_FANX_MIN;
 734
 735         const u8 *REG_PWM;
 736
 737         const u8 *REG_TEMP_OFFSET;
 738         const u8 *REG_TEMP_LOW;
 739         const u8 *REG_TEMP_HIGH;
 740
 741         unsigned short addr;
 742         const char *name;
 743         struct mutex update_lock;
 744         char valid;             /* !=0 if following fields are valid */
 745         unsigned long last_updated;     /* In jiffies */
 746
 747         u16 in_scaled;          /* Internal voltage sensors are scaled */
 748         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 749         u16 has_in;             /* Bitfield, voltage sensors enabled */
 750         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 751         u8 has_fan;             /* Bitfield, fans enabled */
 752         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 753         u8 has_temp;            /* Bitfield, temp sensors enabled */
 754         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 755         u8 num_temp_limit;      /* Number of temperature limit registers */
 756         u8 num_temp_offset;     /* Number of temperature offset registers */
 757         u8 temp_src[4];         /* Up to 4 temperature source registers */
 758         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 759         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 760         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 761         bool has_vid;           /* True if VID supported */
 762         u8 vid;                 /* Register encoding, combined */
 763         u8 vrm;
 764         u32 alarms;             /* Register encoding, combined */
 765         bool has_beep;          /* true if beep supported */
 766         u8 beeps;               /* Register encoding */
 767         u8 fan_main_ctrl;       /* Register value */
 768         u8 fan_ctl;             /* Register value */
 769
 770         /*
 771          * The following 3 arrays correspond to the same registers up to
 772          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 773          * 7, and we want to preserve settings on mode changes, so we have
 774          * to track all values separately.
 775          * Starting with the IT8721F, the manual PWM duty cycles are stored
 776          * in separate registers (8-bit values), so the separate tracking
 777          * is no longer needed, but it is still done to keep the driver
 778          * simple.
 779          */
 780         u8 has_pwm;             /* Bitfield, pwm control enabled */
 781         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 782         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 783         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 784         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 785         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 786         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 787
 788         /* Automatic fan speed control registers */
 789         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 790         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 791 };
 792
 793 static int adc_lsb(const struct it87_data *data, int nr)
 794 {
 795         int lsb;
 796
 797         if (has_12mv_adc(data))
 798                 lsb = 120;
 799         else if (has_10_9mv_adc(data))
 800                 lsb = 109;
 801         else if (has_11mv_adc(data))
 802                 lsb = 110;
 803         else
 804                 lsb = 160;
 805         if (data->in_scaled & BIT(nr))
 806                 lsb <<= 1;
 807         return lsb;
 808 }
 809
 810 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 811 {
 812         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 813         return clamp_val(val, 0, 255);
 814 }
 815
 816 static int in_from_reg(const struct it87_data *data, int nr, int val)
 817 {
 818         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 819 }
 820
 821 static inline u8 FAN_TO_REG(long rpm, int div)
 822 {
 823         if (rpm == 0)
 824                 return 255;
 825         rpm = clamp_val(rpm, 1, 1000000);
 826         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 827 }
 828
 829 static inline u16 FAN16_TO_REG(long rpm)
 830 {
 831         if (rpm == 0)
 832                 return 0xffff;
 833         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 834 }
 835
 836 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 837                                 1350000 / ((val) * (div)))
 838 /* The divider is fixed to 2 in 16-bit mode */
 839 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 840                              1350000 / ((val) * 2))
 841
 842 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 843                                     ((val) + 500) / 1000), -128, 127))
 844 #define TEMP_FROM_REG(val) ((val) * 1000)
 845
 846 static u8 pwm_to_reg(const struct it87_data *data, long val)
 847 {
 848         if (has_newer_autopwm(data))
 849                 return val;
 850         else
 851                 return val >> 1;
 852 }
 853
 854 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 855 {
 856         if (has_newer_autopwm(data))
 857                 return reg;
 858         else
 859                 return (reg & 0x7f) << 1;
 860 }
 861
 862 static int DIV_TO_REG(int val)
 863 {
 864         int answer = 0;
 865
 866         while (answer < 7 && (val >>= 1))
 867                 answer++;
 868         return answer;
 869 }
 870
 871 #define DIV_FROM_REG(val) BIT(val)
 872
 873 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 874 {
 875         u8 map;
 876
 877         map  = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 878         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 879                 map = 0;
 880
 881         return map;
 882 }
 883
 884 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 885 {
 886         u8 ctrl = data->pwm_ctrl[nr];
 887
 888         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 889                (map << data->pwm_temp_map_shift);
 890 }
 891
 892 /*
 893  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 894  * depending on the chip type, to calculate the actual PWM frequency.
 895  *
 896  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 897  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 898  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 899  * sometimes just one. It is unknown if this is a datasheet error or real,
 900  * so this is ignored for now.
 901  */
 902 static const unsigned int pwm_freq[8] = {
 903         48000000,
 904         24000000,
 905         12000000,
 906         8000000,
 907         6000000,
 908         3000000,
 909         1500000,
 910         750000,
 911 };
 912
 913 static int _it87_read_value(struct it87_data *data, u8 reg)
 914 {
 915         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 916         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 917 }
 918
 919 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 920 {
 921         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 922         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 923 }
 924
 925 static u8 it87_set_bank(struct it87_data *data, u8 bank)
 926 {
 927         u8 _bank = bank;
 928
 929         if (has_bank_sel(data)) {
 930                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 931
 932                 _bank = breg >> 5;
 933                 if (bank != _bank) {
 934                         breg &= 0x1f;
 935                         breg |= (bank << 5);
 936                         _it87_write_value(data, IT87_REG_BANK, breg);
 937                 }
 938         }
 939         return _bank;
 940 }
 941
 942 /*
 943  * Must be called with data->update_lock held, except during initialization.
 944  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 945  * would slow down the IT87 access and should not be necessary.
 946  */
 947 static int it87_read_value(struct it87_data *data, u16 reg)
 948 {
 949         u8 bank;
 950         int val;
 951
 952         bank = it87_set_bank(data, reg >> 8);
 953         val = _it87_read_value(data, reg & 0xff);
 954         it87_set_bank(data, bank);
 955
 956         return val;
 957 }
 958
 959 /*
 960  * Must be called with data->update_lock held, except during initialization.
 961  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 962  * would slow down the IT87 access and should not be necessary.
 963  */
 964 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
 965 {
 966         u8 bank;
 967
 968         bank = it87_set_bank(data, reg >> 8);
 969         _it87_write_value(data, reg & 0xff, value);
 970         it87_set_bank(data, bank);
 971 }
 972
 973 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 974 {
 975         u8 ctrl;
 976
 977         ctrl = it87_read_value(data, data->REG_PWM[nr]);
 978         data->pwm_ctrl[nr] = ctrl;
 979         if (has_newer_autopwm(data)) {
 980                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
 981                 data->pwm_duty[nr] = it87_read_value(data,
 982                                                      IT87_REG_PWM_DUTY[nr]);
 983         } else {
 984                 if (ctrl & 0x80)        /* Automatic mode */
 985                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
 986                 else                            /* Manual mode */
 987                         data->pwm_duty[nr] = ctrl & 0x7f;
 988         }
 989
 990         if (has_old_autopwm(data)) {
 991                 int i;
 992
 993                 for (i = 0; i < 5 ; i++)
 994                         data->auto_temp[nr][i] = it87_read_value(data,
 995                                                 IT87_REG_AUTO_TEMP(nr, i));
 996                 for (i = 0; i < 3 ; i++)
 997                         data->auto_pwm[nr][i] = it87_read_value(data,
 998                                                 IT87_REG_AUTO_PWM(nr, i));
 999         } else if (has_newer_autopwm(data)) {
1000                 int i;
1001
1002                 /*
1003                  * 0: temperature hysteresis (base + 5)
1004                  * 1: fan off temperature (base + 0)
1005                  * 2: fan start temperature (base + 1)
1006                  * 3: fan max temperature (base + 2)
1007                  */
1008                 data->auto_temp[nr][0] =
1009                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
1010
1011                 for (i = 0; i < 3 ; i++)
1012                         data->auto_temp[nr][i + 1] =
1013                                 it87_read_value(data,
1014                                                 IT87_REG_AUTO_TEMP(nr, i));
1015                 /*
1016                  * 0: start pwm value (base + 3)
1017                  * 1: pwm slope (base + 4, 1/8th pwm)
1018                  */
1019                 data->auto_pwm[nr][0] =
1020                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
1021                 data->auto_pwm[nr][1] =
1022                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
1023         }
1024 }
1025
1026 static struct it87_data *it87_update_device(struct device *dev)
1027 {
1028         struct it87_data *data = dev_get_drvdata(dev);
1029         int i;
1030
1031         mutex_lock(&data->update_lock);
1032
1033         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1034             !data->valid) {
1035                 if (update_vbat) {
1036                         /*
1037                          * Cleared after each update, so reenable.  Value
1038                          * returned by this read will be previous value
1039                          */
1040                         it87_write_value(data, IT87_REG_CONFIG,
1041                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1042                 }
1043                 for (i = 0; i < NUM_VIN; i++) {
1044                         if (!(data->has_in & BIT(i)))
1045                                 continue;
1046
1047                         data->in[i][0] =
1048                                 it87_read_value(data, IT87_REG_VIN[i]);
1049
1050                         /* VBAT and AVCC don't have limit registers */
1051                         if (i >= NUM_VIN_LIMIT)
1052                                 continue;
1053
1054                         data->in[i][1] =
1055                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
1056                         data->in[i][2] =
1057                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
1058                 }
1059
1060                 for (i = 0; i < NUM_FAN; i++) {
1061                         /* Skip disabled fans */
1062                         if (!(data->has_fan & BIT(i)))
1063                                 continue;
1064
1065                         data->fan[i][1] =
1066                                 it87_read_value(data, data->REG_FAN_MIN[i]);
1067                         data->fan[i][0] = it87_read_value(data,
1068                                        data->REG_FAN[i]);
1069                         /* Add high byte if in 16-bit mode */
1070                         if (has_16bit_fans(data)) {
1071                                 data->fan[i][0] |= it87_read_value(data,
1072                                                 data->REG_FANX[i]) << 8;
1073                                 data->fan[i][1] |= it87_read_value(data,
1074                                                 data->REG_FANX_MIN[i]) << 8;
1075                         }
1076                 }
1077                 for (i = 0; i < NUM_TEMP; i++) {
1078                         if (!(data->has_temp & BIT(i)))
1079                                 continue;
1080                         data->temp[i][0] =
1081                                 it87_read_value(data, IT87_REG_TEMP(i));
1082
1083                         if (i >= data->num_temp_limit)
1084                                 continue;
1085
1086                         if (i < data->num_temp_offset)
1087                                 data->temp[i][3] =
1088                                   it87_read_value(data,
1089                                                   data->REG_TEMP_OFFSET[i]);
1090
1091                         data->temp[i][1] =
1092                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1093                         data->temp[i][2] =
1094                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1095                 }
1096
1097                 /* Newer chips don't have clock dividers */
1098                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1099                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1100                         data->fan_div[0] = i & 0x07;
1101                         data->fan_div[1] = (i >> 3) & 0x07;
1102                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1103                 }
1104
1105                 data->alarms =
1106                         it87_read_value(data, IT87_REG_ALARM1) |
1107                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1108                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1109                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1110
1111                 data->fan_main_ctrl = it87_read_value(data,
1112                                 IT87_REG_FAN_MAIN_CTRL);
1113                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1114                 for (i = 0; i < NUM_PWM; i++) {
1115                         if (!(data->has_pwm & BIT(i)))
1116                                 continue;
1117                         it87_update_pwm_ctrl(data, i);
1118                 }
1119
1120                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1121                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1122                 /*
1123                  * The IT8705F does not have VID capability.
1124                  * The IT8718F and later don't use IT87_REG_VID for the
1125                  * same purpose.
1126                  */
1127                 if (data->type == it8712 || data->type == it8716) {
1128                         data->vid = it87_read_value(data, IT87_REG_VID);
1129                         /*
1130                          * The older IT8712F revisions had only 5 VID pins,
1131                          * but we assume it is always safe to read 6 bits.
1132                          */
1133                         data->vid &= 0x3f;
1134                 }
1135                 data->last_updated = jiffies;
1136                 data->valid = 1;
1137         }
1138
1139         mutex_unlock(&data->update_lock);
1140
1141         return data;
1142 }
1143
1144 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1145                        char *buf)
1146 {
1147         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1148         struct it87_data *data = it87_update_device(dev);
1149         int index = sattr->index;
1150         int nr = sattr->nr;
1151
1152         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1153 }
1154
1155 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1156                       const char *buf, size_t count)
1157 {
1158         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1159         struct it87_data *data = dev_get_drvdata(dev);
1160         int index = sattr->index;
1161         int nr = sattr->nr;
1162         unsigned long val;
1163
1164         if (kstrtoul(buf, 10, &val) < 0)
1165                 return -EINVAL;
1166
1167         mutex_lock(&data->update_lock);
1168         data->in[nr][index] = in_to_reg(data, nr, val);
1169         it87_write_value(data,
1170                          index == 1 ? IT87_REG_VIN_MIN(nr)
1171                                     : IT87_REG_VIN_MAX(nr),
1172                          data->in[nr][index]);
1173         mutex_unlock(&data->update_lock);
1174         return count;
1175 }
1176
1177 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1178 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1179                             0, 1);
1180 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1181                             0, 2);
1182
1183 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1184 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1185                             1, 1);
1186 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1187                             1, 2);
1188
1189 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1190 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1191                             2, 1);
1192 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1193                             2, 2);
1194
1195 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1196 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1197                             3, 1);
1198 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1199                             3, 2);
1200
1201 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1202 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1203                             4, 1);
1204 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1205                             4, 2);
1206
1207 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1208 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1209                             5, 1);
1210 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1211                             5, 2);
1212
1213 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1214 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1215                             6, 1);
1216 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1217                             6, 2);
1218
1219 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1220 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1221                             7, 1);
1222 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1223                             7, 2);
1224
1225 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1226 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1227 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1228 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1229 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1230
1231 /* Up to 6 temperatures */
1232 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1233                          char *buf)
1234 {
1235         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1236         int nr = sattr->nr;
1237         int index = sattr->index;
1238         struct it87_data *data = it87_update_device(dev);
1239
1240         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1241 }
1242
1243 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1244                         const char *buf, size_t count)
1245 {
1246         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1247         int nr = sattr->nr;
1248         int index = sattr->index;
1249         struct it87_data *data = dev_get_drvdata(dev);
1250         long val;
1251         u8 reg, regval;
1252
1253         if (kstrtol(buf, 10, &val) < 0)
1254                 return -EINVAL;
1255
1256         mutex_lock(&data->update_lock);
1257
1258         switch (index) {
1259         default:
1260         case 1:
1261                 reg = data->REG_TEMP_LOW[nr];
1262                 break;
1263         case 2:
1264                 reg = data->REG_TEMP_HIGH[nr];
1265                 break;
1266         case 3:
1267                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1268                 if (!(regval & 0x80)) {
1269                         regval |= 0x80;
1270                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1271                 }
1272                 data->valid = 0;
1273                 reg = data->REG_TEMP_OFFSET[nr];
1274                 break;
1275         }
1276
1277         data->temp[nr][index] = TEMP_TO_REG(val);
1278         it87_write_value(data, reg, data->temp[nr][index]);
1279         mutex_unlock(&data->update_lock);
1280         return count;
1281 }
1282
1283 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1284 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1285                             0, 1);
1286 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1287                             0, 2);
1288 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1289                             set_temp, 0, 3);
1290 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1291 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1292                             1, 1);
1293 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1294                             1, 2);
1295 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1296                             set_temp, 1, 3);
1297 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1298 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1299                             2, 1);
1300 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1301                             2, 2);
1302 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1303                             set_temp, 2, 3);
1304 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1305 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1306                             3, 1);
1307 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1308                             3, 2);
1309 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1310                             set_temp, 3, 3);
1311 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1312 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1313                             4, 1);
1314 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1315                             4, 2);
1316 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1317                             set_temp, 4, 3);
1318 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1319 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1320                             5, 1);
1321 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1322                             5, 2);
1323 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1324                             set_temp, 5, 3);
1325
1326 static const u8 temp_types_8686[NUM_TEMP][9] = {
1327         { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1328         { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1329         { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1330         { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1331         { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1332         { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1333 };
1334
1335 static int get_temp_type(struct it87_data *data, int index)
1336 {
1337         u8 reg, extra;
1338         int type = 0;
1339
1340         if (has_bank_sel(data)) {
1341                 u8 src1, src2;
1342
1343                 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1344
1345                 switch (data->type) {
1346                 case it8686:
1347                         if (src1 < 9)
1348                                 type = temp_types_8686[index][src1];
1349                         break;
1350                 case it8625:
1351                         if (index < 3)
1352                                 break;
1353                 case it8655:
1354                 case it8665:
1355                         if (src1 < 3) {
1356                                 index = src1;
1357                                 break;
1358                         }
1359                         src2 = data->temp_src[3];
1360                         switch(src1) {
1361                         case 3:
1362                                 type = (src2 & BIT(index)) ? 6 : 5;
1363                                 break;
1364                         case 4 ... 8:
1365                                 type = (src2 & BIT(index)) ? 4 : 6;
1366                                 break;
1367                         case 9:
1368                                 type = (src2 & BIT(index)) ? 5 : 0;
1369                                 break;
1370                         default:
1371                                 break;
1372                         }
1373                         return type;
1374                 default:
1375                         return 0;
1376                 }
1377         }
1378         if (type || index >= 3)
1379                 return type;
1380
1381         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1382         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1383
1384         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1385             (has_temp_old_peci(data, index) && (extra & 0x80)))
1386                 type = 6;               /* Intel PECI */
1387         if (reg & BIT(index))
1388                 type = 3;               /* thermal diode */
1389         else if (reg & BIT(index + 3))
1390                 type = 4;               /* thermistor */
1391
1392         return type;
1393 }
1394
1395 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1396                               char *buf)
1397 {
1398         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1399         struct it87_data *data = it87_update_device(dev);
1400         int type = get_temp_type(data, sensor_attr->index);
1401
1402         return sprintf(buf, "%d\n", type);
1403 }
1404
1405 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1406                              const char *buf, size_t count)
1407 {
1408         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1409         int nr = sensor_attr->index;
1410
1411         struct it87_data *data = dev_get_drvdata(dev);
1412         long val;
1413         u8 reg, extra;
1414
1415         if (kstrtol(buf, 10, &val) < 0)
1416                 return -EINVAL;
1417
1418         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1419         reg &= ~(1 << nr);
1420         reg &= ~(8 << nr);
1421         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1422                 reg &= 0x3f;
1423         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1424         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1425                 extra &= 0x7f;
1426         if (val == 2) { /* backwards compatibility */
1427                 dev_warn(dev,
1428                          "Sensor type 2 is deprecated, please use 4 instead\n");
1429                 val = 4;
1430         }
1431         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1432         if (val == 3)
1433                 reg |= 1 << nr;
1434         else if (val == 4)
1435                 reg |= 8 << nr;
1436         else if (has_temp_peci(data, nr) && val == 6)
1437                 reg |= (nr + 1) << 6;
1438         else if (has_temp_old_peci(data, nr) && val == 6)
1439                 extra |= 0x80;
1440         else if (val != 0)
1441                 return -EINVAL;
1442
1443         mutex_lock(&data->update_lock);
1444         data->sensor = reg;
1445         data->extra = extra;
1446         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1447         if (has_temp_old_peci(data, nr))
1448                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1449         data->valid = 0;        /* Force cache refresh */
1450         mutex_unlock(&data->update_lock);
1451         return count;
1452 }
1453
1454 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1455                           set_temp_type, 0);
1456 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1457                           set_temp_type, 1);
1458 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1459                           set_temp_type, 2);
1460 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1461                           set_temp_type, 3);
1462 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1463                           set_temp_type, 4);
1464 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1465                           set_temp_type, 5);
1466
1467 /* 6 Fans */
1468
1469 static int pwm_mode(const struct it87_data *data, int nr)
1470 {
1471         if (has_fanctl_onoff(data) && nr < 3 &&
1472             !(data->fan_main_ctrl & BIT(nr)))
1473                 return 0;                               /* Full speed */
1474         if (data->pwm_ctrl[nr] & 0x80)
1475                 return 2;                               /* Automatic mode */
1476         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1477             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1478                 return 0;                       /* Full speed */
1479
1480         return 1;                               /* Manual mode */
1481 }
1482
1483 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1484                         char *buf)
1485 {
1486         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1487         int nr = sattr->nr;
1488         int index = sattr->index;
1489         int speed;
1490         struct it87_data *data = it87_update_device(dev);
1491
1492         speed = has_16bit_fans(data) ?
1493                 FAN16_FROM_REG(data->fan[nr][index]) :
1494                 FAN_FROM_REG(data->fan[nr][index],
1495                              DIV_FROM_REG(data->fan_div[nr]));
1496         return sprintf(buf, "%d\n", speed);
1497 }
1498
1499 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1500                             char *buf)
1501 {
1502         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1503         struct it87_data *data = it87_update_device(dev);
1504         int nr = sensor_attr->index;
1505
1506         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1507 }
1508
1509 static ssize_t show_pwm_enable(struct device *dev,
1510                                struct device_attribute *attr, char *buf)
1511 {
1512         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1513         struct it87_data *data = it87_update_device(dev);
1514         int nr = sensor_attr->index;
1515
1516         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1517 }
1518
1519 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1520                         char *buf)
1521 {
1522         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1523         struct it87_data *data = it87_update_device(dev);
1524         int nr = sensor_attr->index;
1525
1526         return sprintf(buf, "%d\n",
1527                        pwm_from_reg(data, data->pwm_duty[nr]));
1528 }
1529
1530 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1531                              char *buf)
1532 {
1533         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1534         struct it87_data *data = it87_update_device(dev);
1535         int nr = sensor_attr->index;
1536         unsigned int freq;
1537         int index;
1538
1539         if (has_pwm_freq2(data) && nr == 1)
1540                 index = (data->extra >> 4) & 0x07;
1541         else
1542                 index = (data->fan_ctl >> 4) & 0x07;
1543
1544         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1545
1546         return sprintf(buf, "%u\n", freq);
1547 }
1548
1549 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1550                        const char *buf, size_t count)
1551 {
1552         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1553         int nr = sattr->nr;
1554         int index = sattr->index;
1555
1556         struct it87_data *data = dev_get_drvdata(dev);
1557         long val;
1558         u8 reg;
1559
1560         if (kstrtol(buf, 10, &val) < 0)
1561                 return -EINVAL;
1562
1563         mutex_lock(&data->update_lock);
1564
1565         if (has_16bit_fans(data)) {
1566                 data->fan[nr][index] = FAN16_TO_REG(val);
1567                 it87_write_value(data, data->REG_FAN_MIN[nr],
1568                                  data->fan[nr][index] & 0xff);
1569                 it87_write_value(data, data->REG_FANX_MIN[nr],
1570                                  data->fan[nr][index] >> 8);
1571         } else {
1572                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1573                 switch (nr) {
1574                 case 0:
1575                         data->fan_div[nr] = reg & 0x07;
1576                         break;
1577                 case 1:
1578                         data->fan_div[nr] = (reg >> 3) & 0x07;
1579                         break;
1580                 case 2:
1581                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1582                         break;
1583                 }
1584                 data->fan[nr][index] =
1585                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1586                 it87_write_value(data, data->REG_FAN_MIN[nr],
1587                                  data->fan[nr][index]);
1588         }
1589
1590         mutex_unlock(&data->update_lock);
1591         return count;
1592 }
1593
1594 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1595                            const char *buf, size_t count)
1596 {
1597         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1598         struct it87_data *data = dev_get_drvdata(dev);
1599         int nr = sensor_attr->index;
1600         unsigned long val;
1601         int min;
1602         u8 old;
1603
1604         if (kstrtoul(buf, 10, &val) < 0)
1605                 return -EINVAL;
1606
1607         mutex_lock(&data->update_lock);
1608         old = it87_read_value(data, IT87_REG_FAN_DIV);
1609
1610         /* Save fan min limit */
1611         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1612
1613         switch (nr) {
1614         case 0:
1615         case 1:
1616                 data->fan_div[nr] = DIV_TO_REG(val);
1617                 break;
1618         case 2:
1619                 if (val < 8)
1620                         data->fan_div[nr] = 1;
1621                 else
1622                         data->fan_div[nr] = 3;
1623         }
1624         val = old & 0x80;
1625         val |= (data->fan_div[0] & 0x07);
1626         val |= (data->fan_div[1] & 0x07) << 3;
1627         if (data->fan_div[2] == 3)
1628                 val |= 0x1 << 6;
1629         it87_write_value(data, IT87_REG_FAN_DIV, val);
1630
1631         /* Restore fan min limit */
1632         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1633         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1634
1635         mutex_unlock(&data->update_lock);
1636         return count;
1637 }
1638
1639 /* Returns 0 if OK, -EINVAL otherwise */
1640 static int check_trip_points(struct device *dev, int nr)
1641 {
1642         const struct it87_data *data = dev_get_drvdata(dev);
1643         int i, err = 0;
1644
1645         if (has_old_autopwm(data)) {
1646                 for (i = 0; i < 3; i++) {
1647                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1648                                 err = -EINVAL;
1649                 }
1650                 for (i = 0; i < 2; i++) {
1651                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1652                                 err = -EINVAL;
1653                 }
1654         } else if (has_newer_autopwm(data)) {
1655                 for (i = 1; i < 3; i++) {
1656                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1657                                 err = -EINVAL;
1658                 }
1659         }
1660
1661         if (err) {
1662                 dev_err(dev,
1663                         "Inconsistent trip points, not switching to automatic mode\n");
1664                 dev_err(dev, "Adjust the trip points and try again\n");
1665         }
1666         return err;
1667 }
1668
1669 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1670                               const char *buf, size_t count)
1671 {
1672         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1673         struct it87_data *data = dev_get_drvdata(dev);
1674         int nr = sensor_attr->index;
1675         long val;
1676
1677         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1678                 return -EINVAL;
1679
1680         /* Check trip points before switching to automatic mode */
1681         if (val == 2) {
1682                 if (check_trip_points(dev, nr) < 0)
1683                         return -EINVAL;
1684         }
1685
1686         mutex_lock(&data->update_lock);
1687         it87_update_pwm_ctrl(data, nr);
1688
1689         if (val == 0) {
1690                 if (nr < 3 && has_fanctl_onoff(data)) {
1691                         int tmp;
1692                         /* make sure the fan is on when in on/off mode */
1693                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1694                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1695                         /* set on/off mode */
1696                         data->fan_main_ctrl &= ~BIT(nr);
1697                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1698                                          data->fan_main_ctrl);
1699                 } else {
1700                         u8 ctrl;
1701
1702                         /* No on/off mode, set maximum pwm value */
1703                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1704                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1705                                          data->pwm_duty[nr]);
1706                         /* and set manual mode */
1707                         if (has_newer_autopwm(data)) {
1708                                 ctrl = temp_map_to_reg(data, nr,
1709                                                        data->pwm_temp_map[nr]);
1710                                 ctrl &= 0x7f;
1711                         } else {
1712                                 ctrl = data->pwm_duty[nr];
1713                         }
1714                         data->pwm_ctrl[nr] = ctrl;
1715                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1716                 }
1717         } else {
1718                 u8 ctrl;
1719
1720                 if (has_newer_autopwm(data)) {
1721                         ctrl = temp_map_to_reg(data, nr,
1722                                                data->pwm_temp_map[nr]);
1723                         if (val == 1)
1724                                 ctrl &= 0x7f;
1725                         else
1726                                 ctrl |= 0x80;
1727                 } else {
1728                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1729                 }
1730                 data->pwm_ctrl[nr] = ctrl;
1731                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1732
1733                 if (has_fanctl_onoff(data) && nr < 3) {
1734                         /* set SmartGuardian mode */
1735                         data->fan_main_ctrl |= BIT(nr);
1736                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1737                                          data->fan_main_ctrl);
1738                 }
1739         }
1740
1741         mutex_unlock(&data->update_lock);
1742         return count;
1743 }
1744
1745 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1746                        const char *buf, size_t count)
1747 {
1748         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1749         struct it87_data *data = dev_get_drvdata(dev);
1750         int nr = sensor_attr->index;
1751         long val;
1752
1753         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1754                 return -EINVAL;
1755
1756         mutex_lock(&data->update_lock);
1757         it87_update_pwm_ctrl(data, nr);
1758         if (has_newer_autopwm(data)) {
1759                 /*
1760                  * If we are in automatic mode, the PWM duty cycle register
1761                  * is read-only so we can't write the value.
1762                  */
1763                 if (data->pwm_ctrl[nr] & 0x80) {
1764                         mutex_unlock(&data->update_lock);
1765                         return -EBUSY;
1766                 }
1767                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1768                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1769                                  data->pwm_duty[nr]);
1770         } else {
1771                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1772                 /*
1773                  * If we are in manual mode, write the duty cycle immediately;
1774                  * otherwise, just store it for later use.
1775                  */
1776                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1777                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1778                         it87_write_value(data, data->REG_PWM[nr],
1779                                          data->pwm_ctrl[nr]);
1780                 }
1781         }
1782         mutex_unlock(&data->update_lock);
1783         return count;
1784 }
1785
1786 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1787                             const char *buf, size_t count)
1788 {
1789         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1790         struct it87_data *data = dev_get_drvdata(dev);
1791         int nr = sensor_attr->index;
1792         unsigned long val;
1793         int i;
1794
1795         if (kstrtoul(buf, 10, &val) < 0)
1796                 return -EINVAL;
1797
1798         val = clamp_val(val, 0, 1000000);
1799         val *= has_newer_autopwm(data) ? 256 : 128;
1800
1801         /* Search for the nearest available frequency */
1802         for (i = 0; i < 7; i++) {
1803                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1804                         break;
1805         }
1806
1807         mutex_lock(&data->update_lock);
1808         if (nr == 0) {
1809                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1810                 data->fan_ctl |= i << 4;
1811                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1812         } else {
1813                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1814                 data->extra |= i << 4;
1815                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1816         }
1817         mutex_unlock(&data->update_lock);
1818
1819         return count;
1820 }
1821
1822 static ssize_t show_pwm_temp_map(struct device *dev,
1823                                  struct device_attribute *attr, char *buf)
1824 {
1825         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1826         struct it87_data *data = it87_update_device(dev);
1827         int nr = sensor_attr->index;
1828
1829         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1830 }
1831
1832 static ssize_t set_pwm_temp_map(struct device *dev,
1833                                 struct device_attribute *attr, const char *buf,
1834                                 size_t count)
1835 {
1836         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1837         struct it87_data *data = dev_get_drvdata(dev);
1838         int nr = sensor_attr->index;
1839         unsigned long val;
1840         u8 map;
1841
1842         if (kstrtoul(buf, 10, &val) < 0)
1843                 return -EINVAL;
1844
1845         if (!val || val > data->pwm_num_temp_map)
1846                 return -EINVAL;
1847
1848         map = val - 1;
1849
1850         mutex_lock(&data->update_lock);
1851         it87_update_pwm_ctrl(data, nr);
1852         data->pwm_temp_map[nr] = map;
1853         /*
1854          * If we are in automatic mode, write the temp mapping immediately;
1855          * otherwise, just store it for later use.
1856          */
1857         if (data->pwm_ctrl[nr] & 0x80) {
1858                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
1859                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1860         }
1861         mutex_unlock(&data->update_lock);
1862         return count;
1863 }
1864
1865 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1866                              char *buf)
1867 {
1868         struct it87_data *data = it87_update_device(dev);
1869         struct sensor_device_attribute_2 *sensor_attr =
1870                         to_sensor_dev_attr_2(attr);
1871         int nr = sensor_attr->nr;
1872         int point = sensor_attr->index;
1873
1874         return sprintf(buf, "%d\n",
1875                        pwm_from_reg(data, data->auto_pwm[nr][point]));
1876 }
1877
1878 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1879                             const char *buf, size_t count)
1880 {
1881         struct it87_data *data = dev_get_drvdata(dev);
1882         struct sensor_device_attribute_2 *sensor_attr =
1883                         to_sensor_dev_attr_2(attr);
1884         int nr = sensor_attr->nr;
1885         int point = sensor_attr->index;
1886         int regaddr;
1887         long val;
1888
1889         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1890                 return -EINVAL;
1891
1892         mutex_lock(&data->update_lock);
1893         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1894         if (has_newer_autopwm(data))
1895                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1896         else
1897                 regaddr = IT87_REG_AUTO_PWM(nr, point);
1898         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1899         mutex_unlock(&data->update_lock);
1900         return count;
1901 }
1902
1903 static ssize_t show_auto_pwm_slope(struct device *dev,
1904                                    struct device_attribute *attr, char *buf)
1905 {
1906         struct it87_data *data = it87_update_device(dev);
1907         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1908         int nr = sensor_attr->index;
1909
1910         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1911 }
1912
1913 static ssize_t set_auto_pwm_slope(struct device *dev,
1914                                   struct device_attribute *attr,
1915                                   const char *buf, size_t count)
1916 {
1917         struct it87_data *data = dev_get_drvdata(dev);
1918         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1919         int nr = sensor_attr->index;
1920         unsigned long val;
1921
1922         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1923                 return -EINVAL;
1924
1925         mutex_lock(&data->update_lock);
1926         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1927         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1928                          data->auto_pwm[nr][1]);
1929         mutex_unlock(&data->update_lock);
1930         return count;
1931 }
1932
1933 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1934                               char *buf)
1935 {
1936         struct it87_data *data = it87_update_device(dev);
1937         struct sensor_device_attribute_2 *sensor_attr =
1938                         to_sensor_dev_attr_2(attr);
1939         int nr = sensor_attr->nr;
1940         int point = sensor_attr->index;
1941         int reg;
1942
1943         if (has_old_autopwm(data) || point)
1944                 reg = data->auto_temp[nr][point];
1945         else
1946                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1947
1948         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1949 }
1950
1951 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1952                              const char *buf, size_t count)
1953 {
1954         struct it87_data *data = dev_get_drvdata(dev);
1955         struct sensor_device_attribute_2 *sensor_attr =
1956                         to_sensor_dev_attr_2(attr);
1957         int nr = sensor_attr->nr;
1958         int point = sensor_attr->index;
1959         long val;
1960         int reg;
1961
1962         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1963                 return -EINVAL;
1964
1965         mutex_lock(&data->update_lock);
1966         if (has_newer_autopwm(data) && !point) {
1967                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1968                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1969                 data->auto_temp[nr][0] = reg;
1970                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1971         } else {
1972                 reg = TEMP_TO_REG(val);
1973                 data->auto_temp[nr][point] = reg;
1974                 if (has_newer_autopwm(data))
1975                         point--;
1976                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1977         }
1978         mutex_unlock(&data->update_lock);
1979         return count;
1980 }
1981
1982 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1983 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1984                             0, 1);
1985 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1986                           set_fan_div, 0);
1987
1988 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1989 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1990                             1, 1);
1991 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1992                           set_fan_div, 1);
1993
1994 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1995 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1996                             2, 1);
1997 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1998                           set_fan_div, 2);
1999
2000 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2001 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2002                             3, 1);
2003
2004 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2005 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2006                             4, 1);
2007
2008 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2009 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2010                             5, 1);
2011
2012 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2013                           show_pwm_enable, set_pwm_enable, 0);
2014 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2015 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2016                           set_pwm_freq, 0);
2017 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2018                           show_pwm_temp_map, set_pwm_temp_map, 0);
2019 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2020                             show_auto_pwm, set_auto_pwm, 0, 0);
2021 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2022                             show_auto_pwm, set_auto_pwm, 0, 1);
2023 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2024                             show_auto_pwm, set_auto_pwm, 0, 2);
2025 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2026                             show_auto_pwm, NULL, 0, 3);
2027 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2028                             show_auto_temp, set_auto_temp, 0, 1);
2029 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2030                             show_auto_temp, set_auto_temp, 0, 0);
2031 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2032                             show_auto_temp, set_auto_temp, 0, 2);
2033 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2034                             show_auto_temp, set_auto_temp, 0, 3);
2035 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2036                             show_auto_temp, set_auto_temp, 0, 4);
2037 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2038                             show_auto_pwm, set_auto_pwm, 0, 0);
2039 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2040                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2041
2042 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2043                           show_pwm_enable, set_pwm_enable, 1);
2044 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2045 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2046 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2047                           show_pwm_temp_map, set_pwm_temp_map, 1);
2048 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2049                             show_auto_pwm, set_auto_pwm, 1, 0);
2050 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2051                             show_auto_pwm, set_auto_pwm, 1, 1);
2052 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2053                             show_auto_pwm, set_auto_pwm, 1, 2);
2054 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2055                             show_auto_pwm, NULL, 1, 3);
2056 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2057                             show_auto_temp, set_auto_temp, 1, 1);
2058 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2059                             show_auto_temp, set_auto_temp, 1, 0);
2060 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2061                             show_auto_temp, set_auto_temp, 1, 2);
2062 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2063                             show_auto_temp, set_auto_temp, 1, 3);
2064 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2065                             show_auto_temp, set_auto_temp, 1, 4);
2066 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2067                             show_auto_pwm, set_auto_pwm, 1, 0);
2068 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2069                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2070
2071 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2072                           show_pwm_enable, set_pwm_enable, 2);
2073 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2074 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2075 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2076                           show_pwm_temp_map, set_pwm_temp_map, 2);
2077 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2078                             show_auto_pwm, set_auto_pwm, 2, 0);
2079 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2080                             show_auto_pwm, set_auto_pwm, 2, 1);
2081 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2082                             show_auto_pwm, set_auto_pwm, 2, 2);
2083 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2084                             show_auto_pwm, NULL, 2, 3);
2085 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2086                             show_auto_temp, set_auto_temp, 2, 1);
2087 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2088                             show_auto_temp, set_auto_temp, 2, 0);
2089 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2090                             show_auto_temp, set_auto_temp, 2, 2);
2091 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2092                             show_auto_temp, set_auto_temp, 2, 3);
2093 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2094                             show_auto_temp, set_auto_temp, 2, 4);
2095 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2096                             show_auto_pwm, set_auto_pwm, 2, 0);
2097 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2098                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2099
2100 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2101                           show_pwm_enable, set_pwm_enable, 3);
2102 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2103 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2104 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2105                           show_pwm_temp_map, set_pwm_temp_map, 3);
2106 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2107                             show_auto_temp, set_auto_temp, 2, 1);
2108 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2109                             show_auto_temp, set_auto_temp, 2, 0);
2110 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2111                             show_auto_temp, set_auto_temp, 2, 2);
2112 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2113                             show_auto_temp, set_auto_temp, 2, 3);
2114 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2115                             show_auto_pwm, set_auto_pwm, 3, 0);
2116 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2117                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2118
2119 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2120                           show_pwm_enable, set_pwm_enable, 4);
2121 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2122 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2123 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2124                           show_pwm_temp_map, set_pwm_temp_map, 4);
2125 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2126                             show_auto_temp, set_auto_temp, 2, 1);
2127 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2128                             show_auto_temp, set_auto_temp, 2, 0);
2129 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2130                             show_auto_temp, set_auto_temp, 2, 2);
2131 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2132                             show_auto_temp, set_auto_temp, 2, 3);
2133 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2134                             show_auto_pwm, set_auto_pwm, 4, 0);
2135 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2136                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2137
2138 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2139                           show_pwm_enable, set_pwm_enable, 5);
2140 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2141 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2142 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2143                           show_pwm_temp_map, set_pwm_temp_map, 5);
2144 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2145                             show_auto_temp, set_auto_temp, 2, 1);
2146 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2147                             show_auto_temp, set_auto_temp, 2, 0);
2148 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2149                             show_auto_temp, set_auto_temp, 2, 2);
2150 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2151                             show_auto_temp, set_auto_temp, 2, 3);
2152 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2153                             show_auto_pwm, set_auto_pwm, 5, 0);
2154 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2155                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2156
2157 /* Alarms */
2158 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2159                            char *buf)
2160 {
2161         struct it87_data *data = it87_update_device(dev);
2162
2163         return sprintf(buf, "%u\n", data->alarms);
2164 }
2165 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2166
2167 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2168                           char *buf)
2169 {
2170         struct it87_data *data = it87_update_device(dev);
2171         int bitnr = to_sensor_dev_attr(attr)->index;
2172
2173         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2174 }
2175
2176 static ssize_t clear_intrusion(struct device *dev,
2177                                struct device_attribute *attr, const char *buf,
2178                                size_t count)
2179 {
2180         struct it87_data *data = dev_get_drvdata(dev);
2181         int config;
2182         long val;
2183
2184         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2185                 return -EINVAL;
2186
2187         mutex_lock(&data->update_lock);
2188         config = it87_read_value(data, IT87_REG_CONFIG);
2189         if (config < 0) {
2190                 count = config;
2191         } else {
2192                 config |= BIT(5);
2193                 it87_write_value(data, IT87_REG_CONFIG, config);
2194                 /* Invalidate cache to force re-read */
2195                 data->valid = 0;
2196         }
2197         mutex_unlock(&data->update_lock);
2198
2199         return count;
2200 }
2201
2202 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2203 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2204 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2205 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2206 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2207 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2208 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2209 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2210 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2211 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2212 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2213 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2214 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2215 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2216 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2217 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2218 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2219 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2220 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2221 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2222 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2223                           show_alarm, clear_intrusion, 4);
2224
2225 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2226                          char *buf)
2227 {
2228         struct it87_data *data = it87_update_device(dev);
2229         int bitnr = to_sensor_dev_attr(attr)->index;
2230
2231         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2232 }
2233
2234 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2235                         const char *buf, size_t count)
2236 {
2237         int bitnr = to_sensor_dev_attr(attr)->index;
2238         struct it87_data *data = dev_get_drvdata(dev);
2239         long val;
2240
2241         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2242                 return -EINVAL;
2243
2244         mutex_lock(&data->update_lock);
2245         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2246         if (val)
2247                 data->beeps |= BIT(bitnr);
2248         else
2249                 data->beeps &= ~BIT(bitnr);
2250         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2251         mutex_unlock(&data->update_lock);
2252         return count;
2253 }
2254
2255 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2256                           show_beep, set_beep, 1);
2257 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2258 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2259 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2260 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2261 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2262 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2263 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2264 /* fanX_beep writability is set later */
2265 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2266 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2267 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2268 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2269 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2270 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2271 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2272                           show_beep, set_beep, 2);
2273 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2274 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2275 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2276 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2277 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2278
2279 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2280                             char *buf)
2281 {
2282         struct it87_data *data = dev_get_drvdata(dev);
2283
2284         return sprintf(buf, "%u\n", data->vrm);
2285 }
2286
2287 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2288                              const char *buf, size_t count)
2289 {
2290         struct it87_data *data = dev_get_drvdata(dev);
2291         unsigned long val;
2292
2293         if (kstrtoul(buf, 10, &val) < 0)
2294                 return -EINVAL;
2295
2296         data->vrm = val;
2297
2298         return count;
2299 }
2300 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2301
2302 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2303                             char *buf)
2304 {
2305         struct it87_data *data = it87_update_device(dev);
2306
2307         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2308 }
2309 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2310
2311 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2312                           char *buf)
2313 {
2314         static const char * const labels[] = {
2315                 "+5V",
2316                 "5VSB",
2317                 "Vbat",
2318                 "AVCC",
2319         };
2320         static const char * const labels_it8721[] = {
2321                 "+3.3V",
2322                 "3VSB",
2323                 "Vbat",
2324                 "+3.3V",
2325         };
2326         struct it87_data *data = dev_get_drvdata(dev);
2327         int nr = to_sensor_dev_attr(attr)->index;
2328         const char *label;
2329
2330         if (has_vin3_5v(data) && nr == 0)
2331                 label = labels[0];
2332         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2333                  has_11mv_adc(data))
2334                 label = labels_it8721[nr];
2335         else
2336                 label = labels[nr];
2337
2338         return sprintf(buf, "%s\n", label);
2339 }
2340 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2341 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2342 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2343 /* AVCC3 */
2344 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2345
2346 static umode_t it87_in_is_visible(struct kobject *kobj,
2347                                   struct attribute *attr, int index)
2348 {
2349         struct device *dev = container_of(kobj, struct device, kobj);
2350         struct it87_data *data = dev_get_drvdata(dev);
2351         int i = index / 5;      /* voltage index */
2352         int a = index % 5;      /* attribute index */
2353
2354         if (index >= 40) {      /* in8 and higher only have input attributes */
2355                 i = index - 40 + 8;
2356                 a = 0;
2357         }
2358
2359         if (!(data->has_in & BIT(i)))
2360                 return 0;
2361
2362         if (a == 4 && !data->has_beep)
2363                 return 0;
2364
2365         return attr->mode;
2366 }
2367
2368 static struct attribute *it87_attributes_in[] = {
2369         &sensor_dev_attr_in0_input.dev_attr.attr,
2370         &sensor_dev_attr_in0_min.dev_attr.attr,
2371         &sensor_dev_attr_in0_max.dev_attr.attr,
2372         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2373         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2374
2375         &sensor_dev_attr_in1_input.dev_attr.attr,
2376         &sensor_dev_attr_in1_min.dev_attr.attr,
2377         &sensor_dev_attr_in1_max.dev_attr.attr,
2378         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2379         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2380
2381         &sensor_dev_attr_in2_input.dev_attr.attr,
2382         &sensor_dev_attr_in2_min.dev_attr.attr,
2383         &sensor_dev_attr_in2_max.dev_attr.attr,
2384         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2385         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2386
2387         &sensor_dev_attr_in3_input.dev_attr.attr,
2388         &sensor_dev_attr_in3_min.dev_attr.attr,
2389         &sensor_dev_attr_in3_max.dev_attr.attr,
2390         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2391         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2392
2393         &sensor_dev_attr_in4_input.dev_attr.attr,
2394         &sensor_dev_attr_in4_min.dev_attr.attr,
2395         &sensor_dev_attr_in4_max.dev_attr.attr,
2396         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2397         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2398
2399         &sensor_dev_attr_in5_input.dev_attr.attr,
2400         &sensor_dev_attr_in5_min.dev_attr.attr,
2401         &sensor_dev_attr_in5_max.dev_attr.attr,
2402         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2403         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2404
2405         &sensor_dev_attr_in6_input.dev_attr.attr,
2406         &sensor_dev_attr_in6_min.dev_attr.attr,
2407         &sensor_dev_attr_in6_max.dev_attr.attr,
2408         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2409         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2410
2411         &sensor_dev_attr_in7_input.dev_attr.attr,
2412         &sensor_dev_attr_in7_min.dev_attr.attr,
2413         &sensor_dev_attr_in7_max.dev_attr.attr,
2414         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2415         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2416
2417         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2418         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2419         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2420         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2421         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2422         NULL
2423 };
2424
2425 static const struct attribute_group it87_group_in = {
2426         .attrs = it87_attributes_in,
2427         .is_visible = it87_in_is_visible,
2428 };
2429
2430 static umode_t it87_temp_is_visible(struct kobject *kobj,
2431                                     struct attribute *attr, int index)
2432 {
2433         struct device *dev = container_of(kobj, struct device, kobj);
2434         struct it87_data *data = dev_get_drvdata(dev);
2435         int i = index / 7;      /* temperature index */
2436         int a = index % 7;      /* attribute index */
2437
2438         if (!(data->has_temp & BIT(i)))
2439                 return 0;
2440
2441         if (a && i >= data->num_temp_limit)
2442                 return 0;
2443
2444         if (a == 3) {
2445                 int type = get_temp_type(data, i);
2446
2447                 if (type == 0)
2448                         return 0;
2449                 if (has_bank_sel(data))
2450                         return 0444;
2451                 return attr->mode;
2452         }
2453
2454         if (a == 5 && i >= data->num_temp_offset)
2455                 return 0;
2456
2457         if (a == 6 && !data->has_beep)
2458                 return 0;
2459
2460         return attr->mode;
2461 }
2462
2463 static struct attribute *it87_attributes_temp[] = {
2464         &sensor_dev_attr_temp1_input.dev_attr.attr,
2465         &sensor_dev_attr_temp1_max.dev_attr.attr,
2466         &sensor_dev_attr_temp1_min.dev_attr.attr,
2467         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2468         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2469         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2470         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2471
2472         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2473         &sensor_dev_attr_temp2_max.dev_attr.attr,
2474         &sensor_dev_attr_temp2_min.dev_attr.attr,
2475         &sensor_dev_attr_temp2_type.dev_attr.attr,
2476         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2477         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2478         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2479
2480         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2481         &sensor_dev_attr_temp3_max.dev_attr.attr,
2482         &sensor_dev_attr_temp3_min.dev_attr.attr,
2483         &sensor_dev_attr_temp3_type.dev_attr.attr,
2484         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2485         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2486         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2487
2488         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2489         &sensor_dev_attr_temp4_max.dev_attr.attr,
2490         &sensor_dev_attr_temp4_min.dev_attr.attr,
2491         &sensor_dev_attr_temp4_type.dev_attr.attr,
2492         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2493         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2494         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2495
2496         &sensor_dev_attr_temp5_input.dev_attr.attr,
2497         &sensor_dev_attr_temp5_max.dev_attr.attr,
2498         &sensor_dev_attr_temp5_min.dev_attr.attr,
2499         &sensor_dev_attr_temp5_type.dev_attr.attr,
2500         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2501         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2502         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2503
2504         &sensor_dev_attr_temp6_input.dev_attr.attr,
2505         &sensor_dev_attr_temp6_max.dev_attr.attr,
2506         &sensor_dev_attr_temp6_min.dev_attr.attr,
2507         &sensor_dev_attr_temp6_type.dev_attr.attr,
2508         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2509         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2510         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2511         NULL
2512 };
2513
2514 static const struct attribute_group it87_group_temp = {
2515         .attrs = it87_attributes_temp,
2516         .is_visible = it87_temp_is_visible,
2517 };
2518
2519 static umode_t it87_is_visible(struct kobject *kobj,
2520                                struct attribute *attr, int index)
2521 {
2522         struct device *dev = container_of(kobj, struct device, kobj);
2523         struct it87_data *data = dev_get_drvdata(dev);
2524
2525         if ((index == 2 || index == 3) && !data->has_vid)
2526                 return 0;
2527
2528         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2529                 return 0;
2530
2531         return attr->mode;
2532 }
2533
2534 static struct attribute *it87_attributes[] = {
2535         &dev_attr_alarms.attr,
2536         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2537         &dev_attr_vrm.attr,                             /* 2 */
2538         &dev_attr_cpu0_vid.attr,                        /* 3 */
2539         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2540         &sensor_dev_attr_in7_label.dev_attr.attr,
2541         &sensor_dev_attr_in8_label.dev_attr.attr,
2542         &sensor_dev_attr_in9_label.dev_attr.attr,
2543         NULL
2544 };
2545
2546 static const struct attribute_group it87_group = {
2547         .attrs = it87_attributes,
2548         .is_visible = it87_is_visible,
2549 };
2550
2551 static umode_t it87_fan_is_visible(struct kobject *kobj,
2552                                    struct attribute *attr, int index)
2553 {
2554         struct device *dev = container_of(kobj, struct device, kobj);
2555         struct it87_data *data = dev_get_drvdata(dev);
2556         int i = index / 5;      /* fan index */
2557         int a = index % 5;      /* attribute index */
2558
2559         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2560                 i = (index - 15) / 4 + 3;
2561                 a = (index - 15) % 4;
2562         }
2563
2564         if (!(data->has_fan & BIT(i)))
2565                 return 0;
2566
2567         if (a == 3) {                           /* beep */
2568                 if (!data->has_beep)
2569                         return 0;
2570                 /* first fan beep attribute is writable */
2571                 if (i == __ffs(data->has_fan))
2572                         return attr->mode | S_IWUSR;
2573         }
2574
2575         if (a == 4 && has_16bit_fans(data))     /* divisor */
2576                 return 0;
2577
2578         return attr->mode;
2579 }
2580
2581 static struct attribute *it87_attributes_fan[] = {
2582         &sensor_dev_attr_fan1_input.dev_attr.attr,
2583         &sensor_dev_attr_fan1_min.dev_attr.attr,
2584         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2585         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2586         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2587
2588         &sensor_dev_attr_fan2_input.dev_attr.attr,
2589         &sensor_dev_attr_fan2_min.dev_attr.attr,
2590         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2591         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2592         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2593
2594         &sensor_dev_attr_fan3_input.dev_attr.attr,
2595         &sensor_dev_attr_fan3_min.dev_attr.attr,
2596         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2597         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2598         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2599
2600         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2601         &sensor_dev_attr_fan4_min.dev_attr.attr,
2602         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2603         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2604
2605         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2606         &sensor_dev_attr_fan5_min.dev_attr.attr,
2607         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2608         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2609
2610         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2611         &sensor_dev_attr_fan6_min.dev_attr.attr,
2612         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2613         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2614         NULL
2615 };
2616
2617 static const struct attribute_group it87_group_fan = {
2618         .attrs = it87_attributes_fan,
2619         .is_visible = it87_fan_is_visible,
2620 };
2621
2622 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2623                                    struct attribute *attr, int index)
2624 {
2625         struct device *dev = container_of(kobj, struct device, kobj);
2626         struct it87_data *data = dev_get_drvdata(dev);
2627         int i = index / 4;      /* pwm index */
2628         int a = index % 4;      /* attribute index */
2629
2630         if (!(data->has_pwm & BIT(i)))
2631                 return 0;
2632
2633         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2634         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2635                 return attr->mode | S_IWUSR;
2636
2637         /* pwm2_freq is writable if there are two pwm frequency selects */
2638         if (has_pwm_freq2(data) && i == 1 && a == 2)
2639                 return attr->mode | S_IWUSR;
2640
2641         return attr->mode;
2642 }
2643
2644 static struct attribute *it87_attributes_pwm[] = {
2645         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2646         &sensor_dev_attr_pwm1.dev_attr.attr,
2647         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2648         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2649
2650         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2651         &sensor_dev_attr_pwm2.dev_attr.attr,
2652         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2653         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2654
2655         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2656         &sensor_dev_attr_pwm3.dev_attr.attr,
2657         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2658         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2659
2660         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2661         &sensor_dev_attr_pwm4.dev_attr.attr,
2662         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2663         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2664
2665         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2666         &sensor_dev_attr_pwm5.dev_attr.attr,
2667         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2668         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2669
2670         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2671         &sensor_dev_attr_pwm6.dev_attr.attr,
2672         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2673         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2674
2675         NULL
2676 };
2677
2678 static const struct attribute_group it87_group_pwm = {
2679         .attrs = it87_attributes_pwm,
2680         .is_visible = it87_pwm_is_visible,
2681 };
2682
2683 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2684                                         struct attribute *attr, int index)
2685 {
2686         struct device *dev = container_of(kobj, struct device, kobj);
2687         struct it87_data *data = dev_get_drvdata(dev);
2688         int i = index / 11;     /* pwm index */
2689         int a = index % 11;     /* attribute index */
2690
2691         if (index >= 33) {      /* pwm 4..6 */
2692                 i = (index - 33) / 6 + 3;
2693                 a = (index - 33) % 6 + 4;
2694         }
2695
2696         if (!(data->has_pwm & BIT(i)))
2697                 return 0;
2698
2699         if (has_newer_autopwm(data)) {
2700                 if (a < 4)      /* no auto point pwm */
2701                         return 0;
2702                 if (a == 8)     /* no auto_point4 */
2703                         return 0;
2704         }
2705         if (has_old_autopwm(data)) {
2706                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2707                         return 0;
2708         }
2709
2710         return attr->mode;
2711 }
2712
2713 static struct attribute *it87_attributes_auto_pwm[] = {
2714         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2715         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2716         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2717         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2718         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2719         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2720         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2721         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2722         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2723         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2724         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2725
2726         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2727         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2728         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2729         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2730         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2731         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2732         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2733         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2734         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2735         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2736         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2737
2738         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2739         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2740         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2741         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2742         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2743         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2744         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2745         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2746         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2747         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2748         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2749
2750         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2751         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2752         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2753         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2754         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2755         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2756
2757         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2758         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2759         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2760         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2761         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2762         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2763
2764         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2765         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2766         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2767         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2768         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2769         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2770
2771         NULL,
2772 };
2773
2774 static const struct attribute_group it87_group_auto_pwm = {
2775         .attrs = it87_attributes_auto_pwm,
2776         .is_visible = it87_auto_pwm_is_visible,
2777 };
2778
2779 /* SuperIO detection - will change isa_address if a chip is found */
2780 static int __init it87_find(int sioaddr, unsigned short *address,
2781                             struct it87_sio_data *sio_data)
2782 {
2783         const struct it87_devices *config;
2784         bool doexit = true;
2785         u16 chip_type;
2786         int err;
2787
2788         err = superio_enter(sioaddr);
2789         if (err)
2790                 return err;
2791
2792         err = -ENODEV;
2793         chip_type = superio_inw(sioaddr, DEVID);
2794         if (chip_type == 0xffff)
2795                 goto exit;
2796
2797         if (force_id)
2798                 chip_type = force_id;
2799
2800         switch (chip_type) {
2801         case IT8705F_DEVID:
2802                 sio_data->type = it87;
2803                 break;
2804         case IT8712F_DEVID:
2805                 sio_data->type = it8712;
2806                 break;
2807         case IT8716F_DEVID:
2808         case IT8726F_DEVID:
2809                 sio_data->type = it8716;
2810                 break;
2811         case IT8718F_DEVID:
2812                 sio_data->type = it8718;
2813                 break;
2814         case IT8720F_DEVID:
2815                 sio_data->type = it8720;
2816                 break;
2817         case IT8721F_DEVID:
2818                 sio_data->type = it8721;
2819                 break;
2820         case IT8728F_DEVID:
2821                 sio_data->type = it8728;
2822                 break;
2823         case IT8732F_DEVID:
2824                 sio_data->type = it8732;
2825                 break;
2826         case IT8792E_DEVID:
2827                 sio_data->type = it8792;
2828                 /*
2829                  * Disabling configuration mode on IT8792E can result in system
2830                  * hang-ups and access failures to the Super-IO chip at the
2831                  * second SIO address. Never exit configuration mode on this
2832                  * chip to avoid the problem.
2833                  */
2834                 doexit = false;
2835                 break;
2836         case IT8771E_DEVID:
2837                 sio_data->type = it8771;
2838                 break;
2839         case IT8772E_DEVID:
2840                 sio_data->type = it8772;
2841                 break;
2842         case IT8781F_DEVID:
2843                 sio_data->type = it8781;
2844                 break;
2845         case IT8782F_DEVID:
2846                 sio_data->type = it8782;
2847                 break;
2848         case IT8783E_DEVID:
2849                 sio_data->type = it8783;
2850                 break;
2851         case IT8786E_DEVID:
2852                 sio_data->type = it8786;
2853                 break;
2854         case IT8790E_DEVID:
2855                 sio_data->type = it8790;
2856                 doexit = false;         /* See IT8792E comment above */
2857                 break;
2858         case IT8603E_DEVID:
2859         case IT8623E_DEVID:
2860                 sio_data->type = it8603;
2861                 break;
2862         case IT8607E_DEVID:
2863                 sio_data->type = it8607;
2864                 break;
2865         case IT8613E_DEVID:
2866                 sio_data->type = it8613;
2867                 break;
2868         case IT8620E_DEVID:
2869                 sio_data->type = it8620;
2870                 break;
2871         case IT8622E_DEVID:
2872                 sio_data->type = it8622;
2873                 break;
2874         case IT8625E_DEVID:
2875                 sio_data->type = it8625;
2876                 break;
2877         case IT8628E_DEVID:
2878                 sio_data->type = it8628;
2879                 break;
2880         case IT8655E_DEVID:
2881                 sio_data->type = it8655;
2882                 break;
2883         case IT8665E_DEVID:
2884                 sio_data->type = it8665;
2885                 break;
2886         case IT8686E_DEVID:
2887                 sio_data->type = it8686;
2888                 break;
2889         case 0xffff:    /* No device at all */
2890                 goto exit;
2891         default:
2892                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2893                 goto exit;
2894         }
2895
2896         superio_select(sioaddr, PME);
2897         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2898                 pr_info("Device not activated, skipping\n");
2899                 goto exit;
2900         }
2901
2902         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2903         if (*address == 0) {
2904                 pr_info("Base address not set, skipping\n");
2905                 goto exit;
2906         }
2907
2908         err = 0;
2909         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2910         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2911                 it87_devices[sio_data->type].suffix,
2912                 *address, sio_data->revision);
2913
2914         config = &it87_devices[sio_data->type];
2915
2916         /* in7 (VSB or VCCH5V) is always internal on some chips */
2917         if (has_in7_internal(config))
2918                 sio_data->internal |= BIT(1);
2919
2920         /* in8 (Vbat) is always internal */
2921         sio_data->internal |= BIT(2);
2922
2923         /* in9 (AVCC3), always internal if supported */
2924         if (has_avcc3(config))
2925                 sio_data->internal |= BIT(3); /* in9 is AVCC */
2926         else
2927                 sio_data->skip_in |= BIT(9);
2928
2929         if (!has_four_pwm(config))
2930                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2931         else if (!has_five_pwm(config))
2932                 sio_data->skip_pwm |= BIT(4) | BIT(5);
2933         else if (!has_six_pwm(config))
2934                 sio_data->skip_pwm |= BIT(5);
2935
2936         if (!has_vid(config))
2937                 sio_data->skip_vid = 1;
2938
2939         /* Read GPIO config and VID value from LDN 7 (GPIO) */
2940         if (sio_data->type == it87) {
2941                 /* The IT8705F has a different LD number for GPIO */
2942                 superio_select(sioaddr, 5);
2943                 sio_data->beep_pin = superio_inb(sioaddr,
2944                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2945         } else if (sio_data->type == it8783) {
2946                 int reg25, reg27, reg2a, reg2c, regef;
2947
2948                 superio_select(sioaddr, GPIO);
2949
2950                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2951                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2952                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2953                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2954                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2955
2956                 /* Check if fan3 is there or not */
2957                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2958                         sio_data->skip_fan |= BIT(2);
2959                 if ((reg25 & BIT(4)) ||
2960                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
2961                         sio_data->skip_pwm |= BIT(2);
2962
2963                 /* Check if fan2 is there or not */
2964                 if (reg27 & BIT(7))
2965                         sio_data->skip_fan |= BIT(1);
2966                 if (reg27 & BIT(3))
2967                         sio_data->skip_pwm |= BIT(1);
2968
2969                 /* VIN5 */
2970                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2971                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2972
2973                 /* VIN6 */
2974                 if (reg27 & BIT(1))
2975                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2976
2977                 /*
2978                  * VIN7
2979                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2980                  */
2981                 if (reg27 & BIT(2)) {
2982                         /*
2983                          * The data sheet is a bit unclear regarding the
2984                          * internal voltage divider for VCCH5V. It says
2985                          * "This bit enables and switches VIN7 (pin 91) to the
2986                          * internal voltage divider for VCCH5V".
2987                          * This is different to other chips, where the internal
2988                          * voltage divider would connect VIN7 to an internal
2989                          * voltage source. Maybe that is the case here as well.
2990                          *
2991                          * Since we don't know for sure, re-route it if that is
2992                          * not the case, and ask the user to report if the
2993                          * resulting voltage is sane.
2994                          */
2995                         if (!(reg2c & BIT(1))) {
2996                                 reg2c |= BIT(1);
2997                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2998                                              reg2c);
2999                                 pr_notice("Routing internal VCCH5V to in7.\n");
3000                         }
3001                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3002                         pr_notice("Please report if it displays a reasonable voltage.\n");
3003                 }
3004
3005                 if (reg2c & BIT(0))
3006                         sio_data->internal |= BIT(0);
3007                 if (reg2c & BIT(1))
3008                         sio_data->internal |= BIT(1);
3009
3010                 sio_data->beep_pin = superio_inb(sioaddr,
3011                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3012         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3013                 int reg27, reg29;
3014
3015                 superio_select(sioaddr, GPIO);
3016
3017                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3018
3019                 /* Check if fan3 is there or not */
3020                 if (reg27 & BIT(6))
3021                         sio_data->skip_pwm |= BIT(2);
3022                 if (reg27 & BIT(7))
3023                         sio_data->skip_fan |= BIT(2);
3024
3025                 /* Check if fan2 is there or not */
3026                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3027                 if (reg29 & BIT(1))
3028                         sio_data->skip_pwm |= BIT(1);
3029                 if (reg29 & BIT(2))
3030                         sio_data->skip_fan |= BIT(1);
3031
3032                 switch (sio_data->type) {
3033                 case it8603:
3034                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3035                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3036                         break;
3037                 case it8607:
3038                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3039                         sio_data->skip_fan |= BIT(0);
3040                 default:
3041                         break;
3042                 }
3043
3044                 sio_data->beep_pin = superio_inb(sioaddr,
3045                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3046         } else if (sio_data->type == it8613) {
3047                 int reg27, reg29, reg2a;
3048
3049                 superio_select(sioaddr, GPIO);
3050
3051                 /* Check for pwm3, fan3, pwm5, fan5 */
3052                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3053                 if (reg27 & BIT(1))
3054                         sio_data->skip_fan |= BIT(4);
3055                 if (reg27 & BIT(3))
3056                         sio_data->skip_pwm |= BIT(4);
3057                 if (reg27 & BIT(6))
3058                         sio_data->skip_pwm |= BIT(2);
3059                 if (reg27 & BIT(7))
3060                         sio_data->skip_fan |= BIT(2);
3061
3062                 /* Check for pwm2, fan2 */
3063                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3064                 if (reg29 & BIT(1))
3065                         sio_data->skip_pwm |= BIT(1);
3066                 if (reg29 & BIT(2))
3067                         sio_data->skip_fan |= BIT(1);
3068
3069                 /* Check for pwm4, fan4 */
3070                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3071                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3072                         sio_data->skip_fan |= BIT(3);
3073                         sio_data->skip_pwm |= BIT(3);
3074                 }
3075
3076                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3077                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3078                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3079                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3080
3081                 sio_data->beep_pin = superio_inb(sioaddr,
3082                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3083         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3084                    sio_data->type == it8686) {
3085                 int reg;
3086
3087                 superio_select(sioaddr, GPIO);
3088
3089                 /* Check for pwm5 */
3090                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3091                 if (reg & BIT(6))
3092                         sio_data->skip_pwm |= BIT(4);
3093
3094                 /* Check for fan4, fan5 */
3095                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3096                 if (!(reg & BIT(5)))
3097                         sio_data->skip_fan |= BIT(3);
3098                 if (!(reg & BIT(4)))
3099                         sio_data->skip_fan |= BIT(4);
3100
3101                 /* Check for pwm3, fan3 */
3102                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3103                 if (reg & BIT(6))
3104                         sio_data->skip_pwm |= BIT(2);
3105                 if (reg & BIT(7))
3106                         sio_data->skip_fan |= BIT(2);
3107
3108                 /* Check for pwm4 */
3109                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3110                 if (reg & BIT(2))
3111                         sio_data->skip_pwm |= BIT(3);
3112
3113                 /* Check for pwm2, fan2 */
3114                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3115                 if (reg & BIT(1))
3116                         sio_data->skip_pwm |= BIT(1);
3117                 if (reg & BIT(2))
3118                         sio_data->skip_fan |= BIT(1);
3119                 /* Check for pwm6, fan6 */
3120                 if (!(reg & BIT(7))) {
3121                         sio_data->skip_pwm |= BIT(5);
3122                         sio_data->skip_fan |= BIT(5);
3123                 }
3124
3125                 /* Check if AVCC is on VIN3 */
3126                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3127                 if (reg & BIT(0)) {
3128                         /* For it8686, the bit just enables AVCC3 */
3129                         if (sio_data->type != it8686)
3130                                 sio_data->internal |= BIT(0);
3131                 } else {
3132                         sio_data->internal &= ~BIT(3);
3133                         sio_data->skip_in |= BIT(9);
3134                 }
3135
3136                 sio_data->beep_pin = superio_inb(sioaddr,
3137                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3138         } else if (sio_data->type == it8622) {
3139                 int reg;
3140
3141                 superio_select(sioaddr, GPIO);
3142
3143                 /* Check for pwm4, fan4 */
3144                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3145                 if (reg & BIT(6))
3146                         sio_data->skip_fan |= BIT(3);
3147                 if (reg & BIT(5))
3148                         sio_data->skip_pwm |= BIT(3);
3149
3150                 /* Check for pwm3, fan3, pwm5, fan5 */
3151                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3152                 if (reg & BIT(6))
3153                         sio_data->skip_pwm |= BIT(2);
3154                 if (reg & BIT(7))
3155                         sio_data->skip_fan |= BIT(2);
3156                 if (reg & BIT(3))
3157                         sio_data->skip_pwm |= BIT(4);
3158                 if (reg & BIT(1))
3159                         sio_data->skip_fan |= BIT(4);
3160
3161                 /* Check for pwm2, fan2 */
3162                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3163                 if (reg & BIT(1))
3164                         sio_data->skip_pwm |= BIT(1);
3165                 if (reg & BIT(2))
3166                         sio_data->skip_fan |= BIT(1);
3167
3168                 /* Check for AVCC */
3169                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3170                 if (!(reg & BIT(0)))
3171                         sio_data->skip_in |= BIT(9);
3172
3173                 sio_data->beep_pin = superio_inb(sioaddr,
3174                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3175         } else if (sio_data->type == it8732) {
3176                 int reg;
3177
3178                 superio_select(sioaddr, GPIO);
3179
3180                 /* Check for pwm2, fan2 */
3181                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3182                 if (reg & BIT(1))
3183                         sio_data->skip_pwm |= BIT(1);
3184                 if (reg & BIT(2))
3185                         sio_data->skip_fan |= BIT(1);
3186
3187                 /* Check for pwm3, fan3, fan4 */
3188                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3189                 if (reg & BIT(6))
3190                         sio_data->skip_pwm |= BIT(2);
3191                 if (reg & BIT(7))
3192                         sio_data->skip_fan |= BIT(2);
3193                 if (reg & BIT(5))
3194                         sio_data->skip_fan |= BIT(3);
3195
3196                 /* Check if AVCC is on VIN3 */
3197                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3198                 if (reg & BIT(0))
3199                         sio_data->internal |= BIT(0);
3200
3201                 sio_data->beep_pin = superio_inb(sioaddr,
3202                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3203         } else if (sio_data->type == it8655) {
3204                 int reg;
3205
3206                 superio_select(sioaddr, GPIO);
3207
3208                 /* Check for pwm2 */
3209                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3210                 if (reg & BIT(1))
3211                         sio_data->skip_pwm |= BIT(1);
3212
3213                 /* Check for fan2 */
3214                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3215                 if (reg & BIT(4))
3216                         sio_data->skip_fan |= BIT(1);
3217
3218                 /* Check for pwm3, fan3 */
3219                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3220                 if (reg & BIT(6))
3221                         sio_data->skip_pwm |= BIT(2);
3222                 if (reg & BIT(7))
3223                         sio_data->skip_fan |= BIT(2);
3224
3225                 sio_data->beep_pin = superio_inb(sioaddr,
3226                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3227         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3228                 int reg27, reg29, reg2d, regd3;
3229
3230                 superio_select(sioaddr, GPIO);
3231
3232                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3233                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3234                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3235                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3236
3237                 /* Check for pwm2, fan2 */
3238                 if (reg29 & BIT(1))
3239                         sio_data->skip_pwm |= BIT(1);
3240                 /*
3241                  * Note: Table 6-1 in datasheet claims that FAN_TAC2
3242                  * would be enabled with 29h[2]=0.
3243                  */
3244                 if (reg2d & BIT(4))
3245                         sio_data->skip_fan |= BIT(1);
3246
3247                 /* Check for pwm3, fan3 */
3248                 if (reg27 & BIT(6))
3249                         sio_data->skip_pwm |= BIT(2);
3250                 if (reg27 & BIT(7))
3251                         sio_data->skip_fan |= BIT(2);
3252
3253                 /* Check for pwm4, fan4, pwm5, fan5 */
3254                 if (sio_data->type == it8625) {
3255                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3256
3257                         if (reg25 & BIT(6))
3258                                 sio_data->skip_fan |= BIT(3);
3259                         if (reg25 & BIT(5))
3260                                 sio_data->skip_pwm |= BIT(3);
3261                         if (reg27 & BIT(3))
3262                                 sio_data->skip_pwm |= BIT(4);
3263                         if (reg27 & BIT(1))
3264                                 sio_data->skip_fan |= BIT(4);
3265                 } else {
3266                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3267
3268                         if (regd3 & BIT(2))
3269                                 sio_data->skip_pwm |= BIT(3);
3270                         if (regd3 & BIT(3))
3271                                 sio_data->skip_fan |= BIT(3);
3272                         if (reg26 & BIT(5))
3273                                 sio_data->skip_pwm |= BIT(4);
3274                         if (reg26 & BIT(4))
3275                                 sio_data->skip_fan |= BIT(4);
3276                 }
3277
3278                 /* Check for pwm6, fan6 */
3279                 if (regd3 & BIT(0))
3280                         sio_data->skip_pwm |= BIT(5);
3281                 if (regd3 & BIT(1))
3282                         sio_data->skip_fan |= BIT(5);
3283
3284                 sio_data->beep_pin = superio_inb(sioaddr,
3285                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3286         } else {
3287                 int reg;
3288                 bool uart6;
3289
3290                 superio_select(sioaddr, GPIO);
3291
3292                 /* Check for fan4, fan5 */
3293                 if (has_five_fans(config)) {
3294                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3295                         switch (sio_data->type) {
3296                         case it8718:
3297                                 if (reg & BIT(5))
3298                                         sio_data->skip_fan |= BIT(3);
3299                                 if (reg & BIT(4))
3300                                         sio_data->skip_fan |= BIT(4);
3301                                 break;
3302                         case it8720:
3303                         case it8721:
3304                         case it8728:
3305                                 if (!(reg & BIT(5)))
3306                                         sio_data->skip_fan |= BIT(3);
3307                                 if (!(reg & BIT(4)))
3308                                         sio_data->skip_fan |= BIT(4);
3309                                 break;
3310                         default:
3311                                 break;
3312                         }
3313                 }
3314
3315                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3316                 if (!sio_data->skip_vid) {
3317                         /* We need at least 4 VID pins */
3318                         if (reg & 0x0f) {
3319                                 pr_info("VID is disabled (pins used for GPIO)\n");
3320                                 sio_data->skip_vid = 1;
3321                         }
3322                 }
3323
3324                 /* Check if fan3 is there or not */
3325                 if (reg & BIT(6))
3326                         sio_data->skip_pwm |= BIT(2);
3327                 if (reg & BIT(7))
3328                         sio_data->skip_fan |= BIT(2);
3329
3330                 /* Check if fan2 is there or not */
3331                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3332                 if (reg & BIT(1))
3333                         sio_data->skip_pwm |= BIT(1);
3334                 if (reg & BIT(2))
3335                         sio_data->skip_fan |= BIT(1);
3336
3337                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3338                     !(sio_data->skip_vid))
3339                         sio_data->vid_value = superio_inb(sioaddr,
3340                                                           IT87_SIO_VID_REG);
3341
3342                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3343
3344                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3345
3346                 /*
3347                  * The IT8720F has no VIN7 pin, so VCCH should always be
3348                  * routed internally to VIN7 with an internal divider.
3349                  * Curiously, there still is a configuration bit to control
3350                  * this, which means it can be set incorrectly. And even
3351                  * more curiously, many boards out there are improperly
3352                  * configured, even though the IT8720F datasheet claims
3353                  * that the internal routing of VCCH to VIN7 is the default
3354                  * setting. So we force the internal routing in this case.
3355                  *
3356                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3357                  * If UART6 is enabled, re-route VIN7 to the internal divider
3358                  * if that is not already the case.
3359                  */
3360                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3361                         reg |= BIT(1);
3362                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3363                         pr_notice("Routing internal VCCH to in7\n");
3364                 }
3365                 if (reg & BIT(0))
3366                         sio_data->internal |= BIT(0);
3367                 if (reg & BIT(1))
3368                         sio_data->internal |= BIT(1);
3369
3370                 /*
3371                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3372                  * While VIN7 can be routed to the internal voltage divider,
3373                  * VIN5 and VIN6 are not available if UART6 is enabled.
3374                  *
3375                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3376                  * is the temperature source. Since we can not read the
3377                  * temperature source here, skip_temp is preliminary.
3378                  */
3379                 if (uart6) {
3380                         sio_data->skip_in |= BIT(5) | BIT(6);
3381                         sio_data->skip_temp |= BIT(2);
3382                 }
3383
3384                 sio_data->beep_pin = superio_inb(sioaddr,
3385                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3386         }
3387         if (sio_data->beep_pin)
3388                 pr_info("Beeping is supported\n");
3389
3390 exit:
3391         superio_exit(sioaddr, doexit);
3392         return err;
3393 }
3394
3395 static void it87_init_regs(struct platform_device *pdev)
3396 {
3397         struct it87_data *data = platform_get_drvdata(pdev);
3398
3399         /* Initialize chip specific register pointers */
3400         switch (data->type) {
3401         case it8628:
3402         case it8686:
3403                 data->REG_FAN = IT87_REG_FAN;
3404                 data->REG_FANX = IT87_REG_FANX;
3405                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3406                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3407                 data->REG_PWM = IT87_REG_PWM;
3408                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3409                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3410                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3411                 break;
3412         case it8625:
3413         case it8655:
3414         case it8665:
3415                 data->REG_FAN = IT87_REG_FAN_8665;
3416                 data->REG_FANX = IT87_REG_FANX_8665;
3417                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3418                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3419                 data->REG_PWM = IT87_REG_PWM_8665;
3420                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3421                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3422                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3423                 break;
3424         case it8622:
3425                 data->REG_FAN = IT87_REG_FAN;
3426                 data->REG_FANX = IT87_REG_FANX;
3427                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3428                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3429                 data->REG_PWM = IT87_REG_PWM_8665;
3430                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3431                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3432                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3433                 break;
3434         case it8613:
3435                 data->REG_FAN = IT87_REG_FAN;
3436                 data->REG_FANX = IT87_REG_FANX;
3437                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3438                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3439                 data->REG_PWM = IT87_REG_PWM_8665;
3440                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3441                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3442                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3443                 break;
3444         default:
3445                 data->REG_FAN = IT87_REG_FAN;
3446                 data->REG_FANX = IT87_REG_FANX;
3447                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3448                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3449                 data->REG_PWM = IT87_REG_PWM;
3450                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3451                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3452                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3453                 break;
3454         }
3455 }
3456
3457 /* Called when we have found a new IT87. */
3458 static void it87_init_device(struct platform_device *pdev)
3459 {
3460         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3461         struct it87_data *data = platform_get_drvdata(pdev);
3462         int tmp, i;
3463         u8 mask;
3464
3465         if (has_new_tempmap(data)) {
3466                 data->pwm_temp_map_shift = 3;
3467                 data->pwm_temp_map_mask = 0x07;
3468         } else {
3469                 data->pwm_temp_map_shift = 0;
3470                 data->pwm_temp_map_mask = 0x03;
3471         }
3472
3473         /*
3474          * For each PWM channel:
3475          * - If it is in automatic mode, setting to manual mode should set
3476          *   the fan to full speed by default.
3477          * - If it is in manual mode, we need a mapping to temperature
3478          *   channels to use when later setting to automatic mode later.
3479          *   Map to the first sensor by default (we are clueless.)
3480          * In both cases, the value can (and should) be changed by the user
3481          * prior to switching to a different mode.
3482          * Note that this is no longer needed for the IT8721F and later, as
3483          * these have separate registers for the temperature mapping and the
3484          * manual duty cycle.
3485          */
3486         for (i = 0; i < NUM_AUTO_PWM; i++) {
3487                 data->pwm_temp_map[i] = 0;
3488                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3489                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3490         }
3491
3492         /*
3493          * Some chips seem to have default value 0xff for all limit
3494          * registers. For low voltage limits it makes no sense and triggers
3495          * alarms, so change to 0 instead. For high temperature limits, it
3496          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3497          * but is still confusing, so change to 127 degrees C.
3498          */
3499         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3500                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3501                 if (tmp == 0xff)
3502                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3503         }
3504         for (i = 0; i < data->num_temp_limit; i++) {
3505                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3506                 if (tmp == 0xff)
3507                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3508         }
3509
3510         /*
3511          * Temperature channels are not forcibly enabled, as they can be
3512          * set to two different sensor types and we can't guess which one
3513          * is correct for a given system. These channels can be enabled at
3514          * run-time through the temp{1-3}_type sysfs accessors if needed.
3515          */
3516
3517         /* Check if voltage monitors are reset manually or by some reason */
3518         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3519         if ((tmp & 0xff) == 0) {
3520                 /* Enable all voltage monitors */
3521                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3522         }
3523
3524         /* Check if tachometers are reset manually or by some reason */
3525         mask = 0x70 & ~(sio_data->skip_fan << 4);
3526         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3527         if ((data->fan_main_ctrl & mask) == 0) {
3528                 /* Enable all fan tachometers */
3529                 data->fan_main_ctrl |= mask;
3530                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3531                                  data->fan_main_ctrl);
3532         }
3533         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3534
3535         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3536
3537         /* Set tachometers to 16-bit mode if needed */
3538         if (has_fan16_config(data)) {
3539                 if (~tmp & 0x07 & data->has_fan) {
3540                         dev_dbg(&pdev->dev,
3541                                 "Setting fan1-3 to 16-bit mode\n");
3542                         it87_write_value(data, IT87_REG_FAN_16BIT,
3543                                          tmp | 0x07);
3544                 }
3545         }
3546
3547         /* Check for additional fans */
3548         if (has_four_fans(data) && (tmp & BIT(4)))
3549                 data->has_fan |= BIT(3); /* fan4 enabled */
3550         if (has_five_fans(data) && (tmp & BIT(5)))
3551                 data->has_fan |= BIT(4); /* fan5 enabled */
3552         if (has_six_fans(data)) {
3553                 switch (data->type) {
3554                 case it8620:
3555                 case it8628:
3556                 case it8686:
3557                         if (tmp & BIT(2))
3558                                 data->has_fan |= BIT(5); /* fan6 enabled */
3559                         break;
3560                 case it8625:
3561                 case it8665:
3562                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3563                         if (tmp & BIT(3))
3564                                 data->has_fan |= BIT(5); /* fan6 enabled */
3565                         break;
3566                 default:
3567                         break;
3568                 }
3569         }
3570
3571         /* Fan input pins may be used for alternative functions */
3572         data->has_fan &= ~sio_data->skip_fan;
3573
3574         /* Check if pwm6 is enabled */
3575         if (has_six_pwm(data)) {
3576                 switch (data->type) {
3577                 case it8620:
3578                 case it8686:
3579                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3580                         if (!(tmp & BIT(3)))
3581                                 sio_data->skip_pwm |= BIT(5);
3582                         break;
3583                 default:
3584                         break;
3585                 }
3586         }
3587
3588         if (has_bank_sel(data)) {
3589                 for (i = 0; i < 3; i++)
3590                         data->temp_src[i] =
3591                                 it87_read_value(data, IT87_REG_TEMP_SRC1[i]);
3592                 data->temp_src[3] = it87_read_value(data, IT87_REG_TEMP_SRC2);
3593         }
3594
3595         /* Start monitoring */
3596         it87_write_value(data, IT87_REG_CONFIG,
3597                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3598                          | (update_vbat ? 0x41 : 0x01));
3599 }
3600
3601 /* Return 1 if and only if the PWM interface is safe to use */
3602 static int it87_check_pwm(struct device *dev)
3603 {
3604         struct it87_data *data = dev_get_drvdata(dev);
3605         /*
3606          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3607          * and polarity set to active low is sign that this is the case so we
3608          * disable pwm control to protect the user.
3609          */
3610         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3611
3612         if ((tmp & 0x87) == 0) {
3613                 if (fix_pwm_polarity) {
3614                         /*
3615                          * The user asks us to attempt a chip reconfiguration.
3616                          * This means switching to active high polarity and
3617                          * inverting all fan speed values.
3618                          */
3619                         int i;
3620                         u8 pwm[3];
3621
3622                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3623                                 pwm[i] = it87_read_value(data,
3624                                                          data->REG_PWM[i]);
3625
3626                         /*
3627                          * If any fan is in automatic pwm mode, the polarity
3628                          * might be correct, as suspicious as it seems, so we
3629                          * better don't change anything (but still disable the
3630                          * PWM interface).
3631                          */
3632                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3633                                 dev_info(dev,
3634                                          "Reconfiguring PWM to active high polarity\n");
3635                                 it87_write_value(data, IT87_REG_FAN_CTL,
3636                                                  tmp | 0x87);
3637                                 for (i = 0; i < 3; i++)
3638                                         it87_write_value(data,
3639                                                          data->REG_PWM[i],
3640                                                          0x7f & ~pwm[i]);
3641                                 return 1;
3642                         }
3643
3644                         dev_info(dev,
3645                                  "PWM configuration is too broken to be fixed\n");
3646                 }
3647
3648                 dev_info(dev,
3649                          "Detected broken BIOS defaults, disabling PWM interface\n");
3650                 return 0;
3651         } else if (fix_pwm_polarity) {
3652                 dev_info(dev,
3653                          "PWM configuration looks sane, won't touch\n");
3654         }
3655
3656         return 1;
3657 }
3658
3659 static int it87_probe(struct platform_device *pdev)
3660 {
3661         struct it87_data *data;
3662         struct resource *res;
3663         struct device *dev = &pdev->dev;
3664         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3665         int enable_pwm_interface;
3666         struct device *hwmon_dev;
3667
3668         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3669         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3670                                  DRVNAME)) {
3671                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3672                         (unsigned long)res->start,
3673                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3674                 return -EBUSY;
3675         }
3676
3677         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3678         if (!data)
3679                 return -ENOMEM;
3680
3681         data->addr = res->start;
3682         data->type = sio_data->type;
3683         data->features = it87_devices[sio_data->type].features;
3684         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3685         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3686         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3687         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3688         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3689
3690         /*
3691          * IT8705F Datasheet 0.4.1, 3h == Version G.
3692          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3693          * These are the first revisions with 16-bit tachometer support.
3694          */
3695         switch (data->type) {
3696         case it87:
3697                 if (sio_data->revision >= 0x03) {
3698                         data->features &= ~FEAT_OLD_AUTOPWM;
3699                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3700                 }
3701                 break;
3702         case it8712:
3703                 if (sio_data->revision >= 0x08) {
3704                         data->features &= ~FEAT_OLD_AUTOPWM;
3705                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3706                                           FEAT_FIVE_FANS;
3707                 }
3708                 break;
3709         default:
3710                 break;
3711         }
3712
3713         /* Now, we do the remaining detection. */
3714         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3715             it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3716                 return -ENODEV;
3717
3718         platform_set_drvdata(pdev, data);
3719
3720         mutex_init(&data->update_lock);
3721
3722         /* Initialize register pointers */
3723         it87_init_regs(pdev);
3724
3725         /* Check PWM configuration */
3726         enable_pwm_interface = it87_check_pwm(dev);
3727
3728         /* Starting with IT8721F, we handle scaling of internal voltages */
3729         if (has_scaling(data)) {
3730                 if (sio_data->internal & BIT(0))
3731                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3732                 if (sio_data->internal & BIT(1))
3733                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3734                 if (sio_data->internal & BIT(2))
3735                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3736                 if (sio_data->internal & BIT(3))
3737                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3738         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3739                    sio_data->type == it8783) {
3740                 if (sio_data->internal & BIT(0))
3741                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3742                 if (sio_data->internal & BIT(1))
3743                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3744         }
3745
3746         data->has_temp = 0x07;
3747         if (sio_data->skip_temp & BIT(2)) {
3748                 if (sio_data->type == it8782 &&
3749                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3750                         data->has_temp &= ~BIT(2);
3751         }
3752
3753         data->in_internal = sio_data->internal;
3754         data->has_in = 0x3ff & ~sio_data->skip_in;
3755
3756         if (has_six_temp(data)) {
3757                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3758
3759                 /* Check for additional temperature sensors */
3760                 if ((reg & 0x03) >= 0x02)
3761                         data->has_temp |= BIT(3);
3762                 if (((reg >> 2) & 0x03) >= 0x02)
3763                         data->has_temp |= BIT(4);
3764                 if (((reg >> 4) & 0x03) >= 0x02)
3765                         data->has_temp |= BIT(5);
3766
3767                 /* Check for additional voltage sensors */
3768                 if ((reg & 0x03) == 0x01)
3769                         data->has_in |= BIT(10);
3770                 if (((reg >> 2) & 0x03) == 0x01)
3771                         data->has_in |= BIT(11);
3772                 if (((reg >> 4) & 0x03) == 0x01)
3773                         data->has_in |= BIT(12);
3774         }
3775
3776         data->has_beep = !!sio_data->beep_pin;
3777
3778         /* Initialize the IT87 chip */
3779         it87_init_device(pdev);
3780
3781         if (!sio_data->skip_vid) {
3782                 data->has_vid = true;
3783                 data->vrm = vid_which_vrm();
3784                 /* VID reading from Super-I/O config space if available */
3785                 data->vid = sio_data->vid_value;
3786         }
3787
3788         /* Prepare for sysfs hooks */
3789         data->groups[0] = &it87_group;
3790         data->groups[1] = &it87_group_in;
3791         data->groups[2] = &it87_group_temp;
3792         data->groups[3] = &it87_group_fan;
3793
3794         if (enable_pwm_interface) {
3795                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3796                 data->has_pwm &= ~sio_data->skip_pwm;
3797
3798                 data->groups[4] = &it87_group_pwm;
3799                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3800                         data->groups[5] = &it87_group_auto_pwm;
3801         }
3802
3803         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3804                                         it87_devices[sio_data->type].name,
3805                                         data, data->groups);
3806         return PTR_ERR_OR_ZERO(hwmon_dev);
3807 }
3808
3809 static struct platform_driver it87_driver = {
3810         .driver = {
3811                 .name   = DRVNAME,
3812         },
3813         .probe  = it87_probe,
3814 };
3815
3816 static int __init it87_device_add(int index, unsigned short address,
3817                                   const struct it87_sio_data *sio_data)
3818 {
3819         struct platform_device *pdev;
3820         struct resource res = {
3821                 .start  = address + IT87_EC_OFFSET,
3822                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3823                 .name   = DRVNAME,
3824                 .flags  = IORESOURCE_IO,
3825         };
3826         int err;
3827
3828         err = acpi_check_resource_conflict(&res);
3829         if (err) {
3830                 if (!ignore_resource_conflict)
3831                         return err;
3832         }
3833
3834         pdev = platform_device_alloc(DRVNAME, address);
3835         if (!pdev)
3836                 return -ENOMEM;
3837
3838         err = platform_device_add_resources(pdev, &res, 1);
3839         if (err) {
3840                 pr_err("Device resource addition failed (%d)\n", err);
3841                 goto exit_device_put;
3842         }
3843
3844         err = platform_device_add_data(pdev, sio_data,
3845                                        sizeof(struct it87_sio_data));
3846         if (err) {
3847                 pr_err("Platform data allocation failed\n");
3848                 goto exit_device_put;
3849         }
3850
3851         err = platform_device_add(pdev);
3852         if (err) {
3853                 pr_err("Device addition failed (%d)\n", err);
3854                 goto exit_device_put;
3855         }
3856
3857         it87_pdev[index] = pdev;
3858         return 0;
3859
3860 exit_device_put:
3861         platform_device_put(pdev);
3862         return err;
3863 }
3864
3865 struct it87_dmi_data {
3866         bool sio2_force_config; /* force sio2 into configuration mode   */
3867         u8 skip_pwm;            /* pwm channels to skip for this board  */
3868 };
3869
3870 /*
3871  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
3872  * (IT8792E) needs to be in configuration mode before accessing the first
3873  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
3874  * This needs to be done before accessing the first Super-IO chip since
3875  * the second chip may have been accessed prior to loading this driver.
3876  *
3877  * The problem is also reported to affect IT8795E, which is used on X299 boards
3878  * and has the same chip ID as IT8792E (0x8733). It also appears to affect
3879  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
3880  * Z87X-OC.
3881  * DMI entries for those systems will be added as they become available and
3882  * as the problem is confirmed to affect those boards.
3883  */
3884 static struct it87_dmi_data gigabyte_sio2_force = {
3885         .sio2_force_config = true,
3886 };
3887
3888 /*
3889  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3890  * connected to a fan, but to something else. One user
3891  * has reported instant system power-off when changing
3892  * the PWM2 duty cycle, so we disable it.
3893  * I use the board name string as the trigger in case
3894  * the same board is ever used in other systems.
3895  */
3896 static struct it87_dmi_data nvidia_fn68pt = {
3897         .skip_pwm = BIT(1),
3898 };
3899
3900 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3901         {
3902                 .matches = {
3903                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3904                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
3905                 },
3906                 .driver_data = &gigabyte_sio2_force,
3907         },
3908         {
3909                 .matches = {
3910                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3911                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
3912                 },
3913                 .driver_data = &gigabyte_sio2_force,
3914         },
3915         {
3916                 .matches = {
3917                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3918                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
3919                 },
3920                 .driver_data = &gigabyte_sio2_force,
3921         },
3922         {
3923                 .matches = {
3924                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3925                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3926                 },
3927                 .driver_data = &nvidia_fn68pt,
3928         },
3929         { }
3930 };
3931
3932 static int __init sm_it87_init(void)
3933 {
3934         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3935         struct it87_dmi_data *dmi_data = NULL;
3936         int sioaddr[2] = { REG_2E, REG_4E };
3937         struct it87_sio_data sio_data;
3938         unsigned short isa_address;
3939         bool found = false;
3940         int i, err;
3941
3942         pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
3943
3944         if (dmi)
3945                 dmi_data = dmi->driver_data;
3946
3947         err = platform_driver_register(&it87_driver);
3948         if (err)
3949                 return err;
3950
3951         if (dmi_data && dmi_data->sio2_force_config)
3952                 __superio_enter(REG_4E);
3953
3954         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3955                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3956                 isa_address = 0;
3957                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3958                 if (err || isa_address == 0)
3959                         continue;
3960
3961                 if (dmi_data)
3962                         sio_data.skip_pwm |= dmi_data->skip_pwm;
3963                 err = it87_device_add(i, isa_address, &sio_data);
3964                 if (err)
3965                         goto exit_dev_unregister;
3966                 found = true;
3967         }
3968
3969         if (!found) {
3970                 err = -ENODEV;
3971                 goto exit_unregister;
3972         }
3973         return 0;
3974
3975 exit_dev_unregister:
3976         /* NULL check handled by platform_device_unregister */
3977         platform_device_unregister(it87_pdev[0]);
3978 exit_unregister:
3979         platform_driver_unregister(&it87_driver);
3980         return err;
3981 }
3982
3983 static void __exit sm_it87_exit(void)
3984 {
3985         /* NULL check handled by platform_device_unregister */
3986         platform_device_unregister(it87_pdev[1]);
3987         platform_device_unregister(it87_pdev[0]);
3988         platform_driver_unregister(&it87_driver);
3989 }
3990
3991 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3992 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3993 module_param(update_vbat, bool, 0);
3994 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3995 module_param(fix_pwm_polarity, bool, 0);
3996 MODULE_PARM_DESC(fix_pwm_polarity,
3997                  "Force PWM polarity to active high (DANGEROUS)");
3998 MODULE_LICENSE("GPL");
3999
4000 module_init(sm_it87_init);
4001 module_exit(sm_it87_exit);