2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
13 * Supports: IT8603E Super I/O chip w/LPC interface
14 * IT8606E Super I/O chip w/LPC interface
15 * IT8607E Super I/O chip w/LPC interface
16 * IT8613E Super I/O chip w/LPC interface
17 * IT8620E Super I/O chip w/LPC interface
18 * IT8622E Super I/O chip w/LPC interface
19 * IT8623E Super I/O chip w/LPC interface
20 * IT8625E Super I/O chip w/LPC interface
21 * IT8628E Super I/O chip w/LPC interface
22 * IT8655E Super I/O chip w/LPC interface
23 * IT8665E Super I/O chip w/LPC interface
24 * IT8686E Super I/O chip w/LPC interface
25 * IT8705F Super I/O chip w/LPC interface
26 * IT8712F Super I/O chip w/LPC interface
27 * IT8716F Super I/O chip w/LPC interface
28 * IT8718F Super I/O chip w/LPC interface
29 * IT8720F Super I/O chip w/LPC interface
30 * IT8721F Super I/O chip w/LPC interface
31 * IT8726F Super I/O chip w/LPC interface
32 * IT8728F Super I/O chip w/LPC interface
33 * IT8732F Super I/O chip w/LPC interface
34 * IT8758E Super I/O chip w/LPC interface
35 * IT8771E Super I/O chip w/LPC interface
36 * IT8772E Super I/O chip w/LPC interface
37 * IT8781F Super I/O chip w/LPC interface
38 * IT8782F Super I/O chip w/LPC interface
39 * IT8783E/F Super I/O chip w/LPC interface
40 * IT8786E Super I/O chip w/LPC interface
41 * IT8790E Super I/O chip w/LPC interface
42 * IT8792E Super I/O chip w/LPC interface
43 * Sis950 A clone of the IT8705F
45 * Copyright (C) 2001 Chris Gauthron
46 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
48 * This program is free software; you can redistribute it and/or modify
49 * it under the terms of the GNU General Public License as published by
50 * the Free Software Foundation; either version 2 of the License, or
51 * (at your option) any later version.
53 * This program is distributed in the hope that it will be useful,
54 * but WITHOUT ANY WARRANTY; without even the implied warranty of
55 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
56 * GNU General Public License for more details.
59 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
61 #include <linux/bitops.h>
62 #include <linux/module.h>
63 #include <linux/init.h>
64 #include <linux/slab.h>
65 #include <linux/jiffies.h>
66 #include <linux/platform_device.h>
67 #include <linux/hwmon.h>
68 #include <linux/hwmon-sysfs.h>
69 #include <linux/hwmon-vid.h>
70 #include <linux/err.h>
71 #include <linux/mutex.h>
72 #include <linux/sysfs.h>
73 #include <linux/string.h>
74 #include <linux/dmi.h>
75 #include <linux/acpi.h>
79 #ifndef IT87_DRIVER_VERSION
80 #define IT87_DRIVER_VERSION "<not provided>"
83 #define DRVNAME "it87"
85 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
86 it8771, it8772, it8781, it8782, it8783, it8786, it8790,
87 it8792, it8603, it8606, it8607, it8613, it8620, it8622, it8625,
88 it8628, it8655, it8665, it8686 };
90 static unsigned short force_id;
91 module_param(force_id, ushort, 0000);
92 MODULE_PARM_DESC(force_id, "Override the detected device ID");
94 static bool ignore_resource_conflict;
95 module_param(ignore_resource_conflict, bool, 0000);
96 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
99 module_param(mmio, bool, 0000);
100 MODULE_PARM_DESC(mmio, "Use MMIO if available");
102 static struct platform_device *it87_pdev[2];
104 #define REG_2E 0x2e /* The register to read/write */
105 #define REG_4E 0x4e /* Secondary register to read/write */
107 #define DEV 0x07 /* Register: Logical device select */
108 #define PME 0x04 /* The device with the fan registers in it */
110 /* The device with the IT8718F/IT8720F VID value in it */
113 #define DEVID 0x20 /* Register: Device ID */
114 #define DEVREV 0x22 /* Register: Device Revision */
116 static inline void __superio_enter(int ioreg)
121 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
124 static inline int superio_inb(int ioreg, int reg)
129 val = inb(ioreg + 1);
134 static inline void superio_outb(int ioreg, int reg, int val)
137 outb(val, ioreg + 1);
140 static int superio_inw(int ioreg, int reg)
142 return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
145 static inline void superio_select(int ioreg, int ldn)
148 outb(ldn, ioreg + 1);
151 static inline int superio_enter(int ioreg)
154 * Try to reserve ioreg and ioreg + 1 for exclusive access.
156 if (!request_muxed_region(ioreg, 2, DRVNAME))
159 __superio_enter(ioreg);
163 static inline void superio_exit(int ioreg, bool doexit)
167 outb(0x02, ioreg + 1);
169 release_region(ioreg, 2);
172 /* Logical device 4 registers */
173 #define IT8712F_DEVID 0x8712
174 #define IT8705F_DEVID 0x8705
175 #define IT8716F_DEVID 0x8716
176 #define IT8718F_DEVID 0x8718
177 #define IT8720F_DEVID 0x8720
178 #define IT8721F_DEVID 0x8721
179 #define IT8726F_DEVID 0x8726
180 #define IT8728F_DEVID 0x8728
181 #define IT8732F_DEVID 0x8732
182 #define IT8792E_DEVID 0x8733
183 #define IT8771E_DEVID 0x8771
184 #define IT8772E_DEVID 0x8772
185 #define IT8781F_DEVID 0x8781
186 #define IT8782F_DEVID 0x8782
187 #define IT8783E_DEVID 0x8783
188 #define IT8786E_DEVID 0x8786
189 #define IT8790E_DEVID 0x8790
190 #define IT8603E_DEVID 0x8603
191 #define IT8606E_DEVID 0x8606
192 #define IT8607E_DEVID 0x8607
193 #define IT8613E_DEVID 0x8613
194 #define IT8620E_DEVID 0x8620
195 #define IT8622E_DEVID 0x8622
196 #define IT8623E_DEVID 0x8623
197 #define IT8625E_DEVID 0x8625
198 #define IT8628E_DEVID 0x8628
199 #define IT8655E_DEVID 0x8655
200 #define IT8665E_DEVID 0x8665
201 #define IT8686E_DEVID 0x8686
203 /* Logical device 4 (Environmental Monitor) registers */
204 #define IT87_ACT_REG 0x30
205 #define IT87_BASE_REG 0x60
206 #define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */
208 /* Global configuration registers (IT8712F and later) */
209 #define IT87_EC_HWM_MIO_REG 0x24 /* MMIO configuration register */
210 #define IT87_SIO_GPIO1_REG 0x25
211 #define IT87_SIO_GPIO2_REG 0x26
212 #define IT87_SIO_GPIO3_REG 0x27
213 #define IT87_SIO_GPIO4_REG 0x28
214 #define IT87_SIO_GPIO5_REG 0x29
215 #define IT87_SIO_GPIO9_REG 0xd3
216 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
217 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
218 #define IT87_SIO_PINX4_REG 0x2d /* Pin selection */
220 /* Logical device 7 (GPIO) registers (IT8712F and later) */
221 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
222 #define IT87_SIO_VID_REG 0xfc /* VID value */
223 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
225 /* Update battery voltage after every reading if true */
226 static bool update_vbat;
228 /* Not all BIOSes properly configure the PWM registers */
229 static bool fix_pwm_polarity;
231 /* Many IT87 constants specified below */
233 /* Length of ISA address segment */
234 #define IT87_EXTENT 8
236 /* Length of ISA address segment for Environmental Controller */
237 #define IT87_EC_EXTENT 2
239 /* Offset of EC registers from ISA base address */
240 #define IT87_EC_OFFSET 5
242 /* Where are the ISA address/data registers relative to the EC base address */
243 #define IT87_ADDR_REG_OFFSET 0
244 #define IT87_DATA_REG_OFFSET 1
246 /*----- The IT87 registers -----*/
248 #define IT87_REG_CONFIG 0x00
250 #define IT87_REG_ALARM1 0x01
251 #define IT87_REG_ALARM2 0x02
252 #define IT87_REG_ALARM3 0x03
254 #define IT87_REG_BANK 0x06
257 * The IT8718F and IT8720F have the VID value in a different register, in
258 * Super-I/O configuration space.
260 #define IT87_REG_VID 0x0a
262 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
263 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
266 #define IT87_REG_FAN_DIV 0x0b
267 #define IT87_REG_FAN_16BIT 0x0c
271 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
272 * - up to 6 temp (1 to 6)
273 * - up to 6 fan (1 to 6)
276 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
277 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
278 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
279 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
281 static const u8 IT87_REG_FAN_8665[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
282 static const u8 IT87_REG_FAN_MIN_8665[] = {
283 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
284 static const u8 IT87_REG_FANX_8665[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
285 static const u8 IT87_REG_FANX_MIN_8665[] = {
286 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
288 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
290 static const u8 IT87_REG_TEMP_OFFSET_8686[] = {
291 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
293 #define IT87_REG_FAN_MAIN_CTRL 0x13
294 #define IT87_REG_FAN_CTL 0x14
296 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
297 static const u8 IT87_REG_PWM_8665[] = { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
299 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
301 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
302 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
304 #define IT87_REG_TEMP(nr) (0x29 + (nr))
306 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
307 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
309 static const u8 IT87_REG_TEMP_HIGH[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
310 static const u8 IT87_REG_TEMP_LOW[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
312 static const u8 IT87_REG_TEMP_HIGH_8686[] = {
313 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
314 static const u8 IT87_REG_TEMP_LOW_8686[] = {
315 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
317 #define IT87_REG_VIN_ENABLE 0x50
318 #define IT87_REG_TEMP_ENABLE 0x51
319 #define IT87_REG_TEMP_EXTRA 0x55
320 #define IT87_REG_BEEP_ENABLE 0x5c
322 #define IT87_REG_CHIPID 0x58
324 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
326 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
327 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
329 #define IT87_REG_TEMP456_ENABLE 0x77
331 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
332 #define IT87_REG_TEMP_SRC2 0x23d
334 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
335 #define NUM_VIN_LIMIT 8
337 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
338 #define NUM_FAN_DIV 3
339 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
340 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
342 struct it87_devices {
344 const char * const model;
348 u8 num_temp_map; /* Number of temperature sources for pwm */
351 u8 smbus_bitmap; /* SMBus enable bits in extra config register */
352 u8 ec_special_config;
355 #define FEAT_12MV_ADC BIT(0)
356 #define FEAT_NEWER_AUTOPWM BIT(1)
357 #define FEAT_OLD_AUTOPWM BIT(2)
358 #define FEAT_16BIT_FANS BIT(3)
359 #define FEAT_TEMP_PECI BIT(5)
360 #define FEAT_TEMP_OLD_PECI BIT(6)
361 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
362 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
363 #define FEAT_VID BIT(9) /* Set if chip supports VID */
364 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
365 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */
366 #define FEAT_10_9MV_ADC BIT(12)
367 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
368 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
369 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
370 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
371 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
372 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
373 #define FEAT_FOUR_FANS BIT(19) /* Supports four fans */
374 #define FEAT_FOUR_PWM BIT(20) /* Supports four fan controls */
375 #define FEAT_BANK_SEL BIT(21) /* Chip has multi-bank support */
376 #define FEAT_SCALING BIT(22) /* Internal voltage scaling */
377 #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
378 #define FEAT_11MV_ADC BIT(24)
379 #define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */
380 #define FEAT_MMIO BIT(26) /* Chip supports MMIO */
381 #define FEAT_FOUR_TEMP BIT(27)
383 static const struct it87_devices it87_devices[] = {
387 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
388 /* may need to overwrite */
390 .num_temp_offset = 0,
396 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
397 /* may need to overwrite */
399 .num_temp_offset = 0,
405 .features = FEAT_16BIT_FANS | FEAT_VID
406 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
409 .num_temp_offset = 3,
415 .features = FEAT_16BIT_FANS | FEAT_VID
416 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
417 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
419 .num_temp_offset = 3,
421 .old_peci_mask = 0x4,
426 .features = FEAT_16BIT_FANS | FEAT_VID
427 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
428 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
430 .num_temp_offset = 3,
432 .old_peci_mask = 0x4,
437 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
438 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
439 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
440 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
442 .num_temp_offset = 3,
445 .old_peci_mask = 0x02, /* Actually reports PCH */
450 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
451 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
452 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
455 .num_temp_offset = 3,
462 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
463 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
464 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
465 | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
467 .num_temp_offset = 3,
470 .old_peci_mask = 0x02, /* Actually reports PCH */
475 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
476 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
477 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
478 /* PECI: guesswork */
480 /* 16 bit fans (OHM) */
481 /* three fans, always 16 bit (guesswork) */
483 .num_temp_offset = 3,
490 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
491 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
492 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
493 /* PECI (coreboot) */
494 /* 12mV ADC (HWSensors4, OHM) */
495 /* 16 bit fans (HWSensors4, OHM) */
496 /* three fans, always 16 bit (datasheet) */
498 .num_temp_offset = 3,
505 .features = FEAT_16BIT_FANS
506 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
509 .num_temp_offset = 3,
511 .old_peci_mask = 0x4,
516 .features = FEAT_16BIT_FANS
517 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
520 .num_temp_offset = 3,
522 .old_peci_mask = 0x4,
526 .model = "IT8783E/F",
527 .features = FEAT_16BIT_FANS
528 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
531 .num_temp_offset = 3,
533 .old_peci_mask = 0x4,
538 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
539 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
540 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
542 .num_temp_offset = 3,
549 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
550 | FEAT_16BIT_FANS | FEAT_TEMP_PECI
551 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
553 .num_temp_offset = 3,
559 .model = "IT8792E/IT8795E",
560 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
561 | FEAT_16BIT_FANS | FEAT_TEMP_PECI
562 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
564 .num_temp_offset = 3,
571 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
572 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
573 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
575 .num_temp_offset = 3,
582 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
583 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
584 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
586 .num_temp_offset = 3,
593 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
594 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
595 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
598 .num_temp_offset = 3,
605 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
606 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
607 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
608 | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
610 .num_temp_offset = 6,
617 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
618 | FEAT_TEMP_PECI | FEAT_SIX_FANS
619 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
620 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
623 .num_temp_offset = 3,
630 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
631 | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
632 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
633 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
635 .num_temp_offset = 3,
638 .smbus_bitmap = BIT(1) | BIT(2),
643 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
644 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
645 | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
646 | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
648 .num_temp_offset = 6,
650 .smbus_bitmap = BIT(1) | BIT(2),
655 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
656 | FEAT_TEMP_PECI | FEAT_SIX_FANS
657 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
658 | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
661 .num_temp_offset = 3,
668 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
669 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
670 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
673 .num_temp_offset = 6,
675 .smbus_bitmap = BIT(2),
680 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
681 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
682 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
683 | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO,
685 .num_temp_offset = 6,
687 .smbus_bitmap = BIT(2),
692 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
693 | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
694 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
695 | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
697 .num_temp_offset = 6,
699 .smbus_bitmap = BIT(1) | BIT(2),
703 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
704 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
705 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
706 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
707 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
708 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
709 ((data)->peci_mask & BIT(nr)))
710 #define has_temp_old_peci(data, nr) \
711 (((data)->features & FEAT_TEMP_OLD_PECI) && \
712 ((data)->old_peci_mask & BIT(nr)))
713 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
714 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
716 #define has_vid(data) ((data)->features & FEAT_VID)
717 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
718 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
719 #define has_avcc3(data) ((data)->features & FEAT_AVCC3)
720 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \
722 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
723 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
724 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
725 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
726 #define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \
729 #define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \
732 #define has_bank_sel(data) ((data)->features & FEAT_BANK_SEL)
733 #define has_scaling(data) ((data)->features & FEAT_SCALING)
734 #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
735 #define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC)
736 #define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP)
737 #define has_mmio(data) ((data)->features & FEAT_MMIO)
738 #define has_four_temp(data) ((data)->features & FEAT_FOUR_TEMP)
740 struct it87_sio_data {
744 /* Values read from Super-I/O config space */
748 u8 internal; /* Internal sensors can be labeled */
749 /* Features skipped based on config or DMI */
756 u8 ec_special_config;
760 * For each registered chip, we need to keep some data in memory.
761 * The structure is dynamically allocated.
764 const struct attribute_group *groups[7];
770 u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */
771 u8 ec_special_config; /* EC special config register restore value */
772 u8 sioaddr; /* SIO port address */
773 bool doexit; /* true if exit from sio config is ok */
775 void __iomem *mmio; /* Remapped MMIO address if available */
776 int (*read)(struct it87_data *, u16);
777 void (*write)(struct it87_data *, u16, u8);
781 const u8 *REG_FAN_MIN;
782 const u8 *REG_FANX_MIN;
786 const u8 *REG_TEMP_OFFSET;
787 const u8 *REG_TEMP_LOW;
788 const u8 *REG_TEMP_HIGH;
791 struct mutex update_lock;
792 char valid; /* !=0 if following fields are valid */
793 unsigned long last_updated; /* In jiffies */
795 u16 in_scaled; /* Internal voltage sensors are scaled */
796 u16 in_internal; /* Bitfield, internal sensors (for labels) */
797 u16 has_in; /* Bitfield, voltage sensors enabled */
798 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
799 u8 has_fan; /* Bitfield, fans enabled */
800 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
801 u8 has_temp; /* Bitfield, temp sensors enabled */
802 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
803 u8 num_temp_limit; /* Number of temperature limit registers */
804 u8 num_temp_offset; /* Number of temperature offset registers */
805 u8 temp_src[4]; /* Up to 4 temperature source registers */
806 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
807 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
808 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
809 bool has_vid; /* True if VID supported */
810 u8 vid; /* Register encoding, combined */
812 u32 alarms; /* Register encoding, combined */
813 bool has_beep; /* true if beep supported */
814 u8 beeps; /* Register encoding */
815 u8 fan_main_ctrl; /* Register value */
816 u8 fan_ctl; /* Register value */
819 * The following 3 arrays correspond to the same registers up to
820 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
821 * 7, and we want to preserve settings on mode changes, so we have
822 * to track all values separately.
823 * Starting with the IT8721F, the manual PWM duty cycles are stored
824 * in separate registers (8-bit values), so the separate tracking
825 * is no longer needed, but it is still done to keep the driver
828 u8 has_pwm; /* Bitfield, pwm control enabled */
829 u8 pwm_ctrl[NUM_PWM]; /* Register value */
830 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
831 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
832 u8 pwm_temp_map_mask; /* 0x03 for old, 0x07 for new temp map */
833 u8 pwm_temp_map_shift; /* 0 for old, 3 for new temp map */
834 u8 pwm_num_temp_map; /* from config data, 3..7 depending on chip */
836 /* Automatic fan speed control registers */
837 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
838 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
841 static int adc_lsb(const struct it87_data *data, int nr)
845 if (has_12mv_adc(data))
847 else if (has_10_9mv_adc(data))
849 else if (has_11mv_adc(data))
853 if (data->in_scaled & BIT(nr))
858 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
860 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
861 return clamp_val(val, 0, 255);
864 static int in_from_reg(const struct it87_data *data, int nr, int val)
866 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
869 static inline u8 FAN_TO_REG(long rpm, int div)
873 rpm = clamp_val(rpm, 1, 1000000);
874 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
877 static inline u16 FAN16_TO_REG(long rpm)
881 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
884 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
885 1350000 / ((val) * (div)))
886 /* The divider is fixed to 2 in 16-bit mode */
887 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
888 1350000 / ((val) * 2))
890 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
891 ((val) + 500) / 1000), -128, 127))
892 #define TEMP_FROM_REG(val) ((val) * 1000)
894 static u8 pwm_to_reg(const struct it87_data *data, long val)
896 if (has_newer_autopwm(data))
902 static int pwm_from_reg(const struct it87_data *data, u8 reg)
904 if (has_newer_autopwm(data))
907 return (reg & 0x7f) << 1;
910 static int DIV_TO_REG(int val)
914 while (answer < 7 && (val >>= 1))
919 #define DIV_FROM_REG(val) BIT(val)
921 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
925 map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
926 if (map >= data->pwm_num_temp_map) /* map is 0-based */
932 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
934 u8 ctrl = data->pwm_ctrl[nr];
936 return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
937 (map << data->pwm_temp_map_shift);
941 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
942 * depending on the chip type, to calculate the actual PWM frequency.
944 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
945 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
946 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
947 * sometimes just one. It is unknown if this is a datasheet error or real,
948 * so this is ignored for now.
950 static const unsigned int pwm_freq[8] = {
961 static int smbus_disable(struct it87_data *data)
965 if (data->smbus_bitmap) {
966 err = superio_enter(data->sioaddr);
969 superio_select(data->sioaddr, PME);
970 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
971 data->ec_special_config & ~data->smbus_bitmap);
972 superio_exit(data->sioaddr, data->doexit);
977 static int smbus_enable(struct it87_data *data)
981 if (data->smbus_bitmap) {
982 err = superio_enter(data->sioaddr);
986 superio_select(data->sioaddr, PME);
987 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
988 data->ec_special_config);
989 superio_exit(data->sioaddr, data->doexit);
994 static int _it87_io_read(struct it87_data *data, u16 reg)
996 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
997 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
1000 static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
1002 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
1003 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1006 static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
1010 if (has_bank_sel(data)) {
1011 u8 breg = _it87_io_read(data, IT87_REG_BANK);
1014 if (bank != _bank) {
1016 breg |= (bank << 5);
1017 _it87_io_write(data, IT87_REG_BANK, breg);
1024 * Must be called with data->update_lock held, except during initialization.
1025 * Must be called with SMBus accesses disabled.
1026 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1027 * would slow down the IT87 access and should not be necessary.
1029 static int it87_io_read(struct it87_data *data, u16 reg)
1034 bank = it87_io_set_bank(data, reg >> 8);
1035 val = _it87_io_read(data, reg & 0xff);
1036 it87_io_set_bank(data, bank);
1042 * Must be called with data->update_lock held, except during initialization.
1043 * Must be called with SMBus accesses disabled
1044 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1045 * would slow down the IT87 access and should not be necessary.
1047 static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1051 bank = it87_io_set_bank(data, reg >> 8);
1052 _it87_io_write(data, reg & 0xff, value);
1053 it87_io_set_bank(data, bank);
1056 static int it87_mmio_read(struct it87_data *data, u16 reg)
1058 return readb(data->mmio + reg);
1061 static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1063 writeb(value, data->mmio + reg);
1066 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1070 ctrl = data->read(data, data->REG_PWM[nr]);
1071 data->pwm_ctrl[nr] = ctrl;
1072 if (has_newer_autopwm(data)) {
1073 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1074 data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1076 if (ctrl & 0x80) /* Automatic mode */
1077 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1078 else /* Manual mode */
1079 data->pwm_duty[nr] = ctrl & 0x7f;
1082 if (has_old_autopwm(data)) {
1085 for (i = 0; i < 5 ; i++)
1086 data->auto_temp[nr][i] = data->read(data,
1087 IT87_REG_AUTO_TEMP(nr, i));
1088 for (i = 0; i < 3 ; i++)
1089 data->auto_pwm[nr][i] = data->read(data,
1090 IT87_REG_AUTO_PWM(nr, i));
1091 } else if (has_newer_autopwm(data)) {
1095 * 0: temperature hysteresis (base + 5)
1096 * 1: fan off temperature (base + 0)
1097 * 2: fan start temperature (base + 1)
1098 * 3: fan max temperature (base + 2)
1100 data->auto_temp[nr][0] =
1101 data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1103 for (i = 0; i < 3 ; i++)
1104 data->auto_temp[nr][i + 1] =
1105 data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1107 * 0: start pwm value (base + 3)
1108 * 1: pwm slope (base + 4, 1/8th pwm)
1110 data->auto_pwm[nr][0] =
1111 data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1112 data->auto_pwm[nr][1] =
1113 data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1117 static int it87_lock(struct it87_data *data)
1121 mutex_lock(&data->update_lock);
1122 err = smbus_disable(data);
1124 mutex_unlock(&data->update_lock);
1128 static void it87_unlock(struct it87_data *data)
1131 mutex_unlock(&data->update_lock);
1134 static struct it87_data *it87_update_device(struct device *dev)
1136 struct it87_data *data = dev_get_drvdata(dev);
1137 struct it87_data *ret = data;
1141 mutex_lock(&data->update_lock);
1143 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1145 err = smbus_disable(data);
1152 * Cleared after each update, so reenable. Value
1153 * returned by this read will be previous value
1155 data->write(data, IT87_REG_CONFIG,
1156 data->read(data, IT87_REG_CONFIG) | 0x40);
1158 for (i = 0; i < NUM_VIN; i++) {
1159 if (!(data->has_in & BIT(i)))
1162 data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1164 /* VBAT and AVCC don't have limit registers */
1165 if (i >= NUM_VIN_LIMIT)
1168 data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1169 data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1172 for (i = 0; i < NUM_FAN; i++) {
1173 /* Skip disabled fans */
1174 if (!(data->has_fan & BIT(i)))
1177 data->fan[i][1] = data->read(data,
1178 data->REG_FAN_MIN[i]);
1179 data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1180 /* Add high byte if in 16-bit mode */
1181 if (has_16bit_fans(data)) {
1182 data->fan[i][0] |= data->read(data,
1183 data->REG_FANX[i]) << 8;
1184 data->fan[i][1] |= data->read(data,
1185 data->REG_FANX_MIN[i]) << 8;
1188 for (i = 0; i < NUM_TEMP; i++) {
1189 if (!(data->has_temp & BIT(i)))
1192 data->read(data, IT87_REG_TEMP(i));
1194 if (i >= data->num_temp_limit)
1197 if (i < data->num_temp_offset)
1199 data->read(data, data->REG_TEMP_OFFSET[i]);
1202 data->read(data, data->REG_TEMP_LOW[i]);
1204 data->read(data, data->REG_TEMP_HIGH[i]);
1207 /* Newer chips don't have clock dividers */
1208 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1209 i = data->read(data, IT87_REG_FAN_DIV);
1210 data->fan_div[0] = i & 0x07;
1211 data->fan_div[1] = (i >> 3) & 0x07;
1212 data->fan_div[2] = (i & 0x40) ? 3 : 1;
1216 data->read(data, IT87_REG_ALARM1) |
1217 (data->read(data, IT87_REG_ALARM2) << 8) |
1218 (data->read(data, IT87_REG_ALARM3) << 16);
1219 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1221 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1222 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1223 for (i = 0; i < NUM_PWM; i++) {
1224 if (!(data->has_pwm & BIT(i)))
1226 it87_update_pwm_ctrl(data, i);
1229 data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1230 data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1232 * The IT8705F does not have VID capability.
1233 * The IT8718F and later don't use IT87_REG_VID for the
1236 if (data->type == it8712 || data->type == it8716) {
1237 data->vid = data->read(data, IT87_REG_VID);
1239 * The older IT8712F revisions had only 5 VID pins,
1240 * but we assume it is always safe to read 6 bits.
1244 data->last_updated = jiffies;
1249 mutex_unlock(&data->update_lock);
1253 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1256 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1257 struct it87_data *data = it87_update_device(dev);
1258 int index = sattr->index;
1262 return PTR_ERR(data);
1264 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1267 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1268 const char *buf, size_t count)
1270 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1271 struct it87_data *data = dev_get_drvdata(dev);
1272 int index = sattr->index;
1277 if (kstrtoul(buf, 10, &val) < 0)
1280 err = it87_lock(data);
1284 data->in[nr][index] = in_to_reg(data, nr, val);
1285 data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1286 : IT87_REG_VIN_MAX(nr),
1287 data->in[nr][index]);
1292 static SENSOR_DEVICE_ATTR_2(in0_input, 0444, show_in, NULL, 0, 0);
1293 static SENSOR_DEVICE_ATTR_2(in0_min, 0644, show_in, set_in, 0, 1);
1294 static SENSOR_DEVICE_ATTR_2(in0_max, 0644, show_in, set_in, 0, 2);
1296 static SENSOR_DEVICE_ATTR_2(in1_input, 0444, show_in, NULL, 1, 0);
1297 static SENSOR_DEVICE_ATTR_2(in1_min, 0644, show_in, set_in, 1, 1);
1298 static SENSOR_DEVICE_ATTR_2(in1_max, 0644, show_in, set_in, 1, 2);
1300 static SENSOR_DEVICE_ATTR_2(in2_input, 0444, show_in, NULL, 2, 0);
1301 static SENSOR_DEVICE_ATTR_2(in2_min, 0644, show_in, set_in, 2, 1);
1302 static SENSOR_DEVICE_ATTR_2(in2_max, 0644, show_in, set_in, 2, 2);
1304 static SENSOR_DEVICE_ATTR_2(in3_input, 0444, show_in, NULL, 3, 0);
1305 static SENSOR_DEVICE_ATTR_2(in3_min, 0644, show_in, set_in, 3, 1);
1306 static SENSOR_DEVICE_ATTR_2(in3_max, 0644, show_in, set_in, 3, 2);
1308 static SENSOR_DEVICE_ATTR_2(in4_input, 0444, show_in, NULL, 4, 0);
1309 static SENSOR_DEVICE_ATTR_2(in4_min, 0644, show_in, set_in, 4, 1);
1310 static SENSOR_DEVICE_ATTR_2(in4_max, 0644, show_in, set_in, 4, 2);
1312 static SENSOR_DEVICE_ATTR_2(in5_input, 0444, show_in, NULL, 5, 0);
1313 static SENSOR_DEVICE_ATTR_2(in5_min, 0644, show_in, set_in, 5, 1);
1314 static SENSOR_DEVICE_ATTR_2(in5_max, 0644, show_in, set_in, 5, 2);
1316 static SENSOR_DEVICE_ATTR_2(in6_input, 0444, show_in, NULL, 6, 0);
1317 static SENSOR_DEVICE_ATTR_2(in6_min, 0644, show_in, set_in, 6, 1);
1318 static SENSOR_DEVICE_ATTR_2(in6_max, 0644, show_in, set_in, 6, 2);
1320 static SENSOR_DEVICE_ATTR_2(in7_input, 0444, show_in, NULL, 7, 0);
1321 static SENSOR_DEVICE_ATTR_2(in7_min, 0644, show_in, set_in, 7, 1);
1322 static SENSOR_DEVICE_ATTR_2(in7_max, 0644, show_in, set_in, 7, 2);
1324 static SENSOR_DEVICE_ATTR_2(in8_input, 0444, show_in, NULL, 8, 0);
1325 static SENSOR_DEVICE_ATTR_2(in9_input, 0444, show_in, NULL, 9, 0);
1326 static SENSOR_DEVICE_ATTR_2(in10_input, 0444, show_in, NULL, 10, 0);
1327 static SENSOR_DEVICE_ATTR_2(in11_input, 0444, show_in, NULL, 11, 0);
1328 static SENSOR_DEVICE_ATTR_2(in12_input, 0444, show_in, NULL, 12, 0);
1330 /* Up to 6 temperatures */
1331 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1334 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1336 int index = sattr->index;
1337 struct it87_data *data = it87_update_device(dev);
1340 return PTR_ERR(data);
1342 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1345 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1346 const char *buf, size_t count)
1348 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1350 int index = sattr->index;
1351 struct it87_data *data = dev_get_drvdata(dev);
1356 if (kstrtol(buf, 10, &val) < 0)
1359 err = it87_lock(data);
1366 reg = data->REG_TEMP_LOW[nr];
1369 reg = data->REG_TEMP_HIGH[nr];
1372 regval = data->read(data, IT87_REG_BEEP_ENABLE);
1373 if (!(regval & 0x80)) {
1375 data->write(data, IT87_REG_BEEP_ENABLE, regval);
1378 reg = data->REG_TEMP_OFFSET[nr];
1382 data->temp[nr][index] = TEMP_TO_REG(val);
1383 data->write(data, reg, data->temp[nr][index]);
1388 static SENSOR_DEVICE_ATTR_2(temp1_input, 0444, show_temp, NULL, 0, 0);
1389 static SENSOR_DEVICE_ATTR_2(temp1_min, 0644, show_temp, set_temp, 0, 1);
1390 static SENSOR_DEVICE_ATTR_2(temp1_max, 0644, show_temp, set_temp, 0, 2);
1391 static SENSOR_DEVICE_ATTR_2(temp1_offset, 0644, show_temp, set_temp, 0, 3);
1392 static SENSOR_DEVICE_ATTR_2(temp2_input, 0444, show_temp, NULL, 1, 0);
1393 static SENSOR_DEVICE_ATTR_2(temp2_min, 0644, show_temp, set_temp, 1, 1);
1394 static SENSOR_DEVICE_ATTR_2(temp2_max, 0644, show_temp, set_temp, 1, 2);
1395 static SENSOR_DEVICE_ATTR_2(temp2_offset, 0644, show_temp, set_temp, 1, 3);
1396 static SENSOR_DEVICE_ATTR_2(temp3_input, 0444, show_temp, NULL, 2, 0);
1397 static SENSOR_DEVICE_ATTR_2(temp3_min, 0644, show_temp, set_temp, 2, 1);
1398 static SENSOR_DEVICE_ATTR_2(temp3_max, 0644, show_temp, set_temp, 2, 2);
1399 static SENSOR_DEVICE_ATTR_2(temp3_offset, 0644, show_temp, set_temp, 2, 3);
1400 static SENSOR_DEVICE_ATTR_2(temp4_input, 0444, show_temp, NULL, 3, 0);
1401 static SENSOR_DEVICE_ATTR_2(temp4_min, 0644, show_temp, set_temp, 3, 1);
1402 static SENSOR_DEVICE_ATTR_2(temp4_max, 0644, show_temp, set_temp, 3, 2);
1403 static SENSOR_DEVICE_ATTR_2(temp4_offset, 0644, show_temp, set_temp, 3, 3);
1404 static SENSOR_DEVICE_ATTR_2(temp5_input, 0444, show_temp, NULL, 4, 0);
1405 static SENSOR_DEVICE_ATTR_2(temp5_min, 0644, show_temp, set_temp, 4, 1);
1406 static SENSOR_DEVICE_ATTR_2(temp5_max, 0644, show_temp, set_temp, 4, 2);
1407 static SENSOR_DEVICE_ATTR_2(temp5_offset, 0644, show_temp, set_temp, 4, 3);
1408 static SENSOR_DEVICE_ATTR_2(temp6_input, 0444, show_temp, NULL, 5, 0);
1409 static SENSOR_DEVICE_ATTR_2(temp6_min, 0644, show_temp, set_temp, 5, 1);
1410 static SENSOR_DEVICE_ATTR_2(temp6_max, 0644, show_temp, set_temp, 5, 2);
1411 static SENSOR_DEVICE_ATTR_2(temp6_offset, 0644, show_temp, set_temp, 5, 3);
1413 static const u8 temp_types_8686[NUM_TEMP][9] = {
1414 { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1415 { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1416 { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1417 { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1418 { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1419 { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1422 static int get_temp_type(struct it87_data *data, int index)
1425 int ttype, type = 0;
1427 if (has_bank_sel(data)) {
1430 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1432 switch (data->type) {
1435 type = temp_types_8686[index][src1];
1446 src2 = data->temp_src[3];
1449 type = (src2 & BIT(index)) ? 6 : 5;
1452 type = (src2 & BIT(index)) ? 4 : 6;
1455 type = (src2 & BIT(index)) ? 5 : 0;
1468 /* Dectect PECI vs. AMDTSI if possible */
1470 if ((has_temp_peci(data, index)) && data->type != it8721) {
1471 extra = data->read(data, 0x98); /* PCH/AMDTSI host status */
1476 reg = data->read(data, IT87_REG_TEMP_ENABLE);
1478 /* Per chip special detection */
1479 switch (data->type) {
1481 if (!(reg & 0xc0) && index == 3)
1488 if (type || index >= 3)
1491 extra = data->read(data, IT87_REG_TEMP_EXTRA);
1493 if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1494 (has_temp_old_peci(data, index) && (extra & 0x80)))
1495 type = ttype; /* Intel PECI or AMDTSI */
1496 if (reg & BIT(index))
1497 type = 3; /* thermal diode */
1498 else if (reg & BIT(index + 3))
1499 type = 4; /* thermistor */
1504 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1507 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1508 struct it87_data *data = it87_update_device(dev);
1512 return PTR_ERR(data);
1514 type = get_temp_type(data, sensor_attr->index);
1515 return sprintf(buf, "%d\n", type);
1518 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1519 const char *buf, size_t count)
1521 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1522 int nr = sensor_attr->index;
1524 struct it87_data *data = dev_get_drvdata(dev);
1529 if (kstrtol(buf, 10, &val) < 0)
1532 err = it87_lock(data);
1536 reg = data->read(data, IT87_REG_TEMP_ENABLE);
1539 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1541 extra = data->read(data, IT87_REG_TEMP_EXTRA);
1542 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1544 if (val == 2) { /* backwards compatibility */
1546 "Sensor type 2 is deprecated, please use 4 instead\n");
1549 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1554 else if (has_temp_peci(data, nr) && val == 6)
1555 reg |= (nr + 1) << 6;
1556 else if (has_temp_old_peci(data, nr) && val == 6)
1558 else if (val != 0) {
1564 data->extra = extra;
1565 data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1566 if (has_temp_old_peci(data, nr))
1567 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1568 data->valid = 0; /* Force cache refresh */
1574 static SENSOR_DEVICE_ATTR(temp1_type, 0644, show_temp_type, set_temp_type, 0);
1575 static SENSOR_DEVICE_ATTR(temp2_type, 0644, show_temp_type, set_temp_type, 1);
1576 static SENSOR_DEVICE_ATTR(temp3_type, 0644, show_temp_type, set_temp_type, 2);
1577 static SENSOR_DEVICE_ATTR(temp4_type, 0644, show_temp_type, set_temp_type, 3);
1578 static SENSOR_DEVICE_ATTR(temp5_type, 0644, show_temp_type, set_temp_type, 4);
1579 static SENSOR_DEVICE_ATTR(temp6_type, 0644, show_temp_type, set_temp_type, 5);
1583 static int pwm_mode(const struct it87_data *data, int nr)
1585 if (has_fanctl_onoff(data) && nr < 3 &&
1586 !(data->fan_main_ctrl & BIT(nr)))
1587 return 0; /* Full speed */
1588 if (data->pwm_ctrl[nr] & 0x80)
1589 return 2; /* Automatic mode */
1590 if ((!has_fanctl_onoff(data) || nr >= 3) &&
1591 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1592 return 0; /* Full speed */
1594 return 1; /* Manual mode */
1597 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1600 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1602 int index = sattr->index;
1604 struct it87_data *data = it87_update_device(dev);
1607 return PTR_ERR(data);
1609 speed = has_16bit_fans(data) ?
1610 FAN16_FROM_REG(data->fan[nr][index]) :
1611 FAN_FROM_REG(data->fan[nr][index],
1612 DIV_FROM_REG(data->fan_div[nr]));
1613 return sprintf(buf, "%d\n", speed);
1616 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1619 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1620 struct it87_data *data = it87_update_device(dev);
1621 int nr = sensor_attr->index;
1624 return PTR_ERR(data);
1626 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1629 static ssize_t show_pwm_enable(struct device *dev,
1630 struct device_attribute *attr, char *buf)
1632 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1633 struct it87_data *data = it87_update_device(dev);
1634 int nr = sensor_attr->index;
1637 return PTR_ERR(data);
1639 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1642 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1645 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1646 struct it87_data *data = it87_update_device(dev);
1647 int nr = sensor_attr->index;
1650 return PTR_ERR(data);
1652 return sprintf(buf, "%d\n",
1653 pwm_from_reg(data, data->pwm_duty[nr]));
1656 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1659 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1660 struct it87_data *data = it87_update_device(dev);
1661 int nr = sensor_attr->index;
1666 return PTR_ERR(data);
1668 if (has_pwm_freq2(data) && nr == 1)
1669 index = (data->extra >> 4) & 0x07;
1671 index = (data->fan_ctl >> 4) & 0x07;
1673 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1675 return sprintf(buf, "%u\n", freq);
1678 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1679 const char *buf, size_t count)
1681 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1683 int index = sattr->index;
1685 struct it87_data *data = dev_get_drvdata(dev);
1690 if (kstrtol(buf, 10, &val) < 0)
1693 err = it87_lock(data);
1697 if (has_16bit_fans(data)) {
1698 data->fan[nr][index] = FAN16_TO_REG(val);
1699 data->write(data, data->REG_FAN_MIN[nr],
1700 data->fan[nr][index] & 0xff);
1701 data->write(data, data->REG_FANX_MIN[nr],
1702 data->fan[nr][index] >> 8);
1704 reg = data->read(data, IT87_REG_FAN_DIV);
1707 data->fan_div[nr] = reg & 0x07;
1710 data->fan_div[nr] = (reg >> 3) & 0x07;
1713 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1716 data->fan[nr][index] =
1717 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1718 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1724 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1725 const char *buf, size_t count)
1727 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1728 struct it87_data *data = dev_get_drvdata(dev);
1729 int nr = sensor_attr->index;
1734 if (kstrtoul(buf, 10, &val) < 0)
1737 err = it87_lock(data);
1741 old = data->read(data, IT87_REG_FAN_DIV);
1743 /* Save fan min limit */
1744 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1749 data->fan_div[nr] = DIV_TO_REG(val);
1753 data->fan_div[nr] = 1;
1755 data->fan_div[nr] = 3;
1758 val |= (data->fan_div[0] & 0x07);
1759 val |= (data->fan_div[1] & 0x07) << 3;
1760 if (data->fan_div[2] == 3)
1762 data->write(data, IT87_REG_FAN_DIV, val);
1764 /* Restore fan min limit */
1765 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1766 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1771 /* Returns 0 if OK, -EINVAL otherwise */
1772 static int check_trip_points(struct device *dev, int nr)
1774 const struct it87_data *data = dev_get_drvdata(dev);
1777 if (has_old_autopwm(data)) {
1778 for (i = 0; i < 3; i++) {
1779 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1782 for (i = 0; i < 2; i++) {
1783 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1786 } else if (has_newer_autopwm(data)) {
1787 for (i = 1; i < 3; i++) {
1788 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1795 "Inconsistent trip points, not switching to automatic mode\n");
1796 dev_err(dev, "Adjust the trip points and try again\n");
1801 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1802 const char *buf, size_t count)
1804 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1805 struct it87_data *data = dev_get_drvdata(dev);
1806 int nr = sensor_attr->index;
1810 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1813 /* Check trip points before switching to automatic mode */
1815 if (check_trip_points(dev, nr) < 0)
1819 err = it87_lock(data);
1823 it87_update_pwm_ctrl(data, nr);
1826 if (nr < 3 && has_fanctl_onoff(data)) {
1828 /* make sure the fan is on when in on/off mode */
1829 tmp = data->read(data, IT87_REG_FAN_CTL);
1830 data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1831 /* set on/off mode */
1832 data->fan_main_ctrl &= ~BIT(nr);
1833 data->write(data, IT87_REG_FAN_MAIN_CTRL,
1834 data->fan_main_ctrl);
1838 /* No on/off mode, set maximum pwm value */
1839 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1840 data->write(data, IT87_REG_PWM_DUTY[nr],
1841 data->pwm_duty[nr]);
1842 /* and set manual mode */
1843 if (has_newer_autopwm(data)) {
1844 ctrl = temp_map_to_reg(data, nr,
1845 data->pwm_temp_map[nr]);
1848 ctrl = data->pwm_duty[nr];
1850 data->pwm_ctrl[nr] = ctrl;
1851 data->write(data, data->REG_PWM[nr], ctrl);
1856 if (has_newer_autopwm(data)) {
1857 ctrl = temp_map_to_reg(data, nr,
1858 data->pwm_temp_map[nr]);
1864 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1866 data->pwm_ctrl[nr] = ctrl;
1867 data->write(data, data->REG_PWM[nr], ctrl);
1869 if (has_fanctl_onoff(data) && nr < 3) {
1870 /* set SmartGuardian mode */
1871 data->fan_main_ctrl |= BIT(nr);
1872 data->write(data, IT87_REG_FAN_MAIN_CTRL,
1873 data->fan_main_ctrl);
1880 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1881 const char *buf, size_t count)
1883 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1884 struct it87_data *data = dev_get_drvdata(dev);
1885 int nr = sensor_attr->index;
1889 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1892 err = it87_lock(data);
1896 it87_update_pwm_ctrl(data, nr);
1897 if (has_newer_autopwm(data)) {
1899 * If we are in automatic mode, the PWM duty cycle register
1900 * is read-only so we can't write the value.
1902 if (data->pwm_ctrl[nr] & 0x80) {
1906 data->pwm_duty[nr] = pwm_to_reg(data, val);
1907 data->write(data, IT87_REG_PWM_DUTY[nr],
1908 data->pwm_duty[nr]);
1910 data->pwm_duty[nr] = pwm_to_reg(data, val);
1912 * If we are in manual mode, write the duty cycle immediately;
1913 * otherwise, just store it for later use.
1915 if (!(data->pwm_ctrl[nr] & 0x80)) {
1916 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1917 data->write(data, data->REG_PWM[nr],
1918 data->pwm_ctrl[nr]);
1926 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1927 const char *buf, size_t count)
1929 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1930 struct it87_data *data = dev_get_drvdata(dev);
1931 int nr = sensor_attr->index;
1936 if (kstrtoul(buf, 10, &val) < 0)
1939 val = clamp_val(val, 0, 1000000);
1940 val *= has_newer_autopwm(data) ? 256 : 128;
1942 /* Search for the nearest available frequency */
1943 for (i = 0; i < 7; i++) {
1944 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1948 err = it87_lock(data);
1953 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1954 data->fan_ctl |= i << 4;
1955 data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
1957 data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1958 data->extra |= i << 4;
1959 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1965 static ssize_t show_pwm_temp_map(struct device *dev,
1966 struct device_attribute *attr, char *buf)
1968 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1969 struct it87_data *data = it87_update_device(dev);
1970 int nr = sensor_attr->index;
1973 return PTR_ERR(data);
1975 return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1978 static ssize_t set_pwm_temp_map(struct device *dev,
1979 struct device_attribute *attr, const char *buf,
1982 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1983 struct it87_data *data = dev_get_drvdata(dev);
1984 int nr = sensor_attr->index;
1989 if (kstrtoul(buf, 10, &val) < 0)
1992 if (!val || val > data->pwm_num_temp_map)
1997 err = it87_lock(data);
2001 it87_update_pwm_ctrl(data, nr);
2002 data->pwm_temp_map[nr] = map;
2004 * If we are in automatic mode, write the temp mapping immediately;
2005 * otherwise, just store it for later use.
2007 if (data->pwm_ctrl[nr] & 0x80) {
2008 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
2009 data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
2015 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
2018 struct it87_data *data = it87_update_device(dev);
2019 struct sensor_device_attribute_2 *sensor_attr =
2020 to_sensor_dev_attr_2(attr);
2021 int nr = sensor_attr->nr;
2022 int point = sensor_attr->index;
2025 return PTR_ERR(data);
2027 return sprintf(buf, "%d\n",
2028 pwm_from_reg(data, data->auto_pwm[nr][point]));
2031 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2032 const char *buf, size_t count)
2034 struct it87_data *data = dev_get_drvdata(dev);
2035 struct sensor_device_attribute_2 *sensor_attr =
2036 to_sensor_dev_attr_2(attr);
2037 int nr = sensor_attr->nr;
2038 int point = sensor_attr->index;
2043 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2046 err = it87_lock(data);
2050 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2051 if (has_newer_autopwm(data))
2052 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2054 regaddr = IT87_REG_AUTO_PWM(nr, point);
2055 data->write(data, regaddr, data->auto_pwm[nr][point]);
2060 static ssize_t show_auto_pwm_slope(struct device *dev,
2061 struct device_attribute *attr, char *buf)
2063 struct it87_data *data = it87_update_device(dev);
2064 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2065 int nr = sensor_attr->index;
2068 return PTR_ERR(data);
2070 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2073 static ssize_t set_auto_pwm_slope(struct device *dev,
2074 struct device_attribute *attr,
2075 const char *buf, size_t count)
2077 struct it87_data *data = dev_get_drvdata(dev);
2078 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2079 int nr = sensor_attr->index;
2083 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2086 err = it87_lock(data);
2090 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2091 data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2096 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2099 struct it87_data *data = it87_update_device(dev);
2100 struct sensor_device_attribute_2 *sensor_attr =
2101 to_sensor_dev_attr_2(attr);
2102 int nr = sensor_attr->nr;
2103 int point = sensor_attr->index;
2107 return PTR_ERR(data);
2109 if (has_old_autopwm(data) || point)
2110 reg = data->auto_temp[nr][point];
2112 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2114 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2117 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2118 const char *buf, size_t count)
2120 struct it87_data *data = dev_get_drvdata(dev);
2121 struct sensor_device_attribute_2 *sensor_attr =
2122 to_sensor_dev_attr_2(attr);
2123 int nr = sensor_attr->nr;
2124 int point = sensor_attr->index;
2129 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2132 err = it87_lock(data);
2136 if (has_newer_autopwm(data) && !point) {
2137 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2138 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2139 data->auto_temp[nr][0] = reg;
2140 data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2142 reg = TEMP_TO_REG(val);
2143 data->auto_temp[nr][point] = reg;
2144 if (has_newer_autopwm(data))
2146 data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2152 static SENSOR_DEVICE_ATTR_2(fan1_input, 0444, show_fan, NULL, 0, 0);
2153 static SENSOR_DEVICE_ATTR_2(fan1_min, 0644, show_fan, set_fan, 0, 1);
2154 static SENSOR_DEVICE_ATTR(fan1_div, 0644, show_fan_div, set_fan_div, 0);
2156 static SENSOR_DEVICE_ATTR_2(fan2_input, 0444, show_fan, NULL, 1, 0);
2157 static SENSOR_DEVICE_ATTR_2(fan2_min, 0644, show_fan, set_fan, 1, 1);
2158 static SENSOR_DEVICE_ATTR(fan2_div, 0644, show_fan_div, set_fan_div, 1);
2160 static SENSOR_DEVICE_ATTR_2(fan3_input, 0444, show_fan, NULL, 2, 0);
2161 static SENSOR_DEVICE_ATTR_2(fan3_min, 0644, show_fan, set_fan, 2, 1);
2162 static SENSOR_DEVICE_ATTR(fan3_div, 0644, show_fan_div, set_fan_div, 2);
2164 static SENSOR_DEVICE_ATTR_2(fan4_input, 0444, show_fan, NULL, 3, 0);
2165 static SENSOR_DEVICE_ATTR_2(fan4_min, 0644, show_fan, set_fan, 3, 1);
2167 static SENSOR_DEVICE_ATTR_2(fan5_input, 0444, show_fan, NULL, 4, 0);
2168 static SENSOR_DEVICE_ATTR_2(fan5_min, 0644, show_fan, set_fan, 4, 1);
2170 static SENSOR_DEVICE_ATTR_2(fan6_input, 0444, show_fan, NULL, 5, 0);
2171 static SENSOR_DEVICE_ATTR_2(fan6_min, 0644, show_fan, set_fan, 5, 1);
2173 static SENSOR_DEVICE_ATTR(pwm1_enable, 0644,
2174 show_pwm_enable, set_pwm_enable, 0);
2175 static SENSOR_DEVICE_ATTR(pwm1, 0644, show_pwm, set_pwm, 0);
2176 static SENSOR_DEVICE_ATTR(pwm1_freq, 0644, show_pwm_freq, set_pwm_freq, 0);
2177 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, 0444,
2178 show_pwm_temp_map, set_pwm_temp_map, 0);
2179 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, 0644,
2180 show_auto_pwm, set_auto_pwm, 0, 0);
2181 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, 0644,
2182 show_auto_pwm, set_auto_pwm, 0, 1);
2183 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, 0644,
2184 show_auto_pwm, set_auto_pwm, 0, 2);
2185 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, 0444,
2186 show_auto_pwm, NULL, 0, 3);
2187 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, 0644,
2188 show_auto_temp, set_auto_temp, 0, 1);
2189 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, 0644,
2190 show_auto_temp, set_auto_temp, 0, 0);
2191 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, 0644,
2192 show_auto_temp, set_auto_temp, 0, 2);
2193 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, 0644,
2194 show_auto_temp, set_auto_temp, 0, 3);
2195 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, 0644,
2196 show_auto_temp, set_auto_temp, 0, 4);
2197 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, 0644,
2198 show_auto_pwm, set_auto_pwm, 0, 0);
2199 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, 0644,
2200 show_auto_pwm_slope, set_auto_pwm_slope, 0);
2202 static SENSOR_DEVICE_ATTR(pwm2_enable, 0644,
2203 show_pwm_enable, set_pwm_enable, 1);
2204 static SENSOR_DEVICE_ATTR(pwm2, 0644, show_pwm, set_pwm, 1);
2205 static SENSOR_DEVICE_ATTR(pwm2_freq, 0444, show_pwm_freq, set_pwm_freq, 1);
2206 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, 0444,
2207 show_pwm_temp_map, set_pwm_temp_map, 1);
2208 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, 0644,
2209 show_auto_pwm, set_auto_pwm, 1, 0);
2210 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, 0644,
2211 show_auto_pwm, set_auto_pwm, 1, 1);
2212 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, 0644,
2213 show_auto_pwm, set_auto_pwm, 1, 2);
2214 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, 0444,
2215 show_auto_pwm, NULL, 1, 3);
2216 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, 0644,
2217 show_auto_temp, set_auto_temp, 1, 1);
2218 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, 0644,
2219 show_auto_temp, set_auto_temp, 1, 0);
2220 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, 0644,
2221 show_auto_temp, set_auto_temp, 1, 2);
2222 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, 0644,
2223 show_auto_temp, set_auto_temp, 1, 3);
2224 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, 0644,
2225 show_auto_temp, set_auto_temp, 1, 4);
2226 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, 0644,
2227 show_auto_pwm, set_auto_pwm, 1, 0);
2228 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, 0644,
2229 show_auto_pwm_slope, set_auto_pwm_slope, 1);
2231 static SENSOR_DEVICE_ATTR(pwm3_enable, 0644,
2232 show_pwm_enable, set_pwm_enable, 2);
2233 static SENSOR_DEVICE_ATTR(pwm3, 0644, show_pwm, set_pwm, 2);
2234 static SENSOR_DEVICE_ATTR(pwm3_freq, 0444, show_pwm_freq, NULL, 2);
2235 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, 0444,
2236 show_pwm_temp_map, set_pwm_temp_map, 2);
2237 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, 0644,
2238 show_auto_pwm, set_auto_pwm, 2, 0);
2239 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, 0644,
2240 show_auto_pwm, set_auto_pwm, 2, 1);
2241 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, 0644,
2242 show_auto_pwm, set_auto_pwm, 2, 2);
2243 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, 0444,
2244 show_auto_pwm, NULL, 2, 3);
2245 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, 0644,
2246 show_auto_temp, set_auto_temp, 2, 1);
2247 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, 0644,
2248 show_auto_temp, set_auto_temp, 2, 0);
2249 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, 0644,
2250 show_auto_temp, set_auto_temp, 2, 2);
2251 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, 0644,
2252 show_auto_temp, set_auto_temp, 2, 3);
2253 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, 0644,
2254 show_auto_temp, set_auto_temp, 2, 4);
2255 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, 0644,
2256 show_auto_pwm, set_auto_pwm, 2, 0);
2257 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, 0644,
2258 show_auto_pwm_slope, set_auto_pwm_slope, 2);
2260 static SENSOR_DEVICE_ATTR(pwm4_enable, 0644,
2261 show_pwm_enable, set_pwm_enable, 3);
2262 static SENSOR_DEVICE_ATTR(pwm4, 0644, show_pwm, set_pwm, 3);
2263 static SENSOR_DEVICE_ATTR(pwm4_freq, 0444, show_pwm_freq, NULL, 3);
2264 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, 0444,
2265 show_pwm_temp_map, set_pwm_temp_map, 3);
2266 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, 0644,
2267 show_auto_temp, set_auto_temp, 2, 1);
2268 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, 0644,
2269 show_auto_temp, set_auto_temp, 2, 0);
2270 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, 0644,
2271 show_auto_temp, set_auto_temp, 2, 2);
2272 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, 0644,
2273 show_auto_temp, set_auto_temp, 2, 3);
2274 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, 0644,
2275 show_auto_pwm, set_auto_pwm, 3, 0);
2276 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, 0644,
2277 show_auto_pwm_slope, set_auto_pwm_slope, 3);
2279 static SENSOR_DEVICE_ATTR(pwm5_enable, 0644,
2280 show_pwm_enable, set_pwm_enable, 4);
2281 static SENSOR_DEVICE_ATTR(pwm5, 0644, show_pwm, set_pwm, 4);
2282 static SENSOR_DEVICE_ATTR(pwm5_freq, 0444, show_pwm_freq, NULL, 4);
2283 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, 0444,
2284 show_pwm_temp_map, set_pwm_temp_map, 4);
2285 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, 0644,
2286 show_auto_temp, set_auto_temp, 2, 1);
2287 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, 0644,
2288 show_auto_temp, set_auto_temp, 2, 0);
2289 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, 0644,
2290 show_auto_temp, set_auto_temp, 2, 2);
2291 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, 0644,
2292 show_auto_temp, set_auto_temp, 2, 3);
2293 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, 0644,
2294 show_auto_pwm, set_auto_pwm, 4, 0);
2295 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, 0644,
2296 show_auto_pwm_slope, set_auto_pwm_slope, 4);
2298 static SENSOR_DEVICE_ATTR(pwm6_enable, 0644,
2299 show_pwm_enable, set_pwm_enable, 5);
2300 static SENSOR_DEVICE_ATTR(pwm6, 0644, show_pwm, set_pwm, 5);
2301 static SENSOR_DEVICE_ATTR(pwm6_freq, 0444, show_pwm_freq, NULL, 5);
2302 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, 0444,
2303 show_pwm_temp_map, set_pwm_temp_map, 5);
2304 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, 0644,
2305 show_auto_temp, set_auto_temp, 2, 1);
2306 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, 0644,
2307 show_auto_temp, set_auto_temp, 2, 0);
2308 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, 0644,
2309 show_auto_temp, set_auto_temp, 2, 2);
2310 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, 0644,
2311 show_auto_temp, set_auto_temp, 2, 3);
2312 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, 0644,
2313 show_auto_pwm, set_auto_pwm, 5, 0);
2314 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, 0644,
2315 show_auto_pwm_slope, set_auto_pwm_slope, 5);
2318 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2321 struct it87_data *data = it87_update_device(dev);
2324 return PTR_ERR(data);
2326 return sprintf(buf, "%u\n", data->alarms);
2328 static DEVICE_ATTR(alarms, 0444, show_alarms, NULL);
2330 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2333 struct it87_data *data = it87_update_device(dev);
2334 int bitnr = to_sensor_dev_attr(attr)->index;
2337 return PTR_ERR(data);
2339 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2342 static ssize_t clear_intrusion(struct device *dev,
2343 struct device_attribute *attr, const char *buf,
2346 struct it87_data *data = dev_get_drvdata(dev);
2350 if (kstrtol(buf, 10, &val) < 0 || val != 0)
2353 err = it87_lock(data);
2357 config = data->read(data, IT87_REG_CONFIG);
2359 data->write(data, IT87_REG_CONFIG, config);
2360 /* Invalidate cache to force re-read */
2366 static SENSOR_DEVICE_ATTR(in0_alarm, 0444, show_alarm, NULL, 8);
2367 static SENSOR_DEVICE_ATTR(in1_alarm, 0444, show_alarm, NULL, 9);
2368 static SENSOR_DEVICE_ATTR(in2_alarm, 0444, show_alarm, NULL, 10);
2369 static SENSOR_DEVICE_ATTR(in3_alarm, 0444, show_alarm, NULL, 11);
2370 static SENSOR_DEVICE_ATTR(in4_alarm, 0444, show_alarm, NULL, 12);
2371 static SENSOR_DEVICE_ATTR(in5_alarm, 0444, show_alarm, NULL, 13);
2372 static SENSOR_DEVICE_ATTR(in6_alarm, 0444, show_alarm, NULL, 14);
2373 static SENSOR_DEVICE_ATTR(in7_alarm, 0444, show_alarm, NULL, 15);
2374 static SENSOR_DEVICE_ATTR(fan1_alarm, 0444, show_alarm, NULL, 0);
2375 static SENSOR_DEVICE_ATTR(fan2_alarm, 0444, show_alarm, NULL, 1);
2376 static SENSOR_DEVICE_ATTR(fan3_alarm, 0444, show_alarm, NULL, 2);
2377 static SENSOR_DEVICE_ATTR(fan4_alarm, 0444, show_alarm, NULL, 3);
2378 static SENSOR_DEVICE_ATTR(fan5_alarm, 0444, show_alarm, NULL, 6);
2379 static SENSOR_DEVICE_ATTR(fan6_alarm, 0444, show_alarm, NULL, 7);
2380 static SENSOR_DEVICE_ATTR(temp1_alarm, 0444, show_alarm, NULL, 16);
2381 static SENSOR_DEVICE_ATTR(temp2_alarm, 0444, show_alarm, NULL, 17);
2382 static SENSOR_DEVICE_ATTR(temp3_alarm, 0444, show_alarm, NULL, 18);
2383 static SENSOR_DEVICE_ATTR(temp4_alarm, 0444, show_alarm, NULL, 19);
2384 static SENSOR_DEVICE_ATTR(temp5_alarm, 0444, show_alarm, NULL, 20);
2385 static SENSOR_DEVICE_ATTR(temp6_alarm, 0444, show_alarm, NULL, 21);
2386 static SENSOR_DEVICE_ATTR(intrusion0_alarm, 0644,
2387 show_alarm, clear_intrusion, 4);
2389 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2392 struct it87_data *data = it87_update_device(dev);
2393 int bitnr = to_sensor_dev_attr(attr)->index;
2396 return PTR_ERR(data);
2398 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2401 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2402 const char *buf, size_t count)
2404 int bitnr = to_sensor_dev_attr(attr)->index;
2405 struct it87_data *data = dev_get_drvdata(dev);
2409 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2412 err = it87_lock(data);
2416 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2418 data->beeps |= BIT(bitnr);
2420 data->beeps &= ~BIT(bitnr);
2421 data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2426 static SENSOR_DEVICE_ATTR(in0_beep, 0644,
2427 show_beep, set_beep, 1);
2428 static SENSOR_DEVICE_ATTR(in1_beep, 0444, show_beep, NULL, 1);
2429 static SENSOR_DEVICE_ATTR(in2_beep, 0444, show_beep, NULL, 1);
2430 static SENSOR_DEVICE_ATTR(in3_beep, 0444, show_beep, NULL, 1);
2431 static SENSOR_DEVICE_ATTR(in4_beep, 0444, show_beep, NULL, 1);
2432 static SENSOR_DEVICE_ATTR(in5_beep, 0444, show_beep, NULL, 1);
2433 static SENSOR_DEVICE_ATTR(in6_beep, 0444, show_beep, NULL, 1);
2434 static SENSOR_DEVICE_ATTR(in7_beep, 0444, show_beep, NULL, 1);
2435 /* fanX_beep writability is set later */
2436 static SENSOR_DEVICE_ATTR(fan1_beep, 0444, show_beep, set_beep, 0);
2437 static SENSOR_DEVICE_ATTR(fan2_beep, 0444, show_beep, set_beep, 0);
2438 static SENSOR_DEVICE_ATTR(fan3_beep, 0444, show_beep, set_beep, 0);
2439 static SENSOR_DEVICE_ATTR(fan4_beep, 0444, show_beep, set_beep, 0);
2440 static SENSOR_DEVICE_ATTR(fan5_beep, 0444, show_beep, set_beep, 0);
2441 static SENSOR_DEVICE_ATTR(fan6_beep, 0444, show_beep, set_beep, 0);
2442 static SENSOR_DEVICE_ATTR(temp1_beep, 0644,
2443 show_beep, set_beep, 2);
2444 static SENSOR_DEVICE_ATTR(temp2_beep, 0444, show_beep, NULL, 2);
2445 static SENSOR_DEVICE_ATTR(temp3_beep, 0444, show_beep, NULL, 2);
2446 static SENSOR_DEVICE_ATTR(temp4_beep, 0444, show_beep, NULL, 2);
2447 static SENSOR_DEVICE_ATTR(temp5_beep, 0444, show_beep, NULL, 2);
2448 static SENSOR_DEVICE_ATTR(temp6_beep, 0444, show_beep, NULL, 2);
2450 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2453 struct it87_data *data = dev_get_drvdata(dev);
2455 return sprintf(buf, "%u\n", data->vrm);
2458 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2459 const char *buf, size_t count)
2461 struct it87_data *data = dev_get_drvdata(dev);
2464 if (kstrtoul(buf, 10, &val) < 0)
2471 static DEVICE_ATTR(vrm, 0644, show_vrm_reg, store_vrm_reg);
2473 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2476 struct it87_data *data = it87_update_device(dev);
2479 return PTR_ERR(data);
2481 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2483 static DEVICE_ATTR(cpu0_vid, 0444, show_vid_reg, NULL);
2485 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2488 static const char * const labels[] = {
2494 static const char * const labels_it8721[] = {
2500 struct it87_data *data = dev_get_drvdata(dev);
2501 int nr = to_sensor_dev_attr(attr)->index;
2504 if (has_vin3_5v(data) && nr == 0)
2506 else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2508 label = labels_it8721[nr];
2512 return sprintf(buf, "%s\n", label);
2514 static SENSOR_DEVICE_ATTR(in3_label, 0444, show_label, NULL, 0);
2515 static SENSOR_DEVICE_ATTR(in7_label, 0444, show_label, NULL, 1);
2516 static SENSOR_DEVICE_ATTR(in8_label, 0444, show_label, NULL, 2);
2518 static SENSOR_DEVICE_ATTR(in9_label, 0444, show_label, NULL, 3);
2520 static umode_t it87_in_is_visible(struct kobject *kobj,
2521 struct attribute *attr, int index)
2523 struct device *dev = container_of(kobj, struct device, kobj);
2524 struct it87_data *data = dev_get_drvdata(dev);
2525 int i = index / 5; /* voltage index */
2526 int a = index % 5; /* attribute index */
2528 if (index >= 40) { /* in8 and higher only have input attributes */
2533 if (!(data->has_in & BIT(i)))
2536 if (a == 4 && !data->has_beep)
2542 static struct attribute *it87_attributes_in[] = {
2543 &sensor_dev_attr_in0_input.dev_attr.attr,
2544 &sensor_dev_attr_in0_min.dev_attr.attr,
2545 &sensor_dev_attr_in0_max.dev_attr.attr,
2546 &sensor_dev_attr_in0_alarm.dev_attr.attr,
2547 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
2549 &sensor_dev_attr_in1_input.dev_attr.attr,
2550 &sensor_dev_attr_in1_min.dev_attr.attr,
2551 &sensor_dev_attr_in1_max.dev_attr.attr,
2552 &sensor_dev_attr_in1_alarm.dev_attr.attr,
2553 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
2555 &sensor_dev_attr_in2_input.dev_attr.attr,
2556 &sensor_dev_attr_in2_min.dev_attr.attr,
2557 &sensor_dev_attr_in2_max.dev_attr.attr,
2558 &sensor_dev_attr_in2_alarm.dev_attr.attr,
2559 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
2561 &sensor_dev_attr_in3_input.dev_attr.attr,
2562 &sensor_dev_attr_in3_min.dev_attr.attr,
2563 &sensor_dev_attr_in3_max.dev_attr.attr,
2564 &sensor_dev_attr_in3_alarm.dev_attr.attr,
2565 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
2567 &sensor_dev_attr_in4_input.dev_attr.attr,
2568 &sensor_dev_attr_in4_min.dev_attr.attr,
2569 &sensor_dev_attr_in4_max.dev_attr.attr,
2570 &sensor_dev_attr_in4_alarm.dev_attr.attr,
2571 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
2573 &sensor_dev_attr_in5_input.dev_attr.attr,
2574 &sensor_dev_attr_in5_min.dev_attr.attr,
2575 &sensor_dev_attr_in5_max.dev_attr.attr,
2576 &sensor_dev_attr_in5_alarm.dev_attr.attr,
2577 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
2579 &sensor_dev_attr_in6_input.dev_attr.attr,
2580 &sensor_dev_attr_in6_min.dev_attr.attr,
2581 &sensor_dev_attr_in6_max.dev_attr.attr,
2582 &sensor_dev_attr_in6_alarm.dev_attr.attr,
2583 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
2585 &sensor_dev_attr_in7_input.dev_attr.attr,
2586 &sensor_dev_attr_in7_min.dev_attr.attr,
2587 &sensor_dev_attr_in7_max.dev_attr.attr,
2588 &sensor_dev_attr_in7_alarm.dev_attr.attr,
2589 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2591 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
2592 &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
2593 &sensor_dev_attr_in10_input.dev_attr.attr, /* 42 */
2594 &sensor_dev_attr_in11_input.dev_attr.attr, /* 43 */
2595 &sensor_dev_attr_in12_input.dev_attr.attr, /* 44 */
2599 static const struct attribute_group it87_group_in = {
2600 .attrs = it87_attributes_in,
2601 .is_visible = it87_in_is_visible,
2604 static umode_t it87_temp_is_visible(struct kobject *kobj,
2605 struct attribute *attr, int index)
2607 struct device *dev = container_of(kobj, struct device, kobj);
2608 struct it87_data *data = dev_get_drvdata(dev);
2609 int i = index / 7; /* temperature index */
2610 int a = index % 7; /* attribute index */
2612 if (!(data->has_temp & BIT(i)))
2615 if (a && i >= data->num_temp_limit)
2619 int type = get_temp_type(data, i);
2623 if (has_bank_sel(data))
2628 if (a == 5 && i >= data->num_temp_offset)
2631 if (a == 6 && !data->has_beep)
2637 static struct attribute *it87_attributes_temp[] = {
2638 &sensor_dev_attr_temp1_input.dev_attr.attr,
2639 &sensor_dev_attr_temp1_max.dev_attr.attr,
2640 &sensor_dev_attr_temp1_min.dev_attr.attr,
2641 &sensor_dev_attr_temp1_type.dev_attr.attr, /* 3 */
2642 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2643 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2644 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2646 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
2647 &sensor_dev_attr_temp2_max.dev_attr.attr,
2648 &sensor_dev_attr_temp2_min.dev_attr.attr,
2649 &sensor_dev_attr_temp2_type.dev_attr.attr,
2650 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2651 &sensor_dev_attr_temp2_offset.dev_attr.attr,
2652 &sensor_dev_attr_temp2_beep.dev_attr.attr,
2654 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
2655 &sensor_dev_attr_temp3_max.dev_attr.attr,
2656 &sensor_dev_attr_temp3_min.dev_attr.attr,
2657 &sensor_dev_attr_temp3_type.dev_attr.attr,
2658 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2659 &sensor_dev_attr_temp3_offset.dev_attr.attr,
2660 &sensor_dev_attr_temp3_beep.dev_attr.attr,
2662 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2663 &sensor_dev_attr_temp4_max.dev_attr.attr,
2664 &sensor_dev_attr_temp4_min.dev_attr.attr,
2665 &sensor_dev_attr_temp4_type.dev_attr.attr,
2666 &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2667 &sensor_dev_attr_temp4_offset.dev_attr.attr,
2668 &sensor_dev_attr_temp4_beep.dev_attr.attr,
2670 &sensor_dev_attr_temp5_input.dev_attr.attr,
2671 &sensor_dev_attr_temp5_max.dev_attr.attr,
2672 &sensor_dev_attr_temp5_min.dev_attr.attr,
2673 &sensor_dev_attr_temp5_type.dev_attr.attr,
2674 &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2675 &sensor_dev_attr_temp5_offset.dev_attr.attr,
2676 &sensor_dev_attr_temp5_beep.dev_attr.attr,
2678 &sensor_dev_attr_temp6_input.dev_attr.attr,
2679 &sensor_dev_attr_temp6_max.dev_attr.attr,
2680 &sensor_dev_attr_temp6_min.dev_attr.attr,
2681 &sensor_dev_attr_temp6_type.dev_attr.attr,
2682 &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2683 &sensor_dev_attr_temp6_offset.dev_attr.attr,
2684 &sensor_dev_attr_temp6_beep.dev_attr.attr,
2688 static const struct attribute_group it87_group_temp = {
2689 .attrs = it87_attributes_temp,
2690 .is_visible = it87_temp_is_visible,
2693 static umode_t it87_is_visible(struct kobject *kobj,
2694 struct attribute *attr, int index)
2696 struct device *dev = container_of(kobj, struct device, kobj);
2697 struct it87_data *data = dev_get_drvdata(dev);
2699 if ((index == 2 || index == 3) && !data->has_vid)
2702 if (index > 3 && !(data->in_internal & BIT(index - 4)))
2708 static struct attribute *it87_attributes[] = {
2709 &dev_attr_alarms.attr,
2710 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2711 &dev_attr_vrm.attr, /* 2 */
2712 &dev_attr_cpu0_vid.attr, /* 3 */
2713 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
2714 &sensor_dev_attr_in7_label.dev_attr.attr,
2715 &sensor_dev_attr_in8_label.dev_attr.attr,
2716 &sensor_dev_attr_in9_label.dev_attr.attr,
2720 static const struct attribute_group it87_group = {
2721 .attrs = it87_attributes,
2722 .is_visible = it87_is_visible,
2725 static umode_t it87_fan_is_visible(struct kobject *kobj,
2726 struct attribute *attr, int index)
2728 struct device *dev = container_of(kobj, struct device, kobj);
2729 struct it87_data *data = dev_get_drvdata(dev);
2730 int i = index / 5; /* fan index */
2731 int a = index % 5; /* attribute index */
2733 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
2734 i = (index - 15) / 4 + 3;
2735 a = (index - 15) % 4;
2738 if (!(data->has_fan & BIT(i)))
2741 if (a == 3) { /* beep */
2742 if (!data->has_beep)
2744 /* first fan beep attribute is writable */
2745 if (i == __ffs(data->has_fan))
2746 return attr->mode | 0200;
2749 if (a == 4 && has_16bit_fans(data)) /* divisor */
2755 static struct attribute *it87_attributes_fan[] = {
2756 &sensor_dev_attr_fan1_input.dev_attr.attr,
2757 &sensor_dev_attr_fan1_min.dev_attr.attr,
2758 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2759 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2760 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2762 &sensor_dev_attr_fan2_input.dev_attr.attr,
2763 &sensor_dev_attr_fan2_min.dev_attr.attr,
2764 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2765 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2766 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2768 &sensor_dev_attr_fan3_input.dev_attr.attr,
2769 &sensor_dev_attr_fan3_min.dev_attr.attr,
2770 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2771 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2772 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2774 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
2775 &sensor_dev_attr_fan4_min.dev_attr.attr,
2776 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2777 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2779 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
2780 &sensor_dev_attr_fan5_min.dev_attr.attr,
2781 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2782 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2784 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
2785 &sensor_dev_attr_fan6_min.dev_attr.attr,
2786 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2787 &sensor_dev_attr_fan6_beep.dev_attr.attr,
2791 static const struct attribute_group it87_group_fan = {
2792 .attrs = it87_attributes_fan,
2793 .is_visible = it87_fan_is_visible,
2796 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2797 struct attribute *attr, int index)
2799 struct device *dev = container_of(kobj, struct device, kobj);
2800 struct it87_data *data = dev_get_drvdata(dev);
2801 int i = index / 4; /* pwm index */
2802 int a = index % 4; /* attribute index */
2804 if (!(data->has_pwm & BIT(i)))
2807 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2808 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2809 return attr->mode | 0200;
2811 /* pwm2_freq is writable if there are two pwm frequency selects */
2812 if (has_pwm_freq2(data) && i == 1 && a == 2)
2813 return attr->mode | 0200;
2818 static struct attribute *it87_attributes_pwm[] = {
2819 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2820 &sensor_dev_attr_pwm1.dev_attr.attr,
2821 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2822 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2824 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2825 &sensor_dev_attr_pwm2.dev_attr.attr,
2826 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2827 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2829 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2830 &sensor_dev_attr_pwm3.dev_attr.attr,
2831 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2832 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2834 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2835 &sensor_dev_attr_pwm4.dev_attr.attr,
2836 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2837 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2839 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2840 &sensor_dev_attr_pwm5.dev_attr.attr,
2841 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2842 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2844 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2845 &sensor_dev_attr_pwm6.dev_attr.attr,
2846 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2847 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2852 static const struct attribute_group it87_group_pwm = {
2853 .attrs = it87_attributes_pwm,
2854 .is_visible = it87_pwm_is_visible,
2857 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2858 struct attribute *attr, int index)
2860 struct device *dev = container_of(kobj, struct device, kobj);
2861 struct it87_data *data = dev_get_drvdata(dev);
2862 int i = index / 11; /* pwm index */
2863 int a = index % 11; /* attribute index */
2865 if (index >= 33) { /* pwm 4..6 */
2866 i = (index - 33) / 6 + 3;
2867 a = (index - 33) % 6 + 4;
2870 if (!(data->has_pwm & BIT(i)))
2873 if (has_newer_autopwm(data)) {
2874 if (a < 4) /* no auto point pwm */
2876 if (a == 8) /* no auto_point4 */
2879 if (has_old_autopwm(data)) {
2880 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
2887 static struct attribute *it87_attributes_auto_pwm[] = {
2888 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2889 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2890 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2891 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2892 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2893 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2894 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2895 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2896 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2897 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2898 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2900 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
2901 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2902 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2903 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2904 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2905 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2906 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2907 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2908 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2909 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2910 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2912 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
2913 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2914 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2915 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2916 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2917 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2918 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2919 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2920 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2921 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2922 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2924 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
2925 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2926 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2927 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2928 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2929 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2931 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2932 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2933 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2934 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2935 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2936 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2938 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2939 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2940 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2941 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2942 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2943 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2948 static const struct attribute_group it87_group_auto_pwm = {
2949 .attrs = it87_attributes_auto_pwm,
2950 .is_visible = it87_auto_pwm_is_visible,
2953 /* SuperIO detection - will change isa_address if a chip is found */
2954 static int __init it87_find(int sioaddr, unsigned short *address,
2955 phys_addr_t *mmio_address,
2956 struct it87_sio_data *sio_data)
2958 const struct it87_devices *config;
2959 phys_addr_t base = 0;
2965 err = superio_enter(sioaddr);
2969 sio_data->sioaddr = sioaddr;
2972 chip_type = superio_inw(sioaddr, DEVID);
2973 if (chip_type == 0xffff)
2977 chip_type = force_id;
2979 switch (chip_type) {
2981 sio_data->type = it87;
2984 sio_data->type = it8712;
2988 sio_data->type = it8716;
2991 sio_data->type = it8718;
2994 sio_data->type = it8720;
2997 sio_data->type = it8721;
3000 sio_data->type = it8728;
3003 sio_data->type = it8732;
3006 sio_data->type = it8792;
3008 * Disabling configuration mode on IT8792E can result in system
3009 * hang-ups and access failures to the Super-IO chip at the
3010 * second SIO address. Never exit configuration mode on this
3011 * chip to avoid the problem.
3016 sio_data->type = it8771;
3019 sio_data->type = it8772;
3022 sio_data->type = it8781;
3025 sio_data->type = it8782;
3028 sio_data->type = it8783;
3031 sio_data->type = it8786;
3034 sio_data->type = it8790;
3035 doexit = false; /* See IT8792E comment above */
3039 sio_data->type = it8603;
3042 sio_data->type = it8606;
3045 sio_data->type = it8607;
3048 sio_data->type = it8613;
3051 sio_data->type = it8620;
3054 sio_data->type = it8622;
3057 sio_data->type = it8625;
3060 sio_data->type = it8628;
3063 sio_data->type = it8655;
3066 sio_data->type = it8665;
3069 sio_data->type = it8686;
3071 case 0xffff: /* No device at all */
3074 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3078 superio_select(sioaddr, PME);
3079 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3080 pr_info("Device not activated, skipping\n");
3084 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3085 if (*address == 0) {
3086 pr_info("Base address not set, skipping\n");
3090 sio_data->doexit = doexit;
3093 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3095 config = &it87_devices[sio_data->type];
3097 if (has_mmio(config) && mmio) {
3100 reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
3102 base = 0xf0000000 + ((reg & 0x0f) << 24);
3103 base += (reg & 0xc0) << 14;
3106 *mmio_address = base;
3110 snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
3112 pr_info("Found %s chip at 0x%x%s, revision %d\n",
3113 it87_devices[sio_data->type].model,
3114 *address, mmio_str, sio_data->revision);
3116 /* in7 (VSB or VCCH5V) is always internal on some chips */
3117 if (has_in7_internal(config))
3118 sio_data->internal |= BIT(1);
3120 /* in8 (Vbat) is always internal */
3121 sio_data->internal |= BIT(2);
3123 /* in9 (AVCC3), always internal if supported */
3124 if (has_avcc3(config))
3125 sio_data->internal |= BIT(3); /* in9 is AVCC */
3127 sio_data->skip_in |= BIT(9);
3129 if (!has_four_pwm(config))
3130 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3131 else if (!has_five_pwm(config))
3132 sio_data->skip_pwm |= BIT(4) | BIT(5);
3133 else if (!has_six_pwm(config))
3134 sio_data->skip_pwm |= BIT(5);
3136 if (!has_vid(config))
3137 sio_data->skip_vid = 1;
3139 /* Read GPIO config and VID value from LDN 7 (GPIO) */
3140 if (sio_data->type == it87) {
3141 /* The IT8705F has a different LD number for GPIO */
3142 superio_select(sioaddr, 5);
3143 sio_data->beep_pin = superio_inb(sioaddr,
3144 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3145 } else if (sio_data->type == it8783) {
3146 int reg25, reg27, reg2a, reg2c, regef;
3148 superio_select(sioaddr, GPIO);
3150 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3151 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3152 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3153 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3154 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3156 /* Check if fan3 is there or not */
3157 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3158 sio_data->skip_fan |= BIT(2);
3159 if ((reg25 & BIT(4)) ||
3160 (!(reg2a & BIT(1)) && (regef & BIT(0))))
3161 sio_data->skip_pwm |= BIT(2);
3163 /* Check if fan2 is there or not */
3165 sio_data->skip_fan |= BIT(1);
3167 sio_data->skip_pwm |= BIT(1);
3170 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3171 sio_data->skip_in |= BIT(5); /* No VIN5 */
3175 sio_data->skip_in |= BIT(6); /* No VIN6 */
3179 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3181 if (reg27 & BIT(2)) {
3183 * The data sheet is a bit unclear regarding the
3184 * internal voltage divider for VCCH5V. It says
3185 * "This bit enables and switches VIN7 (pin 91) to the
3186 * internal voltage divider for VCCH5V".
3187 * This is different to other chips, where the internal
3188 * voltage divider would connect VIN7 to an internal
3189 * voltage source. Maybe that is the case here as well.
3191 * Since we don't know for sure, re-route it if that is
3192 * not the case, and ask the user to report if the
3193 * resulting voltage is sane.
3195 if (!(reg2c & BIT(1))) {
3197 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3199 pr_notice("Routing internal VCCH5V to in7.\n");
3201 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3202 pr_notice("Please report if it displays a reasonable voltage.\n");
3206 sio_data->internal |= BIT(0);
3208 sio_data->internal |= BIT(1);
3210 sio_data->beep_pin = superio_inb(sioaddr,
3211 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3212 } else if (sio_data->type == it8603 || sio_data->type == it8606 ||
3213 sio_data->type == it8607) {
3216 superio_select(sioaddr, GPIO);
3218 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3220 /* Check if fan3 is there or not */
3222 sio_data->skip_pwm |= BIT(2);
3224 sio_data->skip_fan |= BIT(2);
3226 /* Check if fan2 is there or not */
3227 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3229 sio_data->skip_pwm |= BIT(1);
3231 sio_data->skip_fan |= BIT(1);
3233 switch (sio_data->type) {
3235 sio_data->skip_in |= BIT(5); /* No VIN5 */
3236 sio_data->skip_in |= BIT(6); /* No VIN6 */
3239 sio_data->skip_pwm |= BIT(0);/* No fan1 */
3240 sio_data->skip_fan |= BIT(0);
3245 sio_data->beep_pin = superio_inb(sioaddr,
3246 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3247 } else if (sio_data->type == it8613) {
3248 int reg27, reg29, reg2a;
3250 superio_select(sioaddr, GPIO);
3252 /* Check for pwm3, fan3, pwm5, fan5 */
3253 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3255 sio_data->skip_fan |= BIT(4);
3257 sio_data->skip_pwm |= BIT(4);
3259 sio_data->skip_pwm |= BIT(2);
3261 sio_data->skip_fan |= BIT(2);
3263 /* Check for pwm2, fan2 */
3264 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3266 sio_data->skip_pwm |= BIT(1);
3268 sio_data->skip_fan |= BIT(1);
3270 /* Check for pwm4, fan4 */
3271 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3272 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3273 sio_data->skip_fan |= BIT(3);
3274 sio_data->skip_pwm |= BIT(3);
3277 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3278 sio_data->skip_fan |= BIT(0); /* No fan1 */
3279 sio_data->skip_in |= BIT(3); /* No VIN3 */
3280 sio_data->skip_in |= BIT(6); /* No VIN6 */
3282 sio_data->beep_pin = superio_inb(sioaddr,
3283 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3284 } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3285 sio_data->type == it8686) {
3288 superio_select(sioaddr, GPIO);
3290 /* Check for pwm5 */
3291 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3293 sio_data->skip_pwm |= BIT(4);
3295 /* Check for fan4, fan5 */
3296 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3297 if (!(reg & BIT(5)))
3298 sio_data->skip_fan |= BIT(3);
3299 if (!(reg & BIT(4)))
3300 sio_data->skip_fan |= BIT(4);
3302 /* Check for pwm3, fan3 */
3303 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3305 sio_data->skip_pwm |= BIT(2);
3307 sio_data->skip_fan |= BIT(2);
3309 /* Check for pwm4 */
3310 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3312 sio_data->skip_pwm |= BIT(3);
3314 /* Check for pwm2, fan2 */
3315 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3317 sio_data->skip_pwm |= BIT(1);
3319 sio_data->skip_fan |= BIT(1);
3320 /* Check for pwm6, fan6 */
3321 if (!(reg & BIT(7))) {
3322 sio_data->skip_pwm |= BIT(5);
3323 sio_data->skip_fan |= BIT(5);
3326 /* Check if AVCC is on VIN3 */
3327 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3329 /* For it8686, the bit just enables AVCC3 */
3330 if (sio_data->type != it8686)
3331 sio_data->internal |= BIT(0);
3333 sio_data->internal &= ~BIT(3);
3334 sio_data->skip_in |= BIT(9);
3337 sio_data->beep_pin = superio_inb(sioaddr,
3338 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3339 } else if (sio_data->type == it8622) {
3342 superio_select(sioaddr, GPIO);
3344 /* Check for pwm4, fan4 */
3345 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3347 sio_data->skip_fan |= BIT(3);
3349 sio_data->skip_pwm |= BIT(3);
3351 /* Check for pwm3, fan3, pwm5, fan5 */
3352 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3354 sio_data->skip_pwm |= BIT(2);
3356 sio_data->skip_fan |= BIT(2);
3358 sio_data->skip_pwm |= BIT(4);
3360 sio_data->skip_fan |= BIT(4);
3362 /* Check for pwm2, fan2 */
3363 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3365 sio_data->skip_pwm |= BIT(1);
3367 sio_data->skip_fan |= BIT(1);
3369 /* Check for AVCC */
3370 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3371 if (!(reg & BIT(0)))
3372 sio_data->skip_in |= BIT(9);
3374 sio_data->beep_pin = superio_inb(sioaddr,
3375 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3376 } else if (sio_data->type == it8732) {
3379 superio_select(sioaddr, GPIO);
3381 /* Check for pwm2, fan2 */
3382 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3384 sio_data->skip_pwm |= BIT(1);
3386 sio_data->skip_fan |= BIT(1);
3388 /* Check for pwm3, fan3, fan4 */
3389 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3391 sio_data->skip_pwm |= BIT(2);
3393 sio_data->skip_fan |= BIT(2);
3395 sio_data->skip_fan |= BIT(3);
3397 /* Check if AVCC is on VIN3 */
3398 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3400 sio_data->internal |= BIT(0);
3402 sio_data->beep_pin = superio_inb(sioaddr,
3403 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3404 } else if (sio_data->type == it8655) {
3407 superio_select(sioaddr, GPIO);
3409 /* Check for pwm2 */
3410 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3412 sio_data->skip_pwm |= BIT(1);
3414 /* Check for fan2 */
3415 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3417 sio_data->skip_fan |= BIT(1);
3419 /* Check for pwm3, fan3 */
3420 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3422 sio_data->skip_pwm |= BIT(2);
3424 sio_data->skip_fan |= BIT(2);
3426 sio_data->beep_pin = superio_inb(sioaddr,
3427 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3428 } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3429 int reg27, reg29, reg2d, regd3;
3431 superio_select(sioaddr, GPIO);
3433 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3434 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3435 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3436 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3438 /* Check for pwm2, fan2 */
3440 sio_data->skip_pwm |= BIT(1);
3442 * Note: Table 6-1 in datasheet claims that FAN_TAC2
3443 * would be enabled with 29h[2]=0.
3446 sio_data->skip_fan |= BIT(1);
3448 /* Check for pwm3, fan3 */
3450 sio_data->skip_pwm |= BIT(2);
3452 sio_data->skip_fan |= BIT(2);
3454 /* Check for pwm4, fan4, pwm5, fan5 */
3455 if (sio_data->type == it8625) {
3456 int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3459 sio_data->skip_fan |= BIT(3);
3461 sio_data->skip_pwm |= BIT(3);
3463 sio_data->skip_pwm |= BIT(4);
3465 sio_data->skip_fan |= BIT(4);
3467 int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3470 sio_data->skip_pwm |= BIT(3);
3472 sio_data->skip_fan |= BIT(3);
3474 sio_data->skip_pwm |= BIT(4);
3476 sio_data->skip_fan |= BIT(4);
3479 /* Check for pwm6, fan6 */
3481 sio_data->skip_pwm |= BIT(5);
3483 sio_data->skip_fan |= BIT(5);
3485 sio_data->beep_pin = superio_inb(sioaddr,
3486 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3491 superio_select(sioaddr, GPIO);
3493 /* Check for fan4, fan5 */
3494 if (has_five_fans(config)) {
3495 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3496 switch (sio_data->type) {
3499 sio_data->skip_fan |= BIT(3);
3501 sio_data->skip_fan |= BIT(4);
3506 if (!(reg & BIT(5)))
3507 sio_data->skip_fan |= BIT(3);
3508 if (!(reg & BIT(4)))
3509 sio_data->skip_fan |= BIT(4);
3516 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3517 if (!sio_data->skip_vid) {
3518 /* We need at least 4 VID pins */
3520 pr_info("VID is disabled (pins used for GPIO)\n");
3521 sio_data->skip_vid = 1;
3525 /* Check if fan3 is there or not */
3527 sio_data->skip_pwm |= BIT(2);
3529 sio_data->skip_fan |= BIT(2);
3531 /* Check if fan2 is there or not */
3532 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3534 sio_data->skip_pwm |= BIT(1);
3536 sio_data->skip_fan |= BIT(1);
3538 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3539 !(sio_data->skip_vid))
3540 sio_data->vid_value = superio_inb(sioaddr,
3543 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3545 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3548 * The IT8720F has no VIN7 pin, so VCCH should always be
3549 * routed internally to VIN7 with an internal divider.
3550 * Curiously, there still is a configuration bit to control
3551 * this, which means it can be set incorrectly. And even
3552 * more curiously, many boards out there are improperly
3553 * configured, even though the IT8720F datasheet claims
3554 * that the internal routing of VCCH to VIN7 is the default
3555 * setting. So we force the internal routing in this case.
3557 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3558 * If UART6 is enabled, re-route VIN7 to the internal divider
3559 * if that is not already the case.
3561 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3563 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3564 pr_notice("Routing internal VCCH to in7\n");
3567 sio_data->internal |= BIT(0);
3569 sio_data->internal |= BIT(1);
3572 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3573 * While VIN7 can be routed to the internal voltage divider,
3574 * VIN5 and VIN6 are not available if UART6 is enabled.
3576 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3577 * is the temperature source. Since we can not read the
3578 * temperature source here, skip_temp is preliminary.
3581 sio_data->skip_in |= BIT(5) | BIT(6);
3582 sio_data->skip_temp |= BIT(2);
3585 sio_data->beep_pin = superio_inb(sioaddr,
3586 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3588 if (sio_data->beep_pin)
3589 pr_info("Beeping is supported\n");
3591 if (config->smbus_bitmap && !base) {
3594 superio_select(sioaddr, PME);
3595 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3596 sio_data->ec_special_config = reg;
3597 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3601 superio_exit(sioaddr, doexit);
3605 static void it87_init_regs(struct platform_device *pdev)
3607 struct it87_data *data = platform_get_drvdata(pdev);
3609 /* Initialize chip specific register pointers */
3610 switch (data->type) {
3613 data->REG_FAN = IT87_REG_FAN;
3614 data->REG_FANX = IT87_REG_FANX;
3615 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3616 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3617 data->REG_PWM = IT87_REG_PWM;
3618 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3619 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3620 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3625 data->REG_FAN = IT87_REG_FAN_8665;
3626 data->REG_FANX = IT87_REG_FANX_8665;
3627 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3628 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3629 data->REG_PWM = IT87_REG_PWM_8665;
3630 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3631 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3632 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3635 data->REG_FAN = IT87_REG_FAN;
3636 data->REG_FANX = IT87_REG_FANX;
3637 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3638 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3639 data->REG_PWM = IT87_REG_PWM_8665;
3640 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3641 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3642 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3645 data->REG_FAN = IT87_REG_FAN;
3646 data->REG_FANX = IT87_REG_FANX;
3647 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3648 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3649 data->REG_PWM = IT87_REG_PWM_8665;
3650 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3651 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3652 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3655 data->REG_FAN = IT87_REG_FAN;
3656 data->REG_FANX = IT87_REG_FANX;
3657 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3658 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3659 data->REG_PWM = IT87_REG_PWM;
3660 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3661 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3662 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3667 data->read = it87_mmio_read;
3668 data->write = it87_mmio_write;
3669 } else if (has_bank_sel(data)) {
3670 data->read = it87_io_read;
3671 data->write = it87_io_write;
3673 data->read = _it87_io_read;
3674 data->write = _it87_io_write;
3678 /* Called when we have found a new IT87. */
3679 static void it87_init_device(struct platform_device *pdev)
3681 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3682 struct it87_data *data = platform_get_drvdata(pdev);
3686 if (has_new_tempmap(data)) {
3687 data->pwm_temp_map_shift = 3;
3688 data->pwm_temp_map_mask = 0x07;
3690 data->pwm_temp_map_shift = 0;
3691 data->pwm_temp_map_mask = 0x03;
3695 * For each PWM channel:
3696 * - If it is in automatic mode, setting to manual mode should set
3697 * the fan to full speed by default.
3698 * - If it is in manual mode, we need a mapping to temperature
3699 * channels to use when later setting to automatic mode later.
3700 * Map to the first sensor by default (we are clueless.)
3701 * In both cases, the value can (and should) be changed by the user
3702 * prior to switching to a different mode.
3703 * Note that this is no longer needed for the IT8721F and later, as
3704 * these have separate registers for the temperature mapping and the
3705 * manual duty cycle.
3707 for (i = 0; i < NUM_AUTO_PWM; i++) {
3708 data->pwm_temp_map[i] = 0;
3709 data->pwm_duty[i] = 0x7f; /* Full speed */
3710 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
3714 * Some chips seem to have default value 0xff for all limit
3715 * registers. For low voltage limits it makes no sense and triggers
3716 * alarms, so change to 0 instead. For high temperature limits, it
3717 * means -1 degree C, which surprisingly doesn't trigger an alarm,
3718 * but is still confusing, so change to 127 degrees C.
3720 for (i = 0; i < NUM_VIN_LIMIT; i++) {
3721 tmp = data->read(data, IT87_REG_VIN_MIN(i));
3723 data->write(data, IT87_REG_VIN_MIN(i), 0);
3725 for (i = 0; i < data->num_temp_limit; i++) {
3726 tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3728 data->write(data, data->REG_TEMP_HIGH[i], 127);
3732 * Temperature channels are not forcibly enabled, as they can be
3733 * set to two different sensor types and we can't guess which one
3734 * is correct for a given system. These channels can be enabled at
3735 * run-time through the temp{1-3}_type sysfs accessors if needed.
3738 /* Check if voltage monitors are reset manually or by some reason */
3739 tmp = data->read(data, IT87_REG_VIN_ENABLE);
3740 if ((tmp & 0xff) == 0) {
3741 /* Enable all voltage monitors */
3742 data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3745 /* Check if tachometers are reset manually or by some reason */
3746 mask = 0x70 & ~(sio_data->skip_fan << 4);
3747 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3748 if ((data->fan_main_ctrl & mask) == 0) {
3749 /* Enable all fan tachometers */
3750 data->fan_main_ctrl |= mask;
3751 data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3753 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3755 tmp = data->read(data, IT87_REG_FAN_16BIT);
3757 /* Set tachometers to 16-bit mode if needed */
3758 if (has_fan16_config(data)) {
3759 if (~tmp & 0x07 & data->has_fan) {
3761 "Setting fan1-3 to 16-bit mode\n");
3762 data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3766 /* Check for additional fans */
3767 if (has_four_fans(data) && (tmp & BIT(4)))
3768 data->has_fan |= BIT(3); /* fan4 enabled */
3769 if (has_five_fans(data) && (tmp & BIT(5)))
3770 data->has_fan |= BIT(4); /* fan5 enabled */
3771 if (has_six_fans(data)) {
3772 switch (data->type) {
3777 data->has_fan |= BIT(5); /* fan6 enabled */
3781 tmp = data->read(data, IT87_REG_FAN_DIV);
3783 data->has_fan |= BIT(5); /* fan6 enabled */
3790 /* Fan input pins may be used for alternative functions */
3791 data->has_fan &= ~sio_data->skip_fan;
3793 /* Check if pwm6 is enabled */
3794 if (has_six_pwm(data)) {
3795 switch (data->type) {
3798 tmp = data->read(data, IT87_REG_FAN_DIV);
3799 if (!(tmp & BIT(3)))
3800 sio_data->skip_pwm |= BIT(5);
3807 if (has_bank_sel(data)) {
3808 for (i = 0; i < 3; i++)
3810 data->read(data, IT87_REG_TEMP_SRC1[i]);
3811 data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3814 /* Start monitoring */
3815 data->write(data, IT87_REG_CONFIG,
3816 (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3817 (update_vbat ? 0x41 : 0x01));
3820 /* Return 1 if and only if the PWM interface is safe to use */
3821 static int it87_check_pwm(struct device *dev)
3823 struct it87_data *data = dev_get_drvdata(dev);
3825 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3826 * and polarity set to active low is sign that this is the case so we
3827 * disable pwm control to protect the user.
3829 int tmp = data->read(data, IT87_REG_FAN_CTL);
3831 if ((tmp & 0x87) == 0) {
3832 if (fix_pwm_polarity) {
3834 * The user asks us to attempt a chip reconfiguration.
3835 * This means switching to active high polarity and
3836 * inverting all fan speed values.
3841 for (i = 0; i < ARRAY_SIZE(pwm); i++)
3842 pwm[i] = data->read(data,
3846 * If any fan is in automatic pwm mode, the polarity
3847 * might be correct, as suspicious as it seems, so we
3848 * better don't change anything (but still disable the
3851 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3853 "Reconfiguring PWM to active high polarity\n");
3854 data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3855 for (i = 0; i < 3; i++)
3856 data->write(data, data->REG_PWM[i],
3862 "PWM configuration is too broken to be fixed\n");
3866 "Detected broken BIOS defaults, disabling PWM interface\n");
3868 } else if (fix_pwm_polarity) {
3870 "PWM configuration looks sane, won't touch\n");
3876 static int it87_probe(struct platform_device *pdev)
3878 struct it87_data *data;
3879 struct resource *res;
3880 struct device *dev = &pdev->dev;
3881 struct it87_sio_data *sio_data = dev_get_platdata(dev);
3882 int enable_pwm_interface;
3883 struct device *hwmon_dev;
3886 data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3890 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3892 if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3894 dev_err(dev, "Failed to request region %pR\n", res);
3898 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3899 data->mmio = devm_ioremap_resource(dev, res);
3900 if (IS_ERR(data->mmio))
3901 return PTR_ERR(data->mmio);
3904 data->addr = res->start;
3905 data->type = sio_data->type;
3906 data->sioaddr = sio_data->sioaddr;
3907 data->smbus_bitmap = sio_data->smbus_bitmap;
3908 data->ec_special_config = sio_data->ec_special_config;
3909 data->doexit = sio_data->doexit;
3910 data->features = it87_devices[sio_data->type].features;
3911 data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3912 data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3913 data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3914 data->peci_mask = it87_devices[sio_data->type].peci_mask;
3915 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3918 * IT8705F Datasheet 0.4.1, 3h == Version G.
3919 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3920 * These are the first revisions with 16-bit tachometer support.
3922 switch (data->type) {
3924 if (sio_data->revision >= 0x03) {
3925 data->features &= ~FEAT_OLD_AUTOPWM;
3926 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3930 if (sio_data->revision >= 0x08) {
3931 data->features &= ~FEAT_OLD_AUTOPWM;
3932 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3940 platform_set_drvdata(pdev, data);
3942 mutex_init(&data->update_lock);
3944 /* Initialize register pointers */
3945 it87_init_regs(pdev);
3947 err = smbus_disable(data);
3951 /* Now, we do the remaining detection. */
3952 if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
3953 data->read(data, IT87_REG_CHIPID) != 0x90) {
3958 /* Check PWM configuration */
3959 enable_pwm_interface = it87_check_pwm(dev);
3961 /* Starting with IT8721F, we handle scaling of internal voltages */
3962 if (has_scaling(data)) {
3963 if (sio_data->internal & BIT(0))
3964 data->in_scaled |= BIT(3); /* in3 is AVCC */
3965 if (sio_data->internal & BIT(1))
3966 data->in_scaled |= BIT(7); /* in7 is VSB */
3967 if (sio_data->internal & BIT(2))
3968 data->in_scaled |= BIT(8); /* in8 is Vbat */
3969 if (sio_data->internal & BIT(3))
3970 data->in_scaled |= BIT(9); /* in9 is AVCC */
3971 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3972 sio_data->type == it8783) {
3973 if (sio_data->internal & BIT(0))
3974 data->in_scaled |= BIT(3); /* in3 is VCC5V */
3975 if (sio_data->internal & BIT(1))
3976 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
3979 data->has_temp = 0x07;
3980 if (sio_data->skip_temp & BIT(2)) {
3981 if (sio_data->type == it8782 &&
3982 !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
3983 data->has_temp &= ~BIT(2);
3986 data->in_internal = sio_data->internal;
3987 data->has_in = 0x3ff & ~sio_data->skip_in;
3989 if (has_four_temp(data)) {
3990 data->has_temp |= BIT(3);
3991 } else if (has_six_temp(data)) {
3992 u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
3994 /* Check for additional temperature sensors */
3995 if ((reg & 0x03) >= 0x02)
3996 data->has_temp |= BIT(3);
3997 if (((reg >> 2) & 0x03) >= 0x02)
3998 data->has_temp |= BIT(4);
3999 if (((reg >> 4) & 0x03) >= 0x02)
4000 data->has_temp |= BIT(5);
4002 /* Check for additional voltage sensors */
4003 if ((reg & 0x03) == 0x01)
4004 data->has_in |= BIT(10);
4005 if (((reg >> 2) & 0x03) == 0x01)
4006 data->has_in |= BIT(11);
4007 if (((reg >> 4) & 0x03) == 0x01)
4008 data->has_in |= BIT(12);
4011 data->has_beep = !!sio_data->beep_pin;
4013 /* Initialize the IT87 chip */
4014 it87_init_device(pdev);
4018 if (!sio_data->skip_vid) {
4019 data->has_vid = true;
4020 data->vrm = vid_which_vrm();
4021 /* VID reading from Super-I/O config space if available */
4022 data->vid = sio_data->vid_value;
4025 /* Prepare for sysfs hooks */
4026 data->groups[0] = &it87_group;
4027 data->groups[1] = &it87_group_in;
4028 data->groups[2] = &it87_group_temp;
4029 data->groups[3] = &it87_group_fan;
4031 if (enable_pwm_interface) {
4032 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
4033 data->has_pwm &= ~sio_data->skip_pwm;
4035 data->groups[4] = &it87_group_pwm;
4036 if (has_old_autopwm(data) || has_newer_autopwm(data))
4037 data->groups[5] = &it87_group_auto_pwm;
4040 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
4041 it87_devices[sio_data->type].name,
4042 data, data->groups);
4043 return PTR_ERR_OR_ZERO(hwmon_dev);
4046 static struct platform_driver it87_driver = {
4050 .probe = it87_probe,
4053 static int __init it87_device_add(int index, unsigned short sio_address,
4054 phys_addr_t mmio_address,
4055 const struct it87_sio_data *sio_data)
4057 struct platform_device *pdev;
4058 struct resource res = {
4064 res.start = mmio_address;
4065 res.end = mmio_address + 0x400 - 1;
4066 res.flags = IORESOURCE_MEM;
4068 res.start = sio_address + IT87_EC_OFFSET;
4069 res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
4070 res.flags = IORESOURCE_IO;
4073 err = acpi_check_resource_conflict(&res);
4075 if (!ignore_resource_conflict)
4079 pdev = platform_device_alloc(DRVNAME, sio_address);
4083 err = platform_device_add_resources(pdev, &res, 1);
4085 pr_err("Device resource addition failed (%d)\n", err);
4086 goto exit_device_put;
4089 err = platform_device_add_data(pdev, sio_data,
4090 sizeof(struct it87_sio_data));
4092 pr_err("Platform data allocation failed\n");
4093 goto exit_device_put;
4096 err = platform_device_add(pdev);
4098 pr_err("Device addition failed (%d)\n", err);
4099 goto exit_device_put;
4102 it87_pdev[index] = pdev;
4106 platform_device_put(pdev);
4110 struct it87_dmi_data {
4111 bool sio2_force_config; /* force sio2 into configuration mode */
4112 u8 skip_pwm; /* pwm channels to skip for this board */
4116 * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4117 * (IT8792E) needs to be in configuration mode before accessing the first
4118 * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4119 * This needs to be done before accessing the first Super-IO chip since
4120 * the second chip may have been accessed prior to loading this driver.
4122 * The problem is also reported to affect IT8795E, which is used on X299 boards
4123 * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4124 * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4126 * DMI entries for those systems will be added as they become available and
4127 * as the problem is confirmed to affect those boards.
4129 static struct it87_dmi_data gigabyte_sio2_force = {
4130 .sio2_force_config = true,
4134 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4135 * connected to a fan, but to something else. One user
4136 * has reported instant system power-off when changing
4137 * the PWM2 duty cycle, so we disable it.
4138 * I use the board name string as the trigger in case
4139 * the same board is ever used in other systems.
4141 static struct it87_dmi_data nvidia_fn68pt = {
4145 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4148 DMI_MATCH(DMI_SYS_VENDOR,
4149 "Gigabyte Technology Co., Ltd."),
4150 DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4152 .driver_data = &gigabyte_sio2_force,
4156 DMI_MATCH(DMI_SYS_VENDOR,
4157 "Gigabyte Technology Co., Ltd."),
4158 DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4160 .driver_data = &gigabyte_sio2_force,
4164 DMI_MATCH(DMI_SYS_VENDOR,
4165 "Gigabyte Technology Co., Ltd."),
4166 DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4168 .driver_data = &gigabyte_sio2_force,
4172 DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4173 DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4175 .driver_data = &nvidia_fn68pt,
4180 static int __init sm_it87_init(void)
4182 const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4183 struct it87_dmi_data *dmi_data = NULL;
4184 int sioaddr[2] = { REG_2E, REG_4E };
4185 struct it87_sio_data sio_data;
4186 unsigned short isa_address;
4187 phys_addr_t mmio_address;
4191 pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4194 dmi_data = dmi->driver_data;
4196 err = platform_driver_register(&it87_driver);
4200 if (dmi_data && dmi_data->sio2_force_config)
4201 __superio_enter(REG_4E);
4203 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4204 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4207 err = it87_find(sioaddr[i], &isa_address, &mmio_address,
4209 if (err || isa_address == 0)
4213 sio_data.skip_pwm |= dmi_data->skip_pwm;
4214 err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4216 goto exit_dev_unregister;
4222 goto exit_unregister;
4226 exit_dev_unregister:
4227 /* NULL check handled by platform_device_unregister */
4228 platform_device_unregister(it87_pdev[0]);
4230 platform_driver_unregister(&it87_driver);
4234 static void __exit sm_it87_exit(void)
4236 /* NULL check handled by platform_device_unregister */
4237 platform_device_unregister(it87_pdev[1]);
4238 platform_device_unregister(it87_pdev[0]);
4239 platform_driver_unregister(&it87_driver);
4242 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4243 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4244 module_param(update_vbat, bool, 0000);
4245 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4246 module_param(fix_pwm_polarity, bool, 0000);
4247 MODULE_PARM_DESC(fix_pwm_polarity,
4248 "Force PWM polarity to active high (DANGEROUS)");
4249 MODULE_LICENSE("GPL");
4251 module_init(sm_it87_init);
4252 module_exit(sm_it87_exit);