git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77
  78 #define DRVNAME "it87"
  79
  80 /* Necessary API not (yet) exported in upstream kernel */
  81 /* #define __IT87_USE_ACPI_MUTEX */
  82
  83 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  84              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  85              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  86              it8655, it8665, it8686 };
  87
  88 static unsigned short force_id;
  89 module_param(force_id, ushort, 0);
  90 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  91
  92 static unsigned short blacklist = 1;
  93 module_param(blacklist, ushort, 0);
  94 MODULE_PARM_DESC(blacklist,
  95                  "Enable/disable blacklist (1=enable, 0=disable, default 1)");
  96
  97 static struct platform_device *it87_pdev[2];
  98 static bool it87_sio4e_broken;
  99 #ifdef __IT87_USE_ACPI_MUTEX
 100 static acpi_handle it87_acpi_sio_handle;
 101 static char *it87_acpi_sio_mutex;
 102 #endif
 103
 104 #define REG_2E  0x2e    /* The register to read/write */
 105 #define REG_4E  0x4e    /* Secondary register to read/write */
 106
 107 #define DEV     0x07    /* Register: Logical device select */
 108 #define PME     0x04    /* The device with the fan registers in it */
 109
 110 /* The device with the IT8718F/IT8720F VID value in it */
 111 #define GPIO    0x07
 112
 113 #define DEVID   0x20    /* Register: Device ID */
 114 #define DEVREV  0x22    /* Register: Device Revision */
 115
 116 static inline void __superio_enter(int ioreg)
 117 {
 118         outb(0x87, ioreg);
 119         outb(0x01, ioreg);
 120         outb(0x55, ioreg);
 121         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 122 }
 123
 124 static inline int superio_inb(int ioreg, int reg)
 125 {
 126         int val;
 127
 128         outb(reg, ioreg);
 129         val = inb(ioreg + 1);
 130         if (it87_sio4e_broken && ioreg == 0x4e && val == 0xff) {
 131                 __superio_enter(ioreg);
 132                 outb(reg, ioreg);
 133                 val = inb(ioreg + 1);
 134                 pr_warn("Retry access 0x4e:0x%x -> 0x%x\n", reg, val);
 135         }
 136
 137         return val;
 138 }
 139
 140 static inline void superio_outb(int ioreg, int reg, int val)
 141 {
 142         outb(reg, ioreg);
 143         outb(val, ioreg + 1);
 144 }
 145
 146 static int superio_inw(int ioreg, int reg)
 147 {
 148         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 149 }
 150
 151 static inline void superio_select(int ioreg, int ldn)
 152 {
 153         outb(DEV, ioreg);
 154         outb(ldn, ioreg + 1);
 155 }
 156
 157 static inline int superio_enter(int ioreg)
 158 {
 159 #ifdef __IT87_USE_ACPI_MUTEX
 160         if (it87_acpi_sio_mutex) {
 161                 acpi_status status;
 162
 163                 status = acpi_acquire_mutex(NULL, it87_acpi_sio_mutex, 0x10);
 164                 if (ACPI_FAILURE(status)) {
 165                         pr_err("Failed to acquire ACPI mutex\n");
 166                         return -EBUSY;
 167                 }
 168         }
 169 #endif
 170         /*
 171          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 172          */
 173         if (!request_muxed_region(ioreg, 2, DRVNAME))
 174                 goto error;
 175
 176         __superio_enter(ioreg);
 177         return 0;
 178
 179 error:
 180 #ifdef __IT87_USE_ACPI_MUTEX
 181         if (it87_acpi_sio_mutex)
 182                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 183 #endif
 184         return -EBUSY;
 185 }
 186
 187 static inline void superio_exit(int ioreg)
 188 {
 189         if (!it87_sio4e_broken || ioreg != 0x4e) {
 190                 outb(0x02, ioreg);
 191                 outb(0x02, ioreg + 1);
 192         }
 193         release_region(ioreg, 2);
 194 #ifdef __IT87_USE_ACPI_MUTEX
 195         if (it87_acpi_sio_mutex)
 196                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 197 #endif
 198 }
 199
 200 /* Logical device 4 registers */
 201 #define IT8712F_DEVID 0x8712
 202 #define IT8705F_DEVID 0x8705
 203 #define IT8716F_DEVID 0x8716
 204 #define IT8718F_DEVID 0x8718
 205 #define IT8720F_DEVID 0x8720
 206 #define IT8721F_DEVID 0x8721
 207 #define IT8726F_DEVID 0x8726
 208 #define IT8728F_DEVID 0x8728
 209 #define IT8732F_DEVID 0x8732
 210 #define IT8792E_DEVID 0x8733
 211 #define IT8771E_DEVID 0x8771
 212 #define IT8772E_DEVID 0x8772
 213 #define IT8781F_DEVID 0x8781
 214 #define IT8782F_DEVID 0x8782
 215 #define IT8783E_DEVID 0x8783
 216 #define IT8786E_DEVID 0x8786
 217 #define IT8790E_DEVID 0x8790
 218 #define IT8603E_DEVID 0x8603
 219 #define IT8607E_DEVID 0x8607
 220 #define IT8613E_DEVID 0x8613
 221 #define IT8620E_DEVID 0x8620
 222 #define IT8622E_DEVID 0x8622
 223 #define IT8623E_DEVID 0x8623
 224 #define IT8625E_DEVID 0x8625
 225 #define IT8628E_DEVID 0x8628
 226 #define IT8655E_DEVID 0x8655
 227 #define IT8665E_DEVID 0x8665
 228 #define IT8686E_DEVID 0x8686
 229 #define IT87_ACT_REG  0x30
 230 #define IT87_BASE_REG 0x60
 231
 232 /* Logical device 7 registers (IT8712F and later) */
 233 #define IT87_SIO_GPIO1_REG      0x25
 234 #define IT87_SIO_GPIO2_REG      0x26
 235 #define IT87_SIO_GPIO3_REG      0x27
 236 #define IT87_SIO_GPIO4_REG      0x28
 237 #define IT87_SIO_GPIO5_REG      0x29
 238 #define IT87_SIO_GPIO9_REG      0xd3
 239 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 240 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 241 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 242 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 243 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 244 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 245
 246 /* Update battery voltage after every reading if true */
 247 static bool update_vbat;
 248
 249 /* Not all BIOSes properly configure the PWM registers */
 250 static bool fix_pwm_polarity;
 251
 252 /* Many IT87 constants specified below */
 253
 254 /* Length of ISA address segment */
 255 #define IT87_EXTENT 8
 256
 257 /* Length of ISA address segment for Environmental Controller */
 258 #define IT87_EC_EXTENT 2
 259
 260 /* Offset of EC registers from ISA base address */
 261 #define IT87_EC_OFFSET 5
 262
 263 /* Where are the ISA address/data registers relative to the EC base address */
 264 #define IT87_ADDR_REG_OFFSET 0
 265 #define IT87_DATA_REG_OFFSET 1
 266
 267 /*----- The IT87 registers -----*/
 268
 269 #define IT87_REG_CONFIG        0x00
 270
 271 #define IT87_REG_ALARM1        0x01
 272 #define IT87_REG_ALARM2        0x02
 273 #define IT87_REG_ALARM3        0x03
 274
 275 #define IT87_REG_BANK           0x06
 276
 277 /*
 278  * The IT8718F and IT8720F have the VID value in a different register, in
 279  * Super-I/O configuration space.
 280  */
 281 #define IT87_REG_VID           0x0a
 282 /*
 283  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 284  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 285  * mode.
 286  */
 287 #define IT87_REG_FAN_DIV       0x0b
 288 #define IT87_REG_FAN_16BIT     0x0c
 289
 290 /*
 291  * Monitors:
 292  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 293  * - up to 6 temp (1 to 6)
 294  * - up to 6 fan (1 to 6)
 295  */
 296
 297 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 298 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 299 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 300 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 301
 302 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 303 static const u8 IT87_REG_FAN_MIN_8665[] =
 304                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 305 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 306 static const u8 IT87_REG_FANX_MIN_8665[] =
 307                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 308
 309 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 310
 311 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 312
 313 #define IT87_REG_FAN_MAIN_CTRL 0x13
 314 #define IT87_REG_FAN_CTL       0x14
 315
 316 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 317 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 318
 319 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 320
 321 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 322                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 323
 324 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 325
 326 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 327 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 328
 329 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 330 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 331
 332 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 333                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 334 static const u8 IT87_REG_TEMP_LOW_8686[] =
 335                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 336
 337 #define IT87_REG_VIN_ENABLE    0x50
 338 #define IT87_REG_TEMP_ENABLE   0x51
 339 #define IT87_REG_TEMP_EXTRA    0x55
 340 #define IT87_REG_BEEP_ENABLE   0x5c
 341
 342 #define IT87_REG_CHIPID        0x58
 343
 344 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 345
 346 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 347 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 348
 349 #define IT87_REG_TEMP456_ENABLE 0x77
 350
 351 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 352 #define IT87_REG_TEMP_SRC2      0x23d
 353
 354 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 355 #define NUM_VIN_LIMIT           8
 356 #define NUM_TEMP                6
 357 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 358 #define NUM_FAN_DIV             3
 359 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 360 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 361
 362 struct it87_devices {
 363         const char *name;
 364         const char * const suffix;
 365         u32 features;
 366         u8 num_temp_limit;
 367         u8 num_temp_offset;
 368         u8 peci_mask;
 369         u8 old_peci_mask;
 370 };
 371
 372 #define FEAT_12MV_ADC           BIT(0)
 373 #define FEAT_NEWER_AUTOPWM      BIT(1)
 374 #define FEAT_OLD_AUTOPWM        BIT(2)
 375 #define FEAT_16BIT_FANS         BIT(3)
 376 #define FEAT_TEMP_PECI          BIT(5)
 377 #define FEAT_TEMP_OLD_PECI      BIT(6)
 378 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 379 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 380 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 381 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 382 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 383 #define FEAT_10_9MV_ADC         BIT(12)
 384 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 385 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 386 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 387 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 388 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 389 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 390 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 391 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 392 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 393 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 394 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 395 #define FEAT_11MV_ADC           BIT(24)
 396 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 397
 398 static const struct it87_devices it87_devices[] = {
 399         [it87] = {
 400                 .name = "it87",
 401                 .suffix = "F",
 402                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 403                                                 /* may need to overwrite */
 404                 .num_temp_limit = 3,
 405                 .num_temp_offset = 0,
 406         },
 407         [it8712] = {
 408                 .name = "it8712",
 409                 .suffix = "F",
 410                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 411                                                 /* may need to overwrite */
 412                 .num_temp_limit = 3,
 413                 .num_temp_offset = 0,
 414         },
 415         [it8716] = {
 416                 .name = "it8716",
 417                 .suffix = "F",
 418                 .features = FEAT_16BIT_FANS | FEAT_VID
 419                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 420                   | FEAT_FANCTL_ONOFF,
 421                 .num_temp_limit = 3,
 422                 .num_temp_offset = 3,
 423         },
 424         [it8718] = {
 425                 .name = "it8718",
 426                 .suffix = "F",
 427                 .features = FEAT_16BIT_FANS | FEAT_VID
 428                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 429                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 430                 .num_temp_limit = 3,
 431                 .num_temp_offset = 3,
 432                 .old_peci_mask = 0x4,
 433         },
 434         [it8720] = {
 435                 .name = "it8720",
 436                 .suffix = "F",
 437                 .features = FEAT_16BIT_FANS | FEAT_VID
 438                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 439                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 440                 .num_temp_limit = 3,
 441                 .num_temp_offset = 3,
 442                 .old_peci_mask = 0x4,
 443         },
 444         [it8721] = {
 445                 .name = "it8721",
 446                 .suffix = "F",
 447                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 448                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 449                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 450                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 451                 .num_temp_limit = 3,
 452                 .num_temp_offset = 3,
 453                 .peci_mask = 0x05,
 454                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 455         },
 456         [it8728] = {
 457                 .name = "it8728",
 458                 .suffix = "F",
 459                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 460                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 461                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 462                   | FEAT_FANCTL_ONOFF,
 463                 .num_temp_limit = 6,
 464                 .num_temp_offset = 3,
 465                 .peci_mask = 0x07,
 466         },
 467         [it8732] = {
 468                 .name = "it8732",
 469                 .suffix = "F",
 470                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 471                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 472                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 473                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 474                 .num_temp_limit = 3,
 475                 .num_temp_offset = 3,
 476                 .peci_mask = 0x07,
 477                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 478         },
 479         [it8771] = {
 480                 .name = "it8771",
 481                 .suffix = "E",
 482                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 483                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 484                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 485                                 /* PECI: guesswork */
 486                                 /* 12mV ADC (OHM) */
 487                                 /* 16 bit fans (OHM) */
 488                                 /* three fans, always 16 bit (guesswork) */
 489                 .num_temp_limit = 3,
 490                 .num_temp_offset = 3,
 491                 .peci_mask = 0x07,
 492         },
 493         [it8772] = {
 494                 .name = "it8772",
 495                 .suffix = "E",
 496                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 497                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 498                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 499                                 /* PECI (coreboot) */
 500                                 /* 12mV ADC (HWSensors4, OHM) */
 501                                 /* 16 bit fans (HWSensors4, OHM) */
 502                                 /* three fans, always 16 bit (datasheet) */
 503                 .num_temp_limit = 3,
 504                 .num_temp_offset = 3,
 505                 .peci_mask = 0x07,
 506         },
 507         [it8781] = {
 508                 .name = "it8781",
 509                 .suffix = "F",
 510                 .features = FEAT_16BIT_FANS
 511                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 512                   | FEAT_FANCTL_ONOFF,
 513                 .num_temp_limit = 3,
 514                 .num_temp_offset = 3,
 515                 .old_peci_mask = 0x4,
 516         },
 517         [it8782] = {
 518                 .name = "it8782",
 519                 .suffix = "F",
 520                 .features = FEAT_16BIT_FANS
 521                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 522                   | FEAT_FANCTL_ONOFF,
 523                 .num_temp_limit = 3,
 524                 .num_temp_offset = 3,
 525                 .old_peci_mask = 0x4,
 526         },
 527         [it8783] = {
 528                 .name = "it8783",
 529                 .suffix = "E/F",
 530                 .features = FEAT_16BIT_FANS
 531                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 532                   | FEAT_FANCTL_ONOFF,
 533                 .num_temp_limit = 3,
 534                 .num_temp_offset = 3,
 535                 .old_peci_mask = 0x4,
 536         },
 537         [it8786] = {
 538                 .name = "it8786",
 539                 .suffix = "E",
 540                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 541                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 542                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 543                 .num_temp_limit = 3,
 544                 .num_temp_offset = 3,
 545                 .peci_mask = 0x07,
 546         },
 547         [it8790] = {
 548                 .name = "it8790",
 549                 .suffix = "E",
 550                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 551                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 552                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 553                 .num_temp_limit = 3,
 554                 .num_temp_offset = 3,
 555                 .peci_mask = 0x07,
 556         },
 557         [it8792] = {
 558                 .name = "it8792",
 559                 .suffix = "E",
 560                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 561                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 562                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 563                 .num_temp_limit = 3,
 564                 .num_temp_offset = 3,
 565                 .peci_mask = 0x07,
 566         },
 567         [it8603] = {
 568                 .name = "it8603",
 569                 .suffix = "E",
 570                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 571                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 572                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 573                 .num_temp_limit = 3,
 574                 .num_temp_offset = 3,
 575                 .peci_mask = 0x07,
 576         },
 577         [it8607] = {
 578                 .name = "it8607",
 579                 .suffix = "E",
 580                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 581                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 582                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 583                   | FEAT_FANCTL_ONOFF,
 584                 .num_temp_limit = 3,
 585                 .num_temp_offset = 3,
 586                 .peci_mask = 0x07,
 587         },
 588         [it8613] = {
 589                 .name = "it8613",
 590                 .suffix = "E",
 591                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 592                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 593                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 594                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 595                 .num_temp_limit = 6,
 596                 .num_temp_offset = 6,
 597                 .peci_mask = 0x07,
 598         },
 599         [it8620] = {
 600                 .name = "it8620",
 601                 .suffix = "E",
 602                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 603                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 604                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 605                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 606                   | FEAT_FANCTL_ONOFF,
 607                 .num_temp_limit = 3,
 608                 .num_temp_offset = 3,
 609                 .peci_mask = 0x07,
 610         },
 611         [it8622] = {
 612                 .name = "it8622",
 613                 .suffix = "E",
 614                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 615                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 616                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 617                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 618                 .num_temp_limit = 3,
 619                 .num_temp_offset = 3,
 620                 .peci_mask = 0x07,
 621         },
 622         [it8625] = {
 623                 .name = "it8625",
 624                 .suffix = "E",
 625                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 626                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 627                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 628                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 629                 .num_temp_limit = 6,
 630                 .num_temp_offset = 6,
 631         },
 632         [it8628] = {
 633                 .name = "it8628",
 634                 .suffix = "E",
 635                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 636                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 637                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 638                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 639                   | FEAT_FANCTL_ONOFF,
 640                 .num_temp_limit = 6,
 641                 .num_temp_offset = 3,
 642                 .peci_mask = 0x07,
 643         },
 644         [it8655] = {
 645                 .name = "it8655",
 646                 .suffix = "E",
 647                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 648                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 649                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 650                 .num_temp_limit = 6,
 651                 .num_temp_offset = 6,
 652         },
 653         [it8665] = {
 654                 .name = "it8665",
 655                 .suffix = "E",
 656                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 657                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 658                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 659                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 660                 .num_temp_limit = 6,
 661                 .num_temp_offset = 6,
 662         },
 663         [it8686] = {
 664                 .name = "it8686",
 665                 .suffix = "E",
 666                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 667                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 668                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 669                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 670                 .num_temp_limit = 6,
 671                 .num_temp_offset = 6,
 672         },
 673 };
 674
 675 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 676 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 677 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 678 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 679 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 680 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 681                                  ((data)->peci_mask & BIT(nr)))
 682 #define has_temp_old_peci(data, nr) \
 683                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 684                                  ((data)->old_peci_mask & BIT(nr)))
 685 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 686 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 687                                                      FEAT_SIX_FANS))
 688 #define has_vid(data)           ((data)->features & FEAT_VID)
 689 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 690 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 691 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 692 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 693                                                      | FEAT_SIX_PWM))
 694 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 695 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 696 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 697 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 698 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 699                                                      FEAT_FIVE_FANS | \
 700                                                      FEAT_SIX_FANS))
 701 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 702                                                      FEAT_FIVE_PWM \
 703                                                      | FEAT_SIX_PWM))
 704 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 705 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 706 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 707 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 708 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 709
 710 struct it87_sio_data {
 711         enum chips type;
 712         /* Values read from Super-I/O config space */
 713         u8 revision;
 714         u8 vid_value;
 715         u8 beep_pin;
 716         u8 internal;    /* Internal sensors can be labeled */
 717         /* Features skipped based on config or DMI */
 718         u16 skip_in;
 719         u8 skip_vid;
 720         u8 skip_fan;
 721         u8 skip_pwm;
 722         u8 skip_temp;
 723 };
 724
 725 /*
 726  * For each registered chip, we need to keep some data in memory.
 727  * The structure is dynamically allocated.
 728  */
 729 struct it87_data {
 730         const struct attribute_group *groups[7];
 731         enum chips type;
 732         u32 features;
 733         u8 bank;
 734         u8 peci_mask;
 735         u8 old_peci_mask;
 736
 737         const u8 *REG_FAN;
 738         const u8 *REG_FANX;
 739         const u8 *REG_FAN_MIN;
 740         const u8 *REG_FANX_MIN;
 741
 742         const u8 *REG_PWM;
 743
 744         const u8 *REG_TEMP_OFFSET;
 745         const u8 *REG_TEMP_LOW;
 746         const u8 *REG_TEMP_HIGH;
 747
 748         unsigned short addr;
 749         const char *name;
 750         struct mutex update_lock;
 751         char valid;             /* !=0 if following fields are valid */
 752         unsigned long last_updated;     /* In jiffies */
 753
 754         u16 in_scaled;          /* Internal voltage sensors are scaled */
 755         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 756         u16 has_in;             /* Bitfield, voltage sensors enabled */
 757         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 758         u8 has_fan;             /* Bitfield, fans enabled */
 759         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 760         u8 has_temp;            /* Bitfield, temp sensors enabled */
 761         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 762         u8 num_temp_limit;      /* Number of temperature limit registers */
 763         u8 num_temp_offset;     /* Number of temperature offset registers */
 764         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 765         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 766         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 767         bool has_vid;           /* True if VID supported */
 768         u8 vid;                 /* Register encoding, combined */
 769         u8 vrm;
 770         u32 alarms;             /* Register encoding, combined */
 771         bool has_beep;          /* true if beep supported */
 772         u8 beeps;               /* Register encoding */
 773         u8 fan_main_ctrl;       /* Register value */
 774         u8 fan_ctl;             /* Register value */
 775
 776         /*
 777          * The following 3 arrays correspond to the same registers up to
 778          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 779          * 7, and we want to preserve settings on mode changes, so we have
 780          * to track all values separately.
 781          * Starting with the IT8721F, the manual PWM duty cycles are stored
 782          * in separate registers (8-bit values), so the separate tracking
 783          * is no longer needed, but it is still done to keep the driver
 784          * simple.
 785          */
 786         u8 has_pwm;             /* Bitfield, pwm control enabled */
 787         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 788         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 789         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 790
 791         /* Automatic fan speed control registers */
 792         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 793         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 794 };
 795
 796 static int adc_lsb(const struct it87_data *data, int nr)
 797 {
 798         int lsb;
 799
 800         if (has_12mv_adc(data))
 801                 lsb = 120;
 802         else if (has_10_9mv_adc(data))
 803                 lsb = 109;
 804         else if (has_11mv_adc(data))
 805                 lsb = 110;
 806         else
 807                 lsb = 160;
 808         if (data->in_scaled & BIT(nr))
 809                 lsb <<= 1;
 810         return lsb;
 811 }
 812
 813 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 814 {
 815         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 816         return clamp_val(val, 0, 255);
 817 }
 818
 819 static int in_from_reg(const struct it87_data *data, int nr, int val)
 820 {
 821         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 822 }
 823
 824 static inline u8 FAN_TO_REG(long rpm, int div)
 825 {
 826         if (rpm == 0)
 827                 return 255;
 828         rpm = clamp_val(rpm, 1, 1000000);
 829         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 830 }
 831
 832 static inline u16 FAN16_TO_REG(long rpm)
 833 {
 834         if (rpm == 0)
 835                 return 0xffff;
 836         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 837 }
 838
 839 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 840                                 1350000 / ((val) * (div)))
 841 /* The divider is fixed to 2 in 16-bit mode */
 842 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 843                              1350000 / ((val) * 2))
 844
 845 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 846                                     ((val) + 500) / 1000), -128, 127))
 847 #define TEMP_FROM_REG(val) ((val) * 1000)
 848
 849 static u8 pwm_to_reg(const struct it87_data *data, long val)
 850 {
 851         if (has_newer_autopwm(data))
 852                 return val;
 853         else
 854                 return val >> 1;
 855 }
 856
 857 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 858 {
 859         if (has_newer_autopwm(data))
 860                 return reg;
 861         else
 862                 return (reg & 0x7f) << 1;
 863 }
 864
 865 static int DIV_TO_REG(int val)
 866 {
 867         int answer = 0;
 868
 869         while (answer < 7 && (val >>= 1))
 870                 answer++;
 871         return answer;
 872 }
 873
 874 #define DIV_FROM_REG(val) BIT(val)
 875
 876 /*
 877  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 878  * depending on the chip type, to calculate the actual PWM frequency.
 879  *
 880  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 881  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 882  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 883  * sometimes just one. It is unknown if this is a datasheet error or real,
 884  * so this is ignored for now.
 885  */
 886 static const unsigned int pwm_freq[8] = {
 887         48000000,
 888         24000000,
 889         12000000,
 890         8000000,
 891         6000000,
 892         3000000,
 893         1500000,
 894         750000,
 895 };
 896
 897 static int _it87_read_value(struct it87_data *data, u8 reg)
 898 {
 899         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 900         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 901 }
 902
 903 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 904 {
 905         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 906         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 907 }
 908
 909 static void it87_set_bank(struct it87_data *data, u8 bank)
 910 {
 911         if (has_bank_sel(data) && bank != data->bank) {
 912                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 913
 914                 breg &= 0x1f;
 915                 breg |= (bank << 5);
 916                 data->bank = bank;
 917                 _it87_write_value(data, IT87_REG_BANK, breg);
 918         }
 919 }
 920
 921 /*
 922  * Must be called with data->update_lock held, except during initialization.
 923  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 924  * would slow down the IT87 access and should not be necessary.
 925  */
 926 static int it87_read_value(struct it87_data *data, u16 reg)
 927 {
 928         it87_set_bank(data, reg >> 8);
 929         return _it87_read_value(data, reg & 0xff);
 930 }
 931
 932 /*
 933  * Must be called with data->update_lock held, except during initialization.
 934  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 935  * would slow down the IT87 access and should not be necessary.
 936  */
 937 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
 938 {
 939         it87_set_bank(data, reg >> 8);
 940         _it87_write_value(data, reg & 0xff, value);
 941 }
 942
 943 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 944 {
 945         data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]);
 946         if (has_newer_autopwm(data)) {
 947                 if (has_new_tempmap(data))
 948                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x38;
 949                 else
 950                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 951                 data->pwm_duty[nr] = it87_read_value(data,
 952                                                      IT87_REG_PWM_DUTY[nr]);
 953         } else {
 954                 if (data->pwm_ctrl[nr] & 0x80)  /* Automatic mode */
 955                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 956                 else                            /* Manual mode */
 957                         data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
 958         }
 959
 960         if (has_old_autopwm(data)) {
 961                 int i;
 962
 963                 for (i = 0; i < 5 ; i++)
 964                         data->auto_temp[nr][i] = it87_read_value(data,
 965                                                 IT87_REG_AUTO_TEMP(nr, i));
 966                 for (i = 0; i < 3 ; i++)
 967                         data->auto_pwm[nr][i] = it87_read_value(data,
 968                                                 IT87_REG_AUTO_PWM(nr, i));
 969         } else if (has_newer_autopwm(data)) {
 970                 int i;
 971
 972                 /*
 973                  * 0: temperature hysteresis (base + 5)
 974                  * 1: fan off temperature (base + 0)
 975                  * 2: fan start temperature (base + 1)
 976                  * 3: fan max temperature (base + 2)
 977                  */
 978                 data->auto_temp[nr][0] =
 979                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
 980
 981                 for (i = 0; i < 3 ; i++)
 982                         data->auto_temp[nr][i + 1] =
 983                                 it87_read_value(data,
 984                                                 IT87_REG_AUTO_TEMP(nr, i));
 985                 /*
 986                  * 0: start pwm value (base + 3)
 987                  * 1: pwm slope (base + 4, 1/8th pwm)
 988                  */
 989                 data->auto_pwm[nr][0] =
 990                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
 991                 data->auto_pwm[nr][1] =
 992                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
 993         }
 994 }
 995
 996 static struct it87_data *it87_update_device(struct device *dev)
 997 {
 998         struct it87_data *data = dev_get_drvdata(dev);
 999         int i;
1000
1001         mutex_lock(&data->update_lock);
1002
1003         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1004             !data->valid) {
1005                 if (update_vbat) {
1006                         /*
1007                          * Cleared after each update, so reenable.  Value
1008                          * returned by this read will be previous value
1009                          */
1010                         it87_write_value(data, IT87_REG_CONFIG,
1011                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1012                 }
1013                 for (i = 0; i < NUM_VIN; i++) {
1014                         if (!(data->has_in & BIT(i)))
1015                                 continue;
1016
1017                         data->in[i][0] =
1018                                 it87_read_value(data, IT87_REG_VIN[i]);
1019
1020                         /* VBAT and AVCC don't have limit registers */
1021                         if (i >= NUM_VIN_LIMIT)
1022                                 continue;
1023
1024                         data->in[i][1] =
1025                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
1026                         data->in[i][2] =
1027                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
1028                 }
1029
1030                 for (i = 0; i < NUM_FAN; i++) {
1031                         /* Skip disabled fans */
1032                         if (!(data->has_fan & BIT(i)))
1033                                 continue;
1034
1035                         data->fan[i][1] =
1036                                 it87_read_value(data, data->REG_FAN_MIN[i]);
1037                         data->fan[i][0] = it87_read_value(data,
1038                                        data->REG_FAN[i]);
1039                         /* Add high byte if in 16-bit mode */
1040                         if (has_16bit_fans(data)) {
1041                                 data->fan[i][0] |= it87_read_value(data,
1042                                                 data->REG_FANX[i]) << 8;
1043                                 data->fan[i][1] |= it87_read_value(data,
1044                                                 data->REG_FANX_MIN[i]) << 8;
1045                         }
1046                 }
1047                 for (i = 0; i < NUM_TEMP; i++) {
1048                         if (!(data->has_temp & BIT(i)))
1049                                 continue;
1050                         data->temp[i][0] =
1051                                 it87_read_value(data, IT87_REG_TEMP(i));
1052
1053                         if (i >= data->num_temp_limit)
1054                                 continue;
1055
1056                         if (i < data->num_temp_offset)
1057                                 data->temp[i][3] =
1058                                   it87_read_value(data,
1059                                                   data->REG_TEMP_OFFSET[i]);
1060
1061                         data->temp[i][1] =
1062                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1063                         data->temp[i][2] =
1064                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1065                 }
1066
1067                 /* Newer chips don't have clock dividers */
1068                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1069                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1070                         data->fan_div[0] = i & 0x07;
1071                         data->fan_div[1] = (i >> 3) & 0x07;
1072                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1073                 }
1074
1075                 data->alarms =
1076                         it87_read_value(data, IT87_REG_ALARM1) |
1077                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1078                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1079                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1080
1081                 data->fan_main_ctrl = it87_read_value(data,
1082                                 IT87_REG_FAN_MAIN_CTRL);
1083                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1084                 for (i = 0; i < NUM_PWM; i++) {
1085                         if (!(data->has_pwm & BIT(i)))
1086                                 continue;
1087                         it87_update_pwm_ctrl(data, i);
1088                 }
1089
1090                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1091                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1092                 /*
1093                  * The IT8705F does not have VID capability.
1094                  * The IT8718F and later don't use IT87_REG_VID for the
1095                  * same purpose.
1096                  */
1097                 if (data->type == it8712 || data->type == it8716) {
1098                         data->vid = it87_read_value(data, IT87_REG_VID);
1099                         /*
1100                          * The older IT8712F revisions had only 5 VID pins,
1101                          * but we assume it is always safe to read 6 bits.
1102                          */
1103                         data->vid &= 0x3f;
1104                 }
1105                 data->last_updated = jiffies;
1106                 data->valid = 1;
1107         }
1108
1109         mutex_unlock(&data->update_lock);
1110
1111         return data;
1112 }
1113
1114 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1115                        char *buf)
1116 {
1117         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1118         struct it87_data *data = it87_update_device(dev);
1119         int index = sattr->index;
1120         int nr = sattr->nr;
1121
1122         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1123 }
1124
1125 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1126                       const char *buf, size_t count)
1127 {
1128         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1129         struct it87_data *data = dev_get_drvdata(dev);
1130         int index = sattr->index;
1131         int nr = sattr->nr;
1132         unsigned long val;
1133
1134         if (kstrtoul(buf, 10, &val) < 0)
1135                 return -EINVAL;
1136
1137         mutex_lock(&data->update_lock);
1138         data->in[nr][index] = in_to_reg(data, nr, val);
1139         it87_write_value(data,
1140                          index == 1 ? IT87_REG_VIN_MIN(nr)
1141                                     : IT87_REG_VIN_MAX(nr),
1142                          data->in[nr][index]);
1143         mutex_unlock(&data->update_lock);
1144         return count;
1145 }
1146
1147 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1148 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1149                             0, 1);
1150 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1151                             0, 2);
1152
1153 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1154 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1155                             1, 1);
1156 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1157                             1, 2);
1158
1159 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1160 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1161                             2, 1);
1162 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1163                             2, 2);
1164
1165 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1166 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1167                             3, 1);
1168 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1169                             3, 2);
1170
1171 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1172 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1173                             4, 1);
1174 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1175                             4, 2);
1176
1177 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1178 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1179                             5, 1);
1180 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1181                             5, 2);
1182
1183 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1184 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1185                             6, 1);
1186 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1187                             6, 2);
1188
1189 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1190 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1191                             7, 1);
1192 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1193                             7, 2);
1194
1195 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1196 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1197 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1198 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1199 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1200
1201 /* Up to 6 temperatures */
1202 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1203                          char *buf)
1204 {
1205         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1206         int nr = sattr->nr;
1207         int index = sattr->index;
1208         struct it87_data *data = it87_update_device(dev);
1209
1210         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1211 }
1212
1213 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1214                         const char *buf, size_t count)
1215 {
1216         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1217         int nr = sattr->nr;
1218         int index = sattr->index;
1219         struct it87_data *data = dev_get_drvdata(dev);
1220         long val;
1221         u8 reg, regval;
1222
1223         if (kstrtol(buf, 10, &val) < 0)
1224                 return -EINVAL;
1225
1226         mutex_lock(&data->update_lock);
1227
1228         switch (index) {
1229         default:
1230         case 1:
1231                 reg = data->REG_TEMP_LOW[nr];
1232                 break;
1233         case 2:
1234                 reg = data->REG_TEMP_HIGH[nr];
1235                 break;
1236         case 3:
1237                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1238                 if (!(regval & 0x80)) {
1239                         regval |= 0x80;
1240                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1241                 }
1242                 data->valid = 0;
1243                 reg = data->REG_TEMP_OFFSET[nr];
1244                 break;
1245         }
1246
1247         data->temp[nr][index] = TEMP_TO_REG(val);
1248         it87_write_value(data, reg, data->temp[nr][index]);
1249         mutex_unlock(&data->update_lock);
1250         return count;
1251 }
1252
1253 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1254 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1255                             0, 1);
1256 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1257                             0, 2);
1258 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1259                             set_temp, 0, 3);
1260 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1261 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1262                             1, 1);
1263 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1264                             1, 2);
1265 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1266                             set_temp, 1, 3);
1267 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1268 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1269                             2, 1);
1270 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1271                             2, 2);
1272 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1273                             set_temp, 2, 3);
1274 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1275 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1276                             3, 1);
1277 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1278                             3, 2);
1279 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1280                             set_temp, 3, 3);
1281 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1282 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1283                             4, 1);
1284 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1285                             4, 2);
1286 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1287                             set_temp, 4, 3);
1288 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1289 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1290                             5, 1);
1291 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1292                             5, 2);
1293 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1294                             set_temp, 5, 3);
1295
1296 static int get_temp_type(struct it87_data *data, int index)
1297 {
1298         u8 reg, extra;
1299         int type = 0;
1300
1301         if (has_bank_sel(data)) {
1302                 int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
1303                 u8 src1, src2;
1304
1305                 src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
1306                 src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
1307
1308                 switch (data->type) {
1309                 case it8686:
1310                         switch (src1) {
1311                         case 0:
1312                                 if (index >= 3)
1313                                         return 4;
1314                                 break;
1315                         case 1:
1316                                 if (index == 1 || index == 2 ||
1317                                           index == 4 || index == 5)
1318                                         return 6;
1319                                 break;
1320                         case 2:
1321                                 if (index == 2 || index == 6)
1322                                         return 5;
1323                                 break;
1324                         default:
1325                                 break;
1326                         }
1327                         break;
1328                 case it8625:
1329                         if (index < 3)
1330                                 break;
1331                 case it8655:
1332                 case it8665:
1333                         if (src1 < 3) {
1334                                 index = src1;
1335                                 break;
1336                         }
1337                         switch(src1) {
1338                         case 3:
1339                                 type = (src2 & BIT(index)) ? 6 : 5;
1340                                 break;
1341                         case 4 ... 8:
1342                                 type = (src2 & BIT(index)) ? 4 : 6;
1343                                 break;
1344                         case 9:
1345                                 type = (src2 & BIT(index)) ? 5 : 0;
1346                                 break;
1347                         default:
1348                                 break;
1349                         }
1350                         return type;
1351                 default:
1352                         return 0;
1353                 }
1354         }
1355         if (index >= 3)
1356                 return 0;
1357
1358         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1359         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1360
1361         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1362             (has_temp_old_peci(data, index) && (extra & 0x80)))
1363                 type = 6;               /* Intel PECI */
1364         if (reg & BIT(index))
1365                 type = 3;               /* thermal diode */
1366         else if (reg & BIT(index + 3))
1367                 type = 4;               /* thermistor */
1368
1369         return type;
1370 }
1371
1372 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1373                               char *buf)
1374 {
1375         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1376         struct it87_data *data = it87_update_device(dev);
1377         int type = get_temp_type(data, sensor_attr->index);
1378
1379         return sprintf(buf, "%d\n", type);
1380 }
1381
1382 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1383                              const char *buf, size_t count)
1384 {
1385         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1386         int nr = sensor_attr->index;
1387
1388         struct it87_data *data = dev_get_drvdata(dev);
1389         long val;
1390         u8 reg, extra;
1391
1392         if (kstrtol(buf, 10, &val) < 0)
1393                 return -EINVAL;
1394
1395         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1396         reg &= ~(1 << nr);
1397         reg &= ~(8 << nr);
1398         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1399                 reg &= 0x3f;
1400         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1401         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1402                 extra &= 0x7f;
1403         if (val == 2) { /* backwards compatibility */
1404                 dev_warn(dev,
1405                          "Sensor type 2 is deprecated, please use 4 instead\n");
1406                 val = 4;
1407         }
1408         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1409         if (val == 3)
1410                 reg |= 1 << nr;
1411         else if (val == 4)
1412                 reg |= 8 << nr;
1413         else if (has_temp_peci(data, nr) && val == 6)
1414                 reg |= (nr + 1) << 6;
1415         else if (has_temp_old_peci(data, nr) && val == 6)
1416                 extra |= 0x80;
1417         else if (val != 0)
1418                 return -EINVAL;
1419
1420         mutex_lock(&data->update_lock);
1421         data->sensor = reg;
1422         data->extra = extra;
1423         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1424         if (has_temp_old_peci(data, nr))
1425                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1426         data->valid = 0;        /* Force cache refresh */
1427         mutex_unlock(&data->update_lock);
1428         return count;
1429 }
1430
1431 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1432                           set_temp_type, 0);
1433 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1434                           set_temp_type, 1);
1435 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1436                           set_temp_type, 2);
1437 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1438                           set_temp_type, 3);
1439 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1440                           set_temp_type, 4);
1441 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1442                           set_temp_type, 5);
1443
1444 /* 6 Fans */
1445
1446 static int pwm_mode(const struct it87_data *data, int nr)
1447 {
1448         if (has_fanctl_onoff(data) && nr < 3 &&
1449             !(data->fan_main_ctrl & BIT(nr)))
1450                 return 0;                               /* Full speed */
1451         if (data->pwm_ctrl[nr] & 0x80)
1452                 return 2;                               /* Automatic mode */
1453         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1454             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1455                 return 0;                       /* Full speed */
1456
1457         return 1;                               /* Manual mode */
1458 }
1459
1460 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1461                         char *buf)
1462 {
1463         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1464         int nr = sattr->nr;
1465         int index = sattr->index;
1466         int speed;
1467         struct it87_data *data = it87_update_device(dev);
1468
1469         speed = has_16bit_fans(data) ?
1470                 FAN16_FROM_REG(data->fan[nr][index]) :
1471                 FAN_FROM_REG(data->fan[nr][index],
1472                              DIV_FROM_REG(data->fan_div[nr]));
1473         return sprintf(buf, "%d\n", speed);
1474 }
1475
1476 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1477                             char *buf)
1478 {
1479         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1480         struct it87_data *data = it87_update_device(dev);
1481         int nr = sensor_attr->index;
1482
1483         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1484 }
1485
1486 static ssize_t show_pwm_enable(struct device *dev,
1487                                struct device_attribute *attr, char *buf)
1488 {
1489         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1490         struct it87_data *data = it87_update_device(dev);
1491         int nr = sensor_attr->index;
1492
1493         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1494 }
1495
1496 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1497                         char *buf)
1498 {
1499         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1500         struct it87_data *data = it87_update_device(dev);
1501         int nr = sensor_attr->index;
1502
1503         return sprintf(buf, "%d\n",
1504                        pwm_from_reg(data, data->pwm_duty[nr]));
1505 }
1506
1507 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1508                              char *buf)
1509 {
1510         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1511         struct it87_data *data = it87_update_device(dev);
1512         int nr = sensor_attr->index;
1513         unsigned int freq;
1514         int index;
1515
1516         if (has_pwm_freq2(data) && nr == 1)
1517                 index = (data->extra >> 4) & 0x07;
1518         else
1519                 index = (data->fan_ctl >> 4) & 0x07;
1520
1521         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1522
1523         return sprintf(buf, "%u\n", freq);
1524 }
1525
1526 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1527                        const char *buf, size_t count)
1528 {
1529         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1530         int nr = sattr->nr;
1531         int index = sattr->index;
1532
1533         struct it87_data *data = dev_get_drvdata(dev);
1534         long val;
1535         u8 reg;
1536
1537         if (kstrtol(buf, 10, &val) < 0)
1538                 return -EINVAL;
1539
1540         mutex_lock(&data->update_lock);
1541
1542         if (has_16bit_fans(data)) {
1543                 data->fan[nr][index] = FAN16_TO_REG(val);
1544                 it87_write_value(data, data->REG_FAN_MIN[nr],
1545                                  data->fan[nr][index] & 0xff);
1546                 it87_write_value(data, data->REG_FANX_MIN[nr],
1547                                  data->fan[nr][index] >> 8);
1548         } else {
1549                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1550                 switch (nr) {
1551                 case 0:
1552                         data->fan_div[nr] = reg & 0x07;
1553                         break;
1554                 case 1:
1555                         data->fan_div[nr] = (reg >> 3) & 0x07;
1556                         break;
1557                 case 2:
1558                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1559                         break;
1560                 }
1561                 data->fan[nr][index] =
1562                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1563                 it87_write_value(data, data->REG_FAN_MIN[nr],
1564                                  data->fan[nr][index]);
1565         }
1566
1567         mutex_unlock(&data->update_lock);
1568         return count;
1569 }
1570
1571 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1572                            const char *buf, size_t count)
1573 {
1574         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1575         struct it87_data *data = dev_get_drvdata(dev);
1576         int nr = sensor_attr->index;
1577         unsigned long val;
1578         int min;
1579         u8 old;
1580
1581         if (kstrtoul(buf, 10, &val) < 0)
1582                 return -EINVAL;
1583
1584         mutex_lock(&data->update_lock);
1585         old = it87_read_value(data, IT87_REG_FAN_DIV);
1586
1587         /* Save fan min limit */
1588         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1589
1590         switch (nr) {
1591         case 0:
1592         case 1:
1593                 data->fan_div[nr] = DIV_TO_REG(val);
1594                 break;
1595         case 2:
1596                 if (val < 8)
1597                         data->fan_div[nr] = 1;
1598                 else
1599                         data->fan_div[nr] = 3;
1600         }
1601         val = old & 0x80;
1602         val |= (data->fan_div[0] & 0x07);
1603         val |= (data->fan_div[1] & 0x07) << 3;
1604         if (data->fan_div[2] == 3)
1605                 val |= 0x1 << 6;
1606         it87_write_value(data, IT87_REG_FAN_DIV, val);
1607
1608         /* Restore fan min limit */
1609         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1610         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1611
1612         mutex_unlock(&data->update_lock);
1613         return count;
1614 }
1615
1616 /* Returns 0 if OK, -EINVAL otherwise */
1617 static int check_trip_points(struct device *dev, int nr)
1618 {
1619         const struct it87_data *data = dev_get_drvdata(dev);
1620         int i, err = 0;
1621
1622         if (has_old_autopwm(data)) {
1623                 for (i = 0; i < 3; i++) {
1624                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1625                                 err = -EINVAL;
1626                 }
1627                 for (i = 0; i < 2; i++) {
1628                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1629                                 err = -EINVAL;
1630                 }
1631         } else if (has_newer_autopwm(data)) {
1632                 for (i = 1; i < 3; i++) {
1633                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1634                                 err = -EINVAL;
1635                 }
1636         }
1637
1638         if (err) {
1639                 dev_err(dev,
1640                         "Inconsistent trip points, not switching to automatic mode\n");
1641                 dev_err(dev, "Adjust the trip points and try again\n");
1642         }
1643         return err;
1644 }
1645
1646 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1647                               const char *buf, size_t count)
1648 {
1649         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1650         struct it87_data *data = dev_get_drvdata(dev);
1651         int nr = sensor_attr->index;
1652         long val;
1653
1654         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1655                 return -EINVAL;
1656
1657         /* Check trip points before switching to automatic mode */
1658         if (val == 2) {
1659                 if (check_trip_points(dev, nr) < 0)
1660                         return -EINVAL;
1661         }
1662
1663         mutex_lock(&data->update_lock);
1664
1665         if (val == 0) {
1666                 if (nr < 3 && has_fanctl_onoff(data)) {
1667                         int tmp;
1668                         /* make sure the fan is on when in on/off mode */
1669                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1670                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1671                         /* set on/off mode */
1672                         data->fan_main_ctrl &= ~BIT(nr);
1673                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1674                                          data->fan_main_ctrl);
1675                 } else {
1676                         u8 ctrl;
1677
1678                         /* No on/off mode, set maximum pwm value */
1679                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1680                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1681                                          data->pwm_duty[nr]);
1682                         /* and set manual mode */
1683                         if (has_newer_autopwm(data)) {
1684                                 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1685                                         data->pwm_temp_map[nr];
1686                         } else {
1687                                 ctrl = data->pwm_duty[nr];
1688                         }
1689                         data->pwm_ctrl[nr] = ctrl;
1690                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1691                 }
1692         } else {
1693                 u8 ctrl;
1694
1695                 if (has_newer_autopwm(data)) {
1696                         ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1697                                 data->pwm_temp_map[nr];
1698                         if (val != 1)
1699                                 ctrl |= 0x80;
1700                 } else {
1701                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1702                 }
1703                 data->pwm_ctrl[nr] = ctrl;
1704                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1705
1706                 if (has_fanctl_onoff(data) && nr < 3) {
1707                         /* set SmartGuardian mode */
1708                         data->fan_main_ctrl |= BIT(nr);
1709                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1710                                          data->fan_main_ctrl);
1711                 }
1712         }
1713
1714         mutex_unlock(&data->update_lock);
1715         return count;
1716 }
1717
1718 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1719                        const char *buf, size_t count)
1720 {
1721         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1722         struct it87_data *data = dev_get_drvdata(dev);
1723         int nr = sensor_attr->index;
1724         long val;
1725
1726         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1727                 return -EINVAL;
1728
1729         mutex_lock(&data->update_lock);
1730         it87_update_pwm_ctrl(data, nr);
1731         if (has_newer_autopwm(data)) {
1732                 /*
1733                  * If we are in automatic mode, the PWM duty cycle register
1734                  * is read-only so we can't write the value.
1735                  */
1736                 if (data->pwm_ctrl[nr] & 0x80) {
1737                         mutex_unlock(&data->update_lock);
1738                         return -EBUSY;
1739                 }
1740                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1741                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1742                                  data->pwm_duty[nr]);
1743         } else {
1744                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1745                 /*
1746                  * If we are in manual mode, write the duty cycle immediately;
1747                  * otherwise, just store it for later use.
1748                  */
1749                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1750                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1751                         it87_write_value(data, data->REG_PWM[nr],
1752                                          data->pwm_ctrl[nr]);
1753                 }
1754         }
1755         mutex_unlock(&data->update_lock);
1756         return count;
1757 }
1758
1759 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1760                             const char *buf, size_t count)
1761 {
1762         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1763         struct it87_data *data = dev_get_drvdata(dev);
1764         int nr = sensor_attr->index;
1765         unsigned long val;
1766         int i;
1767
1768         if (kstrtoul(buf, 10, &val) < 0)
1769                 return -EINVAL;
1770
1771         val = clamp_val(val, 0, 1000000);
1772         val *= has_newer_autopwm(data) ? 256 : 128;
1773
1774         /* Search for the nearest available frequency */
1775         for (i = 0; i < 7; i++) {
1776                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1777                         break;
1778         }
1779
1780         mutex_lock(&data->update_lock);
1781         if (nr == 0) {
1782                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1783                 data->fan_ctl |= i << 4;
1784                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1785         } else {
1786                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1787                 data->extra |= i << 4;
1788                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1789         }
1790         mutex_unlock(&data->update_lock);
1791
1792         return count;
1793 }
1794
1795 static ssize_t show_pwm_temp_map(struct device *dev,
1796                                  struct device_attribute *attr, char *buf)
1797 {
1798         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1799         struct it87_data *data = it87_update_device(dev);
1800         int nr = sensor_attr->index;
1801         int map;
1802
1803         map = data->pwm_temp_map[nr];
1804         if (has_new_tempmap(data)) {
1805                 map >>= 3;
1806                 if (map >= 6)
1807                         map = 0;        /* Should never happen */
1808         } else {
1809                 if (map >= 3)
1810                         map = 0;        /* Should never happen */
1811                 if (nr >= 3)            /* pwm channels 3..6 map to temp4..6 */
1812                         map += 3;
1813         }
1814
1815         return sprintf(buf, "%d\n", (int)BIT(map));
1816 }
1817
1818 static ssize_t set_pwm_temp_map(struct device *dev,
1819                                 struct device_attribute *attr, const char *buf,
1820                                 size_t count)
1821 {
1822         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1823         struct it87_data *data = dev_get_drvdata(dev);
1824         int nr = sensor_attr->index;
1825         long val;
1826         u8 reg;
1827
1828         if (kstrtol(buf, 10, &val) < 0)
1829                 return -EINVAL;
1830
1831         if (nr >= 3 && !has_new_tempmap(data))
1832                 val -= 3;
1833
1834         switch (val) {
1835         case BIT(0):
1836                 reg = 0x00;
1837                 break;
1838         case BIT(1):
1839                 reg = 0x01;
1840                 break;
1841         case BIT(2):
1842                 reg = 0x02;
1843                 break;
1844         case BIT(3):
1845                 reg = 0x03;
1846                 break;
1847         case BIT(4):
1848                 reg = 0x04;
1849                 break;
1850         case BIT(5):
1851                 reg = 0x05;
1852                 break;
1853         case BIT(6):
1854                 reg = 0x06;
1855                 break;
1856         default:
1857                 return -EINVAL;
1858         }
1859
1860         if (has_new_tempmap(data))
1861                 reg <<= 3;
1862         else if (reg > 0x02)
1863                 return -EINVAL;
1864
1865         mutex_lock(&data->update_lock);
1866         it87_update_pwm_ctrl(data, nr);
1867         data->pwm_temp_map[nr] = reg;
1868         /*
1869          * If we are in automatic mode, write the temp mapping immediately;
1870          * otherwise, just store it for later use.
1871          */
1872         if (data->pwm_ctrl[nr] & 0x80) {
1873                 u8 mask = has_new_tempmap(data) ? 0xc7 : 0xfc;
1874
1875                 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & mask) |
1876                                                 data->pwm_temp_map[nr];
1877                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1878         }
1879         mutex_unlock(&data->update_lock);
1880         return count;
1881 }
1882
1883 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1884                              char *buf)
1885 {
1886         struct it87_data *data = it87_update_device(dev);
1887         struct sensor_device_attribute_2 *sensor_attr =
1888                         to_sensor_dev_attr_2(attr);
1889         int nr = sensor_attr->nr;
1890         int point = sensor_attr->index;
1891
1892         return sprintf(buf, "%d\n",
1893                        pwm_from_reg(data, data->auto_pwm[nr][point]));
1894 }
1895
1896 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1897                             const char *buf, size_t count)
1898 {
1899         struct it87_data *data = dev_get_drvdata(dev);
1900         struct sensor_device_attribute_2 *sensor_attr =
1901                         to_sensor_dev_attr_2(attr);
1902         int nr = sensor_attr->nr;
1903         int point = sensor_attr->index;
1904         int regaddr;
1905         long val;
1906
1907         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1908                 return -EINVAL;
1909
1910         mutex_lock(&data->update_lock);
1911         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1912         if (has_newer_autopwm(data))
1913                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1914         else
1915                 regaddr = IT87_REG_AUTO_PWM(nr, point);
1916         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1917         mutex_unlock(&data->update_lock);
1918         return count;
1919 }
1920
1921 static ssize_t show_auto_pwm_slope(struct device *dev,
1922                                    struct device_attribute *attr, char *buf)
1923 {
1924         struct it87_data *data = it87_update_device(dev);
1925         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1926         int nr = sensor_attr->index;
1927
1928         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1929 }
1930
1931 static ssize_t set_auto_pwm_slope(struct device *dev,
1932                                   struct device_attribute *attr,
1933                                   const char *buf, size_t count)
1934 {
1935         struct it87_data *data = dev_get_drvdata(dev);
1936         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1937         int nr = sensor_attr->index;
1938         unsigned long val;
1939
1940         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1941                 return -EINVAL;
1942
1943         mutex_lock(&data->update_lock);
1944         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1945         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1946                          data->auto_pwm[nr][1]);
1947         mutex_unlock(&data->update_lock);
1948         return count;
1949 }
1950
1951 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1952                               char *buf)
1953 {
1954         struct it87_data *data = it87_update_device(dev);
1955         struct sensor_device_attribute_2 *sensor_attr =
1956                         to_sensor_dev_attr_2(attr);
1957         int nr = sensor_attr->nr;
1958         int point = sensor_attr->index;
1959         int reg;
1960
1961         if (has_old_autopwm(data) || point)
1962                 reg = data->auto_temp[nr][point];
1963         else
1964                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1965
1966         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1967 }
1968
1969 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1970                              const char *buf, size_t count)
1971 {
1972         struct it87_data *data = dev_get_drvdata(dev);
1973         struct sensor_device_attribute_2 *sensor_attr =
1974                         to_sensor_dev_attr_2(attr);
1975         int nr = sensor_attr->nr;
1976         int point = sensor_attr->index;
1977         long val;
1978         int reg;
1979
1980         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1981                 return -EINVAL;
1982
1983         mutex_lock(&data->update_lock);
1984         if (has_newer_autopwm(data) && !point) {
1985                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1986                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1987                 data->auto_temp[nr][0] = reg;
1988                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1989         } else {
1990                 reg = TEMP_TO_REG(val);
1991                 data->auto_temp[nr][point] = reg;
1992                 if (has_newer_autopwm(data))
1993                         point--;
1994                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1995         }
1996         mutex_unlock(&data->update_lock);
1997         return count;
1998 }
1999
2000 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
2001 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2002                             0, 1);
2003 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
2004                           set_fan_div, 0);
2005
2006 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
2007 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2008                             1, 1);
2009 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
2010                           set_fan_div, 1);
2011
2012 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
2013 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2014                             2, 1);
2015 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
2016                           set_fan_div, 2);
2017
2018 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2019 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2020                             3, 1);
2021
2022 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2023 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2024                             4, 1);
2025
2026 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2027 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2028                             5, 1);
2029
2030 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2031                           show_pwm_enable, set_pwm_enable, 0);
2032 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2033 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2034                           set_pwm_freq, 0);
2035 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2036                           show_pwm_temp_map, set_pwm_temp_map, 0);
2037 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2038                             show_auto_pwm, set_auto_pwm, 0, 0);
2039 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2040                             show_auto_pwm, set_auto_pwm, 0, 1);
2041 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2042                             show_auto_pwm, set_auto_pwm, 0, 2);
2043 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2044                             show_auto_pwm, NULL, 0, 3);
2045 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2046                             show_auto_temp, set_auto_temp, 0, 1);
2047 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2048                             show_auto_temp, set_auto_temp, 0, 0);
2049 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2050                             show_auto_temp, set_auto_temp, 0, 2);
2051 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2052                             show_auto_temp, set_auto_temp, 0, 3);
2053 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2054                             show_auto_temp, set_auto_temp, 0, 4);
2055 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2056                             show_auto_pwm, set_auto_pwm, 0, 0);
2057 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2058                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2059
2060 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2061                           show_pwm_enable, set_pwm_enable, 1);
2062 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2063 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2064 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2065                           show_pwm_temp_map, set_pwm_temp_map, 1);
2066 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2067                             show_auto_pwm, set_auto_pwm, 1, 0);
2068 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2069                             show_auto_pwm, set_auto_pwm, 1, 1);
2070 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2071                             show_auto_pwm, set_auto_pwm, 1, 2);
2072 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2073                             show_auto_pwm, NULL, 1, 3);
2074 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2075                             show_auto_temp, set_auto_temp, 1, 1);
2076 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2077                             show_auto_temp, set_auto_temp, 1, 0);
2078 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2079                             show_auto_temp, set_auto_temp, 1, 2);
2080 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2081                             show_auto_temp, set_auto_temp, 1, 3);
2082 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2083                             show_auto_temp, set_auto_temp, 1, 4);
2084 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2085                             show_auto_pwm, set_auto_pwm, 1, 0);
2086 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2087                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2088
2089 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2090                           show_pwm_enable, set_pwm_enable, 2);
2091 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2092 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2093 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2094                           show_pwm_temp_map, set_pwm_temp_map, 2);
2095 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2096                             show_auto_pwm, set_auto_pwm, 2, 0);
2097 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2098                             show_auto_pwm, set_auto_pwm, 2, 1);
2099 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2100                             show_auto_pwm, set_auto_pwm, 2, 2);
2101 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2102                             show_auto_pwm, NULL, 2, 3);
2103 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2104                             show_auto_temp, set_auto_temp, 2, 1);
2105 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2106                             show_auto_temp, set_auto_temp, 2, 0);
2107 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2108                             show_auto_temp, set_auto_temp, 2, 2);
2109 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2110                             show_auto_temp, set_auto_temp, 2, 3);
2111 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2112                             show_auto_temp, set_auto_temp, 2, 4);
2113 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2114                             show_auto_pwm, set_auto_pwm, 2, 0);
2115 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2116                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2117
2118 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2119                           show_pwm_enable, set_pwm_enable, 3);
2120 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2121 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2122 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2123                           show_pwm_temp_map, set_pwm_temp_map, 3);
2124 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2125                             show_auto_temp, set_auto_temp, 2, 1);
2126 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2127                             show_auto_temp, set_auto_temp, 2, 0);
2128 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2129                             show_auto_temp, set_auto_temp, 2, 2);
2130 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2131                             show_auto_temp, set_auto_temp, 2, 3);
2132 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2133                             show_auto_pwm, set_auto_pwm, 3, 0);
2134 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2135                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2136
2137 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2138                           show_pwm_enable, set_pwm_enable, 4);
2139 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2140 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2141 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2142                           show_pwm_temp_map, set_pwm_temp_map, 4);
2143 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2144                             show_auto_temp, set_auto_temp, 2, 1);
2145 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2146                             show_auto_temp, set_auto_temp, 2, 0);
2147 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2148                             show_auto_temp, set_auto_temp, 2, 2);
2149 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2150                             show_auto_temp, set_auto_temp, 2, 3);
2151 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2152                             show_auto_pwm, set_auto_pwm, 4, 0);
2153 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2154                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2155
2156 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2157                           show_pwm_enable, set_pwm_enable, 5);
2158 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2159 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2160 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2161                           show_pwm_temp_map, set_pwm_temp_map, 5);
2162 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2163                             show_auto_temp, set_auto_temp, 2, 1);
2164 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2165                             show_auto_temp, set_auto_temp, 2, 0);
2166 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2167                             show_auto_temp, set_auto_temp, 2, 2);
2168 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2169                             show_auto_temp, set_auto_temp, 2, 3);
2170 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2171                             show_auto_pwm, set_auto_pwm, 5, 0);
2172 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2173                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2174
2175 /* Alarms */
2176 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2177                            char *buf)
2178 {
2179         struct it87_data *data = it87_update_device(dev);
2180
2181         return sprintf(buf, "%u\n", data->alarms);
2182 }
2183 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2184
2185 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2186                           char *buf)
2187 {
2188         struct it87_data *data = it87_update_device(dev);
2189         int bitnr = to_sensor_dev_attr(attr)->index;
2190
2191         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2192 }
2193
2194 static ssize_t clear_intrusion(struct device *dev,
2195                                struct device_attribute *attr, const char *buf,
2196                                size_t count)
2197 {
2198         struct it87_data *data = dev_get_drvdata(dev);
2199         int config;
2200         long val;
2201
2202         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2203                 return -EINVAL;
2204
2205         mutex_lock(&data->update_lock);
2206         config = it87_read_value(data, IT87_REG_CONFIG);
2207         if (config < 0) {
2208                 count = config;
2209         } else {
2210                 config |= BIT(5);
2211                 it87_write_value(data, IT87_REG_CONFIG, config);
2212                 /* Invalidate cache to force re-read */
2213                 data->valid = 0;
2214         }
2215         mutex_unlock(&data->update_lock);
2216
2217         return count;
2218 }
2219
2220 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2221 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2222 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2223 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2224 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2225 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2226 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2227 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2228 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2229 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2230 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2231 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2232 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2233 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2234 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2235 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2236 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2237 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2238 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2239 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2240 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2241                           show_alarm, clear_intrusion, 4);
2242
2243 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2244                          char *buf)
2245 {
2246         struct it87_data *data = it87_update_device(dev);
2247         int bitnr = to_sensor_dev_attr(attr)->index;
2248
2249         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2250 }
2251
2252 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2253                         const char *buf, size_t count)
2254 {
2255         int bitnr = to_sensor_dev_attr(attr)->index;
2256         struct it87_data *data = dev_get_drvdata(dev);
2257         long val;
2258
2259         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2260                 return -EINVAL;
2261
2262         mutex_lock(&data->update_lock);
2263         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2264         if (val)
2265                 data->beeps |= BIT(bitnr);
2266         else
2267                 data->beeps &= ~BIT(bitnr);
2268         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2269         mutex_unlock(&data->update_lock);
2270         return count;
2271 }
2272
2273 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2274                           show_beep, set_beep, 1);
2275 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2276 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2277 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2278 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2279 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2280 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2281 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2282 /* fanX_beep writability is set later */
2283 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2284 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2285 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2286 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2287 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2288 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2289 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2290                           show_beep, set_beep, 2);
2291 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2292 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2293 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2294 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2295 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2296
2297 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2298                             char *buf)
2299 {
2300         struct it87_data *data = dev_get_drvdata(dev);
2301
2302         return sprintf(buf, "%u\n", data->vrm);
2303 }
2304
2305 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2306                              const char *buf, size_t count)
2307 {
2308         struct it87_data *data = dev_get_drvdata(dev);
2309         unsigned long val;
2310
2311         if (kstrtoul(buf, 10, &val) < 0)
2312                 return -EINVAL;
2313
2314         data->vrm = val;
2315
2316         return count;
2317 }
2318 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2319
2320 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2321                             char *buf)
2322 {
2323         struct it87_data *data = it87_update_device(dev);
2324
2325         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2326 }
2327 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2328
2329 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2330                           char *buf)
2331 {
2332         static const char * const labels[] = {
2333                 "+5V",
2334                 "5VSB",
2335                 "Vbat",
2336                 "AVCC",
2337         };
2338         static const char * const labels_it8721[] = {
2339                 "+3.3V",
2340                 "3VSB",
2341                 "Vbat",
2342                 "+3.3V",
2343         };
2344         struct it87_data *data = dev_get_drvdata(dev);
2345         int nr = to_sensor_dev_attr(attr)->index;
2346         const char *label;
2347
2348         if (has_vin3_5v(data) && nr == 0)
2349                 label = labels[0];
2350         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2351                  has_11mv_adc(data))
2352                 label = labels_it8721[nr];
2353         else
2354                 label = labels[nr];
2355
2356         return sprintf(buf, "%s\n", label);
2357 }
2358 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2359 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2360 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2361 /* AVCC3 */
2362 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2363
2364 static umode_t it87_in_is_visible(struct kobject *kobj,
2365                                   struct attribute *attr, int index)
2366 {
2367         struct device *dev = container_of(kobj, struct device, kobj);
2368         struct it87_data *data = dev_get_drvdata(dev);
2369         int i = index / 5;      /* voltage index */
2370         int a = index % 5;      /* attribute index */
2371
2372         if (index >= 40) {      /* in8 and higher only have input attributes */
2373                 i = index - 40 + 8;
2374                 a = 0;
2375         }
2376
2377         if (!(data->has_in & BIT(i)))
2378                 return 0;
2379
2380         if (a == 4 && !data->has_beep)
2381                 return 0;
2382
2383         return attr->mode;
2384 }
2385
2386 static struct attribute *it87_attributes_in[] = {
2387         &sensor_dev_attr_in0_input.dev_attr.attr,
2388         &sensor_dev_attr_in0_min.dev_attr.attr,
2389         &sensor_dev_attr_in0_max.dev_attr.attr,
2390         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2391         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2392
2393         &sensor_dev_attr_in1_input.dev_attr.attr,
2394         &sensor_dev_attr_in1_min.dev_attr.attr,
2395         &sensor_dev_attr_in1_max.dev_attr.attr,
2396         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2397         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2398
2399         &sensor_dev_attr_in2_input.dev_attr.attr,
2400         &sensor_dev_attr_in2_min.dev_attr.attr,
2401         &sensor_dev_attr_in2_max.dev_attr.attr,
2402         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2403         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2404
2405         &sensor_dev_attr_in3_input.dev_attr.attr,
2406         &sensor_dev_attr_in3_min.dev_attr.attr,
2407         &sensor_dev_attr_in3_max.dev_attr.attr,
2408         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2409         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2410
2411         &sensor_dev_attr_in4_input.dev_attr.attr,
2412         &sensor_dev_attr_in4_min.dev_attr.attr,
2413         &sensor_dev_attr_in4_max.dev_attr.attr,
2414         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2415         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2416
2417         &sensor_dev_attr_in5_input.dev_attr.attr,
2418         &sensor_dev_attr_in5_min.dev_attr.attr,
2419         &sensor_dev_attr_in5_max.dev_attr.attr,
2420         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2421         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2422
2423         &sensor_dev_attr_in6_input.dev_attr.attr,
2424         &sensor_dev_attr_in6_min.dev_attr.attr,
2425         &sensor_dev_attr_in6_max.dev_attr.attr,
2426         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2427         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2428
2429         &sensor_dev_attr_in7_input.dev_attr.attr,
2430         &sensor_dev_attr_in7_min.dev_attr.attr,
2431         &sensor_dev_attr_in7_max.dev_attr.attr,
2432         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2433         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2434
2435         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2436         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2437         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2438         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2439         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2440         NULL
2441 };
2442
2443 static const struct attribute_group it87_group_in = {
2444         .attrs = it87_attributes_in,
2445         .is_visible = it87_in_is_visible,
2446 };
2447
2448 static umode_t it87_temp_is_visible(struct kobject *kobj,
2449                                     struct attribute *attr, int index)
2450 {
2451         struct device *dev = container_of(kobj, struct device, kobj);
2452         struct it87_data *data = dev_get_drvdata(dev);
2453         int i = index / 7;      /* temperature index */
2454         int a = index % 7;      /* attribute index */
2455
2456         if (!(data->has_temp & BIT(i)))
2457                 return 0;
2458
2459         if (a && i >= data->num_temp_limit)
2460                 return 0;
2461
2462         if (a == 3) {
2463                 int type = get_temp_type(data, i);
2464
2465                 if (type == 0)
2466                         return 0;
2467                 if (has_bank_sel(data))
2468                         return 0444;
2469                 return attr->mode;
2470         }
2471
2472         if (a == 5 && i >= data->num_temp_offset)
2473                 return 0;
2474
2475         if (a == 6 && !data->has_beep)
2476                 return 0;
2477
2478         return attr->mode;
2479 }
2480
2481 static struct attribute *it87_attributes_temp[] = {
2482         &sensor_dev_attr_temp1_input.dev_attr.attr,
2483         &sensor_dev_attr_temp1_max.dev_attr.attr,
2484         &sensor_dev_attr_temp1_min.dev_attr.attr,
2485         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2486         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2487         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2488         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2489
2490         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2491         &sensor_dev_attr_temp2_max.dev_attr.attr,
2492         &sensor_dev_attr_temp2_min.dev_attr.attr,
2493         &sensor_dev_attr_temp2_type.dev_attr.attr,
2494         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2495         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2496         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2497
2498         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2499         &sensor_dev_attr_temp3_max.dev_attr.attr,
2500         &sensor_dev_attr_temp3_min.dev_attr.attr,
2501         &sensor_dev_attr_temp3_type.dev_attr.attr,
2502         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2503         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2504         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2505
2506         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2507         &sensor_dev_attr_temp4_max.dev_attr.attr,
2508         &sensor_dev_attr_temp4_min.dev_attr.attr,
2509         &sensor_dev_attr_temp4_type.dev_attr.attr,
2510         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2511         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2512         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2513
2514         &sensor_dev_attr_temp5_input.dev_attr.attr,
2515         &sensor_dev_attr_temp5_max.dev_attr.attr,
2516         &sensor_dev_attr_temp5_min.dev_attr.attr,
2517         &sensor_dev_attr_temp5_type.dev_attr.attr,
2518         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2519         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2520         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2521
2522         &sensor_dev_attr_temp6_input.dev_attr.attr,
2523         &sensor_dev_attr_temp6_max.dev_attr.attr,
2524         &sensor_dev_attr_temp6_min.dev_attr.attr,
2525         &sensor_dev_attr_temp6_type.dev_attr.attr,
2526         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2527         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2528         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2529         NULL
2530 };
2531
2532 static const struct attribute_group it87_group_temp = {
2533         .attrs = it87_attributes_temp,
2534         .is_visible = it87_temp_is_visible,
2535 };
2536
2537 static umode_t it87_is_visible(struct kobject *kobj,
2538                                struct attribute *attr, int index)
2539 {
2540         struct device *dev = container_of(kobj, struct device, kobj);
2541         struct it87_data *data = dev_get_drvdata(dev);
2542
2543         if ((index == 2 || index == 3) && !data->has_vid)
2544                 return 0;
2545
2546         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2547                 return 0;
2548
2549         return attr->mode;
2550 }
2551
2552 static struct attribute *it87_attributes[] = {
2553         &dev_attr_alarms.attr,
2554         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2555         &dev_attr_vrm.attr,                             /* 2 */
2556         &dev_attr_cpu0_vid.attr,                        /* 3 */
2557         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2558         &sensor_dev_attr_in7_label.dev_attr.attr,
2559         &sensor_dev_attr_in8_label.dev_attr.attr,
2560         &sensor_dev_attr_in9_label.dev_attr.attr,
2561         NULL
2562 };
2563
2564 static const struct attribute_group it87_group = {
2565         .attrs = it87_attributes,
2566         .is_visible = it87_is_visible,
2567 };
2568
2569 static umode_t it87_fan_is_visible(struct kobject *kobj,
2570                                    struct attribute *attr, int index)
2571 {
2572         struct device *dev = container_of(kobj, struct device, kobj);
2573         struct it87_data *data = dev_get_drvdata(dev);
2574         int i = index / 5;      /* fan index */
2575         int a = index % 5;      /* attribute index */
2576
2577         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2578                 i = (index - 15) / 4 + 3;
2579                 a = (index - 15) % 4;
2580         }
2581
2582         if (!(data->has_fan & BIT(i)))
2583                 return 0;
2584
2585         if (a == 3) {                           /* beep */
2586                 if (!data->has_beep)
2587                         return 0;
2588                 /* first fan beep attribute is writable */
2589                 if (i == __ffs(data->has_fan))
2590                         return attr->mode | S_IWUSR;
2591         }
2592
2593         if (a == 4 && has_16bit_fans(data))     /* divisor */
2594                 return 0;
2595
2596         return attr->mode;
2597 }
2598
2599 static struct attribute *it87_attributes_fan[] = {
2600         &sensor_dev_attr_fan1_input.dev_attr.attr,
2601         &sensor_dev_attr_fan1_min.dev_attr.attr,
2602         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2603         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2604         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2605
2606         &sensor_dev_attr_fan2_input.dev_attr.attr,
2607         &sensor_dev_attr_fan2_min.dev_attr.attr,
2608         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2609         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2610         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2611
2612         &sensor_dev_attr_fan3_input.dev_attr.attr,
2613         &sensor_dev_attr_fan3_min.dev_attr.attr,
2614         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2615         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2616         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2617
2618         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2619         &sensor_dev_attr_fan4_min.dev_attr.attr,
2620         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2621         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2622
2623         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2624         &sensor_dev_attr_fan5_min.dev_attr.attr,
2625         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2626         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2627
2628         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2629         &sensor_dev_attr_fan6_min.dev_attr.attr,
2630         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2631         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2632         NULL
2633 };
2634
2635 static const struct attribute_group it87_group_fan = {
2636         .attrs = it87_attributes_fan,
2637         .is_visible = it87_fan_is_visible,
2638 };
2639
2640 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2641                                    struct attribute *attr, int index)
2642 {
2643         struct device *dev = container_of(kobj, struct device, kobj);
2644         struct it87_data *data = dev_get_drvdata(dev);
2645         int i = index / 4;      /* pwm index */
2646         int a = index % 4;      /* attribute index */
2647
2648         if (!(data->has_pwm & BIT(i)))
2649                 return 0;
2650
2651         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2652         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2653                 return attr->mode | S_IWUSR;
2654
2655         /* pwm2_freq is writable if there are two pwm frequency selects */
2656         if (has_pwm_freq2(data) && i == 1 && a == 2)
2657                 return attr->mode | S_IWUSR;
2658
2659         return attr->mode;
2660 }
2661
2662 static struct attribute *it87_attributes_pwm[] = {
2663         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2664         &sensor_dev_attr_pwm1.dev_attr.attr,
2665         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2666         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2667
2668         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2669         &sensor_dev_attr_pwm2.dev_attr.attr,
2670         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2671         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2672
2673         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2674         &sensor_dev_attr_pwm3.dev_attr.attr,
2675         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2676         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2677
2678         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2679         &sensor_dev_attr_pwm4.dev_attr.attr,
2680         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2681         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2682
2683         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2684         &sensor_dev_attr_pwm5.dev_attr.attr,
2685         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2686         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2687
2688         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2689         &sensor_dev_attr_pwm6.dev_attr.attr,
2690         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2691         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2692
2693         NULL
2694 };
2695
2696 static const struct attribute_group it87_group_pwm = {
2697         .attrs = it87_attributes_pwm,
2698         .is_visible = it87_pwm_is_visible,
2699 };
2700
2701 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2702                                         struct attribute *attr, int index)
2703 {
2704         struct device *dev = container_of(kobj, struct device, kobj);
2705         struct it87_data *data = dev_get_drvdata(dev);
2706         int i = index / 11;     /* pwm index */
2707         int a = index % 11;     /* attribute index */
2708
2709         if (index >= 33) {      /* pwm 4..6 */
2710                 i = (index - 33) / 6 + 3;
2711                 a = (index - 33) % 6 + 4;
2712         }
2713
2714         if (!(data->has_pwm & BIT(i)))
2715                 return 0;
2716
2717         if (has_newer_autopwm(data)) {
2718                 if (a < 4)      /* no auto point pwm */
2719                         return 0;
2720                 if (a == 8)     /* no auto_point4 */
2721                         return 0;
2722         }
2723         if (has_old_autopwm(data)) {
2724                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2725                         return 0;
2726         }
2727
2728         return attr->mode;
2729 }
2730
2731 static struct attribute *it87_attributes_auto_pwm[] = {
2732         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2733         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2734         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2735         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2736         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2737         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2738         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2739         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2740         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2741         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2742         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2743
2744         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2745         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2746         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2747         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2748         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2749         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2750         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2751         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2752         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2753         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2754         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2755
2756         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2757         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2758         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2759         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2760         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2761         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2762         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2763         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2764         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2765         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2766         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2767
2768         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2769         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2770         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2771         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2772         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2773         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2774
2775         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2776         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2777         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2778         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2779         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2780         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2781
2782         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2783         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2784         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2785         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2786         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2787         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2788
2789         NULL,
2790 };
2791
2792 static const struct attribute_group it87_group_auto_pwm = {
2793         .attrs = it87_attributes_auto_pwm,
2794         .is_visible = it87_auto_pwm_is_visible,
2795 };
2796
2797 /* SuperIO detection - will change isa_address if a chip is found */
2798 static int __init it87_find(int sioaddr, unsigned short *address,
2799                             struct it87_sio_data *sio_data)
2800 {
2801         int err;
2802         u16 chip_type;
2803         const struct it87_devices *config;
2804
2805         err = superio_enter(sioaddr);
2806         if (err)
2807                 return err;
2808
2809         err = -ENODEV;
2810         chip_type = superio_inw(sioaddr, DEVID);
2811         if (chip_type == 0xffff)
2812                 goto exit;
2813
2814         if (force_id)
2815                 chip_type = force_id;
2816
2817         switch (chip_type) {
2818         case IT8705F_DEVID:
2819                 sio_data->type = it87;
2820                 break;
2821         case IT8712F_DEVID:
2822                 sio_data->type = it8712;
2823                 break;
2824         case IT8716F_DEVID:
2825         case IT8726F_DEVID:
2826                 sio_data->type = it8716;
2827                 break;
2828         case IT8718F_DEVID:
2829                 sio_data->type = it8718;
2830                 break;
2831         case IT8720F_DEVID:
2832                 sio_data->type = it8720;
2833                 break;
2834         case IT8721F_DEVID:
2835                 sio_data->type = it8721;
2836                 break;
2837         case IT8728F_DEVID:
2838                 sio_data->type = it8728;
2839                 break;
2840         case IT8732F_DEVID:
2841                 sio_data->type = it8732;
2842                 break;
2843         case IT8792E_DEVID:
2844                 sio_data->type = it8792;
2845                 break;
2846         case IT8771E_DEVID:
2847                 sio_data->type = it8771;
2848                 break;
2849         case IT8772E_DEVID:
2850                 sio_data->type = it8772;
2851                 break;
2852         case IT8781F_DEVID:
2853                 sio_data->type = it8781;
2854                 break;
2855         case IT8782F_DEVID:
2856                 sio_data->type = it8782;
2857                 break;
2858         case IT8783E_DEVID:
2859                 sio_data->type = it8783;
2860                 break;
2861         case IT8786E_DEVID:
2862                 sio_data->type = it8786;
2863                 break;
2864         case IT8790E_DEVID:
2865                 sio_data->type = it8790;
2866                 break;
2867         case IT8603E_DEVID:
2868         case IT8623E_DEVID:
2869                 sio_data->type = it8603;
2870                 break;
2871         case IT8607E_DEVID:
2872                 sio_data->type = it8607;
2873                 break;
2874         case IT8613E_DEVID:
2875                 sio_data->type = it8613;
2876                 break;
2877         case IT8620E_DEVID:
2878                 sio_data->type = it8620;
2879                 break;
2880         case IT8622E_DEVID:
2881                 sio_data->type = it8622;
2882                 break;
2883         case IT8625E_DEVID:
2884                 sio_data->type = it8625;
2885                 break;
2886         case IT8628E_DEVID:
2887                 sio_data->type = it8628;
2888                 break;
2889         case IT8655E_DEVID:
2890                 sio_data->type = it8655;
2891                 break;
2892         case IT8665E_DEVID:
2893                 sio_data->type = it8665;
2894                 break;
2895         case IT8686E_DEVID:
2896                 sio_data->type = it8686;
2897                 break;
2898         case 0xffff:    /* No device at all */
2899                 goto exit;
2900         default:
2901                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2902                 goto exit;
2903         }
2904
2905         superio_select(sioaddr, PME);
2906         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2907                 pr_info("Device not activated, skipping\n");
2908                 goto exit;
2909         }
2910
2911         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2912         if (*address == 0) {
2913                 pr_info("Base address not set, skipping\n");
2914                 goto exit;
2915         }
2916
2917         err = 0;
2918         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2919         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2920                 it87_devices[sio_data->type].suffix,
2921                 *address, sio_data->revision);
2922
2923         config = &it87_devices[sio_data->type];
2924
2925         /* in7 (VSB or VCCH5V) is always internal on some chips */
2926         if (has_in7_internal(config))
2927                 sio_data->internal |= BIT(1);
2928
2929         /* in8 (Vbat) is always internal */
2930         sio_data->internal |= BIT(2);
2931
2932         /* in9 (AVCC3), always internal if supported */
2933         if (has_avcc3(config))
2934                 sio_data->internal |= BIT(3); /* in9 is AVCC */
2935         else
2936                 sio_data->skip_in |= BIT(9);
2937
2938         if (!has_four_pwm(config))
2939                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2940         else if (!has_five_pwm(config))
2941                 sio_data->skip_pwm |= BIT(4) | BIT(5);
2942         else if (!has_six_pwm(config))
2943                 sio_data->skip_pwm |= BIT(5);
2944
2945         if (!has_vid(config))
2946                 sio_data->skip_vid = 1;
2947
2948         /* Read GPIO config and VID value from LDN 7 (GPIO) */
2949         if (sio_data->type == it87) {
2950                 /* The IT8705F has a different LD number for GPIO */
2951                 superio_select(sioaddr, 5);
2952                 sio_data->beep_pin = superio_inb(sioaddr,
2953                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2954         } else if (sio_data->type == it8783) {
2955                 int reg25, reg27, reg2a, reg2c, regef;
2956
2957                 superio_select(sioaddr, GPIO);
2958
2959                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2960                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2961                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2962                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2963                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2964
2965                 /* Check if fan3 is there or not */
2966                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2967                         sio_data->skip_fan |= BIT(2);
2968                 if ((reg25 & BIT(4)) ||
2969                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
2970                         sio_data->skip_pwm |= BIT(2);
2971
2972                 /* Check if fan2 is there or not */
2973                 if (reg27 & BIT(7))
2974                         sio_data->skip_fan |= BIT(1);
2975                 if (reg27 & BIT(3))
2976                         sio_data->skip_pwm |= BIT(1);
2977
2978                 /* VIN5 */
2979                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2980                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2981
2982                 /* VIN6 */
2983                 if (reg27 & BIT(1))
2984                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2985
2986                 /*
2987                  * VIN7
2988                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2989                  */
2990                 if (reg27 & BIT(2)) {
2991                         /*
2992                          * The data sheet is a bit unclear regarding the
2993                          * internal voltage divider for VCCH5V. It says
2994                          * "This bit enables and switches VIN7 (pin 91) to the
2995                          * internal voltage divider for VCCH5V".
2996                          * This is different to other chips, where the internal
2997                          * voltage divider would connect VIN7 to an internal
2998                          * voltage source. Maybe that is the case here as well.
2999                          *
3000                          * Since we don't know for sure, re-route it if that is
3001                          * not the case, and ask the user to report if the
3002                          * resulting voltage is sane.
3003                          */
3004                         if (!(reg2c & BIT(1))) {
3005                                 reg2c |= BIT(1);
3006                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3007                                              reg2c);
3008                                 pr_notice("Routing internal VCCH5V to in7.\n");
3009                         }
3010                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3011                         pr_notice("Please report if it displays a reasonable voltage.\n");
3012                 }
3013
3014                 if (reg2c & BIT(0))
3015                         sio_data->internal |= BIT(0);
3016                 if (reg2c & BIT(1))
3017                         sio_data->internal |= BIT(1);
3018
3019                 sio_data->beep_pin = superio_inb(sioaddr,
3020                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3021         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3022                 int reg27, reg29;
3023
3024                 superio_select(sioaddr, GPIO);
3025
3026                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3027
3028                 /* Check if fan3 is there or not */
3029                 if (reg27 & BIT(6))
3030                         sio_data->skip_pwm |= BIT(2);
3031                 if (reg27 & BIT(7))
3032                         sio_data->skip_fan |= BIT(2);
3033
3034                 /* Check if fan2 is there or not */
3035                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3036                 if (reg29 & BIT(1))
3037                         sio_data->skip_pwm |= BIT(1);
3038                 if (reg29 & BIT(2))
3039                         sio_data->skip_fan |= BIT(1);
3040
3041                 switch (sio_data->type) {
3042                 case it8603:
3043                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3044                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3045                         break;
3046                 case it8607:
3047                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3048                         sio_data->skip_fan |= BIT(0);
3049                 default:
3050                         break;
3051                 }
3052
3053                 sio_data->beep_pin = superio_inb(sioaddr,
3054                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3055         } else if (sio_data->type == it8613) {
3056                 int reg27, reg29, reg2a;
3057
3058                 superio_select(sioaddr, GPIO);
3059
3060                 /* Check for pwm3, fan3, pwm5, fan5 */
3061                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3062                 if (reg27 & BIT(1))
3063                         sio_data->skip_fan |= BIT(4);
3064                 if (reg27 & BIT(3))
3065                         sio_data->skip_pwm |= BIT(4);
3066                 if (reg27 & BIT(6))
3067                         sio_data->skip_pwm |= BIT(2);
3068                 if (reg27 & BIT(7))
3069                         sio_data->skip_fan |= BIT(2);
3070
3071                 /* Check for pwm2, fan2 */
3072                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3073                 if (reg29 & BIT(1))
3074                         sio_data->skip_pwm |= BIT(1);
3075                 if (reg29 & BIT(2))
3076                         sio_data->skip_fan |= BIT(1);
3077
3078                 /* Check for pwm4, fan4 */
3079                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3080                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3081                         sio_data->skip_fan |= BIT(3);
3082                         sio_data->skip_pwm |= BIT(3);
3083                 }
3084
3085                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3086                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3087                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3088                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3089
3090                 sio_data->beep_pin = superio_inb(sioaddr,
3091                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3092         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3093                    sio_data->type == it8686) {
3094                 int reg;
3095
3096                 superio_select(sioaddr, GPIO);
3097
3098                 /* Check for pwm5 */
3099                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3100                 if (reg & BIT(6))
3101                         sio_data->skip_pwm |= BIT(4);
3102
3103                 /* Check for fan4, fan5 */
3104                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3105                 if (!(reg & BIT(5)))
3106                         sio_data->skip_fan |= BIT(3);
3107                 if (!(reg & BIT(4)))
3108                         sio_data->skip_fan |= BIT(4);
3109
3110                 /* Check for pwm3, fan3 */
3111                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3112                 if (reg & BIT(6))
3113                         sio_data->skip_pwm |= BIT(2);
3114                 if (reg & BIT(7))
3115                         sio_data->skip_fan |= BIT(2);
3116
3117                 /* Check for pwm4 */
3118                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3119                 if (reg & BIT(2))
3120                         sio_data->skip_pwm |= BIT(3);
3121
3122                 /* Check for pwm2, fan2 */
3123                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3124                 if (reg & BIT(1))
3125                         sio_data->skip_pwm |= BIT(1);
3126                 if (reg & BIT(2))
3127                         sio_data->skip_fan |= BIT(1);
3128                 /* Check for pwm6, fan6 */
3129                 if (!(reg & BIT(7))) {
3130                         sio_data->skip_pwm |= BIT(5);
3131                         sio_data->skip_fan |= BIT(5);
3132                 }
3133
3134                 /* Check if AVCC is on VIN3 */
3135                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3136                 if (reg & BIT(0)) {
3137                         /* For it8686, the bit just enables AVCC3 */
3138                         if (sio_data->type != it8686)
3139                                 sio_data->internal |= BIT(0);
3140                 } else {
3141                         sio_data->internal &= ~BIT(3);
3142                         sio_data->skip_in |= BIT(9);
3143                 }
3144
3145                 sio_data->beep_pin = superio_inb(sioaddr,
3146                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3147         } else if (sio_data->type == it8622) {
3148                 int reg;
3149
3150                 superio_select(sioaddr, GPIO);
3151
3152                 /* Check for pwm4, fan4 */
3153                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3154                 if (reg & BIT(6))
3155                         sio_data->skip_fan |= BIT(3);
3156                 if (reg & BIT(5))
3157                         sio_data->skip_pwm |= BIT(3);
3158
3159                 /* Check for pwm3, fan3, pwm5, fan5 */
3160                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3161                 if (reg & BIT(6))
3162                         sio_data->skip_pwm |= BIT(2);
3163                 if (reg & BIT(7))
3164                         sio_data->skip_fan |= BIT(2);
3165                 if (reg & BIT(3))
3166                         sio_data->skip_pwm |= BIT(4);
3167                 if (reg & BIT(1))
3168                         sio_data->skip_fan |= BIT(4);
3169
3170                 /* Check for pwm2, fan2 */
3171                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3172                 if (reg & BIT(1))
3173                         sio_data->skip_pwm |= BIT(1);
3174                 if (reg & BIT(2))
3175                         sio_data->skip_fan |= BIT(1);
3176
3177                 /* Check for AVCC */
3178                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3179                 if (!(reg & BIT(0)))
3180                         sio_data->skip_in |= BIT(9);
3181
3182                 sio_data->beep_pin = superio_inb(sioaddr,
3183                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3184         } else if (sio_data->type == it8732) {
3185                 int reg;
3186
3187                 superio_select(sioaddr, GPIO);
3188
3189                 /* Check for pwm2, fan2 */
3190                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3191                 if (reg & BIT(1))
3192                         sio_data->skip_pwm |= BIT(1);
3193                 if (reg & BIT(2))
3194                         sio_data->skip_fan |= BIT(1);
3195
3196                 /* Check for pwm3, fan3, fan4 */
3197                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3198                 if (reg & BIT(6))
3199                         sio_data->skip_pwm |= BIT(2);
3200                 if (reg & BIT(7))
3201                         sio_data->skip_fan |= BIT(2);
3202                 if (reg & BIT(5))
3203                         sio_data->skip_fan |= BIT(3);
3204
3205                 /* Check if AVCC is on VIN3 */
3206                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3207                 if (reg & BIT(0))
3208                         sio_data->internal |= BIT(0);
3209
3210                 sio_data->beep_pin = superio_inb(sioaddr,
3211                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3212         } else if (sio_data->type == it8655) {
3213                 int reg;
3214
3215                 superio_select(sioaddr, GPIO);
3216
3217                 /* Check for pwm2 */
3218                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3219                 if (reg & BIT(1))
3220                         sio_data->skip_pwm |= BIT(1);
3221
3222                 /* Check for fan2 */
3223                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3224                 if (reg & BIT(4))
3225                         sio_data->skip_fan |= BIT(1);
3226
3227                 /* Check for pwm3, fan3 */
3228                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3229                 if (reg & BIT(6))
3230                         sio_data->skip_pwm |= BIT(2);
3231                 if (reg & BIT(7))
3232                         sio_data->skip_fan |= BIT(2);
3233
3234                 sio_data->beep_pin = superio_inb(sioaddr,
3235                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3236         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3237                 int reg27, reg29, reg2d, regd3;
3238
3239                 superio_select(sioaddr, GPIO);
3240
3241                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3242                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3243                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3244                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3245
3246                 /* Check for pwm2, fan2 */
3247                 if (reg29 & BIT(1))
3248                         sio_data->skip_pwm |= BIT(1);
3249                 if (reg2d & BIT(4))
3250                         sio_data->skip_fan |= BIT(1);
3251
3252                 /* Check for pwm3, fan3 */
3253                 if (reg27 & BIT(6))
3254                         sio_data->skip_pwm |= BIT(2);
3255                 if (reg27 & BIT(7))
3256                         sio_data->skip_fan |= BIT(2);
3257
3258                 /* Check for pwm4, fan4, pwm5, fan5 */
3259                 if (sio_data->type == it8625) {
3260                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3261
3262                         if (reg25 & BIT(6))
3263                                 sio_data->skip_fan |= BIT(3);
3264                         if (reg25 & BIT(5))
3265                                 sio_data->skip_pwm |= BIT(3);
3266                         if (reg27 & BIT(3))
3267                                 sio_data->skip_pwm |= BIT(4);
3268                         if (reg27 & BIT(1))
3269                                 sio_data->skip_fan |= BIT(4);
3270                 } else {
3271                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3272
3273                         if (regd3 & BIT(2))
3274                                 sio_data->skip_pwm |= BIT(3);
3275                         if (regd3 & BIT(3))
3276                                 sio_data->skip_fan |= BIT(3);
3277                         if (reg26 & BIT(5))
3278                                 sio_data->skip_pwm |= BIT(4);
3279                         if (!(reg26 & BIT(4)))
3280                                 sio_data->skip_fan |= BIT(4);
3281                 }
3282
3283                 /* Check for pwm6, fan6 */
3284                 if (regd3 & BIT(0))
3285                         sio_data->skip_pwm |= BIT(5);
3286                 if (regd3 & BIT(1))
3287                         sio_data->skip_fan |= BIT(5);
3288
3289                 sio_data->beep_pin = superio_inb(sioaddr,
3290                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3291         } else {
3292                 int reg;
3293                 bool uart6;
3294
3295                 superio_select(sioaddr, GPIO);
3296
3297                 /* Check for fan4, fan5 */
3298                 if (has_five_fans(config)) {
3299                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3300                         switch (sio_data->type) {
3301                         case it8718:
3302                                 if (reg & BIT(5))
3303                                         sio_data->skip_fan |= BIT(3);
3304                                 if (reg & BIT(4))
3305                                         sio_data->skip_fan |= BIT(4);
3306                                 break;
3307                         case it8720:
3308                         case it8721:
3309                         case it8728:
3310                                 if (!(reg & BIT(5)))
3311                                         sio_data->skip_fan |= BIT(3);
3312                                 if (!(reg & BIT(4)))
3313                                         sio_data->skip_fan |= BIT(4);
3314                                 break;
3315                         default:
3316                                 break;
3317                         }
3318                 }
3319
3320                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3321                 if (!sio_data->skip_vid) {
3322                         /* We need at least 4 VID pins */
3323                         if (reg & 0x0f) {
3324                                 pr_info("VID is disabled (pins used for GPIO)\n");
3325                                 sio_data->skip_vid = 1;
3326                         }
3327                 }
3328
3329                 /* Check if fan3 is there or not */
3330                 if (reg & BIT(6))
3331                         sio_data->skip_pwm |= BIT(2);
3332                 if (reg & BIT(7))
3333                         sio_data->skip_fan |= BIT(2);
3334
3335                 /* Check if fan2 is there or not */
3336                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3337                 if (reg & BIT(1))
3338                         sio_data->skip_pwm |= BIT(1);
3339                 if (reg & BIT(2))
3340                         sio_data->skip_fan |= BIT(1);
3341
3342                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3343                     !(sio_data->skip_vid))
3344                         sio_data->vid_value = superio_inb(sioaddr,
3345                                                           IT87_SIO_VID_REG);
3346
3347                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3348
3349                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3350
3351                 /*
3352                  * The IT8720F has no VIN7 pin, so VCCH should always be
3353                  * routed internally to VIN7 with an internal divider.
3354                  * Curiously, there still is a configuration bit to control
3355                  * this, which means it can be set incorrectly. And even
3356                  * more curiously, many boards out there are improperly
3357                  * configured, even though the IT8720F datasheet claims
3358                  * that the internal routing of VCCH to VIN7 is the default
3359                  * setting. So we force the internal routing in this case.
3360                  *
3361                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3362                  * If UART6 is enabled, re-route VIN7 to the internal divider
3363                  * if that is not already the case.
3364                  */
3365                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3366                         reg |= BIT(1);
3367                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3368                         pr_notice("Routing internal VCCH to in7\n");
3369                 }
3370                 if (reg & BIT(0))
3371                         sio_data->internal |= BIT(0);
3372                 if (reg & BIT(1))
3373                         sio_data->internal |= BIT(1);
3374
3375                 /*
3376                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3377                  * While VIN7 can be routed to the internal voltage divider,
3378                  * VIN5 and VIN6 are not available if UART6 is enabled.
3379                  *
3380                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3381                  * is the temperature source. Since we can not read the
3382                  * temperature source here, skip_temp is preliminary.
3383                  */
3384                 if (uart6) {
3385                         sio_data->skip_in |= BIT(5) | BIT(6);
3386                         sio_data->skip_temp |= BIT(2);
3387                 }
3388
3389                 sio_data->beep_pin = superio_inb(sioaddr,
3390                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3391         }
3392         if (sio_data->beep_pin)
3393                 pr_info("Beeping is supported\n");
3394
3395 exit:
3396         superio_exit(sioaddr);
3397         return err;
3398 }
3399
3400 static void it87_init_regs(struct platform_device *pdev)
3401 {
3402         struct it87_data *data = platform_get_drvdata(pdev);
3403
3404         /* Initialize chip specific register pointers */
3405         switch (data->type) {
3406         case it8628:
3407         case it8686:
3408                 data->REG_FAN = IT87_REG_FAN;
3409                 data->REG_FANX = IT87_REG_FANX;
3410                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3411                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3412                 data->REG_PWM = IT87_REG_PWM;
3413                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3414                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3415                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3416                 break;
3417         case it8625:
3418         case it8655:
3419         case it8665:
3420                 data->REG_FAN = IT87_REG_FAN_8665;
3421                 data->REG_FANX = IT87_REG_FANX_8665;
3422                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3423                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3424                 data->REG_PWM = IT87_REG_PWM_8665;
3425                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3426                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3427                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3428                 break;
3429         case it8622:
3430                 data->REG_FAN = IT87_REG_FAN;
3431                 data->REG_FANX = IT87_REG_FANX;
3432                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3433                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3434                 data->REG_PWM = IT87_REG_PWM_8665;
3435                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3436                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3437                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3438                 break;
3439         case it8613:
3440                 data->REG_FAN = IT87_REG_FAN;
3441                 data->REG_FANX = IT87_REG_FANX;
3442                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3443                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3444                 data->REG_PWM = IT87_REG_PWM_8665;
3445                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3446                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3447                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3448                 break;
3449         default:
3450                 data->REG_FAN = IT87_REG_FAN;
3451                 data->REG_FANX = IT87_REG_FANX;
3452                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3453                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3454                 data->REG_PWM = IT87_REG_PWM;
3455                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3456                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3457                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3458                 break;
3459         }
3460 }
3461
3462 /* Called when we have found a new IT87. */
3463 static void it87_init_device(struct platform_device *pdev)
3464 {
3465         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3466         struct it87_data *data = platform_get_drvdata(pdev);
3467         int tmp, i;
3468         u8 mask;
3469
3470         /*
3471          * For each PWM channel:
3472          * - If it is in automatic mode, setting to manual mode should set
3473          *   the fan to full speed by default.
3474          * - If it is in manual mode, we need a mapping to temperature
3475          *   channels to use when later setting to automatic mode later.
3476          *   Use a 1:1 mapping by default (we are clueless.)
3477          * In both cases, the value can (and should) be changed by the user
3478          * prior to switching to a different mode.
3479          * Note that this is no longer needed for the IT8721F and later, as
3480          * these have separate registers for the temperature mapping and the
3481          * manual duty cycle.
3482          */
3483         for (i = 0; i < NUM_AUTO_PWM; i++) {
3484                 data->pwm_temp_map[i] = i;
3485                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3486                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3487         }
3488
3489         /*
3490          * Some chips seem to have default value 0xff for all limit
3491          * registers. For low voltage limits it makes no sense and triggers
3492          * alarms, so change to 0 instead. For high temperature limits, it
3493          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3494          * but is still confusing, so change to 127 degrees C.
3495          */
3496         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3497                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3498                 if (tmp == 0xff)
3499                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3500         }
3501         for (i = 0; i < data->num_temp_limit; i++) {
3502                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3503                 if (tmp == 0xff)
3504                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3505         }
3506
3507         /*
3508          * Temperature channels are not forcibly enabled, as they can be
3509          * set to two different sensor types and we can't guess which one
3510          * is correct for a given system. These channels can be enabled at
3511          * run-time through the temp{1-3}_type sysfs accessors if needed.
3512          */
3513
3514         /* Check if voltage monitors are reset manually or by some reason */
3515         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3516         if ((tmp & 0xff) == 0) {
3517                 /* Enable all voltage monitors */
3518                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3519         }
3520
3521         /* Check if tachometers are reset manually or by some reason */
3522         mask = 0x70 & ~(sio_data->skip_fan << 4);
3523         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3524         if ((data->fan_main_ctrl & mask) == 0) {
3525                 /* Enable all fan tachometers */
3526                 data->fan_main_ctrl |= mask;
3527                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3528                                  data->fan_main_ctrl);
3529         }
3530         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3531
3532         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3533
3534         /* Set tachometers to 16-bit mode if needed */
3535         if (has_fan16_config(data)) {
3536                 if (~tmp & 0x07 & data->has_fan) {
3537                         dev_dbg(&pdev->dev,
3538                                 "Setting fan1-3 to 16-bit mode\n");
3539                         it87_write_value(data, IT87_REG_FAN_16BIT,
3540                                          tmp | 0x07);
3541                 }
3542         }
3543
3544         /* Check for additional fans */
3545         if (has_four_fans(data) && (tmp & BIT(4)))
3546                 data->has_fan |= BIT(3); /* fan4 enabled */
3547         if (has_five_fans(data) && (tmp & BIT(5)))
3548                 data->has_fan |= BIT(4); /* fan5 enabled */
3549         if (has_six_fans(data)) {
3550                 switch (data->type) {
3551                 case it8620:
3552                 case it8628:
3553                 case it8686:
3554                         if (tmp & BIT(2))
3555                                 data->has_fan |= BIT(5); /* fan6 enabled */
3556                         break;
3557                 case it8625:
3558                 case it8665:
3559                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3560                         if (tmp & BIT(3))
3561                                 data->has_fan |= BIT(5); /* fan6 enabled */
3562                         break;
3563                 default:
3564                         break;
3565                 }
3566         }
3567
3568         /* Fan input pins may be used for alternative functions */
3569         data->has_fan &= ~sio_data->skip_fan;
3570
3571         /* Check if pwm6 is enabled */
3572         if (has_six_pwm(data)) {
3573                 switch (data->type) {
3574                 case it8620:
3575                 case it8686:
3576                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3577                         if (!(tmp & BIT(3)))
3578                                 sio_data->skip_pwm |= BIT(5);
3579                         break;
3580                 default:
3581                         break;
3582                 }
3583         }
3584
3585         /* Start monitoring */
3586         it87_write_value(data, IT87_REG_CONFIG,
3587                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3588                          | (update_vbat ? 0x41 : 0x01));
3589 }
3590
3591 /* Return 1 if and only if the PWM interface is safe to use */
3592 static int it87_check_pwm(struct device *dev)
3593 {
3594         struct it87_data *data = dev_get_drvdata(dev);
3595         /*
3596          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3597          * and polarity set to active low is sign that this is the case so we
3598          * disable pwm control to protect the user.
3599          */
3600         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3601
3602         if ((tmp & 0x87) == 0) {
3603                 if (fix_pwm_polarity) {
3604                         /*
3605                          * The user asks us to attempt a chip reconfiguration.
3606                          * This means switching to active high polarity and
3607                          * inverting all fan speed values.
3608                          */
3609                         int i;
3610                         u8 pwm[3];
3611
3612                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3613                                 pwm[i] = it87_read_value(data,
3614                                                          data->REG_PWM[i]);
3615
3616                         /*
3617                          * If any fan is in automatic pwm mode, the polarity
3618                          * might be correct, as suspicious as it seems, so we
3619                          * better don't change anything (but still disable the
3620                          * PWM interface).
3621                          */
3622                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3623                                 dev_info(dev,
3624                                          "Reconfiguring PWM to active high polarity\n");
3625                                 it87_write_value(data, IT87_REG_FAN_CTL,
3626                                                  tmp | 0x87);
3627                                 for (i = 0; i < 3; i++)
3628                                         it87_write_value(data,
3629                                                          data->REG_PWM[i],
3630                                                          0x7f & ~pwm[i]);
3631                                 return 1;
3632                         }
3633
3634                         dev_info(dev,
3635                                  "PWM configuration is too broken to be fixed\n");
3636                 }
3637
3638                 dev_info(dev,
3639                          "Detected broken BIOS defaults, disabling PWM interface\n");
3640                 return 0;
3641         } else if (fix_pwm_polarity) {
3642                 dev_info(dev,
3643                          "PWM configuration looks sane, won't touch\n");
3644         }
3645
3646         return 1;
3647 }
3648
3649 static int it87_probe(struct platform_device *pdev)
3650 {
3651         struct it87_data *data;
3652         struct resource *res;
3653         struct device *dev = &pdev->dev;
3654         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3655         int enable_pwm_interface;
3656         struct device *hwmon_dev;
3657
3658         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3659         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3660                                  DRVNAME)) {
3661                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3662                         (unsigned long)res->start,
3663                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3664                 return -EBUSY;
3665         }
3666
3667         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3668         if (!data)
3669                 return -ENOMEM;
3670
3671         data->addr = res->start;
3672         data->type = sio_data->type;
3673         data->features = it87_devices[sio_data->type].features;
3674         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3675         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3676         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3677         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3678         data->bank = 0xff;
3679
3680         /*
3681          * IT8705F Datasheet 0.4.1, 3h == Version G.
3682          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3683          * These are the first revisions with 16-bit tachometer support.
3684          */
3685         switch (data->type) {
3686         case it87:
3687                 if (sio_data->revision >= 0x03) {
3688                         data->features &= ~FEAT_OLD_AUTOPWM;
3689                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3690                 }
3691                 break;
3692         case it8712:
3693                 if (sio_data->revision >= 0x08) {
3694                         data->features &= ~FEAT_OLD_AUTOPWM;
3695                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3696                                           FEAT_FIVE_FANS;
3697                 }
3698                 break;
3699         default:
3700                 break;
3701         }
3702
3703         /* Now, we do the remaining detection. */
3704         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3705             it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3706                 return -ENODEV;
3707
3708         platform_set_drvdata(pdev, data);
3709
3710         mutex_init(&data->update_lock);
3711
3712         /* Initialize register pointers */
3713         it87_init_regs(pdev);
3714
3715         /* Check PWM configuration */
3716         enable_pwm_interface = it87_check_pwm(dev);
3717
3718         /* Starting with IT8721F, we handle scaling of internal voltages */
3719         if (has_scaling(data)) {
3720                 if (sio_data->internal & BIT(0))
3721                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3722                 if (sio_data->internal & BIT(1))
3723                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3724                 if (sio_data->internal & BIT(2))
3725                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3726                 if (sio_data->internal & BIT(3))
3727                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3728         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3729                    sio_data->type == it8783) {
3730                 if (sio_data->internal & BIT(0))
3731                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3732                 if (sio_data->internal & BIT(1))
3733                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3734         }
3735
3736         data->has_temp = 0x07;
3737         if (sio_data->skip_temp & BIT(2)) {
3738                 if (sio_data->type == it8782 &&
3739                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3740                         data->has_temp &= ~BIT(2);
3741         }
3742
3743         data->in_internal = sio_data->internal;
3744         data->has_in = 0x3ff & ~sio_data->skip_in;
3745
3746         if (has_six_temp(data)) {
3747                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3748
3749                 /* Check for additional temperature sensors */
3750                 if ((reg & 0x03) >= 0x02)
3751                         data->has_temp |= BIT(3);
3752                 if (((reg >> 2) & 0x03) >= 0x02)
3753                         data->has_temp |= BIT(4);
3754                 if (((reg >> 4) & 0x03) >= 0x02)
3755                         data->has_temp |= BIT(5);
3756
3757                 /* Check for additional voltage sensors */
3758                 if ((reg & 0x03) == 0x01)
3759                         data->has_in |= BIT(10);
3760                 if (((reg >> 2) & 0x03) == 0x01)
3761                         data->has_in |= BIT(11);
3762                 if (((reg >> 4) & 0x03) == 0x01)
3763                         data->has_in |= BIT(12);
3764         }
3765
3766         data->has_beep = !!sio_data->beep_pin;
3767
3768         /* Initialize the IT87 chip */
3769         it87_init_device(pdev);
3770
3771         if (!sio_data->skip_vid) {
3772                 data->has_vid = true;
3773                 data->vrm = vid_which_vrm();
3774                 /* VID reading from Super-I/O config space if available */
3775                 data->vid = sio_data->vid_value;
3776         }
3777
3778         /* Prepare for sysfs hooks */
3779         data->groups[0] = &it87_group;
3780         data->groups[1] = &it87_group_in;
3781         data->groups[2] = &it87_group_temp;
3782         data->groups[3] = &it87_group_fan;
3783
3784         if (enable_pwm_interface) {
3785                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3786                 data->has_pwm &= ~sio_data->skip_pwm;
3787
3788                 data->groups[4] = &it87_group_pwm;
3789                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3790                         data->groups[5] = &it87_group_auto_pwm;
3791         }
3792
3793         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3794                                         it87_devices[sio_data->type].name,
3795                                         data, data->groups);
3796         return PTR_ERR_OR_ZERO(hwmon_dev);
3797 }
3798
3799 static struct platform_driver it87_driver = {
3800         .driver = {
3801                 .name   = DRVNAME,
3802         },
3803         .probe  = it87_probe,
3804 };
3805
3806 static int __init it87_device_add(int index, unsigned short address,
3807                                   const struct it87_sio_data *sio_data)
3808 {
3809         struct platform_device *pdev;
3810         struct resource res = {
3811                 .start  = address + IT87_EC_OFFSET,
3812                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3813                 .name   = DRVNAME,
3814                 .flags  = IORESOURCE_IO,
3815         };
3816         int err;
3817
3818         err = acpi_check_resource_conflict(&res);
3819         if (err)
3820                 return err;
3821
3822         pdev = platform_device_alloc(DRVNAME, address);
3823         if (!pdev)
3824                 return -ENOMEM;
3825
3826         err = platform_device_add_resources(pdev, &res, 1);
3827         if (err) {
3828                 pr_err("Device resource addition failed (%d)\n", err);
3829                 goto exit_device_put;
3830         }
3831
3832         err = platform_device_add_data(pdev, sio_data,
3833                                        sizeof(struct it87_sio_data));
3834         if (err) {
3835                 pr_err("Platform data allocation failed\n");
3836                 goto exit_device_put;
3837         }
3838
3839         err = platform_device_add(pdev);
3840         if (err) {
3841                 pr_err("Device addition failed (%d)\n", err);
3842                 goto exit_device_put;
3843         }
3844
3845         it87_pdev[index] = pdev;
3846         return 0;
3847
3848 exit_device_put:
3849         platform_device_put(pdev);
3850         return err;
3851 }
3852
3853 struct it87_dmi_data {
3854         bool sio4e_broken;      /* SIO accesses @ 0x4e are broken       */
3855         char *sio_mutex;        /* SIO ACPI mutex                       */
3856         u8 skip_pwm;            /* pwm channels to skip for this board  */
3857 };
3858
3859 /*
3860  * On Gigabyte AB350 and AX370 boards, accesses to the Super-IO chip
3861  * at address 0x4e/0x4f can result in a system hang.
3862  * Accesses to address 0x2e/0x2f need to be mutex protected.
3863  */
3864 static struct it87_dmi_data gigabyte_ab350_gaming = {
3865         .sio4e_broken = true,
3866         .sio_mutex = "\\_SB.PCI0.SBRG.SIO1.MUT0",
3867 };
3868
3869 /*
3870  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3871  * connected to a fan, but to something else. One user
3872  * has reported instant system power-off when changing
3873  * the PWM2 duty cycle, so we disable it.
3874  * I use the board name string as the trigger in case
3875  * the same board is ever used in other systems.
3876  */
3877 static struct it87_dmi_data nvidia_fn68pt = {
3878         .skip_pwm = BIT(1),
3879 };
3880
3881 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3882         {
3883                 .matches = {
3884                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3885                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming-CF"),
3886                 },
3887                 .driver_data = &gigabyte_ab350_gaming,
3888         },
3889         {
3890                 .matches = {
3891                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3892                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming 3-CF"),
3893                 },
3894                 .driver_data = &gigabyte_ab350_gaming,
3895         },
3896         {
3897                 .matches = {
3898                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3899                         DMI_MATCH(DMI_BOARD_NAME, "AB350M-D3H-CF"),
3900                 },
3901                 .driver_data = &gigabyte_ab350_gaming,
3902         },
3903         {
3904                 .matches = {
3905                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3906                         DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming K7"),
3907                 },
3908                 .driver_data = &gigabyte_ab350_gaming,
3909         },
3910         {
3911                 .matches = {
3912                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3913                         DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming 5"),
3914                 },
3915                 .driver_data = &gigabyte_ab350_gaming,
3916         },
3917         {
3918                 .matches = {
3919                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3920                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3921                 },
3922                 .driver_data = &nvidia_fn68pt,
3923         },
3924         { }
3925 };
3926
3927 static int __init sm_it87_init(void)
3928 {
3929         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3930         struct it87_dmi_data *dmi_data = NULL;
3931         int sioaddr[2] = { REG_2E, REG_4E };
3932         struct it87_sio_data sio_data;
3933         unsigned short isa_address;
3934         bool found = false;
3935         int i, err;
3936
3937         if (dmi)
3938                 dmi_data = dmi->driver_data;
3939
3940         if (dmi_data) {
3941                 it87_sio4e_broken = dmi_data->sio4e_broken;
3942 #ifdef __IT87_USE_ACPI_MUTEX
3943                 if (dmi_data->sio_mutex) {
3944                         static acpi_status status;
3945
3946                         status = acpi_get_handle(NULL, dmi_data->sio_mutex,
3947                                                  &it87_acpi_sio_handle);
3948                         if (ACPI_SUCCESS(status)) {
3949                                 it87_acpi_sio_mutex = dmi_data->sio_mutex;
3950                                 pr_debug("Found ACPI SIO mutex %s\n",
3951                                          dmi_data->sio_mutex);
3952                         } else {
3953                                 pr_warn("ACPI SIO mutex %s not found\n",
3954                                         dmi_data->sio_mutex);
3955                         }
3956                 }
3957 #endif /* __IT87_USE_ACPI_MUTEX */
3958         }
3959
3960         err = platform_driver_register(&it87_driver);
3961         if (err)
3962                 return err;
3963
3964         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3965                 /*
3966                  * Accessing the second Super-IO chip can result in board
3967                  * hangs. Disable until we figure out what is going on.
3968                  */
3969                 if (blacklist && it87_sio4e_broken && sioaddr[i] == 0x4e)
3970                         continue;
3971                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3972                 isa_address = 0;
3973                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3974                 if (err || isa_address == 0)
3975                         continue;
3976
3977                 if (dmi_data)
3978                         sio_data.skip_pwm |= dmi_data->skip_pwm;
3979                 err = it87_device_add(i, isa_address, &sio_data);
3980                 if (err)
3981                         goto exit_dev_unregister;
3982                 found = true;
3983         }
3984
3985         if (!found) {
3986                 err = -ENODEV;
3987                 goto exit_unregister;
3988         }
3989         return 0;
3990
3991 exit_dev_unregister:
3992         /* NULL check handled by platform_device_unregister */
3993         platform_device_unregister(it87_pdev[0]);
3994 exit_unregister:
3995         platform_driver_unregister(&it87_driver);
3996         return err;
3997 }
3998
3999 static void __exit sm_it87_exit(void)
4000 {
4001         /* NULL check handled by platform_device_unregister */
4002         platform_device_unregister(it87_pdev[1]);
4003         platform_device_unregister(it87_pdev[0]);
4004         platform_driver_unregister(&it87_driver);
4005 }
4006
4007 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4008 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4009 module_param(update_vbat, bool, 0);
4010 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4011 module_param(fix_pwm_polarity, bool, 0);
4012 MODULE_PARM_DESC(fix_pwm_polarity,
4013                  "Force PWM polarity to active high (DANGEROUS)");
4014 MODULE_LICENSE("GPL");
4015
4016 module_init(sm_it87_init);
4017 module_exit(sm_it87_exit);