git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77
  78 #define DRVNAME "it87"
  79
  80 /* Necessary API not (yet) exported in upstream kernel */
  81 /* #define __IT87_USE_ACPI_MUTEX */
  82
  83 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  84              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  85              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  86              it8655, it8665, it8686 };
  87
  88 static unsigned short force_id;
  89 module_param(force_id, ushort, 0);
  90 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  91
  92 static unsigned short blacklist = 1;
  93 module_param(blacklist, ushort, 0);
  94 MODULE_PARM_DESC(blacklist,
  95                  "Enable/disable blacklist (1=enable, 0=disable, default 1)");
  96
  97 static struct platform_device *it87_pdev[2];
  98 static bool it87_sio4e_broken;
  99 #ifdef __IT87_USE_ACPI_MUTEX
 100 static acpi_handle it87_acpi_sio_handle;
 101 static char *it87_acpi_sio_mutex;
 102 #endif
 103
 104 #define REG_2E  0x2e    /* The register to read/write */
 105 #define REG_4E  0x4e    /* Secondary register to read/write */
 106
 107 #define DEV     0x07    /* Register: Logical device select */
 108 #define PME     0x04    /* The device with the fan registers in it */
 109
 110 /* The device with the IT8718F/IT8720F VID value in it */
 111 #define GPIO    0x07
 112
 113 #define DEVID   0x20    /* Register: Device ID */
 114 #define DEVREV  0x22    /* Register: Device Revision */
 115
 116 static inline void __superio_enter(int ioreg)
 117 {
 118         outb(0x87, ioreg);
 119         outb(0x01, ioreg);
 120         outb(0x55, ioreg);
 121         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 122 }
 123
 124 static inline int superio_inb(int ioreg, int reg)
 125 {
 126         int val;
 127
 128         outb(reg, ioreg);
 129         val = inb(ioreg + 1);
 130         if (it87_sio4e_broken && ioreg == 0x4e && val == 0xff) {
 131                 __superio_enter(ioreg);
 132                 outb(reg, ioreg);
 133                 val = inb(ioreg + 1);
 134                 pr_warn("Retry access 0x4e:0x%x -> 0x%x\n", reg, val);
 135         }
 136
 137         return val;
 138 }
 139
 140 static inline void superio_outb(int ioreg, int reg, int val)
 141 {
 142         outb(reg, ioreg);
 143         outb(val, ioreg + 1);
 144 }
 145
 146 static int superio_inw(int ioreg, int reg)
 147 {
 148         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 149 }
 150
 151 static inline void superio_select(int ioreg, int ldn)
 152 {
 153         outb(DEV, ioreg);
 154         outb(ldn, ioreg + 1);
 155 }
 156
 157 static inline int superio_enter(int ioreg)
 158 {
 159 #ifdef __IT87_USE_ACPI_MUTEX
 160         if (it87_acpi_sio_mutex) {
 161                 acpi_status status;
 162
 163                 status = acpi_acquire_mutex(NULL, it87_acpi_sio_mutex, 0x10);
 164                 if (ACPI_FAILURE(status)) {
 165                         pr_err("Failed to acquire ACPI mutex\n");
 166                         return -EBUSY;
 167                 }
 168         }
 169 #endif
 170         /*
 171          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 172          */
 173         if (!request_muxed_region(ioreg, 2, DRVNAME))
 174                 goto error;
 175
 176         __superio_enter(ioreg);
 177         return 0;
 178
 179 error:
 180 #ifdef __IT87_USE_ACPI_MUTEX
 181         if (it87_acpi_sio_mutex)
 182                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 183 #endif
 184         return -EBUSY;
 185 }
 186
 187 static inline void superio_exit(int ioreg)
 188 {
 189         if (!it87_sio4e_broken || ioreg != 0x4e) {
 190                 outb(0x02, ioreg);
 191                 outb(0x02, ioreg + 1);
 192         }
 193         release_region(ioreg, 2);
 194 #ifdef __IT87_USE_ACPI_MUTEX
 195         if (it87_acpi_sio_mutex)
 196                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 197 #endif
 198 }
 199
 200 /* Logical device 4 registers */
 201 #define IT8712F_DEVID 0x8712
 202 #define IT8705F_DEVID 0x8705
 203 #define IT8716F_DEVID 0x8716
 204 #define IT8718F_DEVID 0x8718
 205 #define IT8720F_DEVID 0x8720
 206 #define IT8721F_DEVID 0x8721
 207 #define IT8726F_DEVID 0x8726
 208 #define IT8728F_DEVID 0x8728
 209 #define IT8732F_DEVID 0x8732
 210 #define IT8792E_DEVID 0x8733
 211 #define IT8771E_DEVID 0x8771
 212 #define IT8772E_DEVID 0x8772
 213 #define IT8781F_DEVID 0x8781
 214 #define IT8782F_DEVID 0x8782
 215 #define IT8783E_DEVID 0x8783
 216 #define IT8786E_DEVID 0x8786
 217 #define IT8790E_DEVID 0x8790
 218 #define IT8603E_DEVID 0x8603
 219 #define IT8607E_DEVID 0x8607
 220 #define IT8613E_DEVID 0x8613
 221 #define IT8620E_DEVID 0x8620
 222 #define IT8622E_DEVID 0x8622
 223 #define IT8623E_DEVID 0x8623
 224 #define IT8625E_DEVID 0x8625
 225 #define IT8628E_DEVID 0x8628
 226 #define IT8655E_DEVID 0x8655
 227 #define IT8665E_DEVID 0x8665
 228 #define IT8686E_DEVID 0x8686
 229 #define IT87_ACT_REG  0x30
 230 #define IT87_BASE_REG 0x60
 231
 232 /* Logical device 7 registers (IT8712F and later) */
 233 #define IT87_SIO_GPIO1_REG      0x25
 234 #define IT87_SIO_GPIO2_REG      0x26
 235 #define IT87_SIO_GPIO3_REG      0x27
 236 #define IT87_SIO_GPIO4_REG      0x28
 237 #define IT87_SIO_GPIO5_REG      0x29
 238 #define IT87_SIO_GPIO9_REG      0xd3
 239 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 240 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 241 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 242 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 243 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 244 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 245
 246 /* Update battery voltage after every reading if true */
 247 static bool update_vbat;
 248
 249 /* Not all BIOSes properly configure the PWM registers */
 250 static bool fix_pwm_polarity;
 251
 252 /* Many IT87 constants specified below */
 253
 254 /* Length of ISA address segment */
 255 #define IT87_EXTENT 8
 256
 257 /* Length of ISA address segment for Environmental Controller */
 258 #define IT87_EC_EXTENT 2
 259
 260 /* Offset of EC registers from ISA base address */
 261 #define IT87_EC_OFFSET 5
 262
 263 /* Where are the ISA address/data registers relative to the EC base address */
 264 #define IT87_ADDR_REG_OFFSET 0
 265 #define IT87_DATA_REG_OFFSET 1
 266
 267 /*----- The IT87 registers -----*/
 268
 269 #define IT87_REG_CONFIG        0x00
 270
 271 #define IT87_REG_ALARM1        0x01
 272 #define IT87_REG_ALARM2        0x02
 273 #define IT87_REG_ALARM3        0x03
 274
 275 #define IT87_REG_BANK           0x06
 276
 277 /*
 278  * The IT8718F and IT8720F have the VID value in a different register, in
 279  * Super-I/O configuration space.
 280  */
 281 #define IT87_REG_VID           0x0a
 282 /*
 283  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 284  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 285  * mode.
 286  */
 287 #define IT87_REG_FAN_DIV       0x0b
 288 #define IT87_REG_FAN_16BIT     0x0c
 289
 290 /*
 291  * Monitors:
 292  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 293  * - up to 6 temp (1 to 6)
 294  * - up to 6 fan (1 to 6)
 295  */
 296
 297 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 298 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 299 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 300 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 301
 302 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 303 static const u8 IT87_REG_FAN_MIN_8665[] =
 304                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 305 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 306 static const u8 IT87_REG_FANX_MIN_8665[] =
 307                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 308
 309 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 310
 311 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 312
 313 #define IT87_REG_FAN_MAIN_CTRL 0x13
 314 #define IT87_REG_FAN_CTL       0x14
 315
 316 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 317 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 318
 319 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 320
 321 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 322                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 323
 324 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 325
 326 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 327 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 328
 329 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 330 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 331
 332 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 333                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 334 static const u8 IT87_REG_TEMP_LOW_8686[] =
 335                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 336
 337 #define IT87_REG_VIN_ENABLE    0x50
 338 #define IT87_REG_TEMP_ENABLE   0x51
 339 #define IT87_REG_TEMP_EXTRA    0x55
 340 #define IT87_REG_BEEP_ENABLE   0x5c
 341
 342 #define IT87_REG_CHIPID        0x58
 343
 344 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 345
 346 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 347 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 348
 349 #define IT87_REG_TEMP456_ENABLE 0x77
 350
 351 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 352 #define IT87_REG_TEMP_SRC2      0x23d
 353
 354 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 355 #define NUM_VIN_LIMIT           8
 356 #define NUM_TEMP                6
 357 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 358 #define NUM_FAN_DIV             3
 359 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 360 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 361
 362 struct it87_devices {
 363         const char *name;
 364         const char * const suffix;
 365         u32 features;
 366         u8 num_temp_limit;
 367         u8 peci_mask;
 368         u8 old_peci_mask;
 369 };
 370
 371 #define FEAT_12MV_ADC           BIT(0)
 372 #define FEAT_NEWER_AUTOPWM      BIT(1)
 373 #define FEAT_OLD_AUTOPWM        BIT(2)
 374 #define FEAT_16BIT_FANS         BIT(3)
 375 #define FEAT_TEMP_OFFSET        BIT(4)
 376 #define FEAT_TEMP_PECI          BIT(5)
 377 #define FEAT_TEMP_OLD_PECI      BIT(6)
 378 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 379 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 380 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 381 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 382 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 383 #define FEAT_10_9MV_ADC         BIT(12)
 384 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 385 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 386 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 387 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 388 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 389 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 390 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 391 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 392 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 393 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 394 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 395 #define FEAT_11MV_ADC           BIT(24)
 396 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 397
 398 static const struct it87_devices it87_devices[] = {
 399         [it87] = {
 400                 .name = "it87",
 401                 .suffix = "F",
 402                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 403                                                 /* may need to overwrite */
 404                 .num_temp_limit = 3,
 405         },
 406         [it8712] = {
 407                 .name = "it8712",
 408                 .suffix = "F",
 409                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 410                                                 /* may need to overwrite */
 411                 .num_temp_limit = 3,
 412         },
 413         [it8716] = {
 414                 .name = "it8716",
 415                 .suffix = "F",
 416                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 417                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 418                   | FEAT_FANCTL_ONOFF,
 419                 .num_temp_limit = 3,
 420         },
 421         [it8718] = {
 422                 .name = "it8718",
 423                 .suffix = "F",
 424                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 425                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 426                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 427                 .num_temp_limit = 3,
 428                 .old_peci_mask = 0x4,
 429         },
 430         [it8720] = {
 431                 .name = "it8720",
 432                 .suffix = "F",
 433                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 434                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 435                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 436                 .num_temp_limit = 3,
 437                 .old_peci_mask = 0x4,
 438         },
 439         [it8721] = {
 440                 .name = "it8721",
 441                 .suffix = "F",
 442                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 443                   | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 444                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 445                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 446                 .num_temp_limit = 3,
 447                 .peci_mask = 0x05,
 448                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 449         },
 450         [it8728] = {
 451                 .name = "it8728",
 452                 .suffix = "F",
 453                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 454                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 455                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 456                   | FEAT_FANCTL_ONOFF,
 457                 .num_temp_limit = 3,
 458                 .peci_mask = 0x07,
 459         },
 460         [it8732] = {
 461                 .name = "it8732",
 462                 .suffix = "F",
 463                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 464                   | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 465                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 466                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 467                 .num_temp_limit = 3,
 468                 .peci_mask = 0x07,
 469                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 470         },
 471         [it8771] = {
 472                 .name = "it8771",
 473                 .suffix = "E",
 474                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 475                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 476                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 477                                 /* PECI: guesswork */
 478                                 /* 12mV ADC (OHM) */
 479                                 /* 16 bit fans (OHM) */
 480                                 /* three fans, always 16 bit (guesswork) */
 481                 .num_temp_limit = 3,
 482                 .peci_mask = 0x07,
 483         },
 484         [it8772] = {
 485                 .name = "it8772",
 486                 .suffix = "E",
 487                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 488                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 489                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 490                                 /* PECI (coreboot) */
 491                                 /* 12mV ADC (HWSensors4, OHM) */
 492                                 /* 16 bit fans (HWSensors4, OHM) */
 493                                 /* three fans, always 16 bit (datasheet) */
 494                 .num_temp_limit = 3,
 495                 .peci_mask = 0x07,
 496         },
 497         [it8781] = {
 498                 .name = "it8781",
 499                 .suffix = "F",
 500                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 501                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 502                   | FEAT_FANCTL_ONOFF,
 503                 .num_temp_limit = 3,
 504                 .old_peci_mask = 0x4,
 505         },
 506         [it8782] = {
 507                 .name = "it8782",
 508                 .suffix = "F",
 509                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 510                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 511                   | FEAT_FANCTL_ONOFF,
 512                 .num_temp_limit = 3,
 513                 .old_peci_mask = 0x4,
 514         },
 515         [it8783] = {
 516                 .name = "it8783",
 517                 .suffix = "E/F",
 518                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 519                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 520                   | FEAT_FANCTL_ONOFF,
 521                 .num_temp_limit = 3,
 522                 .old_peci_mask = 0x4,
 523         },
 524         [it8786] = {
 525                 .name = "it8786",
 526                 .suffix = "E",
 527                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 528                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 529                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 530                 .num_temp_limit = 3,
 531                 .peci_mask = 0x07,
 532         },
 533         [it8790] = {
 534                 .name = "it8790",
 535                 .suffix = "E",
 536                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 537                   | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
 538                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 539                 .num_temp_limit = 3,
 540                 .peci_mask = 0x07,
 541         },
 542         [it8792] = {
 543                 .name = "it8792",
 544                 .suffix = "E",
 545                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 546                   | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
 547                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 548                 .num_temp_limit = 3,
 549                 .peci_mask = 0x07,
 550         },
 551         [it8603] = {
 552                 .name = "it8603",
 553                 .suffix = "E",
 554                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 555                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 556                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 557                 .num_temp_limit = 3,
 558                 .peci_mask = 0x07,
 559         },
 560         [it8607] = {
 561                 .name = "it8607",
 562                 .suffix = "E",
 563                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 564                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 565                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 566                   | FEAT_FANCTL_ONOFF,
 567                 .num_temp_limit = 3,
 568                 .peci_mask = 0x07,
 569         },
 570         [it8613] = {
 571                 .name = "it8613",
 572                 .suffix = "E",
 573                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 574                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 575                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 576                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 577                 .num_temp_limit = 6,
 578                 .peci_mask = 0x07,
 579         },
 580         [it8620] = {
 581                 .name = "it8620",
 582                 .suffix = "E",
 583                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 584                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 585                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 586                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 587                   | FEAT_FANCTL_ONOFF,
 588                 .num_temp_limit = 3,
 589                 .peci_mask = 0x07,
 590         },
 591         [it8622] = {
 592                 .name = "it8622",
 593                 .suffix = "E",
 594                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 595                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 596                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 597                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 598                 .num_temp_limit = 3,
 599                 .peci_mask = 0x07,
 600         },
 601         [it8625] = {
 602                 .name = "it8625",
 603                 .suffix = "E",
 604                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 605                   | FEAT_TEMP_OFFSET | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 606                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 607                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 608                 .num_temp_limit = 6,
 609         },
 610         [it8628] = {
 611                 .name = "it8628",
 612                 .suffix = "E",
 613                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 614                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 615                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 616                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 617                   | FEAT_FANCTL_ONOFF,
 618                 .num_temp_limit = 3,
 619                 .peci_mask = 0x07,
 620         },
 621         [it8655] = {
 622                 .name = "it8655",
 623                 .suffix = "E",
 624                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 625                   | FEAT_TEMP_OFFSET | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 626                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 627                 .num_temp_limit = 6,
 628         },
 629         [it8665] = {
 630                 .name = "it8665",
 631                 .suffix = "E",
 632                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 633                   | FEAT_TEMP_OFFSET | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 634                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 635                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 636                 .num_temp_limit = 6,
 637         },
 638         [it8686] = {
 639                 .name = "it8686",
 640                 .suffix = "E",
 641                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 642                   | FEAT_TEMP_OFFSET | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 643                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 644                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 645                 .num_temp_limit = 6,
 646         },
 647 };
 648
 649 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 650 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 651 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 652 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 653 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 654 #define has_temp_offset(data)   ((data)->features & FEAT_TEMP_OFFSET)
 655 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 656                                  ((data)->peci_mask & BIT(nr)))
 657 #define has_temp_old_peci(data, nr) \
 658                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 659                                  ((data)->old_peci_mask & BIT(nr)))
 660 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 661 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 662                                                      FEAT_SIX_FANS))
 663 #define has_vid(data)           ((data)->features & FEAT_VID)
 664 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 665 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 666 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 667 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 668                                                      | FEAT_SIX_PWM))
 669 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 670 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 671 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 672 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 673 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 674                                                      FEAT_FIVE_FANS | \
 675                                                      FEAT_SIX_FANS))
 676 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 677                                                      FEAT_FIVE_PWM \
 678                                                      | FEAT_SIX_PWM))
 679 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 680 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 681 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 682 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 683 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 684
 685 struct it87_sio_data {
 686         enum chips type;
 687         /* Values read from Super-I/O config space */
 688         u8 revision;
 689         u8 vid_value;
 690         u8 beep_pin;
 691         u8 internal;    /* Internal sensors can be labeled */
 692         /* Features skipped based on config or DMI */
 693         u16 skip_in;
 694         u8 skip_vid;
 695         u8 skip_fan;
 696         u8 skip_pwm;
 697         u8 skip_temp;
 698 };
 699
 700 /*
 701  * For each registered chip, we need to keep some data in memory.
 702  * The structure is dynamically allocated.
 703  */
 704 struct it87_data {
 705         const struct attribute_group *groups[7];
 706         enum chips type;
 707         u32 features;
 708         u8 bank;
 709         u8 peci_mask;
 710         u8 old_peci_mask;
 711
 712         const u8 *REG_FAN;
 713         const u8 *REG_FANX;
 714         const u8 *REG_FAN_MIN;
 715         const u8 *REG_FANX_MIN;
 716
 717         const u8 *REG_PWM;
 718
 719         const u8 *REG_TEMP_OFFSET;
 720         const u8 *REG_TEMP_LOW;
 721         const u8 *REG_TEMP_HIGH;
 722
 723         unsigned short addr;
 724         const char *name;
 725         struct mutex update_lock;
 726         char valid;             /* !=0 if following fields are valid */
 727         unsigned long last_updated;     /* In jiffies */
 728
 729         u16 in_scaled;          /* Internal voltage sensors are scaled */
 730         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 731         u16 has_in;             /* Bitfield, voltage sensors enabled */
 732         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 733         u8 has_fan;             /* Bitfield, fans enabled */
 734         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 735         u8 has_temp;            /* Bitfield, temp sensors enabled */
 736         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 737         u8 num_temp_limit;      /* Number of temp limit/offset registers */
 738         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 739         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 740         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 741         bool has_vid;           /* True if VID supported */
 742         u8 vid;                 /* Register encoding, combined */
 743         u8 vrm;
 744         u32 alarms;             /* Register encoding, combined */
 745         bool has_beep;          /* true if beep supported */
 746         u8 beeps;               /* Register encoding */
 747         u8 fan_main_ctrl;       /* Register value */
 748         u8 fan_ctl;             /* Register value */
 749
 750         /*
 751          * The following 3 arrays correspond to the same registers up to
 752          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 753          * 7, and we want to preserve settings on mode changes, so we have
 754          * to track all values separately.
 755          * Starting with the IT8721F, the manual PWM duty cycles are stored
 756          * in separate registers (8-bit values), so the separate tracking
 757          * is no longer needed, but it is still done to keep the driver
 758          * simple.
 759          */
 760         u8 has_pwm;             /* Bitfield, pwm control enabled */
 761         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 762         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 763         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 764
 765         /* Automatic fan speed control registers */
 766         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 767         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 768 };
 769
 770 static int adc_lsb(const struct it87_data *data, int nr)
 771 {
 772         int lsb;
 773
 774         if (has_12mv_adc(data))
 775                 lsb = 120;
 776         else if (has_10_9mv_adc(data))
 777                 lsb = 109;
 778         else if (has_11mv_adc(data))
 779                 lsb = 110;
 780         else
 781                 lsb = 160;
 782         if (data->in_scaled & BIT(nr))
 783                 lsb <<= 1;
 784         return lsb;
 785 }
 786
 787 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 788 {
 789         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 790         return clamp_val(val, 0, 255);
 791 }
 792
 793 static int in_from_reg(const struct it87_data *data, int nr, int val)
 794 {
 795         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 796 }
 797
 798 static inline u8 FAN_TO_REG(long rpm, int div)
 799 {
 800         if (rpm == 0)
 801                 return 255;
 802         rpm = clamp_val(rpm, 1, 1000000);
 803         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 804 }
 805
 806 static inline u16 FAN16_TO_REG(long rpm)
 807 {
 808         if (rpm == 0)
 809                 return 0xffff;
 810         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 811 }
 812
 813 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 814                                 1350000 / ((val) * (div)))
 815 /* The divider is fixed to 2 in 16-bit mode */
 816 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 817                              1350000 / ((val) * 2))
 818
 819 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 820                                     ((val) + 500) / 1000), -128, 127))
 821 #define TEMP_FROM_REG(val) ((val) * 1000)
 822
 823 static u8 pwm_to_reg(const struct it87_data *data, long val)
 824 {
 825         if (has_newer_autopwm(data))
 826                 return val;
 827         else
 828                 return val >> 1;
 829 }
 830
 831 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 832 {
 833         if (has_newer_autopwm(data))
 834                 return reg;
 835         else
 836                 return (reg & 0x7f) << 1;
 837 }
 838
 839 static int DIV_TO_REG(int val)
 840 {
 841         int answer = 0;
 842
 843         while (answer < 7 && (val >>= 1))
 844                 answer++;
 845         return answer;
 846 }
 847
 848 #define DIV_FROM_REG(val) BIT(val)
 849
 850 /*
 851  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 852  * depending on the chip type, to calculate the actual PWM frequency.
 853  *
 854  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 855  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 856  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 857  * sometimes just one. It is unknown if this is a datasheet error or real,
 858  * so this is ignored for now.
 859  */
 860 static const unsigned int pwm_freq[8] = {
 861         48000000,
 862         24000000,
 863         12000000,
 864         8000000,
 865         6000000,
 866         3000000,
 867         1500000,
 868         750000,
 869 };
 870
 871 static int _it87_read_value(struct it87_data *data, u8 reg)
 872 {
 873         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 874         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 875 }
 876
 877 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 878 {
 879         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 880         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 881 }
 882
 883 static void it87_set_bank(struct it87_data *data, u8 bank)
 884 {
 885         if (has_bank_sel(data) && bank != data->bank) {
 886                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 887
 888                 breg &= 0x1f;
 889                 breg |= (bank << 5);
 890                 data->bank = bank;
 891                 _it87_write_value(data, IT87_REG_BANK, breg);
 892         }
 893 }
 894
 895 /*
 896  * Must be called with data->update_lock held, except during initialization.
 897  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 898  * would slow down the IT87 access and should not be necessary.
 899  */
 900 static int it87_read_value(struct it87_data *data, u16 reg)
 901 {
 902         it87_set_bank(data, reg >> 8);
 903         return _it87_read_value(data, reg & 0xff);
 904 }
 905
 906 /*
 907  * Must be called with data->update_lock held, except during initialization.
 908  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 909  * would slow down the IT87 access and should not be necessary.
 910  */
 911 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
 912 {
 913         it87_set_bank(data, reg >> 8);
 914         _it87_write_value(data, reg & 0xff, value);
 915 }
 916
 917 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 918 {
 919         data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]);
 920         if (has_newer_autopwm(data)) {
 921                 if (has_new_tempmap(data))
 922                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x38;
 923                 else
 924                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 925                 data->pwm_duty[nr] = it87_read_value(data,
 926                                                      IT87_REG_PWM_DUTY[nr]);
 927         } else {
 928                 if (data->pwm_ctrl[nr] & 0x80)  /* Automatic mode */
 929                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 930                 else                            /* Manual mode */
 931                         data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
 932         }
 933
 934         if (has_old_autopwm(data)) {
 935                 int i;
 936
 937                 for (i = 0; i < 5 ; i++)
 938                         data->auto_temp[nr][i] = it87_read_value(data,
 939                                                 IT87_REG_AUTO_TEMP(nr, i));
 940                 for (i = 0; i < 3 ; i++)
 941                         data->auto_pwm[nr][i] = it87_read_value(data,
 942                                                 IT87_REG_AUTO_PWM(nr, i));
 943         } else if (has_newer_autopwm(data)) {
 944                 int i;
 945
 946                 /*
 947                  * 0: temperature hysteresis (base + 5)
 948                  * 1: fan off temperature (base + 0)
 949                  * 2: fan start temperature (base + 1)
 950                  * 3: fan max temperature (base + 2)
 951                  */
 952                 data->auto_temp[nr][0] =
 953                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
 954
 955                 for (i = 0; i < 3 ; i++)
 956                         data->auto_temp[nr][i + 1] =
 957                                 it87_read_value(data,
 958                                                 IT87_REG_AUTO_TEMP(nr, i));
 959                 /*
 960                  * 0: start pwm value (base + 3)
 961                  * 1: pwm slope (base + 4, 1/8th pwm)
 962                  */
 963                 data->auto_pwm[nr][0] =
 964                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
 965                 data->auto_pwm[nr][1] =
 966                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
 967         }
 968 }
 969
 970 static struct it87_data *it87_update_device(struct device *dev)
 971 {
 972         struct it87_data *data = dev_get_drvdata(dev);
 973         int i;
 974
 975         mutex_lock(&data->update_lock);
 976
 977         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
 978             !data->valid) {
 979                 if (update_vbat) {
 980                         /*
 981                          * Cleared after each update, so reenable.  Value
 982                          * returned by this read will be previous value
 983                          */
 984                         it87_write_value(data, IT87_REG_CONFIG,
 985                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
 986                 }
 987                 for (i = 0; i < NUM_VIN; i++) {
 988                         if (!(data->has_in & BIT(i)))
 989                                 continue;
 990
 991                         data->in[i][0] =
 992                                 it87_read_value(data, IT87_REG_VIN[i]);
 993
 994                         /* VBAT and AVCC don't have limit registers */
 995                         if (i >= NUM_VIN_LIMIT)
 996                                 continue;
 997
 998                         data->in[i][1] =
 999                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
1000                         data->in[i][2] =
1001                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
1002                 }
1003
1004                 for (i = 0; i < NUM_FAN; i++) {
1005                         /* Skip disabled fans */
1006                         if (!(data->has_fan & BIT(i)))
1007                                 continue;
1008
1009                         data->fan[i][1] =
1010                                 it87_read_value(data, data->REG_FAN_MIN[i]);
1011                         data->fan[i][0] = it87_read_value(data,
1012                                        data->REG_FAN[i]);
1013                         /* Add high byte if in 16-bit mode */
1014                         if (has_16bit_fans(data)) {
1015                                 data->fan[i][0] |= it87_read_value(data,
1016                                                 data->REG_FANX[i]) << 8;
1017                                 data->fan[i][1] |= it87_read_value(data,
1018                                                 data->REG_FANX_MIN[i]) << 8;
1019                         }
1020                 }
1021                 for (i = 0; i < NUM_TEMP; i++) {
1022                         if (!(data->has_temp & BIT(i)))
1023                                 continue;
1024                         data->temp[i][0] =
1025                                 it87_read_value(data, IT87_REG_TEMP(i));
1026
1027                         if (i >= data->num_temp_limit)
1028                                 continue;
1029
1030                         if (has_temp_offset(data))
1031                                 data->temp[i][3] =
1032                                   it87_read_value(data,
1033                                                   data->REG_TEMP_OFFSET[i]);
1034
1035                         data->temp[i][1] =
1036                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1037                         data->temp[i][2] =
1038                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1039                 }
1040
1041                 /* Newer chips don't have clock dividers */
1042                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1043                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1044                         data->fan_div[0] = i & 0x07;
1045                         data->fan_div[1] = (i >> 3) & 0x07;
1046                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1047                 }
1048
1049                 data->alarms =
1050                         it87_read_value(data, IT87_REG_ALARM1) |
1051                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1052                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1053                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1054
1055                 data->fan_main_ctrl = it87_read_value(data,
1056                                 IT87_REG_FAN_MAIN_CTRL);
1057                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1058                 for (i = 0; i < NUM_PWM; i++) {
1059                         if (!(data->has_pwm & BIT(i)))
1060                                 continue;
1061                         it87_update_pwm_ctrl(data, i);
1062                 }
1063
1064                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1065                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1066                 /*
1067                  * The IT8705F does not have VID capability.
1068                  * The IT8718F and later don't use IT87_REG_VID for the
1069                  * same purpose.
1070                  */
1071                 if (data->type == it8712 || data->type == it8716) {
1072                         data->vid = it87_read_value(data, IT87_REG_VID);
1073                         /*
1074                          * The older IT8712F revisions had only 5 VID pins,
1075                          * but we assume it is always safe to read 6 bits.
1076                          */
1077                         data->vid &= 0x3f;
1078                 }
1079                 data->last_updated = jiffies;
1080                 data->valid = 1;
1081         }
1082
1083         mutex_unlock(&data->update_lock);
1084
1085         return data;
1086 }
1087
1088 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1089                        char *buf)
1090 {
1091         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1092         struct it87_data *data = it87_update_device(dev);
1093         int index = sattr->index;
1094         int nr = sattr->nr;
1095
1096         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1097 }
1098
1099 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1100                       const char *buf, size_t count)
1101 {
1102         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1103         struct it87_data *data = dev_get_drvdata(dev);
1104         int index = sattr->index;
1105         int nr = sattr->nr;
1106         unsigned long val;
1107
1108         if (kstrtoul(buf, 10, &val) < 0)
1109                 return -EINVAL;
1110
1111         mutex_lock(&data->update_lock);
1112         data->in[nr][index] = in_to_reg(data, nr, val);
1113         it87_write_value(data,
1114                          index == 1 ? IT87_REG_VIN_MIN(nr)
1115                                     : IT87_REG_VIN_MAX(nr),
1116                          data->in[nr][index]);
1117         mutex_unlock(&data->update_lock);
1118         return count;
1119 }
1120
1121 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1122 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1123                             0, 1);
1124 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1125                             0, 2);
1126
1127 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1128 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1129                             1, 1);
1130 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1131                             1, 2);
1132
1133 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1134 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1135                             2, 1);
1136 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1137                             2, 2);
1138
1139 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1140 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1141                             3, 1);
1142 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1143                             3, 2);
1144
1145 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1146 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1147                             4, 1);
1148 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1149                             4, 2);
1150
1151 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1152 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1153                             5, 1);
1154 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1155                             5, 2);
1156
1157 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1158 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1159                             6, 1);
1160 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1161                             6, 2);
1162
1163 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1164 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1165                             7, 1);
1166 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1167                             7, 2);
1168
1169 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1170 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1171 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1172 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1173 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1174
1175 /* Up to 6 temperatures */
1176 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1177                          char *buf)
1178 {
1179         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1180         int nr = sattr->nr;
1181         int index = sattr->index;
1182         struct it87_data *data = it87_update_device(dev);
1183
1184         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1185 }
1186
1187 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1188                         const char *buf, size_t count)
1189 {
1190         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1191         int nr = sattr->nr;
1192         int index = sattr->index;
1193         struct it87_data *data = dev_get_drvdata(dev);
1194         long val;
1195         u8 reg, regval;
1196
1197         if (kstrtol(buf, 10, &val) < 0)
1198                 return -EINVAL;
1199
1200         mutex_lock(&data->update_lock);
1201
1202         switch (index) {
1203         default:
1204         case 1:
1205                 reg = data->REG_TEMP_LOW[nr];
1206                 break;
1207         case 2:
1208                 reg = data->REG_TEMP_HIGH[nr];
1209                 break;
1210         case 3:
1211                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1212                 if (!(regval & 0x80)) {
1213                         regval |= 0x80;
1214                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1215                 }
1216                 data->valid = 0;
1217                 reg = data->REG_TEMP_OFFSET[nr];
1218                 break;
1219         }
1220
1221         data->temp[nr][index] = TEMP_TO_REG(val);
1222         it87_write_value(data, reg, data->temp[nr][index]);
1223         mutex_unlock(&data->update_lock);
1224         return count;
1225 }
1226
1227 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1228 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1229                             0, 1);
1230 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1231                             0, 2);
1232 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1233                             set_temp, 0, 3);
1234 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1235 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1236                             1, 1);
1237 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1238                             1, 2);
1239 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1240                             set_temp, 1, 3);
1241 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1242 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1243                             2, 1);
1244 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1245                             2, 2);
1246 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1247                             set_temp, 2, 3);
1248 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1249 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1250                             3, 1);
1251 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1252                             3, 2);
1253 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1254                             set_temp, 3, 3);
1255 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1256 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1257                             4, 1);
1258 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1259                             4, 2);
1260 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1261                             set_temp, 4, 3);
1262 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1263 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1264                             5, 1);
1265 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1266                             5, 2);
1267 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1268                             set_temp, 5, 3);
1269
1270 static int get_temp_type(struct it87_data *data, int index)
1271 {
1272         u8 reg, extra;
1273         int type = 0;
1274
1275         if (has_bank_sel(data)) {
1276                 int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
1277                 u8 src1, src2;
1278
1279                 src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
1280                 src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
1281
1282                 switch (data->type) {
1283                 case it8686:
1284                         switch (src1) {
1285                         case 0:
1286                                 if (index >= 3)
1287                                         return 4;
1288                                 break;
1289                         case 1:
1290                                 if (index == 1 || index == 2 ||
1291                                           index == 4 || index == 5)
1292                                         return 6;
1293                                 break;
1294                         case 2:
1295                                 if (index == 2 || index == 6)
1296                                         return 5;
1297                                 break;
1298                         default:
1299                                 break;
1300                         }
1301                         break;
1302                 case it8625:
1303                         if (index < 3)
1304                                 break;
1305                 case it8655:
1306                 case it8665:
1307                         if (src1 < 3) {
1308                                 index = src1;
1309                                 break;
1310                         }
1311                         switch(src1) {
1312                         case 3:
1313                                 type = (src2 & BIT(index)) ? 6 : 5;
1314                                 break;
1315                         case 4 ... 8:
1316                                 type = (src2 & BIT(index)) ? 4 : 6;
1317                                 break;
1318                         case 9:
1319                                 type = (src2 & BIT(index)) ? 5 : 0;
1320                                 break;
1321                         default:
1322                                 break;
1323                         }
1324                         return type;
1325                 default:
1326                         return 0;
1327                 }
1328         }
1329         if (index >= 3)
1330                 return 0;
1331
1332         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1333         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1334
1335         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1336             (has_temp_old_peci(data, index) && (extra & 0x80)))
1337                 type = 6;               /* Intel PECI */
1338         if (reg & BIT(index))
1339                 type = 3;               /* thermal diode */
1340         else if (reg & BIT(index + 3))
1341                 type = 4;               /* thermistor */
1342
1343         return type;
1344 }
1345
1346 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1347                               char *buf)
1348 {
1349         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1350         struct it87_data *data = it87_update_device(dev);
1351         int type = get_temp_type(data, sensor_attr->index);
1352
1353         return sprintf(buf, "%d\n", type);
1354 }
1355
1356 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1357                              const char *buf, size_t count)
1358 {
1359         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1360         int nr = sensor_attr->index;
1361
1362         struct it87_data *data = dev_get_drvdata(dev);
1363         long val;
1364         u8 reg, extra;
1365
1366         if (kstrtol(buf, 10, &val) < 0)
1367                 return -EINVAL;
1368
1369         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1370         reg &= ~(1 << nr);
1371         reg &= ~(8 << nr);
1372         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1373                 reg &= 0x3f;
1374         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1375         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1376                 extra &= 0x7f;
1377         if (val == 2) { /* backwards compatibility */
1378                 dev_warn(dev,
1379                          "Sensor type 2 is deprecated, please use 4 instead\n");
1380                 val = 4;
1381         }
1382         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1383         if (val == 3)
1384                 reg |= 1 << nr;
1385         else if (val == 4)
1386                 reg |= 8 << nr;
1387         else if (has_temp_peci(data, nr) && val == 6)
1388                 reg |= (nr + 1) << 6;
1389         else if (has_temp_old_peci(data, nr) && val == 6)
1390                 extra |= 0x80;
1391         else if (val != 0)
1392                 return -EINVAL;
1393
1394         mutex_lock(&data->update_lock);
1395         data->sensor = reg;
1396         data->extra = extra;
1397         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1398         if (has_temp_old_peci(data, nr))
1399                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1400         data->valid = 0;        /* Force cache refresh */
1401         mutex_unlock(&data->update_lock);
1402         return count;
1403 }
1404
1405 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1406                           set_temp_type, 0);
1407 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1408                           set_temp_type, 1);
1409 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1410                           set_temp_type, 2);
1411 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1412                           set_temp_type, 3);
1413 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1414                           set_temp_type, 4);
1415 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1416                           set_temp_type, 5);
1417
1418 /* 6 Fans */
1419
1420 static int pwm_mode(const struct it87_data *data, int nr)
1421 {
1422         if (has_fanctl_onoff(data) && nr < 3 &&
1423             !(data->fan_main_ctrl & BIT(nr)))
1424                 return 0;                               /* Full speed */
1425         if (data->pwm_ctrl[nr] & 0x80)
1426                 return 2;                               /* Automatic mode */
1427         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1428             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1429                 return 0;                       /* Full speed */
1430
1431         return 1;                               /* Manual mode */
1432 }
1433
1434 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1435                         char *buf)
1436 {
1437         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1438         int nr = sattr->nr;
1439         int index = sattr->index;
1440         int speed;
1441         struct it87_data *data = it87_update_device(dev);
1442
1443         speed = has_16bit_fans(data) ?
1444                 FAN16_FROM_REG(data->fan[nr][index]) :
1445                 FAN_FROM_REG(data->fan[nr][index],
1446                              DIV_FROM_REG(data->fan_div[nr]));
1447         return sprintf(buf, "%d\n", speed);
1448 }
1449
1450 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1451                             char *buf)
1452 {
1453         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1454         struct it87_data *data = it87_update_device(dev);
1455         int nr = sensor_attr->index;
1456
1457         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1458 }
1459
1460 static ssize_t show_pwm_enable(struct device *dev,
1461                                struct device_attribute *attr, char *buf)
1462 {
1463         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1464         struct it87_data *data = it87_update_device(dev);
1465         int nr = sensor_attr->index;
1466
1467         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1468 }
1469
1470 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1471                         char *buf)
1472 {
1473         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1474         struct it87_data *data = it87_update_device(dev);
1475         int nr = sensor_attr->index;
1476
1477         return sprintf(buf, "%d\n",
1478                        pwm_from_reg(data, data->pwm_duty[nr]));
1479 }
1480
1481 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1482                              char *buf)
1483 {
1484         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1485         struct it87_data *data = it87_update_device(dev);
1486         int nr = sensor_attr->index;
1487         unsigned int freq;
1488         int index;
1489
1490         if (has_pwm_freq2(data) && nr == 1)
1491                 index = (data->extra >> 4) & 0x07;
1492         else
1493                 index = (data->fan_ctl >> 4) & 0x07;
1494
1495         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1496
1497         return sprintf(buf, "%u\n", freq);
1498 }
1499
1500 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1501                        const char *buf, size_t count)
1502 {
1503         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1504         int nr = sattr->nr;
1505         int index = sattr->index;
1506
1507         struct it87_data *data = dev_get_drvdata(dev);
1508         long val;
1509         u8 reg;
1510
1511         if (kstrtol(buf, 10, &val) < 0)
1512                 return -EINVAL;
1513
1514         mutex_lock(&data->update_lock);
1515
1516         if (has_16bit_fans(data)) {
1517                 data->fan[nr][index] = FAN16_TO_REG(val);
1518                 it87_write_value(data, data->REG_FAN_MIN[nr],
1519                                  data->fan[nr][index] & 0xff);
1520                 it87_write_value(data, data->REG_FANX_MIN[nr],
1521                                  data->fan[nr][index] >> 8);
1522         } else {
1523                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1524                 switch (nr) {
1525                 case 0:
1526                         data->fan_div[nr] = reg & 0x07;
1527                         break;
1528                 case 1:
1529                         data->fan_div[nr] = (reg >> 3) & 0x07;
1530                         break;
1531                 case 2:
1532                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1533                         break;
1534                 }
1535                 data->fan[nr][index] =
1536                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1537                 it87_write_value(data, data->REG_FAN_MIN[nr],
1538                                  data->fan[nr][index]);
1539         }
1540
1541         mutex_unlock(&data->update_lock);
1542         return count;
1543 }
1544
1545 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1546                            const char *buf, size_t count)
1547 {
1548         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1549         struct it87_data *data = dev_get_drvdata(dev);
1550         int nr = sensor_attr->index;
1551         unsigned long val;
1552         int min;
1553         u8 old;
1554
1555         if (kstrtoul(buf, 10, &val) < 0)
1556                 return -EINVAL;
1557
1558         mutex_lock(&data->update_lock);
1559         old = it87_read_value(data, IT87_REG_FAN_DIV);
1560
1561         /* Save fan min limit */
1562         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1563
1564         switch (nr) {
1565         case 0:
1566         case 1:
1567                 data->fan_div[nr] = DIV_TO_REG(val);
1568                 break;
1569         case 2:
1570                 if (val < 8)
1571                         data->fan_div[nr] = 1;
1572                 else
1573                         data->fan_div[nr] = 3;
1574         }
1575         val = old & 0x80;
1576         val |= (data->fan_div[0] & 0x07);
1577         val |= (data->fan_div[1] & 0x07) << 3;
1578         if (data->fan_div[2] == 3)
1579                 val |= 0x1 << 6;
1580         it87_write_value(data, IT87_REG_FAN_DIV, val);
1581
1582         /* Restore fan min limit */
1583         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1584         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1585
1586         mutex_unlock(&data->update_lock);
1587         return count;
1588 }
1589
1590 /* Returns 0 if OK, -EINVAL otherwise */
1591 static int check_trip_points(struct device *dev, int nr)
1592 {
1593         const struct it87_data *data = dev_get_drvdata(dev);
1594         int i, err = 0;
1595
1596         if (has_old_autopwm(data)) {
1597                 for (i = 0; i < 3; i++) {
1598                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1599                                 err = -EINVAL;
1600                 }
1601                 for (i = 0; i < 2; i++) {
1602                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1603                                 err = -EINVAL;
1604                 }
1605         } else if (has_newer_autopwm(data)) {
1606                 for (i = 1; i < 3; i++) {
1607                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1608                                 err = -EINVAL;
1609                 }
1610         }
1611
1612         if (err) {
1613                 dev_err(dev,
1614                         "Inconsistent trip points, not switching to automatic mode\n");
1615                 dev_err(dev, "Adjust the trip points and try again\n");
1616         }
1617         return err;
1618 }
1619
1620 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1621                               const char *buf, size_t count)
1622 {
1623         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1624         struct it87_data *data = dev_get_drvdata(dev);
1625         int nr = sensor_attr->index;
1626         long val;
1627
1628         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1629                 return -EINVAL;
1630
1631         /* Check trip points before switching to automatic mode */
1632         if (val == 2) {
1633                 if (check_trip_points(dev, nr) < 0)
1634                         return -EINVAL;
1635         }
1636
1637         mutex_lock(&data->update_lock);
1638
1639         if (val == 0) {
1640                 if (nr < 3 && has_fanctl_onoff(data)) {
1641                         int tmp;
1642                         /* make sure the fan is on when in on/off mode */
1643                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1644                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1645                         /* set on/off mode */
1646                         data->fan_main_ctrl &= ~BIT(nr);
1647                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1648                                          data->fan_main_ctrl);
1649                 } else {
1650                         u8 ctrl;
1651
1652                         /* No on/off mode, set maximum pwm value */
1653                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1654                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1655                                          data->pwm_duty[nr]);
1656                         /* and set manual mode */
1657                         if (has_newer_autopwm(data)) {
1658                                 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1659                                         data->pwm_temp_map[nr];
1660                         } else {
1661                                 ctrl = data->pwm_duty[nr];
1662                         }
1663                         data->pwm_ctrl[nr] = ctrl;
1664                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1665                 }
1666         } else {
1667                 u8 ctrl;
1668
1669                 if (has_newer_autopwm(data)) {
1670                         ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1671                                 data->pwm_temp_map[nr];
1672                         if (val != 1)
1673                                 ctrl |= 0x80;
1674                 } else {
1675                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1676                 }
1677                 data->pwm_ctrl[nr] = ctrl;
1678                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1679
1680                 if (has_fanctl_onoff(data) && nr < 3) {
1681                         /* set SmartGuardian mode */
1682                         data->fan_main_ctrl |= BIT(nr);
1683                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1684                                          data->fan_main_ctrl);
1685                 }
1686         }
1687
1688         mutex_unlock(&data->update_lock);
1689         return count;
1690 }
1691
1692 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1693                        const char *buf, size_t count)
1694 {
1695         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1696         struct it87_data *data = dev_get_drvdata(dev);
1697         int nr = sensor_attr->index;
1698         long val;
1699
1700         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1701                 return -EINVAL;
1702
1703         mutex_lock(&data->update_lock);
1704         it87_update_pwm_ctrl(data, nr);
1705         if (has_newer_autopwm(data)) {
1706                 /*
1707                  * If we are in automatic mode, the PWM duty cycle register
1708                  * is read-only so we can't write the value.
1709                  */
1710                 if (data->pwm_ctrl[nr] & 0x80) {
1711                         mutex_unlock(&data->update_lock);
1712                         return -EBUSY;
1713                 }
1714                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1715                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1716                                  data->pwm_duty[nr]);
1717         } else {
1718                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1719                 /*
1720                  * If we are in manual mode, write the duty cycle immediately;
1721                  * otherwise, just store it for later use.
1722                  */
1723                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1724                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1725                         it87_write_value(data, data->REG_PWM[nr],
1726                                          data->pwm_ctrl[nr]);
1727                 }
1728         }
1729         mutex_unlock(&data->update_lock);
1730         return count;
1731 }
1732
1733 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1734                             const char *buf, size_t count)
1735 {
1736         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1737         struct it87_data *data = dev_get_drvdata(dev);
1738         int nr = sensor_attr->index;
1739         unsigned long val;
1740         int i;
1741
1742         if (kstrtoul(buf, 10, &val) < 0)
1743                 return -EINVAL;
1744
1745         val = clamp_val(val, 0, 1000000);
1746         val *= has_newer_autopwm(data) ? 256 : 128;
1747
1748         /* Search for the nearest available frequency */
1749         for (i = 0; i < 7; i++) {
1750                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1751                         break;
1752         }
1753
1754         mutex_lock(&data->update_lock);
1755         if (nr == 0) {
1756                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1757                 data->fan_ctl |= i << 4;
1758                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1759         } else {
1760                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1761                 data->extra |= i << 4;
1762                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1763         }
1764         mutex_unlock(&data->update_lock);
1765
1766         return count;
1767 }
1768
1769 static ssize_t show_pwm_temp_map(struct device *dev,
1770                                  struct device_attribute *attr, char *buf)
1771 {
1772         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1773         struct it87_data *data = it87_update_device(dev);
1774         int nr = sensor_attr->index;
1775         int map;
1776
1777         map = data->pwm_temp_map[nr];
1778         if (has_new_tempmap(data)) {
1779                 map >>= 3;
1780                 if (map >= 6)
1781                         map = 0;        /* Should never happen */
1782         } else {
1783                 if (map >= 3)
1784                         map = 0;        /* Should never happen */
1785                 if (nr >= 3)            /* pwm channels 3..6 map to temp4..6 */
1786                         map += 3;
1787         }
1788
1789         return sprintf(buf, "%d\n", (int)BIT(map));
1790 }
1791
1792 static ssize_t set_pwm_temp_map(struct device *dev,
1793                                 struct device_attribute *attr, const char *buf,
1794                                 size_t count)
1795 {
1796         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1797         struct it87_data *data = dev_get_drvdata(dev);
1798         int nr = sensor_attr->index;
1799         long val;
1800         u8 reg;
1801
1802         if (kstrtol(buf, 10, &val) < 0)
1803                 return -EINVAL;
1804
1805         if (nr >= 3 && !has_new_tempmap(data))
1806                 val -= 3;
1807
1808         switch (val) {
1809         case BIT(0):
1810                 reg = 0x00;
1811                 break;
1812         case BIT(1):
1813                 reg = 0x01;
1814                 break;
1815         case BIT(2):
1816                 reg = 0x02;
1817                 break;
1818         case BIT(3):
1819                 reg = 0x03;
1820                 break;
1821         case BIT(4):
1822                 reg = 0x04;
1823                 break;
1824         case BIT(5):
1825                 reg = 0x05;
1826                 break;
1827         case BIT(6):
1828                 reg = 0x06;
1829                 break;
1830         default:
1831                 return -EINVAL;
1832         }
1833
1834         if (has_new_tempmap(data))
1835                 reg <<= 3;
1836         else if (reg > 0x02)
1837                 return -EINVAL;
1838
1839         mutex_lock(&data->update_lock);
1840         it87_update_pwm_ctrl(data, nr);
1841         data->pwm_temp_map[nr] = reg;
1842         /*
1843          * If we are in automatic mode, write the temp mapping immediately;
1844          * otherwise, just store it for later use.
1845          */
1846         if (data->pwm_ctrl[nr] & 0x80) {
1847                 u8 mask = has_new_tempmap(data) ? 0xc7 : 0xfc;
1848
1849                 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & mask) |
1850                                                 data->pwm_temp_map[nr];
1851                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1852         }
1853         mutex_unlock(&data->update_lock);
1854         return count;
1855 }
1856
1857 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1858                              char *buf)
1859 {
1860         struct it87_data *data = it87_update_device(dev);
1861         struct sensor_device_attribute_2 *sensor_attr =
1862                         to_sensor_dev_attr_2(attr);
1863         int nr = sensor_attr->nr;
1864         int point = sensor_attr->index;
1865
1866         return sprintf(buf, "%d\n",
1867                        pwm_from_reg(data, data->auto_pwm[nr][point]));
1868 }
1869
1870 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1871                             const char *buf, size_t count)
1872 {
1873         struct it87_data *data = dev_get_drvdata(dev);
1874         struct sensor_device_attribute_2 *sensor_attr =
1875                         to_sensor_dev_attr_2(attr);
1876         int nr = sensor_attr->nr;
1877         int point = sensor_attr->index;
1878         int regaddr;
1879         long val;
1880
1881         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1882                 return -EINVAL;
1883
1884         mutex_lock(&data->update_lock);
1885         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1886         if (has_newer_autopwm(data))
1887                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1888         else
1889                 regaddr = IT87_REG_AUTO_PWM(nr, point);
1890         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1891         mutex_unlock(&data->update_lock);
1892         return count;
1893 }
1894
1895 static ssize_t show_auto_pwm_slope(struct device *dev,
1896                                    struct device_attribute *attr, char *buf)
1897 {
1898         struct it87_data *data = it87_update_device(dev);
1899         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1900         int nr = sensor_attr->index;
1901
1902         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1903 }
1904
1905 static ssize_t set_auto_pwm_slope(struct device *dev,
1906                                   struct device_attribute *attr,
1907                                   const char *buf, size_t count)
1908 {
1909         struct it87_data *data = dev_get_drvdata(dev);
1910         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1911         int nr = sensor_attr->index;
1912         unsigned long val;
1913
1914         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1915                 return -EINVAL;
1916
1917         mutex_lock(&data->update_lock);
1918         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1919         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1920                          data->auto_pwm[nr][1]);
1921         mutex_unlock(&data->update_lock);
1922         return count;
1923 }
1924
1925 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1926                               char *buf)
1927 {
1928         struct it87_data *data = it87_update_device(dev);
1929         struct sensor_device_attribute_2 *sensor_attr =
1930                         to_sensor_dev_attr_2(attr);
1931         int nr = sensor_attr->nr;
1932         int point = sensor_attr->index;
1933         int reg;
1934
1935         if (has_old_autopwm(data) || point)
1936                 reg = data->auto_temp[nr][point];
1937         else
1938                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1939
1940         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1941 }
1942
1943 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1944                              const char *buf, size_t count)
1945 {
1946         struct it87_data *data = dev_get_drvdata(dev);
1947         struct sensor_device_attribute_2 *sensor_attr =
1948                         to_sensor_dev_attr_2(attr);
1949         int nr = sensor_attr->nr;
1950         int point = sensor_attr->index;
1951         long val;
1952         int reg;
1953
1954         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1955                 return -EINVAL;
1956
1957         mutex_lock(&data->update_lock);
1958         if (has_newer_autopwm(data) && !point) {
1959                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1960                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1961                 data->auto_temp[nr][0] = reg;
1962                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1963         } else {
1964                 reg = TEMP_TO_REG(val);
1965                 data->auto_temp[nr][point] = reg;
1966                 if (has_newer_autopwm(data))
1967                         point--;
1968                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1969         }
1970         mutex_unlock(&data->update_lock);
1971         return count;
1972 }
1973
1974 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1975 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1976                             0, 1);
1977 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1978                           set_fan_div, 0);
1979
1980 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1981 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1982                             1, 1);
1983 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1984                           set_fan_div, 1);
1985
1986 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1987 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1988                             2, 1);
1989 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1990                           set_fan_div, 2);
1991
1992 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1993 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1994                             3, 1);
1995
1996 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1997 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1998                             4, 1);
1999
2000 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2001 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2002                             5, 1);
2003
2004 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2005                           show_pwm_enable, set_pwm_enable, 0);
2006 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2007 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2008                           set_pwm_freq, 0);
2009 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2010                           show_pwm_temp_map, set_pwm_temp_map, 0);
2011 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2012                             show_auto_pwm, set_auto_pwm, 0, 0);
2013 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2014                             show_auto_pwm, set_auto_pwm, 0, 1);
2015 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2016                             show_auto_pwm, set_auto_pwm, 0, 2);
2017 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2018                             show_auto_pwm, NULL, 0, 3);
2019 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2020                             show_auto_temp, set_auto_temp, 0, 1);
2021 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2022                             show_auto_temp, set_auto_temp, 0, 0);
2023 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2024                             show_auto_temp, set_auto_temp, 0, 2);
2025 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2026                             show_auto_temp, set_auto_temp, 0, 3);
2027 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2028                             show_auto_temp, set_auto_temp, 0, 4);
2029 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2030                             show_auto_pwm, set_auto_pwm, 0, 0);
2031 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2032                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2033
2034 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2035                           show_pwm_enable, set_pwm_enable, 1);
2036 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2037 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2038 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2039                           show_pwm_temp_map, set_pwm_temp_map, 1);
2040 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2041                             show_auto_pwm, set_auto_pwm, 1, 0);
2042 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2043                             show_auto_pwm, set_auto_pwm, 1, 1);
2044 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2045                             show_auto_pwm, set_auto_pwm, 1, 2);
2046 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2047                             show_auto_pwm, NULL, 1, 3);
2048 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2049                             show_auto_temp, set_auto_temp, 1, 1);
2050 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2051                             show_auto_temp, set_auto_temp, 1, 0);
2052 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2053                             show_auto_temp, set_auto_temp, 1, 2);
2054 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2055                             show_auto_temp, set_auto_temp, 1, 3);
2056 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2057                             show_auto_temp, set_auto_temp, 1, 4);
2058 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2059                             show_auto_pwm, set_auto_pwm, 1, 0);
2060 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2061                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2062
2063 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2064                           show_pwm_enable, set_pwm_enable, 2);
2065 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2066 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2067 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2068                           show_pwm_temp_map, set_pwm_temp_map, 2);
2069 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2070                             show_auto_pwm, set_auto_pwm, 2, 0);
2071 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2072                             show_auto_pwm, set_auto_pwm, 2, 1);
2073 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2074                             show_auto_pwm, set_auto_pwm, 2, 2);
2075 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2076                             show_auto_pwm, NULL, 2, 3);
2077 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2078                             show_auto_temp, set_auto_temp, 2, 1);
2079 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2080                             show_auto_temp, set_auto_temp, 2, 0);
2081 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2082                             show_auto_temp, set_auto_temp, 2, 2);
2083 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2084                             show_auto_temp, set_auto_temp, 2, 3);
2085 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2086                             show_auto_temp, set_auto_temp, 2, 4);
2087 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2088                             show_auto_pwm, set_auto_pwm, 2, 0);
2089 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2090                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2091
2092 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2093                           show_pwm_enable, set_pwm_enable, 3);
2094 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2095 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2096 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2097                           show_pwm_temp_map, set_pwm_temp_map, 3);
2098 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2099                             show_auto_temp, set_auto_temp, 2, 1);
2100 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2101                             show_auto_temp, set_auto_temp, 2, 0);
2102 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2103                             show_auto_temp, set_auto_temp, 2, 2);
2104 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2105                             show_auto_temp, set_auto_temp, 2, 3);
2106 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2107                             show_auto_pwm, set_auto_pwm, 3, 0);
2108 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2109                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2110
2111 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2112                           show_pwm_enable, set_pwm_enable, 4);
2113 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2114 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2115 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2116                           show_pwm_temp_map, set_pwm_temp_map, 4);
2117 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2118                             show_auto_temp, set_auto_temp, 2, 1);
2119 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2120                             show_auto_temp, set_auto_temp, 2, 0);
2121 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2122                             show_auto_temp, set_auto_temp, 2, 2);
2123 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2124                             show_auto_temp, set_auto_temp, 2, 3);
2125 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2126                             show_auto_pwm, set_auto_pwm, 4, 0);
2127 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2128                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2129
2130 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2131                           show_pwm_enable, set_pwm_enable, 5);
2132 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2133 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2134 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2135                           show_pwm_temp_map, set_pwm_temp_map, 5);
2136 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2137                             show_auto_temp, set_auto_temp, 2, 1);
2138 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2139                             show_auto_temp, set_auto_temp, 2, 0);
2140 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2141                             show_auto_temp, set_auto_temp, 2, 2);
2142 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2143                             show_auto_temp, set_auto_temp, 2, 3);
2144 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2145                             show_auto_pwm, set_auto_pwm, 5, 0);
2146 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2147                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2148
2149 /* Alarms */
2150 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2151                            char *buf)
2152 {
2153         struct it87_data *data = it87_update_device(dev);
2154
2155         return sprintf(buf, "%u\n", data->alarms);
2156 }
2157 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2158
2159 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2160                           char *buf)
2161 {
2162         struct it87_data *data = it87_update_device(dev);
2163         int bitnr = to_sensor_dev_attr(attr)->index;
2164
2165         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2166 }
2167
2168 static ssize_t clear_intrusion(struct device *dev,
2169                                struct device_attribute *attr, const char *buf,
2170                                size_t count)
2171 {
2172         struct it87_data *data = dev_get_drvdata(dev);
2173         int config;
2174         long val;
2175
2176         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2177                 return -EINVAL;
2178
2179         mutex_lock(&data->update_lock);
2180         config = it87_read_value(data, IT87_REG_CONFIG);
2181         if (config < 0) {
2182                 count = config;
2183         } else {
2184                 config |= BIT(5);
2185                 it87_write_value(data, IT87_REG_CONFIG, config);
2186                 /* Invalidate cache to force re-read */
2187                 data->valid = 0;
2188         }
2189         mutex_unlock(&data->update_lock);
2190
2191         return count;
2192 }
2193
2194 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2195 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2196 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2197 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2198 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2199 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2200 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2201 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2202 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2203 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2204 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2205 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2206 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2207 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2208 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2209 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2210 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2211 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2212 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2213 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2214 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2215                           show_alarm, clear_intrusion, 4);
2216
2217 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2218                          char *buf)
2219 {
2220         struct it87_data *data = it87_update_device(dev);
2221         int bitnr = to_sensor_dev_attr(attr)->index;
2222
2223         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2224 }
2225
2226 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2227                         const char *buf, size_t count)
2228 {
2229         int bitnr = to_sensor_dev_attr(attr)->index;
2230         struct it87_data *data = dev_get_drvdata(dev);
2231         long val;
2232
2233         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2234                 return -EINVAL;
2235
2236         mutex_lock(&data->update_lock);
2237         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2238         if (val)
2239                 data->beeps |= BIT(bitnr);
2240         else
2241                 data->beeps &= ~BIT(bitnr);
2242         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2243         mutex_unlock(&data->update_lock);
2244         return count;
2245 }
2246
2247 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2248                           show_beep, set_beep, 1);
2249 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2250 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2251 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2252 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2253 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2254 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2255 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2256 /* fanX_beep writability is set later */
2257 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2258 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2259 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2260 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2261 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2262 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2263 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2264                           show_beep, set_beep, 2);
2265 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2266 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2267 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2268 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2269 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2270
2271 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2272                             char *buf)
2273 {
2274         struct it87_data *data = dev_get_drvdata(dev);
2275
2276         return sprintf(buf, "%u\n", data->vrm);
2277 }
2278
2279 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2280                              const char *buf, size_t count)
2281 {
2282         struct it87_data *data = dev_get_drvdata(dev);
2283         unsigned long val;
2284
2285         if (kstrtoul(buf, 10, &val) < 0)
2286                 return -EINVAL;
2287
2288         data->vrm = val;
2289
2290         return count;
2291 }
2292 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2293
2294 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2295                             char *buf)
2296 {
2297         struct it87_data *data = it87_update_device(dev);
2298
2299         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2300 }
2301 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2302
2303 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2304                           char *buf)
2305 {
2306         static const char * const labels[] = {
2307                 "+5V",
2308                 "5VSB",
2309                 "Vbat",
2310                 "AVCC",
2311         };
2312         static const char * const labels_it8721[] = {
2313                 "+3.3V",
2314                 "3VSB",
2315                 "Vbat",
2316                 "+3.3V",
2317         };
2318         struct it87_data *data = dev_get_drvdata(dev);
2319         int nr = to_sensor_dev_attr(attr)->index;
2320         const char *label;
2321
2322         if (has_vin3_5v(data) && nr == 0)
2323                 label = labels[0];
2324         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2325                  has_11mv_adc(data))
2326                 label = labels_it8721[nr];
2327         else
2328                 label = labels[nr];
2329
2330         return sprintf(buf, "%s\n", label);
2331 }
2332 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2333 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2334 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2335 /* AVCC3 */
2336 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2337
2338 static umode_t it87_in_is_visible(struct kobject *kobj,
2339                                   struct attribute *attr, int index)
2340 {
2341         struct device *dev = container_of(kobj, struct device, kobj);
2342         struct it87_data *data = dev_get_drvdata(dev);
2343         int i = index / 5;      /* voltage index */
2344         int a = index % 5;      /* attribute index */
2345
2346         if (index >= 40) {      /* in8 and higher only have input attributes */
2347                 i = index - 40 + 8;
2348                 a = 0;
2349         }
2350
2351         if (!(data->has_in & BIT(i)))
2352                 return 0;
2353
2354         if (a == 4 && !data->has_beep)
2355                 return 0;
2356
2357         return attr->mode;
2358 }
2359
2360 static struct attribute *it87_attributes_in[] = {
2361         &sensor_dev_attr_in0_input.dev_attr.attr,
2362         &sensor_dev_attr_in0_min.dev_attr.attr,
2363         &sensor_dev_attr_in0_max.dev_attr.attr,
2364         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2365         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2366
2367         &sensor_dev_attr_in1_input.dev_attr.attr,
2368         &sensor_dev_attr_in1_min.dev_attr.attr,
2369         &sensor_dev_attr_in1_max.dev_attr.attr,
2370         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2371         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2372
2373         &sensor_dev_attr_in2_input.dev_attr.attr,
2374         &sensor_dev_attr_in2_min.dev_attr.attr,
2375         &sensor_dev_attr_in2_max.dev_attr.attr,
2376         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2377         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2378
2379         &sensor_dev_attr_in3_input.dev_attr.attr,
2380         &sensor_dev_attr_in3_min.dev_attr.attr,
2381         &sensor_dev_attr_in3_max.dev_attr.attr,
2382         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2383         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2384
2385         &sensor_dev_attr_in4_input.dev_attr.attr,
2386         &sensor_dev_attr_in4_min.dev_attr.attr,
2387         &sensor_dev_attr_in4_max.dev_attr.attr,
2388         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2389         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2390
2391         &sensor_dev_attr_in5_input.dev_attr.attr,
2392         &sensor_dev_attr_in5_min.dev_attr.attr,
2393         &sensor_dev_attr_in5_max.dev_attr.attr,
2394         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2395         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2396
2397         &sensor_dev_attr_in6_input.dev_attr.attr,
2398         &sensor_dev_attr_in6_min.dev_attr.attr,
2399         &sensor_dev_attr_in6_max.dev_attr.attr,
2400         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2401         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2402
2403         &sensor_dev_attr_in7_input.dev_attr.attr,
2404         &sensor_dev_attr_in7_min.dev_attr.attr,
2405         &sensor_dev_attr_in7_max.dev_attr.attr,
2406         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2407         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2408
2409         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2410         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2411         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2412         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2413         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2414         NULL
2415 };
2416
2417 static const struct attribute_group it87_group_in = {
2418         .attrs = it87_attributes_in,
2419         .is_visible = it87_in_is_visible,
2420 };
2421
2422 static umode_t it87_temp_is_visible(struct kobject *kobj,
2423                                     struct attribute *attr, int index)
2424 {
2425         struct device *dev = container_of(kobj, struct device, kobj);
2426         struct it87_data *data = dev_get_drvdata(dev);
2427         int i = index / 7;      /* temperature index */
2428         int a = index % 7;      /* attribute index */
2429
2430         if (!(data->has_temp & BIT(i)))
2431                 return 0;
2432
2433         if (a && i >= data->num_temp_limit)
2434                 return 0;
2435
2436         if (a == 3) {
2437                 int type = get_temp_type(data, i);
2438
2439                 if (type == 0)
2440                         return 0;
2441                 if (has_bank_sel(data))
2442                         return 0444;
2443                 return attr->mode;
2444         }
2445
2446         if (a == 5 && !has_temp_offset(data))
2447                 return 0;
2448
2449         if (a == 6 && !data->has_beep)
2450                 return 0;
2451
2452         return attr->mode;
2453 }
2454
2455 static struct attribute *it87_attributes_temp[] = {
2456         &sensor_dev_attr_temp1_input.dev_attr.attr,
2457         &sensor_dev_attr_temp1_max.dev_attr.attr,
2458         &sensor_dev_attr_temp1_min.dev_attr.attr,
2459         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2460         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2461         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2462         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2463
2464         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2465         &sensor_dev_attr_temp2_max.dev_attr.attr,
2466         &sensor_dev_attr_temp2_min.dev_attr.attr,
2467         &sensor_dev_attr_temp2_type.dev_attr.attr,
2468         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2469         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2470         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2471
2472         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2473         &sensor_dev_attr_temp3_max.dev_attr.attr,
2474         &sensor_dev_attr_temp3_min.dev_attr.attr,
2475         &sensor_dev_attr_temp3_type.dev_attr.attr,
2476         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2477         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2478         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2479
2480         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2481         &sensor_dev_attr_temp4_max.dev_attr.attr,
2482         &sensor_dev_attr_temp4_min.dev_attr.attr,
2483         &sensor_dev_attr_temp4_type.dev_attr.attr,
2484         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2485         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2486         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2487
2488         &sensor_dev_attr_temp5_input.dev_attr.attr,
2489         &sensor_dev_attr_temp5_max.dev_attr.attr,
2490         &sensor_dev_attr_temp5_min.dev_attr.attr,
2491         &sensor_dev_attr_temp5_type.dev_attr.attr,
2492         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2493         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2494         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2495
2496         &sensor_dev_attr_temp6_input.dev_attr.attr,
2497         &sensor_dev_attr_temp6_max.dev_attr.attr,
2498         &sensor_dev_attr_temp6_min.dev_attr.attr,
2499         &sensor_dev_attr_temp6_type.dev_attr.attr,
2500         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2501         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2502         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2503         NULL
2504 };
2505
2506 static const struct attribute_group it87_group_temp = {
2507         .attrs = it87_attributes_temp,
2508         .is_visible = it87_temp_is_visible,
2509 };
2510
2511 static umode_t it87_is_visible(struct kobject *kobj,
2512                                struct attribute *attr, int index)
2513 {
2514         struct device *dev = container_of(kobj, struct device, kobj);
2515         struct it87_data *data = dev_get_drvdata(dev);
2516
2517         if ((index == 2 || index == 3) && !data->has_vid)
2518                 return 0;
2519
2520         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2521                 return 0;
2522
2523         return attr->mode;
2524 }
2525
2526 static struct attribute *it87_attributes[] = {
2527         &dev_attr_alarms.attr,
2528         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2529         &dev_attr_vrm.attr,                             /* 2 */
2530         &dev_attr_cpu0_vid.attr,                        /* 3 */
2531         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2532         &sensor_dev_attr_in7_label.dev_attr.attr,
2533         &sensor_dev_attr_in8_label.dev_attr.attr,
2534         &sensor_dev_attr_in9_label.dev_attr.attr,
2535         NULL
2536 };
2537
2538 static const struct attribute_group it87_group = {
2539         .attrs = it87_attributes,
2540         .is_visible = it87_is_visible,
2541 };
2542
2543 static umode_t it87_fan_is_visible(struct kobject *kobj,
2544                                    struct attribute *attr, int index)
2545 {
2546         struct device *dev = container_of(kobj, struct device, kobj);
2547         struct it87_data *data = dev_get_drvdata(dev);
2548         int i = index / 5;      /* fan index */
2549         int a = index % 5;      /* attribute index */
2550
2551         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2552                 i = (index - 15) / 4 + 3;
2553                 a = (index - 15) % 4;
2554         }
2555
2556         if (!(data->has_fan & BIT(i)))
2557                 return 0;
2558
2559         if (a == 3) {                           /* beep */
2560                 if (!data->has_beep)
2561                         return 0;
2562                 /* first fan beep attribute is writable */
2563                 if (i == __ffs(data->has_fan))
2564                         return attr->mode | S_IWUSR;
2565         }
2566
2567         if (a == 4 && has_16bit_fans(data))     /* divisor */
2568                 return 0;
2569
2570         return attr->mode;
2571 }
2572
2573 static struct attribute *it87_attributes_fan[] = {
2574         &sensor_dev_attr_fan1_input.dev_attr.attr,
2575         &sensor_dev_attr_fan1_min.dev_attr.attr,
2576         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2577         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2578         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2579
2580         &sensor_dev_attr_fan2_input.dev_attr.attr,
2581         &sensor_dev_attr_fan2_min.dev_attr.attr,
2582         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2583         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2584         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2585
2586         &sensor_dev_attr_fan3_input.dev_attr.attr,
2587         &sensor_dev_attr_fan3_min.dev_attr.attr,
2588         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2589         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2590         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2591
2592         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2593         &sensor_dev_attr_fan4_min.dev_attr.attr,
2594         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2595         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2596
2597         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2598         &sensor_dev_attr_fan5_min.dev_attr.attr,
2599         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2600         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2601
2602         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2603         &sensor_dev_attr_fan6_min.dev_attr.attr,
2604         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2605         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2606         NULL
2607 };
2608
2609 static const struct attribute_group it87_group_fan = {
2610         .attrs = it87_attributes_fan,
2611         .is_visible = it87_fan_is_visible,
2612 };
2613
2614 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2615                                    struct attribute *attr, int index)
2616 {
2617         struct device *dev = container_of(kobj, struct device, kobj);
2618         struct it87_data *data = dev_get_drvdata(dev);
2619         int i = index / 4;      /* pwm index */
2620         int a = index % 4;      /* attribute index */
2621
2622         if (!(data->has_pwm & BIT(i)))
2623                 return 0;
2624
2625         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2626         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2627                 return attr->mode | S_IWUSR;
2628
2629         /* pwm2_freq is writable if there are two pwm frequency selects */
2630         if (has_pwm_freq2(data) && i == 1 && a == 2)
2631                 return attr->mode | S_IWUSR;
2632
2633         return attr->mode;
2634 }
2635
2636 static struct attribute *it87_attributes_pwm[] = {
2637         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2638         &sensor_dev_attr_pwm1.dev_attr.attr,
2639         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2640         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2641
2642         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2643         &sensor_dev_attr_pwm2.dev_attr.attr,
2644         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2645         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2646
2647         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2648         &sensor_dev_attr_pwm3.dev_attr.attr,
2649         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2650         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2651
2652         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2653         &sensor_dev_attr_pwm4.dev_attr.attr,
2654         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2655         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2656
2657         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2658         &sensor_dev_attr_pwm5.dev_attr.attr,
2659         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2660         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2661
2662         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2663         &sensor_dev_attr_pwm6.dev_attr.attr,
2664         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2665         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2666
2667         NULL
2668 };
2669
2670 static const struct attribute_group it87_group_pwm = {
2671         .attrs = it87_attributes_pwm,
2672         .is_visible = it87_pwm_is_visible,
2673 };
2674
2675 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2676                                         struct attribute *attr, int index)
2677 {
2678         struct device *dev = container_of(kobj, struct device, kobj);
2679         struct it87_data *data = dev_get_drvdata(dev);
2680         int i = index / 11;     /* pwm index */
2681         int a = index % 11;     /* attribute index */
2682
2683         if (index >= 33) {      /* pwm 4..6 */
2684                 i = (index - 33) / 6 + 3;
2685                 a = (index - 33) % 6 + 4;
2686         }
2687
2688         if (!(data->has_pwm & BIT(i)))
2689                 return 0;
2690
2691         if (has_newer_autopwm(data)) {
2692                 if (a < 4)      /* no auto point pwm */
2693                         return 0;
2694                 if (a == 8)     /* no auto_point4 */
2695                         return 0;
2696         }
2697         if (has_old_autopwm(data)) {
2698                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2699                         return 0;
2700         }
2701
2702         return attr->mode;
2703 }
2704
2705 static struct attribute *it87_attributes_auto_pwm[] = {
2706         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2707         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2708         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2709         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2710         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2711         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2712         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2713         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2714         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2715         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2716         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2717
2718         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2719         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2720         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2721         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2722         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2723         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2724         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2725         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2726         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2727         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2728         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2729
2730         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2731         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2732         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2733         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2734         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2735         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2736         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2737         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2738         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2739         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2740         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2741
2742         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2743         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2744         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2745         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2746         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2747         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2748
2749         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2750         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2751         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2752         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2753         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2754         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2755
2756         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2757         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2758         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2759         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2760         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2761         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2762
2763         NULL,
2764 };
2765
2766 static const struct attribute_group it87_group_auto_pwm = {
2767         .attrs = it87_attributes_auto_pwm,
2768         .is_visible = it87_auto_pwm_is_visible,
2769 };
2770
2771 /* SuperIO detection - will change isa_address if a chip is found */
2772 static int __init it87_find(int sioaddr, unsigned short *address,
2773                             struct it87_sio_data *sio_data)
2774 {
2775         int err;
2776         u16 chip_type;
2777         const struct it87_devices *config;
2778
2779         err = superio_enter(sioaddr);
2780         if (err)
2781                 return err;
2782
2783         err = -ENODEV;
2784         chip_type = superio_inw(sioaddr, DEVID);
2785         if (chip_type == 0xffff)
2786                 goto exit;
2787
2788         if (force_id)
2789                 chip_type = force_id;
2790
2791         switch (chip_type) {
2792         case IT8705F_DEVID:
2793                 sio_data->type = it87;
2794                 break;
2795         case IT8712F_DEVID:
2796                 sio_data->type = it8712;
2797                 break;
2798         case IT8716F_DEVID:
2799         case IT8726F_DEVID:
2800                 sio_data->type = it8716;
2801                 break;
2802         case IT8718F_DEVID:
2803                 sio_data->type = it8718;
2804                 break;
2805         case IT8720F_DEVID:
2806                 sio_data->type = it8720;
2807                 break;
2808         case IT8721F_DEVID:
2809                 sio_data->type = it8721;
2810                 break;
2811         case IT8728F_DEVID:
2812                 sio_data->type = it8728;
2813                 break;
2814         case IT8732F_DEVID:
2815                 sio_data->type = it8732;
2816                 break;
2817         case IT8792E_DEVID:
2818                 sio_data->type = it8792;
2819                 break;
2820         case IT8771E_DEVID:
2821                 sio_data->type = it8771;
2822                 break;
2823         case IT8772E_DEVID:
2824                 sio_data->type = it8772;
2825                 break;
2826         case IT8781F_DEVID:
2827                 sio_data->type = it8781;
2828                 break;
2829         case IT8782F_DEVID:
2830                 sio_data->type = it8782;
2831                 break;
2832         case IT8783E_DEVID:
2833                 sio_data->type = it8783;
2834                 break;
2835         case IT8786E_DEVID:
2836                 sio_data->type = it8786;
2837                 break;
2838         case IT8790E_DEVID:
2839                 sio_data->type = it8790;
2840                 break;
2841         case IT8603E_DEVID:
2842         case IT8623E_DEVID:
2843                 sio_data->type = it8603;
2844                 break;
2845         case IT8607E_DEVID:
2846                 sio_data->type = it8607;
2847                 break;
2848         case IT8613E_DEVID:
2849                 sio_data->type = it8613;
2850                 break;
2851         case IT8620E_DEVID:
2852                 sio_data->type = it8620;
2853                 break;
2854         case IT8622E_DEVID:
2855                 sio_data->type = it8622;
2856                 break;
2857         case IT8625E_DEVID:
2858                 sio_data->type = it8625;
2859                 break;
2860         case IT8628E_DEVID:
2861                 sio_data->type = it8628;
2862                 break;
2863         case IT8655E_DEVID:
2864                 sio_data->type = it8655;
2865                 break;
2866         case IT8665E_DEVID:
2867                 sio_data->type = it8665;
2868                 break;
2869         case IT8686E_DEVID:
2870                 sio_data->type = it8686;
2871                 break;
2872         case 0xffff:    /* No device at all */
2873                 goto exit;
2874         default:
2875                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2876                 goto exit;
2877         }
2878
2879         superio_select(sioaddr, PME);
2880         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2881                 pr_info("Device not activated, skipping\n");
2882                 goto exit;
2883         }
2884
2885         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2886         if (*address == 0) {
2887                 pr_info("Base address not set, skipping\n");
2888                 goto exit;
2889         }
2890
2891         err = 0;
2892         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2893         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2894                 it87_devices[sio_data->type].suffix,
2895                 *address, sio_data->revision);
2896
2897         config = &it87_devices[sio_data->type];
2898
2899         /* in7 (VSB or VCCH5V) is always internal on some chips */
2900         if (has_in7_internal(config))
2901                 sio_data->internal |= BIT(1);
2902
2903         /* in8 (Vbat) is always internal */
2904         sio_data->internal |= BIT(2);
2905
2906         /* in9 (AVCC3), always internal if supported */
2907         if (has_avcc3(config))
2908                 sio_data->internal |= BIT(3); /* in9 is AVCC */
2909         else
2910                 sio_data->skip_in |= BIT(9);
2911
2912         if (!has_four_pwm(config))
2913                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2914         else if (!has_five_pwm(config))
2915                 sio_data->skip_pwm |= BIT(4) | BIT(5);
2916         else if (!has_six_pwm(config))
2917                 sio_data->skip_pwm |= BIT(5);
2918
2919         if (!has_vid(config))
2920                 sio_data->skip_vid = 1;
2921
2922         /* Read GPIO config and VID value from LDN 7 (GPIO) */
2923         if (sio_data->type == it87) {
2924                 /* The IT8705F has a different LD number for GPIO */
2925                 superio_select(sioaddr, 5);
2926                 sio_data->beep_pin = superio_inb(sioaddr,
2927                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2928         } else if (sio_data->type == it8783) {
2929                 int reg25, reg27, reg2a, reg2c, regef;
2930
2931                 superio_select(sioaddr, GPIO);
2932
2933                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2934                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2935                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2936                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2937                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2938
2939                 /* Check if fan3 is there or not */
2940                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2941                         sio_data->skip_fan |= BIT(2);
2942                 if ((reg25 & BIT(4)) ||
2943                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
2944                         sio_data->skip_pwm |= BIT(2);
2945
2946                 /* Check if fan2 is there or not */
2947                 if (reg27 & BIT(7))
2948                         sio_data->skip_fan |= BIT(1);
2949                 if (reg27 & BIT(3))
2950                         sio_data->skip_pwm |= BIT(1);
2951
2952                 /* VIN5 */
2953                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2954                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2955
2956                 /* VIN6 */
2957                 if (reg27 & BIT(1))
2958                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2959
2960                 /*
2961                  * VIN7
2962                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2963                  */
2964                 if (reg27 & BIT(2)) {
2965                         /*
2966                          * The data sheet is a bit unclear regarding the
2967                          * internal voltage divider for VCCH5V. It says
2968                          * "This bit enables and switches VIN7 (pin 91) to the
2969                          * internal voltage divider for VCCH5V".
2970                          * This is different to other chips, where the internal
2971                          * voltage divider would connect VIN7 to an internal
2972                          * voltage source. Maybe that is the case here as well.
2973                          *
2974                          * Since we don't know for sure, re-route it if that is
2975                          * not the case, and ask the user to report if the
2976                          * resulting voltage is sane.
2977                          */
2978                         if (!(reg2c & BIT(1))) {
2979                                 reg2c |= BIT(1);
2980                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2981                                              reg2c);
2982                                 pr_notice("Routing internal VCCH5V to in7.\n");
2983                         }
2984                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2985                         pr_notice("Please report if it displays a reasonable voltage.\n");
2986                 }
2987
2988                 if (reg2c & BIT(0))
2989                         sio_data->internal |= BIT(0);
2990                 if (reg2c & BIT(1))
2991                         sio_data->internal |= BIT(1);
2992
2993                 sio_data->beep_pin = superio_inb(sioaddr,
2994                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2995         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
2996                 int reg27, reg29;
2997
2998                 superio_select(sioaddr, GPIO);
2999
3000                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3001
3002                 /* Check if fan3 is there or not */
3003                 if (reg27 & BIT(6))
3004                         sio_data->skip_pwm |= BIT(2);
3005                 if (reg27 & BIT(7))
3006                         sio_data->skip_fan |= BIT(2);
3007
3008                 /* Check if fan2 is there or not */
3009                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3010                 if (reg29 & BIT(1))
3011                         sio_data->skip_pwm |= BIT(1);
3012                 if (reg29 & BIT(2))
3013                         sio_data->skip_fan |= BIT(1);
3014
3015                 if (sio_data->type == it8603) {
3016                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3017                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3018                 }
3019
3020                 sio_data->beep_pin = superio_inb(sioaddr,
3021                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3022         } else if (sio_data->type == it8613) {
3023                 int reg27, reg29, reg2a;
3024
3025                 superio_select(sioaddr, GPIO);
3026
3027                 /* Check for pwm3, fan3, pwm5, fan5 */
3028                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3029                 if (reg27 & BIT(1))
3030                         sio_data->skip_fan |= BIT(4);
3031                 if (reg27 & BIT(3))
3032                         sio_data->skip_pwm |= BIT(4);
3033                 if (reg27 & BIT(6))
3034                         sio_data->skip_pwm |= BIT(2);
3035                 if (reg27 & BIT(7))
3036                         sio_data->skip_fan |= BIT(2);
3037
3038                 /* Check for pwm2, fan2 */
3039                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3040                 if (reg29 & BIT(1))
3041                         sio_data->skip_pwm |= BIT(1);
3042                 if (reg29 & BIT(2))
3043                         sio_data->skip_fan |= BIT(1);
3044
3045                 /* Check for pwm4, fan4 */
3046                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3047                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3048                         sio_data->skip_fan |= BIT(3);
3049                         sio_data->skip_pwm |= BIT(3);
3050                 }
3051
3052                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3053                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3054                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3055                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3056
3057                 sio_data->beep_pin = superio_inb(sioaddr,
3058                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3059         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3060                    sio_data->type == it8686) {
3061                 int reg;
3062
3063                 superio_select(sioaddr, GPIO);
3064
3065                 /* Check for pwm5 */
3066                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3067                 if (reg & BIT(6))
3068                         sio_data->skip_pwm |= BIT(4);
3069
3070                 /* Check for fan4, fan5 */
3071                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3072                 if (!(reg & BIT(5)))
3073                         sio_data->skip_fan |= BIT(3);
3074                 if (!(reg & BIT(4)))
3075                         sio_data->skip_fan |= BIT(4);
3076
3077                 /* Check for pwm3, fan3 */
3078                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3079                 if (reg & BIT(6))
3080                         sio_data->skip_pwm |= BIT(2);
3081                 if (reg & BIT(7))
3082                         sio_data->skip_fan |= BIT(2);
3083
3084                 /* Check for pwm4 */
3085                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3086                 if (reg & BIT(2))
3087                         sio_data->skip_pwm |= BIT(3);
3088
3089                 /* Check for pwm2, fan2 */
3090                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3091                 if (reg & BIT(1))
3092                         sio_data->skip_pwm |= BIT(1);
3093                 if (reg & BIT(2))
3094                         sio_data->skip_fan |= BIT(1);
3095                 /* Check for pwm6, fan6 */
3096                 if (!(reg & BIT(7))) {
3097                         sio_data->skip_pwm |= BIT(5);
3098                         sio_data->skip_fan |= BIT(5);
3099                 }
3100
3101                 /* Check if AVCC is on VIN3 */
3102                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3103                 if (reg & BIT(0)) {
3104                         /* For it8686, the bit just enables AVCC3 */
3105                         if (sio_data->type != it8686)
3106                                 sio_data->internal |= BIT(0);
3107                 } else {
3108                         sio_data->internal &= ~BIT(3);
3109                         sio_data->skip_in |= BIT(9);
3110                 }
3111
3112                 sio_data->beep_pin = superio_inb(sioaddr,
3113                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3114         } else if (sio_data->type == it8622) {
3115                 int reg;
3116
3117                 superio_select(sioaddr, GPIO);
3118
3119                 /* Check for pwm4, fan4 */
3120                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3121                 if (reg & BIT(6))
3122                         sio_data->skip_fan |= BIT(3);
3123                 if (reg & BIT(5))
3124                         sio_data->skip_pwm |= BIT(3);
3125
3126                 /* Check for pwm3, fan3, pwm5, fan5 */
3127                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3128                 if (reg & BIT(6))
3129                         sio_data->skip_pwm |= BIT(2);
3130                 if (reg & BIT(7))
3131                         sio_data->skip_fan |= BIT(2);
3132                 if (reg & BIT(3))
3133                         sio_data->skip_pwm |= BIT(4);
3134                 if (reg & BIT(1))
3135                         sio_data->skip_fan |= BIT(4);
3136
3137                 /* Check for pwm2, fan2 */
3138                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3139                 if (reg & BIT(1))
3140                         sio_data->skip_pwm |= BIT(1);
3141                 if (reg & BIT(2))
3142                         sio_data->skip_fan |= BIT(1);
3143
3144                 /* Check for AVCC */
3145                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3146                 if (!(reg & BIT(0)))
3147                         sio_data->skip_in |= BIT(9);
3148
3149                 sio_data->beep_pin = superio_inb(sioaddr,
3150                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3151         } else if (sio_data->type == it8732) {
3152                 int reg;
3153
3154                 superio_select(sioaddr, GPIO);
3155
3156                 /* Check for pwm2, fan2 */
3157                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3158                 if (reg & BIT(1))
3159                         sio_data->skip_pwm |= BIT(1);
3160                 if (reg & BIT(2))
3161                         sio_data->skip_fan |= BIT(1);
3162
3163                 /* Check for pwm3, fan3, fan4 */
3164                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3165                 if (reg & BIT(6))
3166                         sio_data->skip_pwm |= BIT(2);
3167                 if (reg & BIT(7))
3168                         sio_data->skip_fan |= BIT(2);
3169                 if (reg & BIT(5))
3170                         sio_data->skip_fan |= BIT(3);
3171
3172                 /* Check if AVCC is on VIN3 */
3173                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3174                 if (reg & BIT(0))
3175                         sio_data->internal |= BIT(0);
3176
3177                 sio_data->beep_pin = superio_inb(sioaddr,
3178                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3179         } else if (sio_data->type == it8655) {
3180                 int reg;
3181
3182                 superio_select(sioaddr, GPIO);
3183
3184                 /* Check for pwm2 */
3185                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3186                 if (reg & BIT(1))
3187                         sio_data->skip_pwm |= BIT(1);
3188
3189                 /* Check for fan2 */
3190                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3191                 if (reg & BIT(4))
3192                         sio_data->skip_fan |= BIT(1);
3193
3194                 /* Check for pwm3, fan3 */
3195                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3196                 if (reg & BIT(6))
3197                         sio_data->skip_pwm |= BIT(2);
3198                 if (reg & BIT(7))
3199                         sio_data->skip_fan |= BIT(2);
3200
3201                 sio_data->beep_pin = superio_inb(sioaddr,
3202                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3203         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3204                 int reg27, reg29, reg2d, regd3;
3205
3206                 superio_select(sioaddr, GPIO);
3207
3208                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3209                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3210                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3211                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3212
3213                 /* Check for pwm2, fan2 */
3214                 if (reg29 & BIT(1))
3215                         sio_data->skip_pwm |= BIT(1);
3216                 if (reg2d & BIT(4))
3217                         sio_data->skip_fan |= BIT(1);
3218
3219                 /* Check for pwm3, fan3 */
3220                 if (reg27 & BIT(6))
3221                         sio_data->skip_pwm |= BIT(2);
3222                 if (reg27 & BIT(7))
3223                         sio_data->skip_fan |= BIT(2);
3224
3225                 /* Check for pwm4, fan4, pwm5, fan5 */
3226                 if (sio_data->type == it8625) {
3227                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3228
3229                         if (reg25 & BIT(6))
3230                                 sio_data->skip_fan |= BIT(3);
3231                         if (reg25 & BIT(5))
3232                                 sio_data->skip_pwm |= BIT(3);
3233                         if (reg27 & BIT(3))
3234                                 sio_data->skip_pwm |= BIT(4);
3235                         if (reg27 & BIT(1))
3236                                 sio_data->skip_fan |= BIT(4);
3237                 } else {
3238                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3239
3240                         if (regd3 & BIT(2))
3241                                 sio_data->skip_pwm |= BIT(3);
3242                         if (regd3 & BIT(3))
3243                                 sio_data->skip_fan |= BIT(3);
3244                         if (reg26 & BIT(5))
3245                                 sio_data->skip_pwm |= BIT(4);
3246                         if (!(reg26 & BIT(4)))
3247                                 sio_data->skip_fan |= BIT(4);
3248                 }
3249
3250                 /* Check for pwm6, fan6 */
3251                 if (regd3 & BIT(0))
3252                         sio_data->skip_pwm |= BIT(5);
3253                 if (regd3 & BIT(1))
3254                         sio_data->skip_fan |= BIT(5);
3255
3256                 sio_data->beep_pin = superio_inb(sioaddr,
3257                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3258         } else {
3259                 int reg;
3260                 bool uart6;
3261
3262                 superio_select(sioaddr, GPIO);
3263
3264                 /* Check for fan4, fan5 */
3265                 if (has_five_fans(config)) {
3266                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3267                         switch (sio_data->type) {
3268                         case it8718:
3269                                 if (reg & BIT(5))
3270                                         sio_data->skip_fan |= BIT(3);
3271                                 if (reg & BIT(4))
3272                                         sio_data->skip_fan |= BIT(4);
3273                                 break;
3274                         case it8720:
3275                         case it8721:
3276                         case it8728:
3277                                 if (!(reg & BIT(5)))
3278                                         sio_data->skip_fan |= BIT(3);
3279                                 if (!(reg & BIT(4)))
3280                                         sio_data->skip_fan |= BIT(4);
3281                                 break;
3282                         default:
3283                                 break;
3284                         }
3285                 }
3286
3287                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3288                 if (!sio_data->skip_vid) {
3289                         /* We need at least 4 VID pins */
3290                         if (reg & 0x0f) {
3291                                 pr_info("VID is disabled (pins used for GPIO)\n");
3292                                 sio_data->skip_vid = 1;
3293                         }
3294                 }
3295
3296                 /* Check if fan3 is there or not */
3297                 if (reg & BIT(6))
3298                         sio_data->skip_pwm |= BIT(2);
3299                 if (reg & BIT(7))
3300                         sio_data->skip_fan |= BIT(2);
3301
3302                 /* Check if fan2 is there or not */
3303                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3304                 if (reg & BIT(1))
3305                         sio_data->skip_pwm |= BIT(1);
3306                 if (reg & BIT(2))
3307                         sio_data->skip_fan |= BIT(1);
3308
3309                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3310                     !(sio_data->skip_vid))
3311                         sio_data->vid_value = superio_inb(sioaddr,
3312                                                           IT87_SIO_VID_REG);
3313
3314                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3315
3316                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3317
3318                 /*
3319                  * The IT8720F has no VIN7 pin, so VCCH should always be
3320                  * routed internally to VIN7 with an internal divider.
3321                  * Curiously, there still is a configuration bit to control
3322                  * this, which means it can be set incorrectly. And even
3323                  * more curiously, many boards out there are improperly
3324                  * configured, even though the IT8720F datasheet claims
3325                  * that the internal routing of VCCH to VIN7 is the default
3326                  * setting. So we force the internal routing in this case.
3327                  *
3328                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3329                  * If UART6 is enabled, re-route VIN7 to the internal divider
3330                  * if that is not already the case.
3331                  */
3332                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3333                         reg |= BIT(1);
3334                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3335                         pr_notice("Routing internal VCCH to in7\n");
3336                 }
3337                 if (reg & BIT(0))
3338                         sio_data->internal |= BIT(0);
3339                 if (reg & BIT(1))
3340                         sio_data->internal |= BIT(1);
3341
3342                 /*
3343                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3344                  * While VIN7 can be routed to the internal voltage divider,
3345                  * VIN5 and VIN6 are not available if UART6 is enabled.
3346                  *
3347                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3348                  * is the temperature source. Since we can not read the
3349                  * temperature source here, skip_temp is preliminary.
3350                  */
3351                 if (uart6) {
3352                         sio_data->skip_in |= BIT(5) | BIT(6);
3353                         sio_data->skip_temp |= BIT(2);
3354                 }
3355
3356                 sio_data->beep_pin = superio_inb(sioaddr,
3357                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3358         }
3359         if (sio_data->beep_pin)
3360                 pr_info("Beeping is supported\n");
3361
3362 exit:
3363         superio_exit(sioaddr);
3364         return err;
3365 }
3366
3367 static void it87_init_regs(struct platform_device *pdev)
3368 {
3369         struct it87_data *data = platform_get_drvdata(pdev);
3370
3371         /* Initialize chip specific register pointers */
3372         switch (data->type) {
3373         case it8686:
3374                 data->REG_FAN = IT87_REG_FAN;
3375                 data->REG_FANX = IT87_REG_FANX;
3376                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3377                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3378                 data->REG_PWM = IT87_REG_PWM;
3379                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3380                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3381                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3382                 break;
3383         case it8625:
3384         case it8655:
3385         case it8665:
3386                 data->REG_FAN = IT87_REG_FAN_8665;
3387                 data->REG_FANX = IT87_REG_FANX_8665;
3388                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3389                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3390                 data->REG_PWM = IT87_REG_PWM_8665;
3391                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3392                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3393                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3394                 break;
3395         case it8622:
3396                 data->REG_FAN = IT87_REG_FAN;
3397                 data->REG_FANX = IT87_REG_FANX;
3398                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3399                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3400                 data->REG_PWM = IT87_REG_PWM_8665;
3401                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3402                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3403                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3404                 break;
3405         case it8613:
3406                 data->REG_FAN = IT87_REG_FAN;
3407                 data->REG_FANX = IT87_REG_FANX;
3408                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3409                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3410                 data->REG_PWM = IT87_REG_PWM_8665;
3411                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3412                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3413                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3414                 break;
3415         default:
3416                 data->REG_FAN = IT87_REG_FAN;
3417                 data->REG_FANX = IT87_REG_FANX;
3418                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3419                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3420                 data->REG_PWM = IT87_REG_PWM;
3421                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3422                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3423                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3424                 break;
3425         }
3426 }
3427
3428 /* Called when we have found a new IT87. */
3429 static void it87_init_device(struct platform_device *pdev)
3430 {
3431         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3432         struct it87_data *data = platform_get_drvdata(pdev);
3433         int tmp, i;
3434         u8 mask;
3435
3436         /*
3437          * For each PWM channel:
3438          * - If it is in automatic mode, setting to manual mode should set
3439          *   the fan to full speed by default.
3440          * - If it is in manual mode, we need a mapping to temperature
3441          *   channels to use when later setting to automatic mode later.
3442          *   Use a 1:1 mapping by default (we are clueless.)
3443          * In both cases, the value can (and should) be changed by the user
3444          * prior to switching to a different mode.
3445          * Note that this is no longer needed for the IT8721F and later, as
3446          * these have separate registers for the temperature mapping and the
3447          * manual duty cycle.
3448          */
3449         for (i = 0; i < NUM_AUTO_PWM; i++) {
3450                 data->pwm_temp_map[i] = i;
3451                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3452                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3453         }
3454
3455         /*
3456          * Some chips seem to have default value 0xff for all limit
3457          * registers. For low voltage limits it makes no sense and triggers
3458          * alarms, so change to 0 instead. For high temperature limits, it
3459          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3460          * but is still confusing, so change to 127 degrees C.
3461          */
3462         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3463                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3464                 if (tmp == 0xff)
3465                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3466         }
3467         for (i = 0; i < data->num_temp_limit; i++) {
3468                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3469                 if (tmp == 0xff)
3470                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3471         }
3472
3473         /*
3474          * Temperature channels are not forcibly enabled, as they can be
3475          * set to two different sensor types and we can't guess which one
3476          * is correct for a given system. These channels can be enabled at
3477          * run-time through the temp{1-3}_type sysfs accessors if needed.
3478          */
3479
3480         /* Check if voltage monitors are reset manually or by some reason */
3481         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3482         if ((tmp & 0xff) == 0) {
3483                 /* Enable all voltage monitors */
3484                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3485         }
3486
3487         /* Check if tachometers are reset manually or by some reason */
3488         mask = 0x70 & ~(sio_data->skip_fan << 4);
3489         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3490         if ((data->fan_main_ctrl & mask) == 0) {
3491                 /* Enable all fan tachometers */
3492                 data->fan_main_ctrl |= mask;
3493                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3494                                  data->fan_main_ctrl);
3495         }
3496         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3497
3498         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3499
3500         /* Set tachometers to 16-bit mode if needed */
3501         if (has_fan16_config(data)) {
3502                 if (~tmp & 0x07 & data->has_fan) {
3503                         dev_dbg(&pdev->dev,
3504                                 "Setting fan1-3 to 16-bit mode\n");
3505                         it87_write_value(data, IT87_REG_FAN_16BIT,
3506                                          tmp | 0x07);
3507                 }
3508         }
3509
3510         /* Check for additional fans */
3511         if (has_four_fans(data) && (tmp & BIT(4)))
3512                 data->has_fan |= BIT(3); /* fan4 enabled */
3513         if (has_five_fans(data) && (tmp & BIT(5)))
3514                 data->has_fan |= BIT(4); /* fan5 enabled */
3515         if (has_six_fans(data)) {
3516                 switch (data->type) {
3517                 case it8620:
3518                 case it8628:
3519                 case it8686:
3520                         if (tmp & BIT(2))
3521                                 data->has_fan |= BIT(5); /* fan6 enabled */
3522                         break;
3523                 case it8625:
3524                 case it8665:
3525                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3526                         if (tmp & BIT(3))
3527                                 data->has_fan |= BIT(5); /* fan6 enabled */
3528                         break;
3529                 default:
3530                         break;
3531                 }
3532         }
3533
3534         /* Fan input pins may be used for alternative functions */
3535         data->has_fan &= ~sio_data->skip_fan;
3536
3537         /* Check if pwm6 is enabled */
3538         if (has_six_pwm(data)) {
3539                 switch (data->type) {
3540                 case it8620:
3541                 case it8686:
3542                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3543                         if (!(tmp & BIT(3)))
3544                                 sio_data->skip_pwm |= BIT(5);
3545                         break;
3546                 default:
3547                         break;
3548                 }
3549         }
3550
3551         /* Start monitoring */
3552         it87_write_value(data, IT87_REG_CONFIG,
3553                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3554                          | (update_vbat ? 0x41 : 0x01));
3555 }
3556
3557 /* Return 1 if and only if the PWM interface is safe to use */
3558 static int it87_check_pwm(struct device *dev)
3559 {
3560         struct it87_data *data = dev_get_drvdata(dev);
3561         /*
3562          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3563          * and polarity set to active low is sign that this is the case so we
3564          * disable pwm control to protect the user.
3565          */
3566         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3567
3568         if ((tmp & 0x87) == 0) {
3569                 if (fix_pwm_polarity) {
3570                         /*
3571                          * The user asks us to attempt a chip reconfiguration.
3572                          * This means switching to active high polarity and
3573                          * inverting all fan speed values.
3574                          */
3575                         int i;
3576                         u8 pwm[3];
3577
3578                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3579                                 pwm[i] = it87_read_value(data,
3580                                                          data->REG_PWM[i]);
3581
3582                         /*
3583                          * If any fan is in automatic pwm mode, the polarity
3584                          * might be correct, as suspicious as it seems, so we
3585                          * better don't change anything (but still disable the
3586                          * PWM interface).
3587                          */
3588                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3589                                 dev_info(dev,
3590                                          "Reconfiguring PWM to active high polarity\n");
3591                                 it87_write_value(data, IT87_REG_FAN_CTL,
3592                                                  tmp | 0x87);
3593                                 for (i = 0; i < 3; i++)
3594                                         it87_write_value(data,
3595                                                          data->REG_PWM[i],
3596                                                          0x7f & ~pwm[i]);
3597                                 return 1;
3598                         }
3599
3600                         dev_info(dev,
3601                                  "PWM configuration is too broken to be fixed\n");
3602                 }
3603
3604                 dev_info(dev,
3605                          "Detected broken BIOS defaults, disabling PWM interface\n");
3606                 return 0;
3607         } else if (fix_pwm_polarity) {
3608                 dev_info(dev,
3609                          "PWM configuration looks sane, won't touch\n");
3610         }
3611
3612         return 1;
3613 }
3614
3615 static int it87_probe(struct platform_device *pdev)
3616 {
3617         struct it87_data *data;
3618         struct resource *res;
3619         struct device *dev = &pdev->dev;
3620         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3621         int enable_pwm_interface;
3622         struct device *hwmon_dev;
3623
3624         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3625         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3626                                  DRVNAME)) {
3627                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3628                         (unsigned long)res->start,
3629                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3630                 return -EBUSY;
3631         }
3632
3633         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3634         if (!data)
3635                 return -ENOMEM;
3636
3637         data->addr = res->start;
3638         data->type = sio_data->type;
3639         data->features = it87_devices[sio_data->type].features;
3640         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3641         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3642         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3643         data->bank = 0xff;
3644
3645         /*
3646          * IT8705F Datasheet 0.4.1, 3h == Version G.
3647          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3648          * These are the first revisions with 16-bit tachometer support.
3649          */
3650         switch (data->type) {
3651         case it87:
3652                 if (sio_data->revision >= 0x03) {
3653                         data->features &= ~FEAT_OLD_AUTOPWM;
3654                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3655                 }
3656                 break;
3657         case it8712:
3658                 if (sio_data->revision >= 0x08) {
3659                         data->features &= ~FEAT_OLD_AUTOPWM;
3660                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3661                                           FEAT_FIVE_FANS;
3662                 }
3663                 break;
3664         default:
3665                 break;
3666         }
3667
3668         /* Now, we do the remaining detection. */
3669         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3670             it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3671                 return -ENODEV;
3672
3673         platform_set_drvdata(pdev, data);
3674
3675         mutex_init(&data->update_lock);
3676
3677         /* Initialize register pointers */
3678         it87_init_regs(pdev);
3679
3680         /* Check PWM configuration */
3681         enable_pwm_interface = it87_check_pwm(dev);
3682
3683         /* Starting with IT8721F, we handle scaling of internal voltages */
3684         if (has_scaling(data)) {
3685                 if (sio_data->internal & BIT(0))
3686                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3687                 if (sio_data->internal & BIT(1))
3688                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3689                 if (sio_data->internal & BIT(2))
3690                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3691                 if (sio_data->internal & BIT(3))
3692                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3693         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3694                    sio_data->type == it8783) {
3695                 if (sio_data->internal & BIT(0))
3696                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3697                 if (sio_data->internal & BIT(1))
3698                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3699         }
3700
3701         data->has_temp = 0x07;
3702         if (sio_data->skip_temp & BIT(2)) {
3703                 if (sio_data->type == it8782 &&
3704                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3705                         data->has_temp &= ~BIT(2);
3706         }
3707
3708         data->in_internal = sio_data->internal;
3709         data->has_in = 0x3ff & ~sio_data->skip_in;
3710
3711         if (has_six_temp(data)) {
3712                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3713
3714                 /* Check for additional temperature sensors */
3715                 if ((reg & 0x03) >= 0x02)
3716                         data->has_temp |= BIT(3);
3717                 if (((reg >> 2) & 0x03) >= 0x02)
3718                         data->has_temp |= BIT(4);
3719                 if (((reg >> 4) & 0x03) >= 0x02)
3720                         data->has_temp |= BIT(5);
3721
3722                 /* Check for additional voltage sensors */
3723                 if ((reg & 0x03) == 0x01)
3724                         data->has_in |= BIT(10);
3725                 if (((reg >> 2) & 0x03) == 0x01)
3726                         data->has_in |= BIT(11);
3727                 if (((reg >> 4) & 0x03) == 0x01)
3728                         data->has_in |= BIT(12);
3729         }
3730
3731         data->has_beep = !!sio_data->beep_pin;
3732
3733         /* Initialize the IT87 chip */
3734         it87_init_device(pdev);
3735
3736         if (!sio_data->skip_vid) {
3737                 data->has_vid = true;
3738                 data->vrm = vid_which_vrm();
3739                 /* VID reading from Super-I/O config space if available */
3740                 data->vid = sio_data->vid_value;
3741         }
3742
3743         /* Prepare for sysfs hooks */
3744         data->groups[0] = &it87_group;
3745         data->groups[1] = &it87_group_in;
3746         data->groups[2] = &it87_group_temp;
3747         data->groups[3] = &it87_group_fan;
3748
3749         if (enable_pwm_interface) {
3750                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3751                 data->has_pwm &= ~sio_data->skip_pwm;
3752
3753                 data->groups[4] = &it87_group_pwm;
3754                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3755                         data->groups[5] = &it87_group_auto_pwm;
3756         }
3757
3758         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3759                                         it87_devices[sio_data->type].name,
3760                                         data, data->groups);
3761         return PTR_ERR_OR_ZERO(hwmon_dev);
3762 }
3763
3764 static struct platform_driver it87_driver = {
3765         .driver = {
3766                 .name   = DRVNAME,
3767         },
3768         .probe  = it87_probe,
3769 };
3770
3771 static int __init it87_device_add(int index, unsigned short address,
3772                                   const struct it87_sio_data *sio_data)
3773 {
3774         struct platform_device *pdev;
3775         struct resource res = {
3776                 .start  = address + IT87_EC_OFFSET,
3777                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3778                 .name   = DRVNAME,
3779                 .flags  = IORESOURCE_IO,
3780         };
3781         int err;
3782
3783         err = acpi_check_resource_conflict(&res);
3784         if (err)
3785                 return err;
3786
3787         pdev = platform_device_alloc(DRVNAME, address);
3788         if (!pdev)
3789                 return -ENOMEM;
3790
3791         err = platform_device_add_resources(pdev, &res, 1);
3792         if (err) {
3793                 pr_err("Device resource addition failed (%d)\n", err);
3794                 goto exit_device_put;
3795         }
3796
3797         err = platform_device_add_data(pdev, sio_data,
3798                                        sizeof(struct it87_sio_data));
3799         if (err) {
3800                 pr_err("Platform data allocation failed\n");
3801                 goto exit_device_put;
3802         }
3803
3804         err = platform_device_add(pdev);
3805         if (err) {
3806                 pr_err("Device addition failed (%d)\n", err);
3807                 goto exit_device_put;
3808         }
3809
3810         it87_pdev[index] = pdev;
3811         return 0;
3812
3813 exit_device_put:
3814         platform_device_put(pdev);
3815         return err;
3816 }
3817
3818 struct it87_dmi_data {
3819         bool sio4e_broken;      /* SIO accesses @ 0x4e are broken       */
3820         char *sio_mutex;        /* SIO ACPI mutex                       */
3821         u8 skip_pwm;            /* pwm channels to skip for this board  */
3822 };
3823
3824 /*
3825  * On Gigabyte AB350 and AX370 boards, accesses to the Super-IO chip
3826  * at address 0x4e/0x4f can result in a system hang.
3827  * Accesses to address 0x2e/0x2f need to be mutex protected.
3828  */
3829 static struct it87_dmi_data gigabyte_ab350_gaming = {
3830         .sio4e_broken = true,
3831         .sio_mutex = "\\_SB.PCI0.SBRG.SIO1.MUT0",
3832 };
3833
3834 /*
3835  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3836  * connected to a fan, but to something else. One user
3837  * has reported instant system power-off when changing
3838  * the PWM2 duty cycle, so we disable it.
3839  * I use the board name string as the trigger in case
3840  * the same board is ever used in other systems.
3841  */
3842 static struct it87_dmi_data nvidia_fn68pt = {
3843         .skip_pwm = BIT(1),
3844 };
3845
3846 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3847         {
3848                 .matches = {
3849                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3850                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming-CF"),
3851                 },
3852                 .driver_data = &gigabyte_ab350_gaming,
3853         },
3854         {
3855                 .matches = {
3856                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3857                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming 3-CF"),
3858                 },
3859                 .driver_data = &gigabyte_ab350_gaming,
3860         },
3861         {
3862                 .matches = {
3863                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3864                         DMI_MATCH(DMI_BOARD_NAME, "AB350M-D3H-CF"),
3865                 },
3866                 .driver_data = &gigabyte_ab350_gaming,
3867         },
3868         {
3869                 .matches = {
3870                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3871                         DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming K7"),
3872                 },
3873                 .driver_data = &gigabyte_ab350_gaming,
3874         },
3875         {
3876                 .matches = {
3877                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3878                         DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming 5"),
3879                 },
3880                 .driver_data = &gigabyte_ab350_gaming,
3881         },
3882         {
3883                 .matches = {
3884                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3885                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3886                 },
3887                 .driver_data = &nvidia_fn68pt,
3888         },
3889         { }
3890 };
3891
3892 static int __init sm_it87_init(void)
3893 {
3894         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3895         struct it87_dmi_data *dmi_data = NULL;
3896         int sioaddr[2] = { REG_2E, REG_4E };
3897         struct it87_sio_data sio_data;
3898         unsigned short isa_address;
3899         bool found = false;
3900         int i, err;
3901
3902         if (dmi)
3903                 dmi_data = dmi->driver_data;
3904
3905         if (dmi_data) {
3906                 it87_sio4e_broken = dmi_data->sio4e_broken;
3907 #ifdef __IT87_USE_ACPI_MUTEX
3908                 if (dmi_data->sio_mutex) {
3909                         static acpi_status status;
3910
3911                         status = acpi_get_handle(NULL, dmi_data->sio_mutex,
3912                                                  &it87_acpi_sio_handle);
3913                         if (ACPI_SUCCESS(status)) {
3914                                 it87_acpi_sio_mutex = dmi_data->sio_mutex;
3915                                 pr_debug("Found ACPI SIO mutex %s\n",
3916                                          dmi_data->sio_mutex);
3917                         } else {
3918                                 pr_warn("ACPI SIO mutex %s not found\n",
3919                                         dmi_data->sio_mutex);
3920                         }
3921                 }
3922 #endif /* __IT87_USE_ACPI_MUTEX */
3923         }
3924
3925         err = platform_driver_register(&it87_driver);
3926         if (err)
3927                 return err;
3928
3929         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3930                 /*
3931                  * Accessing the second Super-IO chip can result in board
3932                  * hangs. Disable until we figure out what is going on.
3933                  */
3934                 if (blacklist && it87_sio4e_broken && sioaddr[i] == 0x4e)
3935                         continue;
3936                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3937                 isa_address = 0;
3938                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3939                 if (err || isa_address == 0)
3940                         continue;
3941
3942                 if (dmi_data)
3943                         sio_data.skip_pwm |= dmi_data->skip_pwm;
3944                 err = it87_device_add(i, isa_address, &sio_data);
3945                 if (err)
3946                         goto exit_dev_unregister;
3947                 found = true;
3948         }
3949
3950         if (!found) {
3951                 err = -ENODEV;
3952                 goto exit_unregister;
3953         }
3954         return 0;
3955
3956 exit_dev_unregister:
3957         /* NULL check handled by platform_device_unregister */
3958         platform_device_unregister(it87_pdev[0]);
3959 exit_unregister:
3960         platform_driver_unregister(&it87_driver);
3961         return err;
3962 }
3963
3964 static void __exit sm_it87_exit(void)
3965 {
3966         /* NULL check handled by platform_device_unregister */
3967         platform_device_unregister(it87_pdev[1]);
3968         platform_device_unregister(it87_pdev[0]);
3969         platform_driver_unregister(&it87_driver);
3970 }
3971
3972 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3973 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3974 module_param(update_vbat, bool, 0);
3975 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3976 module_param(fix_pwm_polarity, bool, 0);
3977 MODULE_PARM_DESC(fix_pwm_polarity,
3978                  "Force PWM polarity to active high (DANGEROUS)");
3979 MODULE_LICENSE("GPL");
3980
3981 module_init(sm_it87_init);
3982 module_exit(sm_it87_exit);