git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8620E  Super I/O chip w/LPC interface
  16  *            IT8622E  Super I/O chip w/LPC interface
  17  *            IT8623E  Super I/O chip w/LPC interface
  18  *            IT8628E  Super I/O chip w/LPC interface
  19  *            IT8655E  Super I/O chip w/LPC interface
  20  *            IT8665E  Super I/O chip w/LPC interface
  21  *            IT8686E  Super I/O chip w/LPC interface
  22  *            IT8705F  Super I/O chip w/LPC interface
  23  *            IT8712F  Super I/O chip w/LPC interface
  24  *            IT8716F  Super I/O chip w/LPC interface
  25  *            IT8718F  Super I/O chip w/LPC interface
  26  *            IT8720F  Super I/O chip w/LPC interface
  27  *            IT8721F  Super I/O chip w/LPC interface
  28  *            IT8726F  Super I/O chip w/LPC interface
  29  *            IT8728F  Super I/O chip w/LPC interface
  30  *            IT8732F  Super I/O chip w/LPC interface
  31  *            IT8758E  Super I/O chip w/LPC interface
  32  *            IT8771E  Super I/O chip w/LPC interface
  33  *            IT8772E  Super I/O chip w/LPC interface
  34  *            IT8781F  Super I/O chip w/LPC interface
  35  *            IT8782F  Super I/O chip w/LPC interface
  36  *            IT8783E/F Super I/O chip w/LPC interface
  37  *            IT8786E  Super I/O chip w/LPC interface
  38  *            IT8790E  Super I/O chip w/LPC interface
  39  *            IT8792E  Super I/O chip w/LPC interface
  40  *            Sis950   A clone of the IT8705F
  41  *
  42  *  Copyright (C) 2001 Chris Gauthron
  43  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  44  *
  45  *  This program is free software; you can redistribute it and/or modify
  46  *  it under the terms of the GNU General Public License as published by
  47  *  the Free Software Foundation; either version 2 of the License, or
  48  *  (at your option) any later version.
  49  *
  50  *  This program is distributed in the hope that it will be useful,
  51  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  52  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  53  *  GNU General Public License for more details.
  54  */
  55
  56 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  57
  58 #include <linux/bitops.h>
  59 #include <linux/module.h>
  60 #include <linux/init.h>
  61 #include <linux/slab.h>
  62 #include <linux/jiffies.h>
  63 #include <linux/platform_device.h>
  64 #include <linux/hwmon.h>
  65 #include <linux/hwmon-sysfs.h>
  66 #include <linux/hwmon-vid.h>
  67 #include <linux/err.h>
  68 #include <linux/mutex.h>
  69 #include <linux/sysfs.h>
  70 #include <linux/string.h>
  71 #include <linux/dmi.h>
  72 #include <linux/acpi.h>
  73 #include <linux/io.h>
  74 #include "compat.h"
  75
  76 #define DRVNAME "it87"
  77
  78 /* Necessary API not (yet) exported in upstream kernel */
  79 /* #define __IT87_USE_ACPI_MUTEX */
  80
  81 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  82              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  83              it8792, it8603, it8607, it8620, it8622, it8628, it8655, it8665,
  84              it8686 };
  85
  86 static unsigned short force_id;
  87 module_param(force_id, ushort, 0);
  88 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  89
  90 static struct platform_device *it87_pdev[2];
  91 static bool it87_sio4e_broken;
  92 #ifdef __IT87_USE_ACPI_MUTEX
  93 static acpi_handle it87_acpi_sio_handle;
  94 static char *it87_acpi_sio_mutex;
  95 #endif
  96
  97 #define REG_2E  0x2e    /* The register to read/write */
  98 #define REG_4E  0x4e    /* Secondary register to read/write */
  99
 100 #define DEV     0x07    /* Register: Logical device select */
 101 #define PME     0x04    /* The device with the fan registers in it */
 102
 103 /* The device with the IT8718F/IT8720F VID value in it */
 104 #define GPIO    0x07
 105
 106 #define DEVID   0x20    /* Register: Device ID */
 107 #define DEVREV  0x22    /* Register: Device Revision */
 108
 109 static inline void __superio_enter(int ioreg)
 110 {
 111         outb(0x87, ioreg);
 112         outb(0x01, ioreg);
 113         outb(0x55, ioreg);
 114         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 115 }
 116
 117 static inline int superio_inb(int ioreg, int reg)
 118 {
 119         int val;
 120
 121         outb(reg, ioreg);
 122         val = inb(ioreg + 1);
 123         if (it87_sio4e_broken && ioreg == 0x4e && val == 0xff) {
 124                 __superio_enter(ioreg);
 125                 outb(reg, ioreg);
 126                 val = inb(ioreg + 1);
 127                 pr_warn("Retry access 0x4e:0x%x -> 0x%x\n", reg, val);
 128         }
 129
 130         return val;
 131 }
 132
 133 static inline void superio_outb(int ioreg, int reg, int val)
 134 {
 135         outb(reg, ioreg);
 136         outb(val, ioreg + 1);
 137 }
 138
 139 static int superio_inw(int ioreg, int reg)
 140 {
 141         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 142 }
 143
 144 static inline void superio_select(int ioreg, int ldn)
 145 {
 146         outb(DEV, ioreg);
 147         outb(ldn, ioreg + 1);
 148 }
 149
 150 static inline int superio_enter(int ioreg)
 151 {
 152 #ifdef __IT87_USE_ACPI_MUTEX
 153         if (it87_acpi_sio_mutex) {
 154                 acpi_status status;
 155
 156                 status = acpi_acquire_mutex(NULL, it87_acpi_sio_mutex, 0x10);
 157                 if (ACPI_FAILURE(status)) {
 158                         pr_err("Failed to acquire ACPI mutex\n");
 159                         return -EBUSY;
 160                 }
 161         }
 162 #endif
 163         /*
 164          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 165          */
 166         if (!request_muxed_region(ioreg, 2, DRVNAME))
 167                 goto error;
 168
 169         __superio_enter(ioreg);
 170         return 0;
 171
 172 error:
 173 #ifdef __IT87_USE_ACPI_MUTEX
 174         if (it87_acpi_sio_mutex)
 175                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 176 #endif
 177         return -EBUSY;
 178 }
 179
 180 static inline void superio_exit(int ioreg)
 181 {
 182         if (!it87_sio4e_broken || ioreg != 0x4e) {
 183                 outb(0x02, ioreg);
 184                 outb(0x02, ioreg + 1);
 185         }
 186         release_region(ioreg, 2);
 187 #ifdef __IT87_USE_ACPI_MUTEX
 188         if (it87_acpi_sio_mutex)
 189                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 190 #endif
 191 }
 192
 193 /* Logical device 4 registers */
 194 #define IT8712F_DEVID 0x8712
 195 #define IT8705F_DEVID 0x8705
 196 #define IT8716F_DEVID 0x8716
 197 #define IT8718F_DEVID 0x8718
 198 #define IT8720F_DEVID 0x8720
 199 #define IT8721F_DEVID 0x8721
 200 #define IT8726F_DEVID 0x8726
 201 #define IT8728F_DEVID 0x8728
 202 #define IT8732F_DEVID 0x8732
 203 #define IT8792E_DEVID 0x8733
 204 #define IT8771E_DEVID 0x8771
 205 #define IT8772E_DEVID 0x8772
 206 #define IT8781F_DEVID 0x8781
 207 #define IT8782F_DEVID 0x8782
 208 #define IT8783E_DEVID 0x8783
 209 #define IT8786E_DEVID 0x8786
 210 #define IT8790E_DEVID 0x8790
 211 #define IT8603E_DEVID 0x8603
 212 #define IT8607E_DEVID 0x8607
 213 #define IT8620E_DEVID 0x8620
 214 #define IT8622E_DEVID 0x8622
 215 #define IT8623E_DEVID 0x8623
 216 #define IT8628E_DEVID 0x8628
 217 #define IT8655E_DEVID 0x8655
 218 #define IT8665E_DEVID 0x8665
 219 #define IT8686E_DEVID 0x8686
 220 #define IT87_ACT_REG  0x30
 221 #define IT87_BASE_REG 0x60
 222
 223 /* Logical device 7 registers (IT8712F and later) */
 224 #define IT87_SIO_GPIO1_REG      0x25
 225 #define IT87_SIO_GPIO2_REG      0x26
 226 #define IT87_SIO_GPIO3_REG      0x27
 227 #define IT87_SIO_GPIO4_REG      0x28
 228 #define IT87_SIO_GPIO5_REG      0x29
 229 #define IT87_SIO_GPIO9_REG      0xd3
 230 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 231 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 232 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 233 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 234 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 235 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 236
 237 /* Update battery voltage after every reading if true */
 238 static bool update_vbat;
 239
 240 /* Not all BIOSes properly configure the PWM registers */
 241 static bool fix_pwm_polarity;
 242
 243 /* Many IT87 constants specified below */
 244
 245 /* Length of ISA address segment */
 246 #define IT87_EXTENT 8
 247
 248 /* Length of ISA address segment for Environmental Controller */
 249 #define IT87_EC_EXTENT 2
 250
 251 /* Offset of EC registers from ISA base address */
 252 #define IT87_EC_OFFSET 5
 253
 254 /* Where are the ISA address/data registers relative to the EC base address */
 255 #define IT87_ADDR_REG_OFFSET 0
 256 #define IT87_DATA_REG_OFFSET 1
 257
 258 /*----- The IT87 registers -----*/
 259
 260 #define IT87_REG_CONFIG        0x00
 261
 262 #define IT87_REG_ALARM1        0x01
 263 #define IT87_REG_ALARM2        0x02
 264 #define IT87_REG_ALARM3        0x03
 265
 266 #define IT87_REG_BANK           0x06
 267
 268 /*
 269  * The IT8718F and IT8720F have the VID value in a different register, in
 270  * Super-I/O configuration space.
 271  */
 272 #define IT87_REG_VID           0x0a
 273 /*
 274  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 275  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 276  * mode.
 277  */
 278 #define IT87_REG_FAN_DIV       0x0b
 279 #define IT87_REG_FAN_16BIT     0x0c
 280
 281 /*
 282  * Monitors:
 283  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 284  * - up to 6 temp (1 to 6)
 285  * - up to 6 fan (1 to 6)
 286  */
 287
 288 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 289 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 290 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 291 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 292
 293 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 294 static const u8 IT87_REG_FAN_MIN_8665[] =
 295                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 296 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 297 static const u8 IT87_REG_FANX_MIN_8665[] =
 298                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 299
 300 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 301
 302 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 303
 304 #define IT87_REG_FAN_MAIN_CTRL 0x13
 305 #define IT87_REG_FAN_CTL       0x14
 306
 307 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 308 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 309
 310 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 311
 312 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 313                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 314
 315 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 316
 317 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 318 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 319
 320 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 321 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 322
 323 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 324                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 325 static const u8 IT87_REG_TEMP_LOW_8686[] =
 326                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 327
 328 #define IT87_REG_VIN_ENABLE    0x50
 329 #define IT87_REG_TEMP_ENABLE   0x51
 330 #define IT87_REG_TEMP_EXTRA    0x55
 331 #define IT87_REG_BEEP_ENABLE   0x5c
 332
 333 #define IT87_REG_CHIPID        0x58
 334
 335 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 336
 337 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 338 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 339
 340 #define IT87_REG_TEMP456_ENABLE 0x77
 341
 342 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 343 #define IT87_REG_TEMP_SRC2      0x23d
 344
 345 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 346 #define NUM_VIN_LIMIT           8
 347 #define NUM_TEMP                6
 348 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 349 #define NUM_FAN_DIV             3
 350 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 351 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 352
 353 struct it87_devices {
 354         const char *name;
 355         const char * const suffix;
 356         u32 features;
 357         u8 num_temp_limit;
 358         u8 peci_mask;
 359         u8 old_peci_mask;
 360 };
 361
 362 #define FEAT_12MV_ADC           BIT(0)
 363 #define FEAT_NEWER_AUTOPWM      BIT(1)
 364 #define FEAT_OLD_AUTOPWM        BIT(2)
 365 #define FEAT_16BIT_FANS         BIT(3)
 366 #define FEAT_TEMP_OFFSET        BIT(4)
 367 #define FEAT_TEMP_PECI          BIT(5)
 368 #define FEAT_TEMP_OLD_PECI      BIT(6)
 369 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 370 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 371 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 372 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 373 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 374 #define FEAT_10_9MV_ADC         BIT(12)
 375 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 376 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 377 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 378 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 379 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 380 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 381 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 382 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 383 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 384 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 385 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 386 #define FEAT_11MV_ADC           BIT(24)
 387
 388 static const struct it87_devices it87_devices[] = {
 389         [it87] = {
 390                 .name = "it87",
 391                 .suffix = "F",
 392                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 393                                                 /* may need to overwrite */
 394                 .num_temp_limit = 3,
 395         },
 396         [it8712] = {
 397                 .name = "it8712",
 398                 .suffix = "F",
 399                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 400                                                 /* may need to overwrite */
 401                 .num_temp_limit = 3,
 402         },
 403         [it8716] = {
 404                 .name = "it8716",
 405                 .suffix = "F",
 406                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 407                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 408                   | FEAT_FANCTL_ONOFF,
 409                 .num_temp_limit = 3,
 410         },
 411         [it8718] = {
 412                 .name = "it8718",
 413                 .suffix = "F",
 414                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 415                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 416                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 417                 .num_temp_limit = 3,
 418                 .old_peci_mask = 0x4,
 419         },
 420         [it8720] = {
 421                 .name = "it8720",
 422                 .suffix = "F",
 423                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 424                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 425                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 426                 .num_temp_limit = 3,
 427                 .old_peci_mask = 0x4,
 428         },
 429         [it8721] = {
 430                 .name = "it8721",
 431                 .suffix = "F",
 432                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 433                   | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 434                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 435                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 436                 .num_temp_limit = 3,
 437                 .peci_mask = 0x05,
 438                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 439         },
 440         [it8728] = {
 441                 .name = "it8728",
 442                 .suffix = "F",
 443                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 444                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 445                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 446                   | FEAT_FANCTL_ONOFF,
 447                 .num_temp_limit = 3,
 448                 .peci_mask = 0x07,
 449         },
 450         [it8732] = {
 451                 .name = "it8732",
 452                 .suffix = "F",
 453                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 454                   | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 455                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 456                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 457                 .num_temp_limit = 3,
 458                 .peci_mask = 0x07,
 459                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 460         },
 461         [it8771] = {
 462                 .name = "it8771",
 463                 .suffix = "E",
 464                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 465                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 466                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 467                                 /* PECI: guesswork */
 468                                 /* 12mV ADC (OHM) */
 469                                 /* 16 bit fans (OHM) */
 470                                 /* three fans, always 16 bit (guesswork) */
 471                 .num_temp_limit = 3,
 472                 .peci_mask = 0x07,
 473         },
 474         [it8772] = {
 475                 .name = "it8772",
 476                 .suffix = "E",
 477                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 478                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 479                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 480                                 /* PECI (coreboot) */
 481                                 /* 12mV ADC (HWSensors4, OHM) */
 482                                 /* 16 bit fans (HWSensors4, OHM) */
 483                                 /* three fans, always 16 bit (datasheet) */
 484                 .num_temp_limit = 3,
 485                 .peci_mask = 0x07,
 486         },
 487         [it8781] = {
 488                 .name = "it8781",
 489                 .suffix = "F",
 490                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 491                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 492                   | FEAT_FANCTL_ONOFF,
 493                 .num_temp_limit = 3,
 494                 .old_peci_mask = 0x4,
 495         },
 496         [it8782] = {
 497                 .name = "it8782",
 498                 .suffix = "F",
 499                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 500                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 501                   | FEAT_FANCTL_ONOFF,
 502                 .num_temp_limit = 3,
 503                 .old_peci_mask = 0x4,
 504         },
 505         [it8783] = {
 506                 .name = "it8783",
 507                 .suffix = "E/F",
 508                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 509                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 510                   | FEAT_FANCTL_ONOFF,
 511                 .num_temp_limit = 3,
 512                 .old_peci_mask = 0x4,
 513         },
 514         [it8786] = {
 515                 .name = "it8786",
 516                 .suffix = "E",
 517                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 518                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 519                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 520                 .num_temp_limit = 3,
 521                 .peci_mask = 0x07,
 522         },
 523         [it8790] = {
 524                 .name = "it8790",
 525                 .suffix = "E",
 526                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 527                   | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
 528                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 529                 .num_temp_limit = 3,
 530                 .peci_mask = 0x07,
 531         },
 532         [it8792] = {
 533                 .name = "it8792",
 534                 .suffix = "E",
 535                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 536                   | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
 537                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 538                 .num_temp_limit = 3,
 539                 .peci_mask = 0x07,
 540         },
 541         [it8603] = {
 542                 .name = "it8603",
 543                 .suffix = "E",
 544                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 545                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 546                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 547                 .num_temp_limit = 3,
 548                 .peci_mask = 0x07,
 549         },
 550         [it8607] = {
 551                 .name = "it8607",
 552                 .suffix = "E",
 553                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 554                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 555                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 556                   | FEAT_FANCTL_ONOFF,
 557                 .num_temp_limit = 3,
 558                 .peci_mask = 0x07,
 559         },
 560         [it8620] = {
 561                 .name = "it8620",
 562                 .suffix = "E",
 563                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 564                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 565                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 566                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 567                   | FEAT_FANCTL_ONOFF,
 568                 .num_temp_limit = 3,
 569                 .peci_mask = 0x07,
 570         },
 571         [it8622] = {
 572                 .name = "it8622",
 573                 .suffix = "E",
 574                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 575                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 576                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 577                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 578                 .num_temp_limit = 3,
 579                 .peci_mask = 0x07,
 580         },
 581         [it8628] = {
 582                 .name = "it8628",
 583                 .suffix = "E",
 584                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 585                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 586                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 587                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 588                   | FEAT_FANCTL_ONOFF,
 589                 .num_temp_limit = 3,
 590                 .peci_mask = 0x07,
 591         },
 592         [it8655] = {
 593                 .name = "it8655",
 594                 .suffix = "E",
 595                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 596                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_AVCC3
 597                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 598                 .num_temp_limit = 6,
 599                 .peci_mask = 0x07,
 600         },
 601         [it8665] = {
 602                 .name = "it8665",
 603                 .suffix = "E",
 604                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 605                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_AVCC3
 606                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 607                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 608                 .num_temp_limit = 6,
 609                 .peci_mask = 0x07,
 610         },
 611         [it8686] = {
 612                 .name = "it8686",
 613                 .suffix = "E",
 614                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 615                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 616                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 617                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 618                 .num_temp_limit = 6,
 619                 .peci_mask = 0x07,
 620         },
 621 };
 622
 623 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 624 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 625 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 626 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 627 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 628 #define has_temp_offset(data)   ((data)->features & FEAT_TEMP_OFFSET)
 629 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 630                                  ((data)->peci_mask & BIT(nr)))
 631 #define has_temp_old_peci(data, nr) \
 632                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 633                                  ((data)->old_peci_mask & BIT(nr)))
 634 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 635 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 636                                                      FEAT_SIX_FANS))
 637 #define has_vid(data)           ((data)->features & FEAT_VID)
 638 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 639 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 640 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 641 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 642                                                      | FEAT_SIX_PWM))
 643 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 644 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 645 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 646 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 647 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 648                                                      FEAT_FIVE_FANS | \
 649                                                      FEAT_SIX_FANS))
 650 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 651                                                      FEAT_FIVE_PWM \
 652                                                      | FEAT_SIX_PWM))
 653 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 654 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 655 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 656 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 657
 658 struct it87_sio_data {
 659         enum chips type;
 660         /* Values read from Super-I/O config space */
 661         u8 revision;
 662         u8 vid_value;
 663         u8 beep_pin;
 664         u8 internal;    /* Internal sensors can be labeled */
 665         /* Features skipped based on config or DMI */
 666         u16 skip_in;
 667         u8 skip_vid;
 668         u8 skip_fan;
 669         u8 skip_pwm;
 670         u8 skip_temp;
 671 };
 672
 673 /*
 674  * For each registered chip, we need to keep some data in memory.
 675  * The structure is dynamically allocated.
 676  */
 677 struct it87_data {
 678         const struct attribute_group *groups[7];
 679         enum chips type;
 680         u32 features;
 681         u8 bank;
 682         u8 peci_mask;
 683         u8 old_peci_mask;
 684
 685         const u8 *REG_FAN;
 686         const u8 *REG_FANX;
 687         const u8 *REG_FAN_MIN;
 688         const u8 *REG_FANX_MIN;
 689
 690         const u8 *REG_PWM;
 691
 692         const u8 *REG_TEMP_OFFSET;
 693         const u8 *REG_TEMP_LOW;
 694         const u8 *REG_TEMP_HIGH;
 695
 696         unsigned short addr;
 697         const char *name;
 698         struct mutex update_lock;
 699         char valid;             /* !=0 if following fields are valid */
 700         unsigned long last_updated;     /* In jiffies */
 701
 702         u16 in_scaled;          /* Internal voltage sensors are scaled */
 703         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 704         u16 has_in;             /* Bitfield, voltage sensors enabled */
 705         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 706         u8 has_fan;             /* Bitfield, fans enabled */
 707         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 708         u8 has_temp;            /* Bitfield, temp sensors enabled */
 709         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 710         u8 num_temp_limit;      /* Number of temp limit/offset registers */
 711         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 712         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 713         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 714         bool has_vid;           /* True if VID supported */
 715         u8 vid;                 /* Register encoding, combined */
 716         u8 vrm;
 717         u32 alarms;             /* Register encoding, combined */
 718         bool has_beep;          /* true if beep supported */
 719         u8 beeps;               /* Register encoding */
 720         u8 fan_main_ctrl;       /* Register value */
 721         u8 fan_ctl;             /* Register value */
 722
 723         /*
 724          * The following 3 arrays correspond to the same registers up to
 725          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 726          * 7, and we want to preserve settings on mode changes, so we have
 727          * to track all values separately.
 728          * Starting with the IT8721F, the manual PWM duty cycles are stored
 729          * in separate registers (8-bit values), so the separate tracking
 730          * is no longer needed, but it is still done to keep the driver
 731          * simple.
 732          */
 733         u8 has_pwm;             /* Bitfield, pwm control enabled */
 734         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 735         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 736         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 737
 738         /* Automatic fan speed control registers */
 739         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 740         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 741 };
 742
 743 static int adc_lsb(const struct it87_data *data, int nr)
 744 {
 745         int lsb;
 746
 747         if (has_12mv_adc(data))
 748                 lsb = 120;
 749         else if (has_10_9mv_adc(data))
 750                 lsb = 109;
 751         else if (has_11mv_adc(data))
 752                 lsb = 110;
 753         else
 754                 lsb = 160;
 755         if (data->in_scaled & BIT(nr))
 756                 lsb <<= 1;
 757         return lsb;
 758 }
 759
 760 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 761 {
 762         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 763         return clamp_val(val, 0, 255);
 764 }
 765
 766 static int in_from_reg(const struct it87_data *data, int nr, int val)
 767 {
 768         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 769 }
 770
 771 static inline u8 FAN_TO_REG(long rpm, int div)
 772 {
 773         if (rpm == 0)
 774                 return 255;
 775         rpm = clamp_val(rpm, 1, 1000000);
 776         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 777 }
 778
 779 static inline u16 FAN16_TO_REG(long rpm)
 780 {
 781         if (rpm == 0)
 782                 return 0xffff;
 783         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 784 }
 785
 786 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 787                                 1350000 / ((val) * (div)))
 788 /* The divider is fixed to 2 in 16-bit mode */
 789 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 790                              1350000 / ((val) * 2))
 791
 792 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 793                                     ((val) + 500) / 1000), -128, 127))
 794 #define TEMP_FROM_REG(val) ((val) * 1000)
 795
 796 static u8 pwm_to_reg(const struct it87_data *data, long val)
 797 {
 798         if (has_newer_autopwm(data))
 799                 return val;
 800         else
 801                 return val >> 1;
 802 }
 803
 804 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 805 {
 806         if (has_newer_autopwm(data))
 807                 return reg;
 808         else
 809                 return (reg & 0x7f) << 1;
 810 }
 811
 812 static int DIV_TO_REG(int val)
 813 {
 814         int answer = 0;
 815
 816         while (answer < 7 && (val >>= 1))
 817                 answer++;
 818         return answer;
 819 }
 820
 821 #define DIV_FROM_REG(val) BIT(val)
 822
 823 /*
 824  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 825  * depending on the chip type, to calculate the actual PWM frequency.
 826  *
 827  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 828  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 829  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 830  * sometimes just one. It is unknown if this is a datasheet error or real,
 831  * so this is ignored for now.
 832  */
 833 static const unsigned int pwm_freq[8] = {
 834         48000000,
 835         24000000,
 836         12000000,
 837         8000000,
 838         6000000,
 839         3000000,
 840         1500000,
 841         750000,
 842 };
 843
 844 static int _it87_read_value(struct it87_data *data, u8 reg)
 845 {
 846         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 847         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 848 }
 849
 850 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 851 {
 852         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 853         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 854 }
 855
 856 static void it87_set_bank(struct it87_data *data, u8 bank)
 857 {
 858         if (has_bank_sel(data) && bank != data->bank) {
 859                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 860
 861                 breg &= 0x1f;
 862                 breg |= (bank << 5);
 863                 data->bank = bank;
 864                 _it87_write_value(data, IT87_REG_BANK, breg);
 865         }
 866 }
 867
 868 /*
 869  * Must be called with data->update_lock held, except during initialization.
 870  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 871  * would slow down the IT87 access and should not be necessary.
 872  */
 873 static int it87_read_value(struct it87_data *data, u16 reg)
 874 {
 875         it87_set_bank(data, reg >> 8);
 876         return _it87_read_value(data, reg & 0xff);
 877 }
 878
 879 /*
 880  * Must be called with data->update_lock held, except during initialization.
 881  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 882  * would slow down the IT87 access and should not be necessary.
 883  */
 884 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
 885 {
 886         it87_set_bank(data, reg >> 8);
 887         _it87_write_value(data, reg & 0xff, value);
 888 }
 889
 890 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 891 {
 892         data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]);
 893         if (has_newer_autopwm(data)) {
 894                 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 895                 data->pwm_duty[nr] = it87_read_value(data,
 896                                                      IT87_REG_PWM_DUTY[nr]);
 897         } else {
 898                 if (data->pwm_ctrl[nr] & 0x80)  /* Automatic mode */
 899                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 900                 else                            /* Manual mode */
 901                         data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
 902         }
 903
 904         if (has_old_autopwm(data)) {
 905                 int i;
 906
 907                 for (i = 0; i < 5 ; i++)
 908                         data->auto_temp[nr][i] = it87_read_value(data,
 909                                                 IT87_REG_AUTO_TEMP(nr, i));
 910                 for (i = 0; i < 3 ; i++)
 911                         data->auto_pwm[nr][i] = it87_read_value(data,
 912                                                 IT87_REG_AUTO_PWM(nr, i));
 913         } else if (has_newer_autopwm(data)) {
 914                 int i;
 915
 916                 /*
 917                  * 0: temperature hysteresis (base + 5)
 918                  * 1: fan off temperature (base + 0)
 919                  * 2: fan start temperature (base + 1)
 920                  * 3: fan max temperature (base + 2)
 921                  */
 922                 data->auto_temp[nr][0] =
 923                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
 924
 925                 for (i = 0; i < 3 ; i++)
 926                         data->auto_temp[nr][i + 1] =
 927                                 it87_read_value(data,
 928                                                 IT87_REG_AUTO_TEMP(nr, i));
 929                 /*
 930                  * 0: start pwm value (base + 3)
 931                  * 1: pwm slope (base + 4, 1/8th pwm)
 932                  */
 933                 data->auto_pwm[nr][0] =
 934                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
 935                 data->auto_pwm[nr][1] =
 936                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
 937         }
 938 }
 939
 940 static struct it87_data *it87_update_device(struct device *dev)
 941 {
 942         struct it87_data *data = dev_get_drvdata(dev);
 943         int i;
 944
 945         mutex_lock(&data->update_lock);
 946
 947         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
 948             !data->valid) {
 949                 if (update_vbat) {
 950                         /*
 951                          * Cleared after each update, so reenable.  Value
 952                          * returned by this read will be previous value
 953                          */
 954                         it87_write_value(data, IT87_REG_CONFIG,
 955                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
 956                 }
 957                 for (i = 0; i < NUM_VIN; i++) {
 958                         if (!(data->has_in & BIT(i)))
 959                                 continue;
 960
 961                         data->in[i][0] =
 962                                 it87_read_value(data, IT87_REG_VIN[i]);
 963
 964                         /* VBAT and AVCC don't have limit registers */
 965                         if (i >= NUM_VIN_LIMIT)
 966                                 continue;
 967
 968                         data->in[i][1] =
 969                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
 970                         data->in[i][2] =
 971                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
 972                 }
 973
 974                 for (i = 0; i < NUM_FAN; i++) {
 975                         /* Skip disabled fans */
 976                         if (!(data->has_fan & BIT(i)))
 977                                 continue;
 978
 979                         data->fan[i][1] =
 980                                 it87_read_value(data, data->REG_FAN_MIN[i]);
 981                         data->fan[i][0] = it87_read_value(data,
 982                                        data->REG_FAN[i]);
 983                         /* Add high byte if in 16-bit mode */
 984                         if (has_16bit_fans(data)) {
 985                                 data->fan[i][0] |= it87_read_value(data,
 986                                                 data->REG_FANX[i]) << 8;
 987                                 data->fan[i][1] |= it87_read_value(data,
 988                                                 data->REG_FANX_MIN[i]) << 8;
 989                         }
 990                 }
 991                 for (i = 0; i < NUM_TEMP; i++) {
 992                         if (!(data->has_temp & BIT(i)))
 993                                 continue;
 994                         data->temp[i][0] =
 995                                 it87_read_value(data, IT87_REG_TEMP(i));
 996
 997                         if (i >= data->num_temp_limit)
 998                                 continue;
 999
1000                         if (has_temp_offset(data))
1001                                 data->temp[i][3] =
1002                                   it87_read_value(data,
1003                                                   data->REG_TEMP_OFFSET[i]);
1004
1005                         data->temp[i][1] =
1006                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1007                         data->temp[i][2] =
1008                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1009                 }
1010
1011                 /* Newer chips don't have clock dividers */
1012                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1013                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1014                         data->fan_div[0] = i & 0x07;
1015                         data->fan_div[1] = (i >> 3) & 0x07;
1016                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1017                 }
1018
1019                 data->alarms =
1020                         it87_read_value(data, IT87_REG_ALARM1) |
1021                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1022                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1023                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1024
1025                 data->fan_main_ctrl = it87_read_value(data,
1026                                 IT87_REG_FAN_MAIN_CTRL);
1027                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1028                 for (i = 0; i < NUM_PWM; i++) {
1029                         if (!(data->has_pwm & BIT(i)))
1030                                 continue;
1031                         it87_update_pwm_ctrl(data, i);
1032                 }
1033
1034                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1035                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1036                 /*
1037                  * The IT8705F does not have VID capability.
1038                  * The IT8718F and later don't use IT87_REG_VID for the
1039                  * same purpose.
1040                  */
1041                 if (data->type == it8712 || data->type == it8716) {
1042                         data->vid = it87_read_value(data, IT87_REG_VID);
1043                         /*
1044                          * The older IT8712F revisions had only 5 VID pins,
1045                          * but we assume it is always safe to read 6 bits.
1046                          */
1047                         data->vid &= 0x3f;
1048                 }
1049                 data->last_updated = jiffies;
1050                 data->valid = 1;
1051         }
1052
1053         mutex_unlock(&data->update_lock);
1054
1055         return data;
1056 }
1057
1058 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1059                        char *buf)
1060 {
1061         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1062         struct it87_data *data = it87_update_device(dev);
1063         int index = sattr->index;
1064         int nr = sattr->nr;
1065
1066         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1067 }
1068
1069 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1070                       const char *buf, size_t count)
1071 {
1072         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1073         struct it87_data *data = dev_get_drvdata(dev);
1074         int index = sattr->index;
1075         int nr = sattr->nr;
1076         unsigned long val;
1077
1078         if (kstrtoul(buf, 10, &val) < 0)
1079                 return -EINVAL;
1080
1081         mutex_lock(&data->update_lock);
1082         data->in[nr][index] = in_to_reg(data, nr, val);
1083         it87_write_value(data,
1084                          index == 1 ? IT87_REG_VIN_MIN(nr)
1085                                     : IT87_REG_VIN_MAX(nr),
1086                          data->in[nr][index]);
1087         mutex_unlock(&data->update_lock);
1088         return count;
1089 }
1090
1091 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1092 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1093                             0, 1);
1094 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1095                             0, 2);
1096
1097 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1098 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1099                             1, 1);
1100 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1101                             1, 2);
1102
1103 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1104 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1105                             2, 1);
1106 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1107                             2, 2);
1108
1109 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1110 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1111                             3, 1);
1112 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1113                             3, 2);
1114
1115 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1116 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1117                             4, 1);
1118 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1119                             4, 2);
1120
1121 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1122 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1123                             5, 1);
1124 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1125                             5, 2);
1126
1127 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1128 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1129                             6, 1);
1130 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1131                             6, 2);
1132
1133 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1134 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1135                             7, 1);
1136 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1137                             7, 2);
1138
1139 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1140 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1141 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1142 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1143 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1144
1145 /* Up to 6 temperatures */
1146 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1147                          char *buf)
1148 {
1149         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1150         int nr = sattr->nr;
1151         int index = sattr->index;
1152         struct it87_data *data = it87_update_device(dev);
1153
1154         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1155 }
1156
1157 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1158                         const char *buf, size_t count)
1159 {
1160         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1161         int nr = sattr->nr;
1162         int index = sattr->index;
1163         struct it87_data *data = dev_get_drvdata(dev);
1164         long val;
1165         u8 reg, regval;
1166
1167         if (kstrtol(buf, 10, &val) < 0)
1168                 return -EINVAL;
1169
1170         mutex_lock(&data->update_lock);
1171
1172         switch (index) {
1173         default:
1174         case 1:
1175                 reg = data->REG_TEMP_LOW[nr];
1176                 break;
1177         case 2:
1178                 reg = data->REG_TEMP_HIGH[nr];
1179                 break;
1180         case 3:
1181                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1182                 if (!(regval & 0x80)) {
1183                         regval |= 0x80;
1184                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1185                 }
1186                 data->valid = 0;
1187                 reg = data->REG_TEMP_OFFSET[nr];
1188                 break;
1189         }
1190
1191         data->temp[nr][index] = TEMP_TO_REG(val);
1192         it87_write_value(data, reg, data->temp[nr][index]);
1193         mutex_unlock(&data->update_lock);
1194         return count;
1195 }
1196
1197 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1198 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1199                             0, 1);
1200 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1201                             0, 2);
1202 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1203                             set_temp, 0, 3);
1204 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1205 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1206                             1, 1);
1207 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1208                             1, 2);
1209 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1210                             set_temp, 1, 3);
1211 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1212 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1213                             2, 1);
1214 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1215                             2, 2);
1216 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1217                             set_temp, 2, 3);
1218 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1219 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1220                             3, 1);
1221 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1222                             3, 2);
1223 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1224                             set_temp, 3, 3);
1225 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1226 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1227                             4, 1);
1228 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1229                             4, 2);
1230 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1231                             set_temp, 4, 3);
1232 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1233 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1234                             5, 1);
1235 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1236                             5, 2);
1237 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1238                             set_temp, 5, 3);
1239
1240 static int get_temp_type(struct it87_data *data, int index)
1241 {
1242         u8 reg, extra;
1243         int type = 0;
1244
1245         if (has_bank_sel(data)) {
1246                 int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
1247                 u8 src1, src2;
1248
1249                 src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
1250                 src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
1251
1252                 switch (data->type) {
1253                 case it8686:
1254                         switch (src1) {
1255                         case 0:
1256                                 if (index >= 3)
1257                                         return 4;
1258                                 break;
1259                         case 1:
1260                                 if (index == 1 || index == 2 ||
1261                                           index == 4 || index == 5)
1262                                         return 6;
1263                                 break;
1264                         case 2:
1265                                 if (index == 2 || index == 6)
1266                                         return 5;
1267                                 break;
1268                         default:
1269                                 break;
1270                         }
1271                         break;
1272                 case it8655:
1273                 case it8665:
1274                         if (src1 < 3) {
1275                                 index = src1;
1276                                 break;
1277                         }
1278                         switch(src1) {
1279                         case 3:
1280                                 type = (src2 & BIT(index)) ? 6 : 5;
1281                                 break;
1282                         case 4 ... 8:
1283                                 type = (src2 & BIT(index)) ? 4 : 6;
1284                                 break;
1285                         case 9:
1286                                 type = (src2 & BIT(index)) ? 5 : 0;
1287                                 break;
1288                         default:
1289                                 break;
1290                         }
1291                         return type;
1292                 default:
1293                         return 0;
1294                 }
1295         }
1296         if (index >= 3)
1297                 return 0;
1298
1299         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1300         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1301
1302         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1303             (has_temp_old_peci(data, index) && (extra & 0x80)))
1304                 type = 6;               /* Intel PECI */
1305         if (reg & BIT(index))
1306                 type = 3;               /* thermal diode */
1307         else if (reg & BIT(index + 3))
1308                 type = 4;               /* thermistor */
1309
1310         return type;
1311 }
1312
1313 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1314                               char *buf)
1315 {
1316         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1317         struct it87_data *data = it87_update_device(dev);
1318         int type = get_temp_type(data, sensor_attr->index);
1319
1320         return sprintf(buf, "%d\n", type);
1321 }
1322
1323 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1324                              const char *buf, size_t count)
1325 {
1326         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1327         int nr = sensor_attr->index;
1328
1329         struct it87_data *data = dev_get_drvdata(dev);
1330         long val;
1331         u8 reg, extra;
1332
1333         if (kstrtol(buf, 10, &val) < 0)
1334                 return -EINVAL;
1335
1336         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1337         reg &= ~(1 << nr);
1338         reg &= ~(8 << nr);
1339         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1340                 reg &= 0x3f;
1341         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1342         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1343                 extra &= 0x7f;
1344         if (val == 2) { /* backwards compatibility */
1345                 dev_warn(dev,
1346                          "Sensor type 2 is deprecated, please use 4 instead\n");
1347                 val = 4;
1348         }
1349         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1350         if (val == 3)
1351                 reg |= 1 << nr;
1352         else if (val == 4)
1353                 reg |= 8 << nr;
1354         else if (has_temp_peci(data, nr) && val == 6)
1355                 reg |= (nr + 1) << 6;
1356         else if (has_temp_old_peci(data, nr) && val == 6)
1357                 extra |= 0x80;
1358         else if (val != 0)
1359                 return -EINVAL;
1360
1361         mutex_lock(&data->update_lock);
1362         data->sensor = reg;
1363         data->extra = extra;
1364         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1365         if (has_temp_old_peci(data, nr))
1366                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1367         data->valid = 0;        /* Force cache refresh */
1368         mutex_unlock(&data->update_lock);
1369         return count;
1370 }
1371
1372 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1373                           set_temp_type, 0);
1374 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1375                           set_temp_type, 1);
1376 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1377                           set_temp_type, 2);
1378 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1379                           set_temp_type, 3);
1380 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1381                           set_temp_type, 4);
1382 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1383                           set_temp_type, 5);
1384
1385 /* 6 Fans */
1386
1387 static int pwm_mode(const struct it87_data *data, int nr)
1388 {
1389         if (has_fanctl_onoff(data) && nr < 3 &&
1390             !(data->fan_main_ctrl & BIT(nr)))
1391                 return 0;                               /* Full speed */
1392         if (data->pwm_ctrl[nr] & 0x80)
1393                 return 2;                               /* Automatic mode */
1394         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1395             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1396                 return 0;                       /* Full speed */
1397
1398         return 1;                               /* Manual mode */
1399 }
1400
1401 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1402                         char *buf)
1403 {
1404         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1405         int nr = sattr->nr;
1406         int index = sattr->index;
1407         int speed;
1408         struct it87_data *data = it87_update_device(dev);
1409
1410         speed = has_16bit_fans(data) ?
1411                 FAN16_FROM_REG(data->fan[nr][index]) :
1412                 FAN_FROM_REG(data->fan[nr][index],
1413                              DIV_FROM_REG(data->fan_div[nr]));
1414         return sprintf(buf, "%d\n", speed);
1415 }
1416
1417 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1418                             char *buf)
1419 {
1420         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1421         struct it87_data *data = it87_update_device(dev);
1422         int nr = sensor_attr->index;
1423
1424         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1425 }
1426
1427 static ssize_t show_pwm_enable(struct device *dev,
1428                                struct device_attribute *attr, char *buf)
1429 {
1430         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1431         struct it87_data *data = it87_update_device(dev);
1432         int nr = sensor_attr->index;
1433
1434         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1435 }
1436
1437 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1438                         char *buf)
1439 {
1440         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1441         struct it87_data *data = it87_update_device(dev);
1442         int nr = sensor_attr->index;
1443
1444         return sprintf(buf, "%d\n",
1445                        pwm_from_reg(data, data->pwm_duty[nr]));
1446 }
1447
1448 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1449                              char *buf)
1450 {
1451         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1452         struct it87_data *data = it87_update_device(dev);
1453         int nr = sensor_attr->index;
1454         unsigned int freq;
1455         int index;
1456
1457         if (has_pwm_freq2(data) && nr == 1)
1458                 index = (data->extra >> 4) & 0x07;
1459         else
1460                 index = (data->fan_ctl >> 4) & 0x07;
1461
1462         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1463
1464         return sprintf(buf, "%u\n", freq);
1465 }
1466
1467 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1468                        const char *buf, size_t count)
1469 {
1470         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1471         int nr = sattr->nr;
1472         int index = sattr->index;
1473
1474         struct it87_data *data = dev_get_drvdata(dev);
1475         long val;
1476         u8 reg;
1477
1478         if (kstrtol(buf, 10, &val) < 0)
1479                 return -EINVAL;
1480
1481         mutex_lock(&data->update_lock);
1482
1483         if (has_16bit_fans(data)) {
1484                 data->fan[nr][index] = FAN16_TO_REG(val);
1485                 it87_write_value(data, data->REG_FAN_MIN[nr],
1486                                  data->fan[nr][index] & 0xff);
1487                 it87_write_value(data, data->REG_FANX_MIN[nr],
1488                                  data->fan[nr][index] >> 8);
1489         } else {
1490                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1491                 switch (nr) {
1492                 case 0:
1493                         data->fan_div[nr] = reg & 0x07;
1494                         break;
1495                 case 1:
1496                         data->fan_div[nr] = (reg >> 3) & 0x07;
1497                         break;
1498                 case 2:
1499                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1500                         break;
1501                 }
1502                 data->fan[nr][index] =
1503                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1504                 it87_write_value(data, data->REG_FAN_MIN[nr],
1505                                  data->fan[nr][index]);
1506         }
1507
1508         mutex_unlock(&data->update_lock);
1509         return count;
1510 }
1511
1512 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1513                            const char *buf, size_t count)
1514 {
1515         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1516         struct it87_data *data = dev_get_drvdata(dev);
1517         int nr = sensor_attr->index;
1518         unsigned long val;
1519         int min;
1520         u8 old;
1521
1522         if (kstrtoul(buf, 10, &val) < 0)
1523                 return -EINVAL;
1524
1525         mutex_lock(&data->update_lock);
1526         old = it87_read_value(data, IT87_REG_FAN_DIV);
1527
1528         /* Save fan min limit */
1529         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1530
1531         switch (nr) {
1532         case 0:
1533         case 1:
1534                 data->fan_div[nr] = DIV_TO_REG(val);
1535                 break;
1536         case 2:
1537                 if (val < 8)
1538                         data->fan_div[nr] = 1;
1539                 else
1540                         data->fan_div[nr] = 3;
1541         }
1542         val = old & 0x80;
1543         val |= (data->fan_div[0] & 0x07);
1544         val |= (data->fan_div[1] & 0x07) << 3;
1545         if (data->fan_div[2] == 3)
1546                 val |= 0x1 << 6;
1547         it87_write_value(data, IT87_REG_FAN_DIV, val);
1548
1549         /* Restore fan min limit */
1550         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1551         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1552
1553         mutex_unlock(&data->update_lock);
1554         return count;
1555 }
1556
1557 /* Returns 0 if OK, -EINVAL otherwise */
1558 static int check_trip_points(struct device *dev, int nr)
1559 {
1560         const struct it87_data *data = dev_get_drvdata(dev);
1561         int i, err = 0;
1562
1563         if (has_old_autopwm(data)) {
1564                 for (i = 0; i < 3; i++) {
1565                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1566                                 err = -EINVAL;
1567                 }
1568                 for (i = 0; i < 2; i++) {
1569                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1570                                 err = -EINVAL;
1571                 }
1572         } else if (has_newer_autopwm(data)) {
1573                 for (i = 1; i < 3; i++) {
1574                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1575                                 err = -EINVAL;
1576                 }
1577         }
1578
1579         if (err) {
1580                 dev_err(dev,
1581                         "Inconsistent trip points, not switching to automatic mode\n");
1582                 dev_err(dev, "Adjust the trip points and try again\n");
1583         }
1584         return err;
1585 }
1586
1587 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1588                               const char *buf, size_t count)
1589 {
1590         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1591         struct it87_data *data = dev_get_drvdata(dev);
1592         int nr = sensor_attr->index;
1593         long val;
1594
1595         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1596                 return -EINVAL;
1597
1598         /* Check trip points before switching to automatic mode */
1599         if (val == 2) {
1600                 if (check_trip_points(dev, nr) < 0)
1601                         return -EINVAL;
1602         }
1603
1604         mutex_lock(&data->update_lock);
1605
1606         if (val == 0) {
1607                 if (nr < 3 && has_fanctl_onoff(data)) {
1608                         int tmp;
1609                         /* make sure the fan is on when in on/off mode */
1610                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1611                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1612                         /* set on/off mode */
1613                         data->fan_main_ctrl &= ~BIT(nr);
1614                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1615                                          data->fan_main_ctrl);
1616                 } else {
1617                         u8 ctrl;
1618
1619                         /* No on/off mode, set maximum pwm value */
1620                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1621                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1622                                          data->pwm_duty[nr]);
1623                         /* and set manual mode */
1624                         if (has_newer_autopwm(data)) {
1625                                 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1626                                         data->pwm_temp_map[nr];
1627                         } else {
1628                                 ctrl = data->pwm_duty[nr];
1629                         }
1630                         data->pwm_ctrl[nr] = ctrl;
1631                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1632                 }
1633         } else {
1634                 u8 ctrl;
1635
1636                 if (has_newer_autopwm(data)) {
1637                         ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1638                                 data->pwm_temp_map[nr];
1639                         if (val != 1)
1640                                 ctrl |= 0x80;
1641                 } else {
1642                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1643                 }
1644                 data->pwm_ctrl[nr] = ctrl;
1645                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1646
1647                 if (has_fanctl_onoff(data) && nr < 3) {
1648                         /* set SmartGuardian mode */
1649                         data->fan_main_ctrl |= BIT(nr);
1650                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1651                                          data->fan_main_ctrl);
1652                 }
1653         }
1654
1655         mutex_unlock(&data->update_lock);
1656         return count;
1657 }
1658
1659 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1660                        const char *buf, size_t count)
1661 {
1662         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1663         struct it87_data *data = dev_get_drvdata(dev);
1664         int nr = sensor_attr->index;
1665         long val;
1666
1667         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1668                 return -EINVAL;
1669
1670         mutex_lock(&data->update_lock);
1671         it87_update_pwm_ctrl(data, nr);
1672         if (has_newer_autopwm(data)) {
1673                 /*
1674                  * If we are in automatic mode, the PWM duty cycle register
1675                  * is read-only so we can't write the value.
1676                  */
1677                 if (data->pwm_ctrl[nr] & 0x80) {
1678                         mutex_unlock(&data->update_lock);
1679                         return -EBUSY;
1680                 }
1681                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1682                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1683                                  data->pwm_duty[nr]);
1684         } else {
1685                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1686                 /*
1687                  * If we are in manual mode, write the duty cycle immediately;
1688                  * otherwise, just store it for later use.
1689                  */
1690                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1691                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1692                         it87_write_value(data, data->REG_PWM[nr],
1693                                          data->pwm_ctrl[nr]);
1694                 }
1695         }
1696         mutex_unlock(&data->update_lock);
1697         return count;
1698 }
1699
1700 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1701                             const char *buf, size_t count)
1702 {
1703         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1704         struct it87_data *data = dev_get_drvdata(dev);
1705         int nr = sensor_attr->index;
1706         unsigned long val;
1707         int i;
1708
1709         if (kstrtoul(buf, 10, &val) < 0)
1710                 return -EINVAL;
1711
1712         val = clamp_val(val, 0, 1000000);
1713         val *= has_newer_autopwm(data) ? 256 : 128;
1714
1715         /* Search for the nearest available frequency */
1716         for (i = 0; i < 7; i++) {
1717                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1718                         break;
1719         }
1720
1721         mutex_lock(&data->update_lock);
1722         if (nr == 0) {
1723                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1724                 data->fan_ctl |= i << 4;
1725                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1726         } else {
1727                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1728                 data->extra |= i << 4;
1729                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1730         }
1731         mutex_unlock(&data->update_lock);
1732
1733         return count;
1734 }
1735
1736 static ssize_t show_pwm_temp_map(struct device *dev,
1737                                  struct device_attribute *attr, char *buf)
1738 {
1739         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1740         struct it87_data *data = it87_update_device(dev);
1741         int nr = sensor_attr->index;
1742         int map;
1743
1744         map = data->pwm_temp_map[nr];
1745         if (map >= 3)
1746                 map = 0;        /* Should never happen */
1747         if (nr >= 3)            /* pwm channels 3..6 map to temp4..6 */
1748                 map += 3;
1749
1750         return sprintf(buf, "%d\n", (int)BIT(map));
1751 }
1752
1753 static ssize_t set_pwm_temp_map(struct device *dev,
1754                                 struct device_attribute *attr, const char *buf,
1755                                 size_t count)
1756 {
1757         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1758         struct it87_data *data = dev_get_drvdata(dev);
1759         int nr = sensor_attr->index;
1760         long val;
1761         u8 reg;
1762
1763         if (kstrtol(buf, 10, &val) < 0)
1764                 return -EINVAL;
1765
1766         if (nr >= 3)
1767                 val -= 3;
1768
1769         switch (val) {
1770         case BIT(0):
1771                 reg = 0x00;
1772                 break;
1773         case BIT(1):
1774                 reg = 0x01;
1775                 break;
1776         case BIT(2):
1777                 reg = 0x02;
1778                 break;
1779         default:
1780                 return -EINVAL;
1781         }
1782
1783         mutex_lock(&data->update_lock);
1784         it87_update_pwm_ctrl(data, nr);
1785         data->pwm_temp_map[nr] = reg;
1786         /*
1787          * If we are in automatic mode, write the temp mapping immediately;
1788          * otherwise, just store it for later use.
1789          */
1790         if (data->pwm_ctrl[nr] & 0x80) {
1791                 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
1792                                                 data->pwm_temp_map[nr];
1793                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1794         }
1795         mutex_unlock(&data->update_lock);
1796         return count;
1797 }
1798
1799 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1800                              char *buf)
1801 {
1802         struct it87_data *data = it87_update_device(dev);
1803         struct sensor_device_attribute_2 *sensor_attr =
1804                         to_sensor_dev_attr_2(attr);
1805         int nr = sensor_attr->nr;
1806         int point = sensor_attr->index;
1807
1808         return sprintf(buf, "%d\n",
1809                        pwm_from_reg(data, data->auto_pwm[nr][point]));
1810 }
1811
1812 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1813                             const char *buf, size_t count)
1814 {
1815         struct it87_data *data = dev_get_drvdata(dev);
1816         struct sensor_device_attribute_2 *sensor_attr =
1817                         to_sensor_dev_attr_2(attr);
1818         int nr = sensor_attr->nr;
1819         int point = sensor_attr->index;
1820         int regaddr;
1821         long val;
1822
1823         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1824                 return -EINVAL;
1825
1826         mutex_lock(&data->update_lock);
1827         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1828         if (has_newer_autopwm(data))
1829                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1830         else
1831                 regaddr = IT87_REG_AUTO_PWM(nr, point);
1832         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1833         mutex_unlock(&data->update_lock);
1834         return count;
1835 }
1836
1837 static ssize_t show_auto_pwm_slope(struct device *dev,
1838                                    struct device_attribute *attr, char *buf)
1839 {
1840         struct it87_data *data = it87_update_device(dev);
1841         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1842         int nr = sensor_attr->index;
1843
1844         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1845 }
1846
1847 static ssize_t set_auto_pwm_slope(struct device *dev,
1848                                   struct device_attribute *attr,
1849                                   const char *buf, size_t count)
1850 {
1851         struct it87_data *data = dev_get_drvdata(dev);
1852         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1853         int nr = sensor_attr->index;
1854         unsigned long val;
1855
1856         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1857                 return -EINVAL;
1858
1859         mutex_lock(&data->update_lock);
1860         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1861         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1862                          data->auto_pwm[nr][1]);
1863         mutex_unlock(&data->update_lock);
1864         return count;
1865 }
1866
1867 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1868                               char *buf)
1869 {
1870         struct it87_data *data = it87_update_device(dev);
1871         struct sensor_device_attribute_2 *sensor_attr =
1872                         to_sensor_dev_attr_2(attr);
1873         int nr = sensor_attr->nr;
1874         int point = sensor_attr->index;
1875         int reg;
1876
1877         if (has_old_autopwm(data) || point)
1878                 reg = data->auto_temp[nr][point];
1879         else
1880                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1881
1882         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1883 }
1884
1885 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1886                              const char *buf, size_t count)
1887 {
1888         struct it87_data *data = dev_get_drvdata(dev);
1889         struct sensor_device_attribute_2 *sensor_attr =
1890                         to_sensor_dev_attr_2(attr);
1891         int nr = sensor_attr->nr;
1892         int point = sensor_attr->index;
1893         long val;
1894         int reg;
1895
1896         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1897                 return -EINVAL;
1898
1899         mutex_lock(&data->update_lock);
1900         if (has_newer_autopwm(data) && !point) {
1901                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1902                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1903                 data->auto_temp[nr][0] = reg;
1904                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1905         } else {
1906                 reg = TEMP_TO_REG(val);
1907                 data->auto_temp[nr][point] = reg;
1908                 if (has_newer_autopwm(data))
1909                         point--;
1910                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1911         }
1912         mutex_unlock(&data->update_lock);
1913         return count;
1914 }
1915
1916 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1917 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1918                             0, 1);
1919 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1920                           set_fan_div, 0);
1921
1922 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1923 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1924                             1, 1);
1925 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1926                           set_fan_div, 1);
1927
1928 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1929 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1930                             2, 1);
1931 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1932                           set_fan_div, 2);
1933
1934 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1935 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1936                             3, 1);
1937
1938 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1939 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1940                             4, 1);
1941
1942 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1943 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1944                             5, 1);
1945
1946 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1947                           show_pwm_enable, set_pwm_enable, 0);
1948 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1949 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1950                           set_pwm_freq, 0);
1951 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
1952                           show_pwm_temp_map, set_pwm_temp_map, 0);
1953 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1954                             show_auto_pwm, set_auto_pwm, 0, 0);
1955 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1956                             show_auto_pwm, set_auto_pwm, 0, 1);
1957 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1958                             show_auto_pwm, set_auto_pwm, 0, 2);
1959 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1960                             show_auto_pwm, NULL, 0, 3);
1961 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1962                             show_auto_temp, set_auto_temp, 0, 1);
1963 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1964                             show_auto_temp, set_auto_temp, 0, 0);
1965 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1966                             show_auto_temp, set_auto_temp, 0, 2);
1967 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1968                             show_auto_temp, set_auto_temp, 0, 3);
1969 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1970                             show_auto_temp, set_auto_temp, 0, 4);
1971 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
1972                             show_auto_pwm, set_auto_pwm, 0, 0);
1973 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
1974                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
1975
1976 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1977                           show_pwm_enable, set_pwm_enable, 1);
1978 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1979 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
1980 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
1981                           show_pwm_temp_map, set_pwm_temp_map, 1);
1982 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1983                             show_auto_pwm, set_auto_pwm, 1, 0);
1984 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1985                             show_auto_pwm, set_auto_pwm, 1, 1);
1986 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1987                             show_auto_pwm, set_auto_pwm, 1, 2);
1988 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1989                             show_auto_pwm, NULL, 1, 3);
1990 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1991                             show_auto_temp, set_auto_temp, 1, 1);
1992 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1993                             show_auto_temp, set_auto_temp, 1, 0);
1994 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1995                             show_auto_temp, set_auto_temp, 1, 2);
1996 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1997                             show_auto_temp, set_auto_temp, 1, 3);
1998 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1999                             show_auto_temp, set_auto_temp, 1, 4);
2000 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2001                             show_auto_pwm, set_auto_pwm, 1, 0);
2002 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2003                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2004
2005 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2006                           show_pwm_enable, set_pwm_enable, 2);
2007 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2008 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2009 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2010                           show_pwm_temp_map, set_pwm_temp_map, 2);
2011 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2012                             show_auto_pwm, set_auto_pwm, 2, 0);
2013 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2014                             show_auto_pwm, set_auto_pwm, 2, 1);
2015 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2016                             show_auto_pwm, set_auto_pwm, 2, 2);
2017 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2018                             show_auto_pwm, NULL, 2, 3);
2019 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2020                             show_auto_temp, set_auto_temp, 2, 1);
2021 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2022                             show_auto_temp, set_auto_temp, 2, 0);
2023 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2024                             show_auto_temp, set_auto_temp, 2, 2);
2025 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2026                             show_auto_temp, set_auto_temp, 2, 3);
2027 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2028                             show_auto_temp, set_auto_temp, 2, 4);
2029 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2030                             show_auto_pwm, set_auto_pwm, 2, 0);
2031 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2032                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2033
2034 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2035                           show_pwm_enable, set_pwm_enable, 3);
2036 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2037 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2038 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2039                           show_pwm_temp_map, set_pwm_temp_map, 3);
2040 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2041                             show_auto_temp, set_auto_temp, 2, 1);
2042 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2043                             show_auto_temp, set_auto_temp, 2, 0);
2044 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2045                             show_auto_temp, set_auto_temp, 2, 2);
2046 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2047                             show_auto_temp, set_auto_temp, 2, 3);
2048 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2049                             show_auto_pwm, set_auto_pwm, 3, 0);
2050 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2051                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2052
2053 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2054                           show_pwm_enable, set_pwm_enable, 4);
2055 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2056 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2057 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2058                           show_pwm_temp_map, set_pwm_temp_map, 4);
2059 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2060                             show_auto_temp, set_auto_temp, 2, 1);
2061 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2062                             show_auto_temp, set_auto_temp, 2, 0);
2063 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2064                             show_auto_temp, set_auto_temp, 2, 2);
2065 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2066                             show_auto_temp, set_auto_temp, 2, 3);
2067 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2068                             show_auto_pwm, set_auto_pwm, 4, 0);
2069 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2070                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2071
2072 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2073                           show_pwm_enable, set_pwm_enable, 5);
2074 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2075 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2076 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2077                           show_pwm_temp_map, set_pwm_temp_map, 5);
2078 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2079                             show_auto_temp, set_auto_temp, 2, 1);
2080 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2081                             show_auto_temp, set_auto_temp, 2, 0);
2082 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2083                             show_auto_temp, set_auto_temp, 2, 2);
2084 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2085                             show_auto_temp, set_auto_temp, 2, 3);
2086 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2087                             show_auto_pwm, set_auto_pwm, 5, 0);
2088 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2089                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2090
2091 /* Alarms */
2092 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2093                            char *buf)
2094 {
2095         struct it87_data *data = it87_update_device(dev);
2096
2097         return sprintf(buf, "%u\n", data->alarms);
2098 }
2099 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2100
2101 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2102                           char *buf)
2103 {
2104         struct it87_data *data = it87_update_device(dev);
2105         int bitnr = to_sensor_dev_attr(attr)->index;
2106
2107         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2108 }
2109
2110 static ssize_t clear_intrusion(struct device *dev,
2111                                struct device_attribute *attr, const char *buf,
2112                                size_t count)
2113 {
2114         struct it87_data *data = dev_get_drvdata(dev);
2115         int config;
2116         long val;
2117
2118         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2119                 return -EINVAL;
2120
2121         mutex_lock(&data->update_lock);
2122         config = it87_read_value(data, IT87_REG_CONFIG);
2123         if (config < 0) {
2124                 count = config;
2125         } else {
2126                 config |= BIT(5);
2127                 it87_write_value(data, IT87_REG_CONFIG, config);
2128                 /* Invalidate cache to force re-read */
2129                 data->valid = 0;
2130         }
2131         mutex_unlock(&data->update_lock);
2132
2133         return count;
2134 }
2135
2136 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2137 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2138 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2139 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2140 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2141 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2142 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2143 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2144 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2145 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2146 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2147 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2148 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2149 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2150 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2151 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2152 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2153 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2154 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2155 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2156 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2157                           show_alarm, clear_intrusion, 4);
2158
2159 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2160                          char *buf)
2161 {
2162         struct it87_data *data = it87_update_device(dev);
2163         int bitnr = to_sensor_dev_attr(attr)->index;
2164
2165         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2166 }
2167
2168 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2169                         const char *buf, size_t count)
2170 {
2171         int bitnr = to_sensor_dev_attr(attr)->index;
2172         struct it87_data *data = dev_get_drvdata(dev);
2173         long val;
2174
2175         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2176                 return -EINVAL;
2177
2178         mutex_lock(&data->update_lock);
2179         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2180         if (val)
2181                 data->beeps |= BIT(bitnr);
2182         else
2183                 data->beeps &= ~BIT(bitnr);
2184         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2185         mutex_unlock(&data->update_lock);
2186         return count;
2187 }
2188
2189 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2190                           show_beep, set_beep, 1);
2191 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2192 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2193 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2194 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2195 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2196 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2197 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2198 /* fanX_beep writability is set later */
2199 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2200 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2201 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2202 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2203 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2204 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2205 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2206                           show_beep, set_beep, 2);
2207 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2208 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2209 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2210 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2211 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2212
2213 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2214                             char *buf)
2215 {
2216         struct it87_data *data = dev_get_drvdata(dev);
2217
2218         return sprintf(buf, "%u\n", data->vrm);
2219 }
2220
2221 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2222                              const char *buf, size_t count)
2223 {
2224         struct it87_data *data = dev_get_drvdata(dev);
2225         unsigned long val;
2226
2227         if (kstrtoul(buf, 10, &val) < 0)
2228                 return -EINVAL;
2229
2230         data->vrm = val;
2231
2232         return count;
2233 }
2234 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2235
2236 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2237                             char *buf)
2238 {
2239         struct it87_data *data = it87_update_device(dev);
2240
2241         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2242 }
2243 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2244
2245 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2246                           char *buf)
2247 {
2248         static const char * const labels[] = {
2249                 "+5V",
2250                 "5VSB",
2251                 "Vbat",
2252                 "AVCC",
2253         };
2254         static const char * const labels_it8721[] = {
2255                 "+3.3V",
2256                 "3VSB",
2257                 "Vbat",
2258                 "+3.3V",
2259         };
2260         struct it87_data *data = dev_get_drvdata(dev);
2261         int nr = to_sensor_dev_attr(attr)->index;
2262         const char *label;
2263
2264         if (has_vin3_5v(data) && nr == 0)
2265                 label = labels[0];
2266         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2267                  has_11mv_adc(data))
2268                 label = labels_it8721[nr];
2269         else
2270                 label = labels[nr];
2271
2272         return sprintf(buf, "%s\n", label);
2273 }
2274 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2275 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2276 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2277 /* AVCC3 */
2278 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2279
2280 static umode_t it87_in_is_visible(struct kobject *kobj,
2281                                   struct attribute *attr, int index)
2282 {
2283         struct device *dev = container_of(kobj, struct device, kobj);
2284         struct it87_data *data = dev_get_drvdata(dev);
2285         int i = index / 5;      /* voltage index */
2286         int a = index % 5;      /* attribute index */
2287
2288         if (index >= 40) {      /* in8 and higher only have input attributes */
2289                 i = index - 40 + 8;
2290                 a = 0;
2291         }
2292
2293         if (!(data->has_in & BIT(i)))
2294                 return 0;
2295
2296         if (a == 4 && !data->has_beep)
2297                 return 0;
2298
2299         return attr->mode;
2300 }
2301
2302 static struct attribute *it87_attributes_in[] = {
2303         &sensor_dev_attr_in0_input.dev_attr.attr,
2304         &sensor_dev_attr_in0_min.dev_attr.attr,
2305         &sensor_dev_attr_in0_max.dev_attr.attr,
2306         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2307         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2308
2309         &sensor_dev_attr_in1_input.dev_attr.attr,
2310         &sensor_dev_attr_in1_min.dev_attr.attr,
2311         &sensor_dev_attr_in1_max.dev_attr.attr,
2312         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2313         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2314
2315         &sensor_dev_attr_in2_input.dev_attr.attr,
2316         &sensor_dev_attr_in2_min.dev_attr.attr,
2317         &sensor_dev_attr_in2_max.dev_attr.attr,
2318         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2319         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2320
2321         &sensor_dev_attr_in3_input.dev_attr.attr,
2322         &sensor_dev_attr_in3_min.dev_attr.attr,
2323         &sensor_dev_attr_in3_max.dev_attr.attr,
2324         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2325         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2326
2327         &sensor_dev_attr_in4_input.dev_attr.attr,
2328         &sensor_dev_attr_in4_min.dev_attr.attr,
2329         &sensor_dev_attr_in4_max.dev_attr.attr,
2330         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2331         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2332
2333         &sensor_dev_attr_in5_input.dev_attr.attr,
2334         &sensor_dev_attr_in5_min.dev_attr.attr,
2335         &sensor_dev_attr_in5_max.dev_attr.attr,
2336         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2337         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2338
2339         &sensor_dev_attr_in6_input.dev_attr.attr,
2340         &sensor_dev_attr_in6_min.dev_attr.attr,
2341         &sensor_dev_attr_in6_max.dev_attr.attr,
2342         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2343         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2344
2345         &sensor_dev_attr_in7_input.dev_attr.attr,
2346         &sensor_dev_attr_in7_min.dev_attr.attr,
2347         &sensor_dev_attr_in7_max.dev_attr.attr,
2348         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2349         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2350
2351         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2352         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2353         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2354         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2355         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2356         NULL
2357 };
2358
2359 static const struct attribute_group it87_group_in = {
2360         .attrs = it87_attributes_in,
2361         .is_visible = it87_in_is_visible,
2362 };
2363
2364 static umode_t it87_temp_is_visible(struct kobject *kobj,
2365                                     struct attribute *attr, int index)
2366 {
2367         struct device *dev = container_of(kobj, struct device, kobj);
2368         struct it87_data *data = dev_get_drvdata(dev);
2369         int i = index / 7;      /* temperature index */
2370         int a = index % 7;      /* attribute index */
2371
2372         if (!(data->has_temp & BIT(i)))
2373                 return 0;
2374
2375         if (a && i >= data->num_temp_limit)
2376                 return 0;
2377
2378         if (a == 3) {
2379                 int type = get_temp_type(data, i);
2380
2381                 if (type == 0)
2382                         return 0;
2383                 if (has_bank_sel(data))
2384                         return 0444;
2385                 return attr->mode;
2386         }
2387
2388         if (a == 5 && !has_temp_offset(data))
2389                 return 0;
2390
2391         if (a == 6 && !data->has_beep)
2392                 return 0;
2393
2394         return attr->mode;
2395 }
2396
2397 static struct attribute *it87_attributes_temp[] = {
2398         &sensor_dev_attr_temp1_input.dev_attr.attr,
2399         &sensor_dev_attr_temp1_max.dev_attr.attr,
2400         &sensor_dev_attr_temp1_min.dev_attr.attr,
2401         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2402         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2403         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2404         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2405
2406         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2407         &sensor_dev_attr_temp2_max.dev_attr.attr,
2408         &sensor_dev_attr_temp2_min.dev_attr.attr,
2409         &sensor_dev_attr_temp2_type.dev_attr.attr,
2410         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2411         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2412         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2413
2414         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2415         &sensor_dev_attr_temp3_max.dev_attr.attr,
2416         &sensor_dev_attr_temp3_min.dev_attr.attr,
2417         &sensor_dev_attr_temp3_type.dev_attr.attr,
2418         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2419         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2420         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2421
2422         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2423         &sensor_dev_attr_temp4_max.dev_attr.attr,
2424         &sensor_dev_attr_temp4_min.dev_attr.attr,
2425         &sensor_dev_attr_temp4_type.dev_attr.attr,
2426         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2427         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2428         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2429
2430         &sensor_dev_attr_temp5_input.dev_attr.attr,
2431         &sensor_dev_attr_temp5_max.dev_attr.attr,
2432         &sensor_dev_attr_temp5_min.dev_attr.attr,
2433         &sensor_dev_attr_temp5_type.dev_attr.attr,
2434         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2435         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2436         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2437
2438         &sensor_dev_attr_temp6_input.dev_attr.attr,
2439         &sensor_dev_attr_temp6_max.dev_attr.attr,
2440         &sensor_dev_attr_temp6_min.dev_attr.attr,
2441         &sensor_dev_attr_temp6_type.dev_attr.attr,
2442         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2443         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2444         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2445         NULL
2446 };
2447
2448 static const struct attribute_group it87_group_temp = {
2449         .attrs = it87_attributes_temp,
2450         .is_visible = it87_temp_is_visible,
2451 };
2452
2453 static umode_t it87_is_visible(struct kobject *kobj,
2454                                struct attribute *attr, int index)
2455 {
2456         struct device *dev = container_of(kobj, struct device, kobj);
2457         struct it87_data *data = dev_get_drvdata(dev);
2458
2459         if ((index == 2 || index == 3) && !data->has_vid)
2460                 return 0;
2461
2462         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2463                 return 0;
2464
2465         return attr->mode;
2466 }
2467
2468 static struct attribute *it87_attributes[] = {
2469         &dev_attr_alarms.attr,
2470         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2471         &dev_attr_vrm.attr,                             /* 2 */
2472         &dev_attr_cpu0_vid.attr,                        /* 3 */
2473         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2474         &sensor_dev_attr_in7_label.dev_attr.attr,
2475         &sensor_dev_attr_in8_label.dev_attr.attr,
2476         &sensor_dev_attr_in9_label.dev_attr.attr,
2477         NULL
2478 };
2479
2480 static const struct attribute_group it87_group = {
2481         .attrs = it87_attributes,
2482         .is_visible = it87_is_visible,
2483 };
2484
2485 static umode_t it87_fan_is_visible(struct kobject *kobj,
2486                                    struct attribute *attr, int index)
2487 {
2488         struct device *dev = container_of(kobj, struct device, kobj);
2489         struct it87_data *data = dev_get_drvdata(dev);
2490         int i = index / 5;      /* fan index */
2491         int a = index % 5;      /* attribute index */
2492
2493         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2494                 i = (index - 15) / 4 + 3;
2495                 a = (index - 15) % 4;
2496         }
2497
2498         if (!(data->has_fan & BIT(i)))
2499                 return 0;
2500
2501         if (a == 3) {                           /* beep */
2502                 if (!data->has_beep)
2503                         return 0;
2504                 /* first fan beep attribute is writable */
2505                 if (i == __ffs(data->has_fan))
2506                         return attr->mode | S_IWUSR;
2507         }
2508
2509         if (a == 4 && has_16bit_fans(data))     /* divisor */
2510                 return 0;
2511
2512         return attr->mode;
2513 }
2514
2515 static struct attribute *it87_attributes_fan[] = {
2516         &sensor_dev_attr_fan1_input.dev_attr.attr,
2517         &sensor_dev_attr_fan1_min.dev_attr.attr,
2518         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2519         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2520         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2521
2522         &sensor_dev_attr_fan2_input.dev_attr.attr,
2523         &sensor_dev_attr_fan2_min.dev_attr.attr,
2524         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2525         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2526         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2527
2528         &sensor_dev_attr_fan3_input.dev_attr.attr,
2529         &sensor_dev_attr_fan3_min.dev_attr.attr,
2530         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2531         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2532         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2533
2534         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2535         &sensor_dev_attr_fan4_min.dev_attr.attr,
2536         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2537         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2538
2539         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2540         &sensor_dev_attr_fan5_min.dev_attr.attr,
2541         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2542         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2543
2544         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2545         &sensor_dev_attr_fan6_min.dev_attr.attr,
2546         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2547         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2548         NULL
2549 };
2550
2551 static const struct attribute_group it87_group_fan = {
2552         .attrs = it87_attributes_fan,
2553         .is_visible = it87_fan_is_visible,
2554 };
2555
2556 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2557                                    struct attribute *attr, int index)
2558 {
2559         struct device *dev = container_of(kobj, struct device, kobj);
2560         struct it87_data *data = dev_get_drvdata(dev);
2561         int i = index / 4;      /* pwm index */
2562         int a = index % 4;      /* attribute index */
2563
2564         if (!(data->has_pwm & BIT(i)))
2565                 return 0;
2566
2567         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2568         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2569                 return attr->mode | S_IWUSR;
2570
2571         /* pwm2_freq is writable if there are two pwm frequency selects */
2572         if (has_pwm_freq2(data) && i == 1 && a == 2)
2573                 return attr->mode | S_IWUSR;
2574
2575         return attr->mode;
2576 }
2577
2578 static struct attribute *it87_attributes_pwm[] = {
2579         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2580         &sensor_dev_attr_pwm1.dev_attr.attr,
2581         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2582         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2583
2584         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2585         &sensor_dev_attr_pwm2.dev_attr.attr,
2586         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2587         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2588
2589         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2590         &sensor_dev_attr_pwm3.dev_attr.attr,
2591         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2592         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2593
2594         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2595         &sensor_dev_attr_pwm4.dev_attr.attr,
2596         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2597         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2598
2599         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2600         &sensor_dev_attr_pwm5.dev_attr.attr,
2601         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2602         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2603
2604         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2605         &sensor_dev_attr_pwm6.dev_attr.attr,
2606         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2607         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2608
2609         NULL
2610 };
2611
2612 static const struct attribute_group it87_group_pwm = {
2613         .attrs = it87_attributes_pwm,
2614         .is_visible = it87_pwm_is_visible,
2615 };
2616
2617 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2618                                         struct attribute *attr, int index)
2619 {
2620         struct device *dev = container_of(kobj, struct device, kobj);
2621         struct it87_data *data = dev_get_drvdata(dev);
2622         int i = index / 11;     /* pwm index */
2623         int a = index % 11;     /* attribute index */
2624
2625         if (index >= 33) {      /* pwm 4..6 */
2626                 i = (index - 33) / 6 + 3;
2627                 a = (index - 33) % 6 + 4;
2628         }
2629
2630         if (!(data->has_pwm & BIT(i)))
2631                 return 0;
2632
2633         if (has_newer_autopwm(data)) {
2634                 if (a < 4)      /* no auto point pwm */
2635                         return 0;
2636                 if (a == 8)     /* no auto_point4 */
2637                         return 0;
2638         }
2639         if (has_old_autopwm(data)) {
2640                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2641                         return 0;
2642         }
2643
2644         return attr->mode;
2645 }
2646
2647 static struct attribute *it87_attributes_auto_pwm[] = {
2648         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2649         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2650         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2651         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2652         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2653         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2654         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2655         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2656         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2657         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2658         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2659
2660         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2661         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2662         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2663         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2664         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2665         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2666         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2667         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2668         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2669         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2670         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2671
2672         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2673         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2674         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2675         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2676         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2677         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2678         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2679         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2680         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2681         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2682         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2683
2684         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2685         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2686         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2687         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2688         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2689         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2690
2691         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2692         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2693         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2694         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2695         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2696         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2697
2698         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2699         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2700         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2701         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2702         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2703         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2704
2705         NULL,
2706 };
2707
2708 static const struct attribute_group it87_group_auto_pwm = {
2709         .attrs = it87_attributes_auto_pwm,
2710         .is_visible = it87_auto_pwm_is_visible,
2711 };
2712
2713 /* SuperIO detection - will change isa_address if a chip is found */
2714 static int __init it87_find(int sioaddr, unsigned short *address,
2715                             struct it87_sio_data *sio_data)
2716 {
2717         int err;
2718         u16 chip_type;
2719         const struct it87_devices *config;
2720
2721         err = superio_enter(sioaddr);
2722         if (err)
2723                 return err;
2724
2725         err = -ENODEV;
2726         chip_type = superio_inw(sioaddr, DEVID);
2727         if (chip_type == 0xffff)
2728                 goto exit;
2729
2730         if (force_id)
2731                 chip_type = force_id;
2732
2733         switch (chip_type) {
2734         case IT8705F_DEVID:
2735                 sio_data->type = it87;
2736                 break;
2737         case IT8712F_DEVID:
2738                 sio_data->type = it8712;
2739                 break;
2740         case IT8716F_DEVID:
2741         case IT8726F_DEVID:
2742                 sio_data->type = it8716;
2743                 break;
2744         case IT8718F_DEVID:
2745                 sio_data->type = it8718;
2746                 break;
2747         case IT8720F_DEVID:
2748                 sio_data->type = it8720;
2749                 break;
2750         case IT8721F_DEVID:
2751                 sio_data->type = it8721;
2752                 break;
2753         case IT8728F_DEVID:
2754                 sio_data->type = it8728;
2755                 break;
2756         case IT8732F_DEVID:
2757                 sio_data->type = it8732;
2758                 break;
2759         case IT8792E_DEVID:
2760                 sio_data->type = it8792;
2761                 break;
2762         case IT8771E_DEVID:
2763                 sio_data->type = it8771;
2764                 break;
2765         case IT8772E_DEVID:
2766                 sio_data->type = it8772;
2767                 break;
2768         case IT8781F_DEVID:
2769                 sio_data->type = it8781;
2770                 break;
2771         case IT8782F_DEVID:
2772                 sio_data->type = it8782;
2773                 break;
2774         case IT8783E_DEVID:
2775                 sio_data->type = it8783;
2776                 break;
2777         case IT8786E_DEVID:
2778                 sio_data->type = it8786;
2779                 break;
2780         case IT8790E_DEVID:
2781                 sio_data->type = it8790;
2782                 break;
2783         case IT8603E_DEVID:
2784         case IT8623E_DEVID:
2785                 sio_data->type = it8603;
2786                 break;
2787         case IT8607E_DEVID:
2788                 sio_data->type = it8607;
2789                 break;
2790         case IT8620E_DEVID:
2791                 sio_data->type = it8620;
2792                 break;
2793         case IT8622E_DEVID:
2794                 sio_data->type = it8622;
2795                 break;
2796         case IT8628E_DEVID:
2797                 sio_data->type = it8628;
2798                 break;
2799         case IT8655E_DEVID:
2800                 sio_data->type = it8655;
2801                 break;
2802         case IT8665E_DEVID:
2803                 sio_data->type = it8665;
2804                 break;
2805         case IT8686E_DEVID:
2806                 sio_data->type = it8686;
2807                 break;
2808         case 0xffff:    /* No device at all */
2809                 goto exit;
2810         default:
2811                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2812                 goto exit;
2813         }
2814
2815         superio_select(sioaddr, PME);
2816         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2817                 pr_info("Device not activated, skipping\n");
2818                 goto exit;
2819         }
2820
2821         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2822         if (*address == 0) {
2823                 pr_info("Base address not set, skipping\n");
2824                 goto exit;
2825         }
2826
2827         err = 0;
2828         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2829         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2830                 it87_devices[sio_data->type].suffix,
2831                 *address, sio_data->revision);
2832
2833         config = &it87_devices[sio_data->type];
2834
2835         /* in7 (VSB or VCCH5V) is always internal on some chips */
2836         if (has_in7_internal(config))
2837                 sio_data->internal |= BIT(1);
2838
2839         /* in8 (Vbat) is always internal */
2840         sio_data->internal |= BIT(2);
2841
2842         /* in9 (AVCC3), always internal if supported */
2843         if (has_avcc3(config))
2844                 sio_data->internal |= BIT(3); /* in9 is AVCC */
2845         else
2846                 sio_data->skip_in |= BIT(9);
2847
2848         if (!has_four_pwm(config))
2849                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2850         else if (!has_five_pwm(config))
2851                 sio_data->skip_pwm |= BIT(4) | BIT(5);
2852         else if (!has_six_pwm(config))
2853                 sio_data->skip_pwm |= BIT(5);
2854
2855         if (!has_vid(config))
2856                 sio_data->skip_vid = 1;
2857
2858         /* Read GPIO config and VID value from LDN 7 (GPIO) */
2859         if (sio_data->type == it87) {
2860                 /* The IT8705F has a different LD number for GPIO */
2861                 superio_select(sioaddr, 5);
2862                 sio_data->beep_pin = superio_inb(sioaddr,
2863                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2864         } else if (sio_data->type == it8783) {
2865                 int reg25, reg27, reg2a, reg2c, regef;
2866
2867                 superio_select(sioaddr, GPIO);
2868
2869                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2870                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2871                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2872                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2873                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2874
2875                 /* Check if fan3 is there or not */
2876                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2877                         sio_data->skip_fan |= BIT(2);
2878                 if ((reg25 & BIT(4)) ||
2879                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
2880                         sio_data->skip_pwm |= BIT(2);
2881
2882                 /* Check if fan2 is there or not */
2883                 if (reg27 & BIT(7))
2884                         sio_data->skip_fan |= BIT(1);
2885                 if (reg27 & BIT(3))
2886                         sio_data->skip_pwm |= BIT(1);
2887
2888                 /* VIN5 */
2889                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2890                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2891
2892                 /* VIN6 */
2893                 if (reg27 & BIT(1))
2894                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2895
2896                 /*
2897                  * VIN7
2898                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2899                  */
2900                 if (reg27 & BIT(2)) {
2901                         /*
2902                          * The data sheet is a bit unclear regarding the
2903                          * internal voltage divider for VCCH5V. It says
2904                          * "This bit enables and switches VIN7 (pin 91) to the
2905                          * internal voltage divider for VCCH5V".
2906                          * This is different to other chips, where the internal
2907                          * voltage divider would connect VIN7 to an internal
2908                          * voltage source. Maybe that is the case here as well.
2909                          *
2910                          * Since we don't know for sure, re-route it if that is
2911                          * not the case, and ask the user to report if the
2912                          * resulting voltage is sane.
2913                          */
2914                         if (!(reg2c & BIT(1))) {
2915                                 reg2c |= BIT(1);
2916                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2917                                              reg2c);
2918                                 pr_notice("Routing internal VCCH5V to in7.\n");
2919                         }
2920                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2921                         pr_notice("Please report if it displays a reasonable voltage.\n");
2922                 }
2923
2924                 if (reg2c & BIT(0))
2925                         sio_data->internal |= BIT(0);
2926                 if (reg2c & BIT(1))
2927                         sio_data->internal |= BIT(1);
2928
2929                 sio_data->beep_pin = superio_inb(sioaddr,
2930                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2931         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
2932                 int reg27, reg29;
2933
2934                 superio_select(sioaddr, GPIO);
2935
2936                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2937
2938                 /* Check if fan3 is there or not */
2939                 if (reg27 & BIT(6))
2940                         sio_data->skip_pwm |= BIT(2);
2941                 if (reg27 & BIT(7))
2942                         sio_data->skip_fan |= BIT(2);
2943
2944                 /* Check if fan2 is there or not */
2945                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2946                 if (reg29 & BIT(1))
2947                         sio_data->skip_pwm |= BIT(1);
2948                 if (reg29 & BIT(2))
2949                         sio_data->skip_fan |= BIT(1);
2950
2951                 if (sio_data->type == it8603) {
2952                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2953                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2954                 }
2955
2956                 sio_data->beep_pin = superio_inb(sioaddr,
2957                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2958         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
2959                    sio_data->type == it8686) {
2960                 int reg;
2961
2962                 superio_select(sioaddr, GPIO);
2963
2964                 /* Check for pwm5 */
2965                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2966                 if (reg & BIT(6))
2967                         sio_data->skip_pwm |= BIT(4);
2968
2969                 /* Check for fan4, fan5 */
2970                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2971                 if (!(reg & BIT(5)))
2972                         sio_data->skip_fan |= BIT(3);
2973                 if (!(reg & BIT(4)))
2974                         sio_data->skip_fan |= BIT(4);
2975
2976                 /* Check for pwm3, fan3 */
2977                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2978                 if (reg & BIT(6))
2979                         sio_data->skip_pwm |= BIT(2);
2980                 if (reg & BIT(7))
2981                         sio_data->skip_fan |= BIT(2);
2982
2983                 /* Check for pwm4 */
2984                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
2985                 if (reg & BIT(2))
2986                         sio_data->skip_pwm |= BIT(3);
2987
2988                 /* Check for pwm2, fan2 */
2989                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2990                 if (reg & BIT(1))
2991                         sio_data->skip_pwm |= BIT(1);
2992                 if (reg & BIT(2))
2993                         sio_data->skip_fan |= BIT(1);
2994                 /* Check for pwm6, fan6 */
2995                 if (!(reg & BIT(7))) {
2996                         sio_data->skip_pwm |= BIT(5);
2997                         sio_data->skip_fan |= BIT(5);
2998                 }
2999
3000                 /* Check if AVCC is on VIN3 */
3001                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3002                 if (reg & BIT(0)) {
3003                         /* For it8686, the bit just enables AVCC3 */
3004                         if (sio_data->type != it8686)
3005                                 sio_data->internal |= BIT(0);
3006                 } else {
3007                         sio_data->internal &= ~BIT(3);
3008                         sio_data->skip_in |= BIT(9);
3009                 }
3010
3011                 sio_data->beep_pin = superio_inb(sioaddr,
3012                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3013         } else if (sio_data->type == it8622) {
3014                 int reg;
3015
3016                 superio_select(sioaddr, GPIO);
3017
3018                 /* Check for pwm4, fan4 */
3019                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3020                 if (reg & BIT(6))
3021                         sio_data->skip_fan |= BIT(3);
3022                 if (reg & BIT(5))
3023                         sio_data->skip_pwm |= BIT(3);
3024
3025                 /* Check for pwm3, fan3, pwm5, fan5 */
3026                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3027                 if (reg & BIT(6))
3028                         sio_data->skip_pwm |= BIT(2);
3029                 if (reg & BIT(7))
3030                         sio_data->skip_fan |= BIT(2);
3031                 if (reg & BIT(3))
3032                         sio_data->skip_pwm |= BIT(4);
3033                 if (reg & BIT(1))
3034                         sio_data->skip_fan |= BIT(4);
3035
3036                 /* Check for pwm2, fan2 */
3037                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3038                 if (reg & BIT(1))
3039                         sio_data->skip_pwm |= BIT(1);
3040                 if (reg & BIT(2))
3041                         sio_data->skip_fan |= BIT(1);
3042
3043                 /* Check for AVCC */
3044                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3045                 if (!(reg & BIT(0)))
3046                         sio_data->skip_in |= BIT(9);
3047
3048                 sio_data->beep_pin = superio_inb(sioaddr,
3049                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3050         } else if (sio_data->type == it8732) {
3051                 int reg;
3052
3053                 superio_select(sioaddr, GPIO);
3054
3055                 /* Check for pwm2, fan2 */
3056                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3057                 if (reg & BIT(1))
3058                         sio_data->skip_pwm |= BIT(1);
3059                 if (reg & BIT(2))
3060                         sio_data->skip_fan |= BIT(1);
3061
3062                 /* Check for pwm3, fan3, fan4 */
3063                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3064                 if (reg & BIT(6))
3065                         sio_data->skip_pwm |= BIT(2);
3066                 if (reg & BIT(7))
3067                         sio_data->skip_fan |= BIT(2);
3068                 if (reg & BIT(5))
3069                         sio_data->skip_fan |= BIT(3);
3070
3071                 /* Check if AVCC is on VIN3 */
3072                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3073                 if (reg & BIT(0))
3074                         sio_data->internal |= BIT(0);
3075
3076                 sio_data->beep_pin = superio_inb(sioaddr,
3077                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3078         } else if (sio_data->type == it8655) {
3079                 int reg;
3080
3081                 superio_select(sioaddr, GPIO);
3082
3083                 /* Check for pwm2 */
3084                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3085                 if (reg & BIT(1))
3086                         sio_data->skip_pwm |= BIT(1);
3087
3088                 /* Check for fan2 */
3089                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3090                 if (reg & BIT(4))
3091                         sio_data->skip_fan |= BIT(1);
3092
3093                 /* Check for pwm3, fan3 */
3094                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3095                 if (reg & BIT(6))
3096                         sio_data->skip_pwm |= BIT(2);
3097                 if (reg & BIT(7))
3098                         sio_data->skip_fan |= BIT(2);
3099
3100                 sio_data->beep_pin = superio_inb(sioaddr,
3101                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3102         } else if (sio_data->type == it8665) {
3103                 int reg;
3104
3105                 superio_select(sioaddr, GPIO);
3106
3107                 /* Check for pwm2 */
3108                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3109                 if (reg & BIT(1))
3110                         sio_data->skip_pwm |= BIT(1);
3111
3112                 /* Check for fan2 */
3113                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3114                 if (reg & BIT(4))
3115                         sio_data->skip_fan |= BIT(1);
3116
3117                 /* Check for pwm3, fan3 */
3118                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3119                 if (reg & BIT(6))
3120                         sio_data->skip_pwm |= BIT(2);
3121                 if (reg & BIT(7))
3122                         sio_data->skip_fan |= BIT(2);
3123
3124                 /* Check for pwm5, fan5 */
3125                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3126                 if (reg & BIT(5))
3127                         sio_data->skip_pwm |= BIT(4);
3128                 if (!(reg & BIT(4)))
3129                         sio_data->skip_fan |= BIT(4);
3130
3131                 /* Check for pwm4, fan4, pwm6, fan6 */
3132                 reg = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3133                 if (reg & BIT(2))
3134                         sio_data->skip_pwm |= BIT(3);
3135                 if (reg & BIT(3))
3136                         sio_data->skip_fan |= BIT(3);
3137                 if (reg & BIT(0))
3138                         sio_data->skip_pwm |= BIT(5);
3139                 if (reg & BIT(1))
3140                         sio_data->skip_fan |= BIT(5);
3141
3142                 sio_data->beep_pin = superio_inb(sioaddr,
3143                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3144         } else {
3145                 int reg;
3146                 bool uart6;
3147
3148                 superio_select(sioaddr, GPIO);
3149
3150                 /* Check for fan4, fan5 */
3151                 if (has_five_fans(config)) {
3152                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3153                         switch (sio_data->type) {
3154                         case it8718:
3155                                 if (reg & BIT(5))
3156                                         sio_data->skip_fan |= BIT(3);
3157                                 if (reg & BIT(4))
3158                                         sio_data->skip_fan |= BIT(4);
3159                                 break;
3160                         case it8720:
3161                         case it8721:
3162                         case it8728:
3163                                 if (!(reg & BIT(5)))
3164                                         sio_data->skip_fan |= BIT(3);
3165                                 if (!(reg & BIT(4)))
3166                                         sio_data->skip_fan |= BIT(4);
3167                                 break;
3168                         default:
3169                                 break;
3170                         }
3171                 }
3172
3173                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3174                 if (!sio_data->skip_vid) {
3175                         /* We need at least 4 VID pins */
3176                         if (reg & 0x0f) {
3177                                 pr_info("VID is disabled (pins used for GPIO)\n");
3178                                 sio_data->skip_vid = 1;
3179                         }
3180                 }
3181
3182                 /* Check if fan3 is there or not */
3183                 if (reg & BIT(6))
3184                         sio_data->skip_pwm |= BIT(2);
3185                 if (reg & BIT(7))
3186                         sio_data->skip_fan |= BIT(2);
3187
3188                 /* Check if fan2 is there or not */
3189                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3190                 if (reg & BIT(1))
3191                         sio_data->skip_pwm |= BIT(1);
3192                 if (reg & BIT(2))
3193                         sio_data->skip_fan |= BIT(1);
3194
3195                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3196                     !(sio_data->skip_vid))
3197                         sio_data->vid_value = superio_inb(sioaddr,
3198                                                           IT87_SIO_VID_REG);
3199
3200                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3201
3202                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3203
3204                 /*
3205                  * The IT8720F has no VIN7 pin, so VCCH should always be
3206                  * routed internally to VIN7 with an internal divider.
3207                  * Curiously, there still is a configuration bit to control
3208                  * this, which means it can be set incorrectly. And even
3209                  * more curiously, many boards out there are improperly
3210                  * configured, even though the IT8720F datasheet claims
3211                  * that the internal routing of VCCH to VIN7 is the default
3212                  * setting. So we force the internal routing in this case.
3213                  *
3214                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3215                  * If UART6 is enabled, re-route VIN7 to the internal divider
3216                  * if that is not already the case.
3217                  */
3218                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3219                         reg |= BIT(1);
3220                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3221                         pr_notice("Routing internal VCCH to in7\n");
3222                 }
3223                 if (reg & BIT(0))
3224                         sio_data->internal |= BIT(0);
3225                 if (reg & BIT(1))
3226                         sio_data->internal |= BIT(1);
3227
3228                 /*
3229                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3230                  * While VIN7 can be routed to the internal voltage divider,
3231                  * VIN5 and VIN6 are not available if UART6 is enabled.
3232                  *
3233                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3234                  * is the temperature source. Since we can not read the
3235                  * temperature source here, skip_temp is preliminary.
3236                  */
3237                 if (uart6) {
3238                         sio_data->skip_in |= BIT(5) | BIT(6);
3239                         sio_data->skip_temp |= BIT(2);
3240                 }
3241
3242                 sio_data->beep_pin = superio_inb(sioaddr,
3243                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3244         }
3245         if (sio_data->beep_pin)
3246                 pr_info("Beeping is supported\n");
3247
3248 exit:
3249         superio_exit(sioaddr);
3250         return err;
3251 }
3252
3253 /* Called when we have found a new IT87. */
3254 static void it87_init_device(struct platform_device *pdev)
3255 {
3256         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3257         struct it87_data *data = platform_get_drvdata(pdev);
3258         int tmp, i;
3259         u8 mask;
3260
3261         /* Initialize chip specific register pointers */
3262         switch (data->type) {
3263         case it8686:
3264                 data->REG_FAN = IT87_REG_FAN;
3265                 data->REG_FANX = IT87_REG_FANX;
3266                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3267                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3268                 data->REG_PWM = IT87_REG_PWM;
3269                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3270                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3271                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3272                 break;
3273         case it8655:
3274         case it8665:
3275                 data->REG_FAN = IT87_REG_FAN_8665;
3276                 data->REG_FANX = IT87_REG_FANX_8665;
3277                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3278                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3279                 data->REG_PWM = IT87_REG_PWM_8665;
3280                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3281                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3282                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3283                 break;
3284         case it8622:
3285                 data->REG_FAN = IT87_REG_FAN;
3286                 data->REG_FANX = IT87_REG_FANX;
3287                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3288                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3289                 data->REG_PWM = IT87_REG_PWM_8665;
3290                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3291                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3292                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3293                 break;
3294         default:
3295                 data->REG_FAN = IT87_REG_FAN;
3296                 data->REG_FANX = IT87_REG_FANX;
3297                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3298                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3299                 data->REG_PWM = IT87_REG_PWM;
3300                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3301                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3302                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3303                 break;
3304         }
3305
3306         /*
3307          * For each PWM channel:
3308          * - If it is in automatic mode, setting to manual mode should set
3309          *   the fan to full speed by default.
3310          * - If it is in manual mode, we need a mapping to temperature
3311          *   channels to use when later setting to automatic mode later.
3312          *   Use a 1:1 mapping by default (we are clueless.)
3313          * In both cases, the value can (and should) be changed by the user
3314          * prior to switching to a different mode.
3315          * Note that this is no longer needed for the IT8721F and later, as
3316          * these have separate registers for the temperature mapping and the
3317          * manual duty cycle.
3318          */
3319         for (i = 0; i < NUM_AUTO_PWM; i++) {
3320                 data->pwm_temp_map[i] = i;
3321                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3322                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3323         }
3324
3325         /*
3326          * Some chips seem to have default value 0xff for all limit
3327          * registers. For low voltage limits it makes no sense and triggers
3328          * alarms, so change to 0 instead. For high temperature limits, it
3329          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3330          * but is still confusing, so change to 127 degrees C.
3331          */
3332         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3333                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3334                 if (tmp == 0xff)
3335                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3336         }
3337         for (i = 0; i < data->num_temp_limit; i++) {
3338                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3339                 if (tmp == 0xff)
3340                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3341         }
3342
3343         /*
3344          * Temperature channels are not forcibly enabled, as they can be
3345          * set to two different sensor types and we can't guess which one
3346          * is correct for a given system. These channels can be enabled at
3347          * run-time through the temp{1-3}_type sysfs accessors if needed.
3348          */
3349
3350         /* Check if voltage monitors are reset manually or by some reason */
3351         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3352         if ((tmp & 0xff) == 0) {
3353                 /* Enable all voltage monitors */
3354                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3355         }
3356
3357         /* Check if tachometers are reset manually or by some reason */
3358         mask = 0x70 & ~(sio_data->skip_fan << 4);
3359         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3360         if ((data->fan_main_ctrl & mask) == 0) {
3361                 /* Enable all fan tachometers */
3362                 data->fan_main_ctrl |= mask;
3363                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3364                                  data->fan_main_ctrl);
3365         }
3366         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3367
3368         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3369
3370         /* Set tachometers to 16-bit mode if needed */
3371         if (has_fan16_config(data)) {
3372                 if (~tmp & 0x07 & data->has_fan) {
3373                         dev_dbg(&pdev->dev,
3374                                 "Setting fan1-3 to 16-bit mode\n");
3375                         it87_write_value(data, IT87_REG_FAN_16BIT,
3376                                          tmp | 0x07);
3377                 }
3378         }
3379
3380         /* Check for additional fans */
3381         if (has_four_fans(data) && (tmp & BIT(4)))
3382                 data->has_fan |= BIT(3); /* fan4 enabled */
3383         if (has_five_fans(data) && (tmp & BIT(5)))
3384                 data->has_fan |= BIT(4); /* fan5 enabled */
3385         if (has_six_fans(data)) {
3386                 switch (data->type) {
3387                 case it8620:
3388                 case it8628:
3389                 case it8686:
3390                         if (tmp & BIT(2))
3391                                 data->has_fan |= BIT(5); /* fan6 enabled */
3392                         break;
3393                 case it8665:
3394                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3395                         if (tmp & BIT(3))
3396                                 data->has_fan |= BIT(5); /* fan6 enabled */
3397                         break;
3398                 default:
3399                         break;
3400                 }
3401         }
3402
3403         /* Fan input pins may be used for alternative functions */
3404         data->has_fan &= ~sio_data->skip_fan;
3405
3406         /* Check if pwm6 is enabled */
3407         if (has_six_pwm(data)) {
3408                 switch (data->type) {
3409                 case it8620:
3410                 case it8686:
3411                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3412                         if (!(tmp & BIT(3)))
3413                                 sio_data->skip_pwm |= BIT(5);
3414                         break;
3415                 default:
3416                         break;
3417                 }
3418         }
3419
3420         /* Start monitoring */
3421         it87_write_value(data, IT87_REG_CONFIG,
3422                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3423                          | (update_vbat ? 0x41 : 0x01));
3424 }
3425
3426 /* Return 1 if and only if the PWM interface is safe to use */
3427 static int it87_check_pwm(struct device *dev)
3428 {
3429         struct it87_data *data = dev_get_drvdata(dev);
3430         /*
3431          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3432          * and polarity set to active low is sign that this is the case so we
3433          * disable pwm control to protect the user.
3434          */
3435         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3436
3437         if ((tmp & 0x87) == 0) {
3438                 if (fix_pwm_polarity) {
3439                         /*
3440                          * The user asks us to attempt a chip reconfiguration.
3441                          * This means switching to active high polarity and
3442                          * inverting all fan speed values.
3443                          */
3444                         int i;
3445                         u8 pwm[3];
3446
3447                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3448                                 pwm[i] = it87_read_value(data,
3449                                                          data->REG_PWM[i]);
3450
3451                         /*
3452                          * If any fan is in automatic pwm mode, the polarity
3453                          * might be correct, as suspicious as it seems, so we
3454                          * better don't change anything (but still disable the
3455                          * PWM interface).
3456                          */
3457                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3458                                 dev_info(dev,
3459                                          "Reconfiguring PWM to active high polarity\n");
3460                                 it87_write_value(data, IT87_REG_FAN_CTL,
3461                                                  tmp | 0x87);
3462                                 for (i = 0; i < 3; i++)
3463                                         it87_write_value(data,
3464                                                          data->REG_PWM[i],
3465                                                          0x7f & ~pwm[i]);
3466                                 return 1;
3467                         }
3468
3469                         dev_info(dev,
3470                                  "PWM configuration is too broken to be fixed\n");
3471                 }
3472
3473                 dev_info(dev,
3474                          "Detected broken BIOS defaults, disabling PWM interface\n");
3475                 return 0;
3476         } else if (fix_pwm_polarity) {
3477                 dev_info(dev,
3478                          "PWM configuration looks sane, won't touch\n");
3479         }
3480
3481         return 1;
3482 }
3483
3484 static int it87_probe(struct platform_device *pdev)
3485 {
3486         struct it87_data *data;
3487         struct resource *res;
3488         struct device *dev = &pdev->dev;
3489         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3490         int enable_pwm_interface;
3491         struct device *hwmon_dev;
3492
3493         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3494         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3495                                  DRVNAME)) {
3496                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3497                         (unsigned long)res->start,
3498                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3499                 return -EBUSY;
3500         }
3501
3502         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3503         if (!data)
3504                 return -ENOMEM;
3505
3506         data->addr = res->start;
3507         data->type = sio_data->type;
3508         data->features = it87_devices[sio_data->type].features;
3509         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3510         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3511         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3512         data->bank = 0xff;
3513
3514         /*
3515          * IT8705F Datasheet 0.4.1, 3h == Version G.
3516          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3517          * These are the first revisions with 16-bit tachometer support.
3518          */
3519         switch (data->type) {
3520         case it87:
3521                 if (sio_data->revision >= 0x03) {
3522                         data->features &= ~FEAT_OLD_AUTOPWM;
3523                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3524                 }
3525                 break;
3526         case it8712:
3527                 if (sio_data->revision >= 0x08) {
3528                         data->features &= ~FEAT_OLD_AUTOPWM;
3529                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3530                                           FEAT_FIVE_FANS;
3531                 }
3532                 break;
3533         default:
3534                 break;
3535         }
3536
3537         /* Now, we do the remaining detection. */
3538         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3539             it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3540                 return -ENODEV;
3541
3542         platform_set_drvdata(pdev, data);
3543
3544         mutex_init(&data->update_lock);
3545
3546         /* Check PWM configuration */
3547         enable_pwm_interface = it87_check_pwm(dev);
3548
3549         /* Starting with IT8721F, we handle scaling of internal voltages */
3550         if (has_scaling(data)) {
3551                 if (sio_data->internal & BIT(0))
3552                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3553                 if (sio_data->internal & BIT(1))
3554                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3555                 if (sio_data->internal & BIT(2))
3556                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3557                 if (sio_data->internal & BIT(3))
3558                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3559         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3560                    sio_data->type == it8783) {
3561                 if (sio_data->internal & BIT(0))
3562                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3563                 if (sio_data->internal & BIT(1))
3564                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3565         }
3566
3567         data->has_temp = 0x07;
3568         if (sio_data->skip_temp & BIT(2)) {
3569                 if (sio_data->type == it8782 &&
3570                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3571                         data->has_temp &= ~BIT(2);
3572         }
3573
3574         data->in_internal = sio_data->internal;
3575         data->has_in = 0x3ff & ~sio_data->skip_in;
3576
3577         if (has_six_temp(data)) {
3578                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3579
3580                 /* Check for additional temperature sensors */
3581                 if ((reg & 0x03) >= 0x02)
3582                         data->has_temp |= BIT(3);
3583                 if (((reg >> 2) & 0x03) >= 0x02)
3584                         data->has_temp |= BIT(4);
3585                 if (((reg >> 4) & 0x03) >= 0x02)
3586                         data->has_temp |= BIT(5);
3587
3588                 /* Check for additional voltage sensors */
3589                 if ((reg & 0x03) == 0x01)
3590                         data->has_in |= BIT(10);
3591                 if (((reg >> 2) & 0x03) == 0x01)
3592                         data->has_in |= BIT(11);
3593                 if (((reg >> 4) & 0x03) == 0x01)
3594                         data->has_in |= BIT(12);
3595         }
3596
3597         data->has_beep = !!sio_data->beep_pin;
3598
3599         /* Initialize the IT87 chip */
3600         it87_init_device(pdev);
3601
3602         if (!sio_data->skip_vid) {
3603                 data->has_vid = true;
3604                 data->vrm = vid_which_vrm();
3605                 /* VID reading from Super-I/O config space if available */
3606                 data->vid = sio_data->vid_value;
3607         }
3608
3609         /* Prepare for sysfs hooks */
3610         data->groups[0] = &it87_group;
3611         data->groups[1] = &it87_group_in;
3612         data->groups[2] = &it87_group_temp;
3613         data->groups[3] = &it87_group_fan;
3614
3615         if (enable_pwm_interface) {
3616                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3617                 data->has_pwm &= ~sio_data->skip_pwm;
3618
3619                 data->groups[4] = &it87_group_pwm;
3620                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3621                         data->groups[5] = &it87_group_auto_pwm;
3622         }
3623
3624         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3625                                         it87_devices[sio_data->type].name,
3626                                         data, data->groups);
3627         return PTR_ERR_OR_ZERO(hwmon_dev);
3628 }
3629
3630 static struct platform_driver it87_driver = {
3631         .driver = {
3632                 .name   = DRVNAME,
3633         },
3634         .probe  = it87_probe,
3635 };
3636
3637 static int __init it87_device_add(int index, unsigned short address,
3638                                   const struct it87_sio_data *sio_data)
3639 {
3640         struct platform_device *pdev;
3641         struct resource res = {
3642                 .start  = address + IT87_EC_OFFSET,
3643                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3644                 .name   = DRVNAME,
3645                 .flags  = IORESOURCE_IO,
3646         };
3647         int err;
3648
3649         err = acpi_check_resource_conflict(&res);
3650         if (err)
3651                 return err;
3652
3653         pdev = platform_device_alloc(DRVNAME, address);
3654         if (!pdev)
3655                 return -ENOMEM;
3656
3657         err = platform_device_add_resources(pdev, &res, 1);
3658         if (err) {
3659                 pr_err("Device resource addition failed (%d)\n", err);
3660                 goto exit_device_put;
3661         }
3662
3663         err = platform_device_add_data(pdev, sio_data,
3664                                        sizeof(struct it87_sio_data));
3665         if (err) {
3666                 pr_err("Platform data allocation failed\n");
3667                 goto exit_device_put;
3668         }
3669
3670         err = platform_device_add(pdev);
3671         if (err) {
3672                 pr_err("Device addition failed (%d)\n", err);
3673                 goto exit_device_put;
3674         }
3675
3676         it87_pdev[index] = pdev;
3677         return 0;
3678
3679 exit_device_put:
3680         platform_device_put(pdev);
3681         return err;
3682 }
3683
3684 struct it87_dmi_data {
3685         bool sio4e_broken;      /* SIO accesses @ 0x4e are broken       */
3686         char *sio_mutex;        /* SIO ACPI mutex                       */
3687         u8 skip_pwm;            /* pwm channels to skip for this board  */
3688 };
3689
3690 /*
3691  * On Gigabyte AB350 boards, accesses to the Super-IO chip
3692  * at address 0x4e/0x4f can result in a system hang.
3693  * Accesses to address 0x2e/0x2f need to be mutex protected.
3694  */
3695 static struct it87_dmi_data gigabyte_ab350_gaming = {
3696         .sio4e_broken = true,
3697         .sio_mutex = "\\_SB.PCI0.SBRG.SIO1.MUT0",
3698 };
3699
3700 /*
3701  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3702  * connected to a fan, but to something else. One user
3703  * has reported instant system power-off when changing
3704  * the PWM2 duty cycle, so we disable it.
3705  * I use the board name string as the trigger in case
3706  * the same board is ever used in other systems.
3707  */
3708 static struct it87_dmi_data nvidia_fn68pt = {
3709         .skip_pwm = BIT(1),
3710 };
3711
3712 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3713         {
3714                 .matches = {
3715                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3716                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming-CF"),
3717                 },
3718                 .driver_data = &gigabyte_ab350_gaming,
3719         },
3720         {
3721                 .matches = {
3722                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3723                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming 3-CF"),
3724                 },
3725                 .driver_data = &gigabyte_ab350_gaming,
3726         },
3727         {
3728                 .matches = {
3729                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3730                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3731                 },
3732                 .driver_data = &nvidia_fn68pt,
3733         },
3734         { }
3735 };
3736
3737 static int __init sm_it87_init(void)
3738 {
3739         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3740         struct it87_dmi_data *dmi_data = NULL;
3741         int sioaddr[2] = { REG_2E, REG_4E };
3742         struct it87_sio_data sio_data;
3743         unsigned short isa_address;
3744         bool found = false;
3745         int i, err;
3746
3747         if (dmi)
3748                 dmi_data = dmi->driver_data;
3749
3750         if (dmi_data) {
3751                 it87_sio4e_broken = dmi_data->sio4e_broken;
3752 #ifdef __IT87_USE_ACPI_MUTEX
3753                 if (dmi_data->sio_mutex) {
3754                         static acpi_status status;
3755
3756                         status = acpi_get_handle(NULL, dmi_data->sio_mutex,
3757                                                  &it87_acpi_sio_handle);
3758                         if (ACPI_SUCCESS(status)) {
3759                                 it87_acpi_sio_mutex = dmi_data->sio_mutex;
3760                                 pr_debug("Found ACPI SIO mutex %s\n",
3761                                          dmi_data->sio_mutex);
3762                         } else {
3763                                 pr_warn("ACPI SIO mutex %s not found\n",
3764                                         dmi_data->sio_mutex);
3765                         }
3766                 }
3767 #endif /* __IT87_USE_ACPI_MUTEX */
3768         }
3769
3770         err = platform_driver_register(&it87_driver);
3771         if (err)
3772                 return err;
3773
3774         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3775                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3776                 isa_address = 0;
3777                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3778                 if (err || isa_address == 0)
3779                         continue;
3780
3781                 if (dmi_data)
3782                         sio_data.skip_pwm |= dmi_data->skip_pwm;
3783                 err = it87_device_add(i, isa_address, &sio_data);
3784                 if (err)
3785                         goto exit_dev_unregister;
3786                 found = true;
3787         }
3788
3789         if (!found) {
3790                 err = -ENODEV;
3791                 goto exit_unregister;
3792         }
3793         return 0;
3794
3795 exit_dev_unregister:
3796         /* NULL check handled by platform_device_unregister */
3797         platform_device_unregister(it87_pdev[0]);
3798 exit_unregister:
3799         platform_driver_unregister(&it87_driver);
3800         return err;
3801 }
3802
3803 static void __exit sm_it87_exit(void)
3804 {
3805         /* NULL check handled by platform_device_unregister */
3806         platform_device_unregister(it87_pdev[1]);
3807         platform_device_unregister(it87_pdev[0]);
3808         platform_driver_unregister(&it87_driver);
3809 }
3810
3811 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3812 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3813 module_param(update_vbat, bool, 0);
3814 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3815 module_param(fix_pwm_polarity, bool, 0);
3816 MODULE_PARM_DESC(fix_pwm_polarity,
3817                  "Force PWM polarity to active high (DANGEROUS)");
3818 MODULE_LICENSE("GPL");
3819
3820 module_init(sm_it87_init);
3821 module_exit(sm_it87_exit);