git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8620E  Super I/O chip w/LPC interface
  16  *            IT8622E  Super I/O chip w/LPC interface
  17  *            IT8623E  Super I/O chip w/LPC interface
  18  *            IT8628E  Super I/O chip w/LPC interface
  19  *            IT8655E  Super I/O chip w/LPC interface
  20  *            IT8665E  Super I/O chip w/LPC interface
  21  *            IT8686E  Super I/O chip w/LPC interface
  22  *            IT8705F  Super I/O chip w/LPC interface
  23  *            IT8712F  Super I/O chip w/LPC interface
  24  *            IT8716F  Super I/O chip w/LPC interface
  25  *            IT8718F  Super I/O chip w/LPC interface
  26  *            IT8720F  Super I/O chip w/LPC interface
  27  *            IT8721F  Super I/O chip w/LPC interface
  28  *            IT8726F  Super I/O chip w/LPC interface
  29  *            IT8728F  Super I/O chip w/LPC interface
  30  *            IT8732F  Super I/O chip w/LPC interface
  31  *            IT8758E  Super I/O chip w/LPC interface
  32  *            IT8771E  Super I/O chip w/LPC interface
  33  *            IT8772E  Super I/O chip w/LPC interface
  34  *            IT8781F  Super I/O chip w/LPC interface
  35  *            IT8782F  Super I/O chip w/LPC interface
  36  *            IT8783E/F Super I/O chip w/LPC interface
  37  *            IT8786E  Super I/O chip w/LPC interface
  38  *            IT8790E  Super I/O chip w/LPC interface
  39  *            IT8792E  Super I/O chip w/LPC interface
  40  *            Sis950   A clone of the IT8705F
  41  *
  42  *  Copyright (C) 2001 Chris Gauthron
  43  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  44  *
  45  *  This program is free software; you can redistribute it and/or modify
  46  *  it under the terms of the GNU General Public License as published by
  47  *  the Free Software Foundation; either version 2 of the License, or
  48  *  (at your option) any later version.
  49  *
  50  *  This program is distributed in the hope that it will be useful,
  51  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  52  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  53  *  GNU General Public License for more details.
  54  */
  55
  56 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  57
  58 #include <linux/bitops.h>
  59 #include <linux/module.h>
  60 #include <linux/init.h>
  61 #include <linux/slab.h>
  62 #include <linux/jiffies.h>
  63 #include <linux/platform_device.h>
  64 #include <linux/hwmon.h>
  65 #include <linux/hwmon-sysfs.h>
  66 #include <linux/hwmon-vid.h>
  67 #include <linux/err.h>
  68 #include <linux/mutex.h>
  69 #include <linux/sysfs.h>
  70 #include <linux/string.h>
  71 #include <linux/dmi.h>
  72 #include <linux/acpi.h>
  73 #include <linux/io.h>
  74 #include "compat.h"
  75
  76 #define DRVNAME "it87"
  77
  78 /* Necessary API not (yet) exported in upstream kernel */
  79 /* #define __IT87_USE_ACPI_MUTEX */
  80
  81 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  82              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  83              it8792, it8603, it8607, it8620, it8622, it8628, it8655, it8665,
  84              it8686 };
  85
  86 static unsigned short force_id;
  87 module_param(force_id, ushort, 0);
  88 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  89
  90 static struct platform_device *it87_pdev[2];
  91 static bool it87_sio4e_broken;
  92 #ifdef __IT87_USE_ACPI_MUTEX
  93 static acpi_handle it87_acpi_sio_handle;
  94 static char *it87_acpi_sio_mutex;
  95 #endif
  96
  97 #define REG_2E  0x2e    /* The register to read/write */
  98 #define REG_4E  0x4e    /* Secondary register to read/write */
  99
 100 #define DEV     0x07    /* Register: Logical device select */
 101 #define PME     0x04    /* The device with the fan registers in it */
 102
 103 /* The device with the IT8718F/IT8720F VID value in it */
 104 #define GPIO    0x07
 105
 106 #define DEVID   0x20    /* Register: Device ID */
 107 #define DEVREV  0x22    /* Register: Device Revision */
 108
 109 static inline void __superio_enter(int ioreg)
 110 {
 111         outb(0x87, ioreg);
 112         outb(0x01, ioreg);
 113         outb(0x55, ioreg);
 114         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 115 }
 116
 117 static inline int superio_inb(int ioreg, int reg)
 118 {
 119         int val;
 120
 121         outb(reg, ioreg);
 122         val = inb(ioreg + 1);
 123         if (it87_sio4e_broken && ioreg == 0x4e && val == 0xff) {
 124                 __superio_enter(ioreg);
 125                 outb(reg, ioreg);
 126                 val = inb(ioreg + 1);
 127                 pr_warn("Retry access 0x4e:0x%x -> 0x%x\n", reg, val);
 128         }
 129
 130         return val;
 131 }
 132
 133 static inline void superio_outb(int ioreg, int reg, int val)
 134 {
 135         outb(reg, ioreg);
 136         outb(val, ioreg + 1);
 137 }
 138
 139 static int superio_inw(int ioreg, int reg)
 140 {
 141         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 142 }
 143
 144 static inline void superio_select(int ioreg, int ldn)
 145 {
 146         outb(DEV, ioreg);
 147         outb(ldn, ioreg + 1);
 148 }
 149
 150 static inline int superio_enter(int ioreg)
 151 {
 152 #ifdef __IT87_USE_ACPI_MUTEX
 153         if (it87_acpi_sio_mutex) {
 154                 acpi_status status;
 155
 156                 status = acpi_acquire_mutex(NULL, it87_acpi_sio_mutex, 0x10);
 157                 if (ACPI_FAILURE(status)) {
 158                         pr_err("Failed to acquire ACPI mutex\n");
 159                         return -EBUSY;
 160                 }
 161         }
 162 #endif
 163         /*
 164          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 165          */
 166         if (!request_muxed_region(ioreg, 2, DRVNAME))
 167                 goto error;
 168
 169         __superio_enter(ioreg);
 170         return 0;
 171
 172 error:
 173 #ifdef __IT87_USE_ACPI_MUTEX
 174         if (it87_acpi_sio_mutex)
 175                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 176 #endif
 177         return -EBUSY;
 178 }
 179
 180 static inline void superio_exit(int ioreg)
 181 {
 182         if (!it87_sio4e_broken || ioreg != 0x4e) {
 183                 outb(0x02, ioreg);
 184                 outb(0x02, ioreg + 1);
 185         }
 186         release_region(ioreg, 2);
 187 #ifdef __IT87_USE_ACPI_MUTEX
 188         if (it87_acpi_sio_mutex)
 189                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 190 #endif
 191 }
 192
 193 /* Logical device 4 registers */
 194 #define IT8712F_DEVID 0x8712
 195 #define IT8705F_DEVID 0x8705
 196 #define IT8716F_DEVID 0x8716
 197 #define IT8718F_DEVID 0x8718
 198 #define IT8720F_DEVID 0x8720
 199 #define IT8721F_DEVID 0x8721
 200 #define IT8726F_DEVID 0x8726
 201 #define IT8728F_DEVID 0x8728
 202 #define IT8732F_DEVID 0x8732
 203 #define IT8792E_DEVID 0x8733
 204 #define IT8771E_DEVID 0x8771
 205 #define IT8772E_DEVID 0x8772
 206 #define IT8781F_DEVID 0x8781
 207 #define IT8782F_DEVID 0x8782
 208 #define IT8783E_DEVID 0x8783
 209 #define IT8786E_DEVID 0x8786
 210 #define IT8790E_DEVID 0x8790
 211 #define IT8603E_DEVID 0x8603
 212 #define IT8607E_DEVID 0x8607
 213 #define IT8620E_DEVID 0x8620
 214 #define IT8622E_DEVID 0x8622
 215 #define IT8623E_DEVID 0x8623
 216 #define IT8628E_DEVID 0x8628
 217 #define IT8655E_DEVID 0x8655
 218 #define IT8665E_DEVID 0x8665
 219 #define IT8686E_DEVID 0x8686
 220 #define IT87_ACT_REG  0x30
 221 #define IT87_BASE_REG 0x60
 222
 223 /* Logical device 7 registers (IT8712F and later) */
 224 #define IT87_SIO_GPIO1_REG      0x25
 225 #define IT87_SIO_GPIO2_REG      0x26
 226 #define IT87_SIO_GPIO3_REG      0x27
 227 #define IT87_SIO_GPIO4_REG      0x28
 228 #define IT87_SIO_GPIO5_REG      0x29
 229 #define IT87_SIO_GPIO9_REG      0xd3
 230 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 231 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 232 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 233 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 234 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 235 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 236
 237 /* Update battery voltage after every reading if true */
 238 static bool update_vbat;
 239
 240 /* Not all BIOSes properly configure the PWM registers */
 241 static bool fix_pwm_polarity;
 242
 243 /* Many IT87 constants specified below */
 244
 245 /* Length of ISA address segment */
 246 #define IT87_EXTENT 8
 247
 248 /* Length of ISA address segment for Environmental Controller */
 249 #define IT87_EC_EXTENT 2
 250
 251 /* Offset of EC registers from ISA base address */
 252 #define IT87_EC_OFFSET 5
 253
 254 /* Where are the ISA address/data registers relative to the EC base address */
 255 #define IT87_ADDR_REG_OFFSET 0
 256 #define IT87_DATA_REG_OFFSET 1
 257
 258 /*----- The IT87 registers -----*/
 259
 260 #define IT87_REG_CONFIG        0x00
 261
 262 #define IT87_REG_ALARM1        0x01
 263 #define IT87_REG_ALARM2        0x02
 264 #define IT87_REG_ALARM3        0x03
 265
 266 #define IT87_REG_BANK           0x06
 267
 268 /*
 269  * The IT8718F and IT8720F have the VID value in a different register, in
 270  * Super-I/O configuration space.
 271  */
 272 #define IT87_REG_VID           0x0a
 273 /*
 274  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 275  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 276  * mode.
 277  */
 278 #define IT87_REG_FAN_DIV       0x0b
 279 #define IT87_REG_FAN_16BIT     0x0c
 280
 281 /*
 282  * Monitors:
 283  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 284  * - up to 6 temp (1 to 6)
 285  * - up to 6 fan (1 to 6)
 286  */
 287
 288 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 289 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 290 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 291 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 292
 293 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 294 static const u8 IT87_REG_FAN_MIN_8665[] =
 295                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 296 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 297 static const u8 IT87_REG_FANX_MIN_8665[] =
 298                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 299
 300 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 301
 302 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 303
 304 #define IT87_REG_FAN_MAIN_CTRL 0x13
 305 #define IT87_REG_FAN_CTL       0x14
 306
 307 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 308 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 309
 310 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 311
 312 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 313                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 314
 315 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 316
 317 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 318 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 319
 320 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 321 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 322
 323 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 324                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 325 static const u8 IT87_REG_TEMP_LOW_8686[] =
 326                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 327
 328 #define IT87_REG_VIN_ENABLE    0x50
 329 #define IT87_REG_TEMP_ENABLE   0x51
 330 #define IT87_REG_TEMP_EXTRA    0x55
 331 #define IT87_REG_BEEP_ENABLE   0x5c
 332
 333 #define IT87_REG_CHIPID        0x58
 334
 335 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 336
 337 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 338 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 339
 340 #define IT87_REG_TEMP456_ENABLE 0x77
 341
 342 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 343 #define IT87_REG_TEMP_SRC2      0x23d
 344
 345 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 346 #define NUM_VIN_LIMIT           8
 347 #define NUM_TEMP                6
 348 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 349 #define NUM_FAN_DIV             3
 350 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 351 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 352
 353 struct it87_devices {
 354         const char *name;
 355         const char * const suffix;
 356         u32 features;
 357         u8 num_temp_limit;
 358         u8 peci_mask;
 359         u8 old_peci_mask;
 360 };
 361
 362 #define FEAT_12MV_ADC           BIT(0)
 363 #define FEAT_NEWER_AUTOPWM      BIT(1)
 364 #define FEAT_OLD_AUTOPWM        BIT(2)
 365 #define FEAT_16BIT_FANS         BIT(3)
 366 #define FEAT_TEMP_OFFSET        BIT(4)
 367 #define FEAT_TEMP_PECI          BIT(5)
 368 #define FEAT_TEMP_OLD_PECI      BIT(6)
 369 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 370 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 371 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 372 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 373 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 374 #define FEAT_10_9MV_ADC         BIT(12)
 375 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 376 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 377 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 378 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 379 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 380 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 381 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 382 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 383 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 384 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 385 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 386
 387 static const struct it87_devices it87_devices[] = {
 388         [it87] = {
 389                 .name = "it87",
 390                 .suffix = "F",
 391                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 392                                                 /* may need to overwrite */
 393                 .num_temp_limit = 3,
 394         },
 395         [it8712] = {
 396                 .name = "it8712",
 397                 .suffix = "F",
 398                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 399                                                 /* may need to overwrite */
 400                 .num_temp_limit = 3,
 401         },
 402         [it8716] = {
 403                 .name = "it8716",
 404                 .suffix = "F",
 405                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 406                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 407                   | FEAT_FANCTL_ONOFF,
 408                 .num_temp_limit = 3,
 409         },
 410         [it8718] = {
 411                 .name = "it8718",
 412                 .suffix = "F",
 413                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 414                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 415                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 416                 .num_temp_limit = 3,
 417                 .old_peci_mask = 0x4,
 418         },
 419         [it8720] = {
 420                 .name = "it8720",
 421                 .suffix = "F",
 422                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 423                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 424                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 425                 .num_temp_limit = 3,
 426                 .old_peci_mask = 0x4,
 427         },
 428         [it8721] = {
 429                 .name = "it8721",
 430                 .suffix = "F",
 431                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 432                   | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 433                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 434                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 435                 .num_temp_limit = 3,
 436                 .peci_mask = 0x05,
 437                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 438         },
 439         [it8728] = {
 440                 .name = "it8728",
 441                 .suffix = "F",
 442                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 443                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 444                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 445                   | FEAT_FANCTL_ONOFF,
 446                 .num_temp_limit = 3,
 447                 .peci_mask = 0x07,
 448         },
 449         [it8732] = {
 450                 .name = "it8732",
 451                 .suffix = "F",
 452                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 453                   | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 454                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 455                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 456                 .num_temp_limit = 3,
 457                 .peci_mask = 0x07,
 458                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 459         },
 460         [it8771] = {
 461                 .name = "it8771",
 462                 .suffix = "E",
 463                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 464                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 465                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 466                                 /* PECI: guesswork */
 467                                 /* 12mV ADC (OHM) */
 468                                 /* 16 bit fans (OHM) */
 469                                 /* three fans, always 16 bit (guesswork) */
 470                 .num_temp_limit = 3,
 471                 .peci_mask = 0x07,
 472         },
 473         [it8772] = {
 474                 .name = "it8772",
 475                 .suffix = "E",
 476                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 477                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 478                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 479                                 /* PECI (coreboot) */
 480                                 /* 12mV ADC (HWSensors4, OHM) */
 481                                 /* 16 bit fans (HWSensors4, OHM) */
 482                                 /* three fans, always 16 bit (datasheet) */
 483                 .num_temp_limit = 3,
 484                 .peci_mask = 0x07,
 485         },
 486         [it8781] = {
 487                 .name = "it8781",
 488                 .suffix = "F",
 489                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 490                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 491                   | FEAT_FANCTL_ONOFF,
 492                 .num_temp_limit = 3,
 493                 .old_peci_mask = 0x4,
 494         },
 495         [it8782] = {
 496                 .name = "it8782",
 497                 .suffix = "F",
 498                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 499                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 500                   | FEAT_FANCTL_ONOFF,
 501                 .num_temp_limit = 3,
 502                 .old_peci_mask = 0x4,
 503         },
 504         [it8783] = {
 505                 .name = "it8783",
 506                 .suffix = "E/F",
 507                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 508                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 509                   | FEAT_FANCTL_ONOFF,
 510                 .num_temp_limit = 3,
 511                 .old_peci_mask = 0x4,
 512         },
 513         [it8786] = {
 514                 .name = "it8786",
 515                 .suffix = "E",
 516                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 517                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 518                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 519                 .num_temp_limit = 3,
 520                 .peci_mask = 0x07,
 521         },
 522         [it8790] = {
 523                 .name = "it8790",
 524                 .suffix = "E",
 525                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 526                   | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
 527                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 528                 .num_temp_limit = 3,
 529                 .peci_mask = 0x07,
 530         },
 531         [it8792] = {
 532                 .name = "it8792",
 533                 .suffix = "E",
 534                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 535                   | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
 536                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 537                 .num_temp_limit = 3,
 538                 .peci_mask = 0x07,
 539         },
 540         [it8603] = {
 541                 .name = "it8603",
 542                 .suffix = "E",
 543                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 544                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 545                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 546                 .num_temp_limit = 3,
 547                 .peci_mask = 0x07,
 548         },
 549         [it8607] = {
 550                 .name = "it8607",
 551                 .suffix = "E",
 552                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 553                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 554                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 555                   | FEAT_FANCTL_ONOFF,
 556                 .num_temp_limit = 3,
 557                 .peci_mask = 0x07,
 558         },
 559         [it8620] = {
 560                 .name = "it8620",
 561                 .suffix = "E",
 562                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 563                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 564                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 565                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 566                   | FEAT_FANCTL_ONOFF,
 567                 .num_temp_limit = 3,
 568                 .peci_mask = 0x07,
 569         },
 570         [it8622] = {
 571                 .name = "it8622",
 572                 .suffix = "E",
 573                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 574                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 575                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 576                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 577                 .num_temp_limit = 3,
 578                 .peci_mask = 0x07,
 579         },
 580         [it8628] = {
 581                 .name = "it8628",
 582                 .suffix = "E",
 583                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 584                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 585                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 586                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 587                   | FEAT_FANCTL_ONOFF,
 588                 .num_temp_limit = 3,
 589                 .peci_mask = 0x07,
 590         },
 591         [it8655] = {
 592                 .name = "it8655",
 593                 .suffix = "E",
 594                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 595                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_AVCC3
 596                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 597                 .num_temp_limit = 6,
 598                 .peci_mask = 0x07,
 599         },
 600         [it8665] = {
 601                 .name = "it8665",
 602                 .suffix = "E",
 603                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 604                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_AVCC3
 605                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 606                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 607                 .num_temp_limit = 6,
 608                 .peci_mask = 0x07,
 609         },
 610         [it8686] = {
 611                 .name = "it8686",
 612                 .suffix = "E",
 613                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 614                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 615                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 616                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 617                 .num_temp_limit = 6,
 618                 .peci_mask = 0x07,
 619         },
 620 };
 621
 622 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 623 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 624 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 625 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 626 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 627 #define has_temp_offset(data)   ((data)->features & FEAT_TEMP_OFFSET)
 628 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 629                                  ((data)->peci_mask & BIT(nr)))
 630 #define has_temp_old_peci(data, nr) \
 631                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 632                                  ((data)->old_peci_mask & BIT(nr)))
 633 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 634 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 635                                                      FEAT_SIX_FANS))
 636 #define has_vid(data)           ((data)->features & FEAT_VID)
 637 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 638 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 639 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 640 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 641                                                      | FEAT_SIX_PWM))
 642 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 643 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 644 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 645 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 646 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 647                                                      FEAT_FIVE_FANS | \
 648                                                      FEAT_SIX_FANS))
 649 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 650                                                      FEAT_FIVE_PWM \
 651                                                      | FEAT_SIX_PWM))
 652 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 653 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 654 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 655
 656 struct it87_sio_data {
 657         enum chips type;
 658         /* Values read from Super-I/O config space */
 659         u8 revision;
 660         u8 vid_value;
 661         u8 beep_pin;
 662         u8 internal;    /* Internal sensors can be labeled */
 663         /* Features skipped based on config or DMI */
 664         u16 skip_in;
 665         u8 skip_vid;
 666         u8 skip_fan;
 667         u8 skip_pwm;
 668         u8 skip_temp;
 669 };
 670
 671 /*
 672  * For each registered chip, we need to keep some data in memory.
 673  * The structure is dynamically allocated.
 674  */
 675 struct it87_data {
 676         const struct attribute_group *groups[7];
 677         enum chips type;
 678         u32 features;
 679         u8 bank;
 680         u8 peci_mask;
 681         u8 old_peci_mask;
 682
 683         const u8 *REG_FAN;
 684         const u8 *REG_FANX;
 685         const u8 *REG_FAN_MIN;
 686         const u8 *REG_FANX_MIN;
 687
 688         const u8 *REG_PWM;
 689
 690         const u8 *REG_TEMP_OFFSET;
 691         const u8 *REG_TEMP_LOW;
 692         const u8 *REG_TEMP_HIGH;
 693
 694         unsigned short addr;
 695         const char *name;
 696         struct mutex update_lock;
 697         char valid;             /* !=0 if following fields are valid */
 698         unsigned long last_updated;     /* In jiffies */
 699
 700         u16 in_scaled;          /* Internal voltage sensors are scaled */
 701         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 702         u16 has_in;             /* Bitfield, voltage sensors enabled */
 703         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 704         u8 has_fan;             /* Bitfield, fans enabled */
 705         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 706         u8 has_temp;            /* Bitfield, temp sensors enabled */
 707         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 708         u8 num_temp_limit;      /* Number of temp limit/offset registers */
 709         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 710         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 711         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 712         bool has_vid;           /* True if VID supported */
 713         u8 vid;                 /* Register encoding, combined */
 714         u8 vrm;
 715         u32 alarms;             /* Register encoding, combined */
 716         bool has_beep;          /* true if beep supported */
 717         u8 beeps;               /* Register encoding */
 718         u8 fan_main_ctrl;       /* Register value */
 719         u8 fan_ctl;             /* Register value */
 720
 721         /*
 722          * The following 3 arrays correspond to the same registers up to
 723          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 724          * 7, and we want to preserve settings on mode changes, so we have
 725          * to track all values separately.
 726          * Starting with the IT8721F, the manual PWM duty cycles are stored
 727          * in separate registers (8-bit values), so the separate tracking
 728          * is no longer needed, but it is still done to keep the driver
 729          * simple.
 730          */
 731         u8 has_pwm;             /* Bitfield, pwm control enabled */
 732         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 733         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 734         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 735
 736         /* Automatic fan speed control registers */
 737         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 738         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 739 };
 740
 741 static int adc_lsb(const struct it87_data *data, int nr)
 742 {
 743         int lsb;
 744
 745         if (has_12mv_adc(data))
 746                 lsb = 120;
 747         else if (has_10_9mv_adc(data))
 748                 lsb = 109;
 749         else
 750                 lsb = 160;
 751         if (data->in_scaled & BIT(nr))
 752                 lsb <<= 1;
 753         return lsb;
 754 }
 755
 756 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 757 {
 758         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 759         return clamp_val(val, 0, 255);
 760 }
 761
 762 static int in_from_reg(const struct it87_data *data, int nr, int val)
 763 {
 764         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 765 }
 766
 767 static inline u8 FAN_TO_REG(long rpm, int div)
 768 {
 769         if (rpm == 0)
 770                 return 255;
 771         rpm = clamp_val(rpm, 1, 1000000);
 772         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 773 }
 774
 775 static inline u16 FAN16_TO_REG(long rpm)
 776 {
 777         if (rpm == 0)
 778                 return 0xffff;
 779         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 780 }
 781
 782 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 783                                 1350000 / ((val) * (div)))
 784 /* The divider is fixed to 2 in 16-bit mode */
 785 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 786                              1350000 / ((val) * 2))
 787
 788 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 789                                     ((val) + 500) / 1000), -128, 127))
 790 #define TEMP_FROM_REG(val) ((val) * 1000)
 791
 792 static u8 pwm_to_reg(const struct it87_data *data, long val)
 793 {
 794         if (has_newer_autopwm(data))
 795                 return val;
 796         else
 797                 return val >> 1;
 798 }
 799
 800 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 801 {
 802         if (has_newer_autopwm(data))
 803                 return reg;
 804         else
 805                 return (reg & 0x7f) << 1;
 806 }
 807
 808 static int DIV_TO_REG(int val)
 809 {
 810         int answer = 0;
 811
 812         while (answer < 7 && (val >>= 1))
 813                 answer++;
 814         return answer;
 815 }
 816
 817 #define DIV_FROM_REG(val) BIT(val)
 818
 819 /*
 820  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 821  * depending on the chip type, to calculate the actual PWM frequency.
 822  *
 823  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 824  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 825  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 826  * sometimes just one. It is unknown if this is a datasheet error or real,
 827  * so this is ignored for now.
 828  */
 829 static const unsigned int pwm_freq[8] = {
 830         48000000,
 831         24000000,
 832         12000000,
 833         8000000,
 834         6000000,
 835         3000000,
 836         1500000,
 837         750000,
 838 };
 839
 840 static int _it87_read_value(struct it87_data *data, u8 reg)
 841 {
 842         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 843         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 844 }
 845
 846 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 847 {
 848         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 849         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 850 }
 851
 852 static void it87_set_bank(struct it87_data *data, u8 bank)
 853 {
 854         if (has_bank_sel(data) && bank != data->bank) {
 855                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 856
 857                 breg &= 0x1f;
 858                 breg |= (bank << 5);
 859                 data->bank = bank;
 860                 _it87_write_value(data, IT87_REG_BANK, breg);
 861         }
 862 }
 863
 864 /*
 865  * Must be called with data->update_lock held, except during initialization.
 866  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 867  * would slow down the IT87 access and should not be necessary.
 868  */
 869 static int it87_read_value(struct it87_data *data, u16 reg)
 870 {
 871         it87_set_bank(data, reg >> 8);
 872         return _it87_read_value(data, reg & 0xff);
 873 }
 874
 875 /*
 876  * Must be called with data->update_lock held, except during initialization.
 877  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 878  * would slow down the IT87 access and should not be necessary.
 879  */
 880 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
 881 {
 882         it87_set_bank(data, reg >> 8);
 883         _it87_write_value(data, reg & 0xff, value);
 884 }
 885
 886 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 887 {
 888         data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]);
 889         if (has_newer_autopwm(data)) {
 890                 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 891                 data->pwm_duty[nr] = it87_read_value(data,
 892                                                      IT87_REG_PWM_DUTY[nr]);
 893         } else {
 894                 if (data->pwm_ctrl[nr] & 0x80)  /* Automatic mode */
 895                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 896                 else                            /* Manual mode */
 897                         data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
 898         }
 899
 900         if (has_old_autopwm(data)) {
 901                 int i;
 902
 903                 for (i = 0; i < 5 ; i++)
 904                         data->auto_temp[nr][i] = it87_read_value(data,
 905                                                 IT87_REG_AUTO_TEMP(nr, i));
 906                 for (i = 0; i < 3 ; i++)
 907                         data->auto_pwm[nr][i] = it87_read_value(data,
 908                                                 IT87_REG_AUTO_PWM(nr, i));
 909         } else if (has_newer_autopwm(data)) {
 910                 int i;
 911
 912                 /*
 913                  * 0: temperature hysteresis (base + 5)
 914                  * 1: fan off temperature (base + 0)
 915                  * 2: fan start temperature (base + 1)
 916                  * 3: fan max temperature (base + 2)
 917                  */
 918                 data->auto_temp[nr][0] =
 919                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
 920
 921                 for (i = 0; i < 3 ; i++)
 922                         data->auto_temp[nr][i + 1] =
 923                                 it87_read_value(data,
 924                                                 IT87_REG_AUTO_TEMP(nr, i));
 925                 /*
 926                  * 0: start pwm value (base + 3)
 927                  * 1: pwm slope (base + 4, 1/8th pwm)
 928                  */
 929                 data->auto_pwm[nr][0] =
 930                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
 931                 data->auto_pwm[nr][1] =
 932                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
 933         }
 934 }
 935
 936 static struct it87_data *it87_update_device(struct device *dev)
 937 {
 938         struct it87_data *data = dev_get_drvdata(dev);
 939         int i;
 940
 941         mutex_lock(&data->update_lock);
 942
 943         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
 944             !data->valid) {
 945                 if (update_vbat) {
 946                         /*
 947                          * Cleared after each update, so reenable.  Value
 948                          * returned by this read will be previous value
 949                          */
 950                         it87_write_value(data, IT87_REG_CONFIG,
 951                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
 952                 }
 953                 for (i = 0; i < NUM_VIN; i++) {
 954                         if (!(data->has_in & BIT(i)))
 955                                 continue;
 956
 957                         data->in[i][0] =
 958                                 it87_read_value(data, IT87_REG_VIN[i]);
 959
 960                         /* VBAT and AVCC don't have limit registers */
 961                         if (i >= NUM_VIN_LIMIT)
 962                                 continue;
 963
 964                         data->in[i][1] =
 965                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
 966                         data->in[i][2] =
 967                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
 968                 }
 969
 970                 for (i = 0; i < NUM_FAN; i++) {
 971                         /* Skip disabled fans */
 972                         if (!(data->has_fan & BIT(i)))
 973                                 continue;
 974
 975                         data->fan[i][1] =
 976                                 it87_read_value(data, data->REG_FAN_MIN[i]);
 977                         data->fan[i][0] = it87_read_value(data,
 978                                        data->REG_FAN[i]);
 979                         /* Add high byte if in 16-bit mode */
 980                         if (has_16bit_fans(data)) {
 981                                 data->fan[i][0] |= it87_read_value(data,
 982                                                 data->REG_FANX[i]) << 8;
 983                                 data->fan[i][1] |= it87_read_value(data,
 984                                                 data->REG_FANX_MIN[i]) << 8;
 985                         }
 986                 }
 987                 for (i = 0; i < NUM_TEMP; i++) {
 988                         if (!(data->has_temp & BIT(i)))
 989                                 continue;
 990                         data->temp[i][0] =
 991                                 it87_read_value(data, IT87_REG_TEMP(i));
 992
 993                         if (i >= data->num_temp_limit)
 994                                 continue;
 995
 996                         if (has_temp_offset(data))
 997                                 data->temp[i][3] =
 998                                   it87_read_value(data,
 999                                                   data->REG_TEMP_OFFSET[i]);
1000
1001                         data->temp[i][1] =
1002                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1003                         data->temp[i][2] =
1004                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1005                 }
1006
1007                 /* Newer chips don't have clock dividers */
1008                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1009                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1010                         data->fan_div[0] = i & 0x07;
1011                         data->fan_div[1] = (i >> 3) & 0x07;
1012                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1013                 }
1014
1015                 data->alarms =
1016                         it87_read_value(data, IT87_REG_ALARM1) |
1017                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1018                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1019                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1020
1021                 data->fan_main_ctrl = it87_read_value(data,
1022                                 IT87_REG_FAN_MAIN_CTRL);
1023                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1024                 for (i = 0; i < NUM_PWM; i++) {
1025                         if (!(data->has_pwm & BIT(i)))
1026                                 continue;
1027                         it87_update_pwm_ctrl(data, i);
1028                 }
1029
1030                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1031                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1032                 /*
1033                  * The IT8705F does not have VID capability.
1034                  * The IT8718F and later don't use IT87_REG_VID for the
1035                  * same purpose.
1036                  */
1037                 if (data->type == it8712 || data->type == it8716) {
1038                         data->vid = it87_read_value(data, IT87_REG_VID);
1039                         /*
1040                          * The older IT8712F revisions had only 5 VID pins,
1041                          * but we assume it is always safe to read 6 bits.
1042                          */
1043                         data->vid &= 0x3f;
1044                 }
1045                 data->last_updated = jiffies;
1046                 data->valid = 1;
1047         }
1048
1049         mutex_unlock(&data->update_lock);
1050
1051         return data;
1052 }
1053
1054 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1055                        char *buf)
1056 {
1057         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1058         struct it87_data *data = it87_update_device(dev);
1059         int index = sattr->index;
1060         int nr = sattr->nr;
1061
1062         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1063 }
1064
1065 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1066                       const char *buf, size_t count)
1067 {
1068         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1069         struct it87_data *data = dev_get_drvdata(dev);
1070         int index = sattr->index;
1071         int nr = sattr->nr;
1072         unsigned long val;
1073
1074         if (kstrtoul(buf, 10, &val) < 0)
1075                 return -EINVAL;
1076
1077         mutex_lock(&data->update_lock);
1078         data->in[nr][index] = in_to_reg(data, nr, val);
1079         it87_write_value(data,
1080                          index == 1 ? IT87_REG_VIN_MIN(nr)
1081                                     : IT87_REG_VIN_MAX(nr),
1082                          data->in[nr][index]);
1083         mutex_unlock(&data->update_lock);
1084         return count;
1085 }
1086
1087 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1088 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1089                             0, 1);
1090 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1091                             0, 2);
1092
1093 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1094 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1095                             1, 1);
1096 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1097                             1, 2);
1098
1099 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1100 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1101                             2, 1);
1102 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1103                             2, 2);
1104
1105 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1106 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1107                             3, 1);
1108 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1109                             3, 2);
1110
1111 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1112 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1113                             4, 1);
1114 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1115                             4, 2);
1116
1117 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1118 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1119                             5, 1);
1120 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1121                             5, 2);
1122
1123 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1124 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1125                             6, 1);
1126 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1127                             6, 2);
1128
1129 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1130 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1131                             7, 1);
1132 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1133                             7, 2);
1134
1135 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1136 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1137 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1138 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1139 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1140
1141 /* Up to 6 temperatures */
1142 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1143                          char *buf)
1144 {
1145         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1146         int nr = sattr->nr;
1147         int index = sattr->index;
1148         struct it87_data *data = it87_update_device(dev);
1149
1150         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1151 }
1152
1153 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1154                         const char *buf, size_t count)
1155 {
1156         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1157         int nr = sattr->nr;
1158         int index = sattr->index;
1159         struct it87_data *data = dev_get_drvdata(dev);
1160         long val;
1161         u8 reg, regval;
1162
1163         if (kstrtol(buf, 10, &val) < 0)
1164                 return -EINVAL;
1165
1166         mutex_lock(&data->update_lock);
1167
1168         switch (index) {
1169         default:
1170         case 1:
1171                 reg = data->REG_TEMP_LOW[nr];
1172                 break;
1173         case 2:
1174                 reg = data->REG_TEMP_HIGH[nr];
1175                 break;
1176         case 3:
1177                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1178                 if (!(regval & 0x80)) {
1179                         regval |= 0x80;
1180                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1181                 }
1182                 data->valid = 0;
1183                 reg = data->REG_TEMP_OFFSET[nr];
1184                 break;
1185         }
1186
1187         data->temp[nr][index] = TEMP_TO_REG(val);
1188         it87_write_value(data, reg, data->temp[nr][index]);
1189         mutex_unlock(&data->update_lock);
1190         return count;
1191 }
1192
1193 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1194 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1195                             0, 1);
1196 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1197                             0, 2);
1198 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1199                             set_temp, 0, 3);
1200 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1201 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1202                             1, 1);
1203 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1204                             1, 2);
1205 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1206                             set_temp, 1, 3);
1207 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1208 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1209                             2, 1);
1210 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1211                             2, 2);
1212 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1213                             set_temp, 2, 3);
1214 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1215 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1216                             3, 1);
1217 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1218                             3, 2);
1219 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1220                             set_temp, 3, 3);
1221 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1222 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1223                             4, 1);
1224 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1225                             4, 2);
1226 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1227                             set_temp, 4, 3);
1228 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1229 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1230                             5, 1);
1231 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1232                             5, 2);
1233 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1234                             set_temp, 5, 3);
1235
1236 static int get_temp_type(struct it87_data *data, int index)
1237 {
1238         u8 reg, extra;
1239         int type = 0;
1240
1241         if (has_bank_sel(data)) {
1242                 int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
1243                 u8 src1, src2;
1244
1245                 src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
1246                 src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
1247
1248                 switch (data->type) {
1249                 case it8686:
1250                         switch (src1) {
1251                         case 0:
1252                                 if (index >= 3)
1253                                         return 4;
1254                                 break;
1255                         case 1:
1256                                 if (index == 1 || index == 2 ||
1257                                           index == 4 || index == 5)
1258                                         return 6;
1259                                 break;
1260                         case 2:
1261                                 if (index == 2 || index == 6)
1262                                         return 5;
1263                                 break;
1264                         default:
1265                                 break;
1266                         }
1267                         break;
1268                 case it8655:
1269                 case it8665:
1270                         if (src1 < 3) {
1271                                 index = src1;
1272                                 break;
1273                         }
1274                         switch(src1) {
1275                         case 3:
1276                                 type = (src2 & BIT(index)) ? 6 : 5;
1277                                 break;
1278                         case 4 ... 8:
1279                                 type = (src2 & BIT(index)) ? 4 : 6;
1280                                 break;
1281                         case 9:
1282                                 type = (src2 & BIT(index)) ? 5 : 0;
1283                                 break;
1284                         default:
1285                                 break;
1286                         }
1287                         return type;
1288                 default:
1289                         return 0;
1290                 }
1291         }
1292         if (index >= 3)
1293                 return 0;
1294
1295         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1296         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1297
1298         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1299             (has_temp_old_peci(data, index) && (extra & 0x80)))
1300                 type = 6;               /* Intel PECI */
1301         if (reg & BIT(index))
1302                 type = 3;               /* thermal diode */
1303         else if (reg & BIT(index + 3))
1304                 type = 4;               /* thermistor */
1305
1306         return type;
1307 }
1308
1309 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1310                               char *buf)
1311 {
1312         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1313         struct it87_data *data = it87_update_device(dev);
1314         int type = get_temp_type(data, sensor_attr->index);
1315
1316         return sprintf(buf, "%d\n", type);
1317 }
1318
1319 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1320                              const char *buf, size_t count)
1321 {
1322         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1323         int nr = sensor_attr->index;
1324
1325         struct it87_data *data = dev_get_drvdata(dev);
1326         long val;
1327         u8 reg, extra;
1328
1329         if (kstrtol(buf, 10, &val) < 0)
1330                 return -EINVAL;
1331
1332         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1333         reg &= ~(1 << nr);
1334         reg &= ~(8 << nr);
1335         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1336                 reg &= 0x3f;
1337         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1338         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1339                 extra &= 0x7f;
1340         if (val == 2) { /* backwards compatibility */
1341                 dev_warn(dev,
1342                          "Sensor type 2 is deprecated, please use 4 instead\n");
1343                 val = 4;
1344         }
1345         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1346         if (val == 3)
1347                 reg |= 1 << nr;
1348         else if (val == 4)
1349                 reg |= 8 << nr;
1350         else if (has_temp_peci(data, nr) && val == 6)
1351                 reg |= (nr + 1) << 6;
1352         else if (has_temp_old_peci(data, nr) && val == 6)
1353                 extra |= 0x80;
1354         else if (val != 0)
1355                 return -EINVAL;
1356
1357         mutex_lock(&data->update_lock);
1358         data->sensor = reg;
1359         data->extra = extra;
1360         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1361         if (has_temp_old_peci(data, nr))
1362                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1363         data->valid = 0;        /* Force cache refresh */
1364         mutex_unlock(&data->update_lock);
1365         return count;
1366 }
1367
1368 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1369                           set_temp_type, 0);
1370 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1371                           set_temp_type, 1);
1372 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1373                           set_temp_type, 2);
1374 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1375                           set_temp_type, 3);
1376 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1377                           set_temp_type, 4);
1378 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1379                           set_temp_type, 5);
1380
1381 /* 6 Fans */
1382
1383 static int pwm_mode(const struct it87_data *data, int nr)
1384 {
1385         if (has_fanctl_onoff(data) && nr < 3 &&
1386             !(data->fan_main_ctrl & BIT(nr)))
1387                 return 0;                               /* Full speed */
1388         if (data->pwm_ctrl[nr] & 0x80)
1389                 return 2;                               /* Automatic mode */
1390         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1391             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1392                 return 0;                       /* Full speed */
1393
1394         return 1;                               /* Manual mode */
1395 }
1396
1397 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1398                         char *buf)
1399 {
1400         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1401         int nr = sattr->nr;
1402         int index = sattr->index;
1403         int speed;
1404         struct it87_data *data = it87_update_device(dev);
1405
1406         speed = has_16bit_fans(data) ?
1407                 FAN16_FROM_REG(data->fan[nr][index]) :
1408                 FAN_FROM_REG(data->fan[nr][index],
1409                              DIV_FROM_REG(data->fan_div[nr]));
1410         return sprintf(buf, "%d\n", speed);
1411 }
1412
1413 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1414                             char *buf)
1415 {
1416         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1417         struct it87_data *data = it87_update_device(dev);
1418         int nr = sensor_attr->index;
1419
1420         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1421 }
1422
1423 static ssize_t show_pwm_enable(struct device *dev,
1424                                struct device_attribute *attr, char *buf)
1425 {
1426         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1427         struct it87_data *data = it87_update_device(dev);
1428         int nr = sensor_attr->index;
1429
1430         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1431 }
1432
1433 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1434                         char *buf)
1435 {
1436         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1437         struct it87_data *data = it87_update_device(dev);
1438         int nr = sensor_attr->index;
1439
1440         return sprintf(buf, "%d\n",
1441                        pwm_from_reg(data, data->pwm_duty[nr]));
1442 }
1443
1444 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1445                              char *buf)
1446 {
1447         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1448         struct it87_data *data = it87_update_device(dev);
1449         int nr = sensor_attr->index;
1450         unsigned int freq;
1451         int index;
1452
1453         if (has_pwm_freq2(data) && nr == 1)
1454                 index = (data->extra >> 4) & 0x07;
1455         else
1456                 index = (data->fan_ctl >> 4) & 0x07;
1457
1458         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1459
1460         return sprintf(buf, "%u\n", freq);
1461 }
1462
1463 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1464                        const char *buf, size_t count)
1465 {
1466         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1467         int nr = sattr->nr;
1468         int index = sattr->index;
1469
1470         struct it87_data *data = dev_get_drvdata(dev);
1471         long val;
1472         u8 reg;
1473
1474         if (kstrtol(buf, 10, &val) < 0)
1475                 return -EINVAL;
1476
1477         mutex_lock(&data->update_lock);
1478
1479         if (has_16bit_fans(data)) {
1480                 data->fan[nr][index] = FAN16_TO_REG(val);
1481                 it87_write_value(data, data->REG_FAN_MIN[nr],
1482                                  data->fan[nr][index] & 0xff);
1483                 it87_write_value(data, data->REG_FANX_MIN[nr],
1484                                  data->fan[nr][index] >> 8);
1485         } else {
1486                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1487                 switch (nr) {
1488                 case 0:
1489                         data->fan_div[nr] = reg & 0x07;
1490                         break;
1491                 case 1:
1492                         data->fan_div[nr] = (reg >> 3) & 0x07;
1493                         break;
1494                 case 2:
1495                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1496                         break;
1497                 }
1498                 data->fan[nr][index] =
1499                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1500                 it87_write_value(data, data->REG_FAN_MIN[nr],
1501                                  data->fan[nr][index]);
1502         }
1503
1504         mutex_unlock(&data->update_lock);
1505         return count;
1506 }
1507
1508 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1509                            const char *buf, size_t count)
1510 {
1511         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1512         struct it87_data *data = dev_get_drvdata(dev);
1513         int nr = sensor_attr->index;
1514         unsigned long val;
1515         int min;
1516         u8 old;
1517
1518         if (kstrtoul(buf, 10, &val) < 0)
1519                 return -EINVAL;
1520
1521         mutex_lock(&data->update_lock);
1522         old = it87_read_value(data, IT87_REG_FAN_DIV);
1523
1524         /* Save fan min limit */
1525         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1526
1527         switch (nr) {
1528         case 0:
1529         case 1:
1530                 data->fan_div[nr] = DIV_TO_REG(val);
1531                 break;
1532         case 2:
1533                 if (val < 8)
1534                         data->fan_div[nr] = 1;
1535                 else
1536                         data->fan_div[nr] = 3;
1537         }
1538         val = old & 0x80;
1539         val |= (data->fan_div[0] & 0x07);
1540         val |= (data->fan_div[1] & 0x07) << 3;
1541         if (data->fan_div[2] == 3)
1542                 val |= 0x1 << 6;
1543         it87_write_value(data, IT87_REG_FAN_DIV, val);
1544
1545         /* Restore fan min limit */
1546         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1547         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1548
1549         mutex_unlock(&data->update_lock);
1550         return count;
1551 }
1552
1553 /* Returns 0 if OK, -EINVAL otherwise */
1554 static int check_trip_points(struct device *dev, int nr)
1555 {
1556         const struct it87_data *data = dev_get_drvdata(dev);
1557         int i, err = 0;
1558
1559         if (has_old_autopwm(data)) {
1560                 for (i = 0; i < 3; i++) {
1561                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1562                                 err = -EINVAL;
1563                 }
1564                 for (i = 0; i < 2; i++) {
1565                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1566                                 err = -EINVAL;
1567                 }
1568         } else if (has_newer_autopwm(data)) {
1569                 for (i = 1; i < 3; i++) {
1570                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1571                                 err = -EINVAL;
1572                 }
1573         }
1574
1575         if (err) {
1576                 dev_err(dev,
1577                         "Inconsistent trip points, not switching to automatic mode\n");
1578                 dev_err(dev, "Adjust the trip points and try again\n");
1579         }
1580         return err;
1581 }
1582
1583 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1584                               const char *buf, size_t count)
1585 {
1586         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1587         struct it87_data *data = dev_get_drvdata(dev);
1588         int nr = sensor_attr->index;
1589         long val;
1590
1591         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1592                 return -EINVAL;
1593
1594         /* Check trip points before switching to automatic mode */
1595         if (val == 2) {
1596                 if (check_trip_points(dev, nr) < 0)
1597                         return -EINVAL;
1598         }
1599
1600         mutex_lock(&data->update_lock);
1601
1602         if (val == 0) {
1603                 if (nr < 3 && has_fanctl_onoff(data)) {
1604                         int tmp;
1605                         /* make sure the fan is on when in on/off mode */
1606                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1607                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1608                         /* set on/off mode */
1609                         data->fan_main_ctrl &= ~BIT(nr);
1610                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1611                                          data->fan_main_ctrl);
1612                 } else {
1613                         u8 ctrl;
1614
1615                         /* No on/off mode, set maximum pwm value */
1616                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1617                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1618                                          data->pwm_duty[nr]);
1619                         /* and set manual mode */
1620                         if (has_newer_autopwm(data)) {
1621                                 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1622                                         data->pwm_temp_map[nr];
1623                         } else {
1624                                 ctrl = data->pwm_duty[nr];
1625                         }
1626                         data->pwm_ctrl[nr] = ctrl;
1627                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1628                 }
1629         } else {
1630                 u8 ctrl;
1631
1632                 if (has_newer_autopwm(data)) {
1633                         ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1634                                 data->pwm_temp_map[nr];
1635                         if (val != 1)
1636                                 ctrl |= 0x80;
1637                 } else {
1638                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1639                 }
1640                 data->pwm_ctrl[nr] = ctrl;
1641                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1642
1643                 if (has_fanctl_onoff(data) && nr < 3) {
1644                         /* set SmartGuardian mode */
1645                         data->fan_main_ctrl |= BIT(nr);
1646                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1647                                          data->fan_main_ctrl);
1648                 }
1649         }
1650
1651         mutex_unlock(&data->update_lock);
1652         return count;
1653 }
1654
1655 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1656                        const char *buf, size_t count)
1657 {
1658         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1659         struct it87_data *data = dev_get_drvdata(dev);
1660         int nr = sensor_attr->index;
1661         long val;
1662
1663         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1664                 return -EINVAL;
1665
1666         mutex_lock(&data->update_lock);
1667         it87_update_pwm_ctrl(data, nr);
1668         if (has_newer_autopwm(data)) {
1669                 /*
1670                  * If we are in automatic mode, the PWM duty cycle register
1671                  * is read-only so we can't write the value.
1672                  */
1673                 if (data->pwm_ctrl[nr] & 0x80) {
1674                         mutex_unlock(&data->update_lock);
1675                         return -EBUSY;
1676                 }
1677                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1678                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1679                                  data->pwm_duty[nr]);
1680         } else {
1681                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1682                 /*
1683                  * If we are in manual mode, write the duty cycle immediately;
1684                  * otherwise, just store it for later use.
1685                  */
1686                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1687                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1688                         it87_write_value(data, data->REG_PWM[nr],
1689                                          data->pwm_ctrl[nr]);
1690                 }
1691         }
1692         mutex_unlock(&data->update_lock);
1693         return count;
1694 }
1695
1696 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1697                             const char *buf, size_t count)
1698 {
1699         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1700         struct it87_data *data = dev_get_drvdata(dev);
1701         int nr = sensor_attr->index;
1702         unsigned long val;
1703         int i;
1704
1705         if (kstrtoul(buf, 10, &val) < 0)
1706                 return -EINVAL;
1707
1708         val = clamp_val(val, 0, 1000000);
1709         val *= has_newer_autopwm(data) ? 256 : 128;
1710
1711         /* Search for the nearest available frequency */
1712         for (i = 0; i < 7; i++) {
1713                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1714                         break;
1715         }
1716
1717         mutex_lock(&data->update_lock);
1718         if (nr == 0) {
1719                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1720                 data->fan_ctl |= i << 4;
1721                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1722         } else {
1723                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1724                 data->extra |= i << 4;
1725                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1726         }
1727         mutex_unlock(&data->update_lock);
1728
1729         return count;
1730 }
1731
1732 static ssize_t show_pwm_temp_map(struct device *dev,
1733                                  struct device_attribute *attr, char *buf)
1734 {
1735         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1736         struct it87_data *data = it87_update_device(dev);
1737         int nr = sensor_attr->index;
1738         int map;
1739
1740         map = data->pwm_temp_map[nr];
1741         if (map >= 3)
1742                 map = 0;        /* Should never happen */
1743         if (nr >= 3)            /* pwm channels 3..6 map to temp4..6 */
1744                 map += 3;
1745
1746         return sprintf(buf, "%d\n", (int)BIT(map));
1747 }
1748
1749 static ssize_t set_pwm_temp_map(struct device *dev,
1750                                 struct device_attribute *attr, const char *buf,
1751                                 size_t count)
1752 {
1753         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1754         struct it87_data *data = dev_get_drvdata(dev);
1755         int nr = sensor_attr->index;
1756         long val;
1757         u8 reg;
1758
1759         if (kstrtol(buf, 10, &val) < 0)
1760                 return -EINVAL;
1761
1762         if (nr >= 3)
1763                 val -= 3;
1764
1765         switch (val) {
1766         case BIT(0):
1767                 reg = 0x00;
1768                 break;
1769         case BIT(1):
1770                 reg = 0x01;
1771                 break;
1772         case BIT(2):
1773                 reg = 0x02;
1774                 break;
1775         default:
1776                 return -EINVAL;
1777         }
1778
1779         mutex_lock(&data->update_lock);
1780         it87_update_pwm_ctrl(data, nr);
1781         data->pwm_temp_map[nr] = reg;
1782         /*
1783          * If we are in automatic mode, write the temp mapping immediately;
1784          * otherwise, just store it for later use.
1785          */
1786         if (data->pwm_ctrl[nr] & 0x80) {
1787                 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
1788                                                 data->pwm_temp_map[nr];
1789                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1790         }
1791         mutex_unlock(&data->update_lock);
1792         return count;
1793 }
1794
1795 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1796                              char *buf)
1797 {
1798         struct it87_data *data = it87_update_device(dev);
1799         struct sensor_device_attribute_2 *sensor_attr =
1800                         to_sensor_dev_attr_2(attr);
1801         int nr = sensor_attr->nr;
1802         int point = sensor_attr->index;
1803
1804         return sprintf(buf, "%d\n",
1805                        pwm_from_reg(data, data->auto_pwm[nr][point]));
1806 }
1807
1808 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1809                             const char *buf, size_t count)
1810 {
1811         struct it87_data *data = dev_get_drvdata(dev);
1812         struct sensor_device_attribute_2 *sensor_attr =
1813                         to_sensor_dev_attr_2(attr);
1814         int nr = sensor_attr->nr;
1815         int point = sensor_attr->index;
1816         int regaddr;
1817         long val;
1818
1819         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1820                 return -EINVAL;
1821
1822         mutex_lock(&data->update_lock);
1823         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1824         if (has_newer_autopwm(data))
1825                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1826         else
1827                 regaddr = IT87_REG_AUTO_PWM(nr, point);
1828         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1829         mutex_unlock(&data->update_lock);
1830         return count;
1831 }
1832
1833 static ssize_t show_auto_pwm_slope(struct device *dev,
1834                                    struct device_attribute *attr, char *buf)
1835 {
1836         struct it87_data *data = it87_update_device(dev);
1837         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1838         int nr = sensor_attr->index;
1839
1840         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1841 }
1842
1843 static ssize_t set_auto_pwm_slope(struct device *dev,
1844                                   struct device_attribute *attr,
1845                                   const char *buf, size_t count)
1846 {
1847         struct it87_data *data = dev_get_drvdata(dev);
1848         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1849         int nr = sensor_attr->index;
1850         unsigned long val;
1851
1852         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1853                 return -EINVAL;
1854
1855         mutex_lock(&data->update_lock);
1856         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1857         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1858                          data->auto_pwm[nr][1]);
1859         mutex_unlock(&data->update_lock);
1860         return count;
1861 }
1862
1863 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1864                               char *buf)
1865 {
1866         struct it87_data *data = it87_update_device(dev);
1867         struct sensor_device_attribute_2 *sensor_attr =
1868                         to_sensor_dev_attr_2(attr);
1869         int nr = sensor_attr->nr;
1870         int point = sensor_attr->index;
1871         int reg;
1872
1873         if (has_old_autopwm(data) || point)
1874                 reg = data->auto_temp[nr][point];
1875         else
1876                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1877
1878         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1879 }
1880
1881 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1882                              const char *buf, size_t count)
1883 {
1884         struct it87_data *data = dev_get_drvdata(dev);
1885         struct sensor_device_attribute_2 *sensor_attr =
1886                         to_sensor_dev_attr_2(attr);
1887         int nr = sensor_attr->nr;
1888         int point = sensor_attr->index;
1889         long val;
1890         int reg;
1891
1892         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1893                 return -EINVAL;
1894
1895         mutex_lock(&data->update_lock);
1896         if (has_newer_autopwm(data) && !point) {
1897                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1898                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1899                 data->auto_temp[nr][0] = reg;
1900                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1901         } else {
1902                 reg = TEMP_TO_REG(val);
1903                 data->auto_temp[nr][point] = reg;
1904                 if (has_newer_autopwm(data))
1905                         point--;
1906                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1907         }
1908         mutex_unlock(&data->update_lock);
1909         return count;
1910 }
1911
1912 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1913 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1914                             0, 1);
1915 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1916                           set_fan_div, 0);
1917
1918 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1919 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1920                             1, 1);
1921 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1922                           set_fan_div, 1);
1923
1924 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1925 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1926                             2, 1);
1927 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1928                           set_fan_div, 2);
1929
1930 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1931 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1932                             3, 1);
1933
1934 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1935 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1936                             4, 1);
1937
1938 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1939 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1940                             5, 1);
1941
1942 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1943                           show_pwm_enable, set_pwm_enable, 0);
1944 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1945 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1946                           set_pwm_freq, 0);
1947 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
1948                           show_pwm_temp_map, set_pwm_temp_map, 0);
1949 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1950                             show_auto_pwm, set_auto_pwm, 0, 0);
1951 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1952                             show_auto_pwm, set_auto_pwm, 0, 1);
1953 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1954                             show_auto_pwm, set_auto_pwm, 0, 2);
1955 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1956                             show_auto_pwm, NULL, 0, 3);
1957 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1958                             show_auto_temp, set_auto_temp, 0, 1);
1959 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1960                             show_auto_temp, set_auto_temp, 0, 0);
1961 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1962                             show_auto_temp, set_auto_temp, 0, 2);
1963 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1964                             show_auto_temp, set_auto_temp, 0, 3);
1965 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1966                             show_auto_temp, set_auto_temp, 0, 4);
1967 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
1968                             show_auto_pwm, set_auto_pwm, 0, 0);
1969 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
1970                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
1971
1972 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1973                           show_pwm_enable, set_pwm_enable, 1);
1974 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1975 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
1976 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
1977                           show_pwm_temp_map, set_pwm_temp_map, 1);
1978 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1979                             show_auto_pwm, set_auto_pwm, 1, 0);
1980 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1981                             show_auto_pwm, set_auto_pwm, 1, 1);
1982 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1983                             show_auto_pwm, set_auto_pwm, 1, 2);
1984 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1985                             show_auto_pwm, NULL, 1, 3);
1986 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1987                             show_auto_temp, set_auto_temp, 1, 1);
1988 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1989                             show_auto_temp, set_auto_temp, 1, 0);
1990 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1991                             show_auto_temp, set_auto_temp, 1, 2);
1992 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1993                             show_auto_temp, set_auto_temp, 1, 3);
1994 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1995                             show_auto_temp, set_auto_temp, 1, 4);
1996 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
1997                             show_auto_pwm, set_auto_pwm, 1, 0);
1998 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
1999                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2000
2001 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2002                           show_pwm_enable, set_pwm_enable, 2);
2003 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2004 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2005 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2006                           show_pwm_temp_map, set_pwm_temp_map, 2);
2007 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2008                             show_auto_pwm, set_auto_pwm, 2, 0);
2009 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2010                             show_auto_pwm, set_auto_pwm, 2, 1);
2011 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2012                             show_auto_pwm, set_auto_pwm, 2, 2);
2013 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2014                             show_auto_pwm, NULL, 2, 3);
2015 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2016                             show_auto_temp, set_auto_temp, 2, 1);
2017 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2018                             show_auto_temp, set_auto_temp, 2, 0);
2019 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2020                             show_auto_temp, set_auto_temp, 2, 2);
2021 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2022                             show_auto_temp, set_auto_temp, 2, 3);
2023 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2024                             show_auto_temp, set_auto_temp, 2, 4);
2025 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2026                             show_auto_pwm, set_auto_pwm, 2, 0);
2027 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2028                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2029
2030 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2031                           show_pwm_enable, set_pwm_enable, 3);
2032 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2033 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2034 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2035                           show_pwm_temp_map, set_pwm_temp_map, 3);
2036 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2037                             show_auto_temp, set_auto_temp, 2, 1);
2038 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2039                             show_auto_temp, set_auto_temp, 2, 0);
2040 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2041                             show_auto_temp, set_auto_temp, 2, 2);
2042 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2043                             show_auto_temp, set_auto_temp, 2, 3);
2044 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2045                             show_auto_pwm, set_auto_pwm, 3, 0);
2046 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2047                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2048
2049 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2050                           show_pwm_enable, set_pwm_enable, 4);
2051 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2052 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2053 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2054                           show_pwm_temp_map, set_pwm_temp_map, 4);
2055 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2056                             show_auto_temp, set_auto_temp, 2, 1);
2057 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2058                             show_auto_temp, set_auto_temp, 2, 0);
2059 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2060                             show_auto_temp, set_auto_temp, 2, 2);
2061 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2062                             show_auto_temp, set_auto_temp, 2, 3);
2063 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2064                             show_auto_pwm, set_auto_pwm, 4, 0);
2065 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2066                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2067
2068 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2069                           show_pwm_enable, set_pwm_enable, 5);
2070 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2071 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2072 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2073                           show_pwm_temp_map, set_pwm_temp_map, 5);
2074 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2075                             show_auto_temp, set_auto_temp, 2, 1);
2076 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2077                             show_auto_temp, set_auto_temp, 2, 0);
2078 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2079                             show_auto_temp, set_auto_temp, 2, 2);
2080 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2081                             show_auto_temp, set_auto_temp, 2, 3);
2082 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2083                             show_auto_pwm, set_auto_pwm, 5, 0);
2084 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2085                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2086
2087 /* Alarms */
2088 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2089                            char *buf)
2090 {
2091         struct it87_data *data = it87_update_device(dev);
2092
2093         return sprintf(buf, "%u\n", data->alarms);
2094 }
2095 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2096
2097 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2098                           char *buf)
2099 {
2100         struct it87_data *data = it87_update_device(dev);
2101         int bitnr = to_sensor_dev_attr(attr)->index;
2102
2103         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2104 }
2105
2106 static ssize_t clear_intrusion(struct device *dev,
2107                                struct device_attribute *attr, const char *buf,
2108                                size_t count)
2109 {
2110         struct it87_data *data = dev_get_drvdata(dev);
2111         int config;
2112         long val;
2113
2114         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2115                 return -EINVAL;
2116
2117         mutex_lock(&data->update_lock);
2118         config = it87_read_value(data, IT87_REG_CONFIG);
2119         if (config < 0) {
2120                 count = config;
2121         } else {
2122                 config |= BIT(5);
2123                 it87_write_value(data, IT87_REG_CONFIG, config);
2124                 /* Invalidate cache to force re-read */
2125                 data->valid = 0;
2126         }
2127         mutex_unlock(&data->update_lock);
2128
2129         return count;
2130 }
2131
2132 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2133 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2134 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2135 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2136 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2137 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2138 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2139 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2140 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2141 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2142 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2143 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2144 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2145 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2146 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2147 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2148 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2149 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2150 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2151 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2152 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2153                           show_alarm, clear_intrusion, 4);
2154
2155 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2156                          char *buf)
2157 {
2158         struct it87_data *data = it87_update_device(dev);
2159         int bitnr = to_sensor_dev_attr(attr)->index;
2160
2161         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2162 }
2163
2164 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2165                         const char *buf, size_t count)
2166 {
2167         int bitnr = to_sensor_dev_attr(attr)->index;
2168         struct it87_data *data = dev_get_drvdata(dev);
2169         long val;
2170
2171         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2172                 return -EINVAL;
2173
2174         mutex_lock(&data->update_lock);
2175         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2176         if (val)
2177                 data->beeps |= BIT(bitnr);
2178         else
2179                 data->beeps &= ~BIT(bitnr);
2180         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2181         mutex_unlock(&data->update_lock);
2182         return count;
2183 }
2184
2185 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2186                           show_beep, set_beep, 1);
2187 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2188 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2189 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2190 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2191 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2192 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2193 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2194 /* fanX_beep writability is set later */
2195 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2196 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2197 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2198 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2199 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2200 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2201 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2202                           show_beep, set_beep, 2);
2203 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2204 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2205 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2206 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2207 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2208
2209 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2210                             char *buf)
2211 {
2212         struct it87_data *data = dev_get_drvdata(dev);
2213
2214         return sprintf(buf, "%u\n", data->vrm);
2215 }
2216
2217 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2218                              const char *buf, size_t count)
2219 {
2220         struct it87_data *data = dev_get_drvdata(dev);
2221         unsigned long val;
2222
2223         if (kstrtoul(buf, 10, &val) < 0)
2224                 return -EINVAL;
2225
2226         data->vrm = val;
2227
2228         return count;
2229 }
2230 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2231
2232 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2233                             char *buf)
2234 {
2235         struct it87_data *data = it87_update_device(dev);
2236
2237         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2238 }
2239 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2240
2241 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2242                           char *buf)
2243 {
2244         static const char * const labels[] = {
2245                 "+5V",
2246                 "5VSB",
2247                 "Vbat",
2248                 "AVCC",
2249         };
2250         static const char * const labels_it8721[] = {
2251                 "+3.3V",
2252                 "3VSB",
2253                 "Vbat",
2254                 "+3.3V",
2255         };
2256         struct it87_data *data = dev_get_drvdata(dev);
2257         int nr = to_sensor_dev_attr(attr)->index;
2258         const char *label;
2259
2260         if (has_vin3_5v(data) && nr == 0)
2261                 label = labels[0];
2262         else if (has_12mv_adc(data) || has_10_9mv_adc(data))
2263                 label = labels_it8721[nr];
2264         else
2265                 label = labels[nr];
2266
2267         return sprintf(buf, "%s\n", label);
2268 }
2269 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2270 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2271 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2272 /* AVCC3 */
2273 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2274
2275 static umode_t it87_in_is_visible(struct kobject *kobj,
2276                                   struct attribute *attr, int index)
2277 {
2278         struct device *dev = container_of(kobj, struct device, kobj);
2279         struct it87_data *data = dev_get_drvdata(dev);
2280         int i = index / 5;      /* voltage index */
2281         int a = index % 5;      /* attribute index */
2282
2283         if (index >= 40) {      /* in8 and higher only have input attributes */
2284                 i = index - 40 + 8;
2285                 a = 0;
2286         }
2287
2288         if (!(data->has_in & BIT(i)))
2289                 return 0;
2290
2291         if (a == 4 && !data->has_beep)
2292                 return 0;
2293
2294         return attr->mode;
2295 }
2296
2297 static struct attribute *it87_attributes_in[] = {
2298         &sensor_dev_attr_in0_input.dev_attr.attr,
2299         &sensor_dev_attr_in0_min.dev_attr.attr,
2300         &sensor_dev_attr_in0_max.dev_attr.attr,
2301         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2302         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2303
2304         &sensor_dev_attr_in1_input.dev_attr.attr,
2305         &sensor_dev_attr_in1_min.dev_attr.attr,
2306         &sensor_dev_attr_in1_max.dev_attr.attr,
2307         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2308         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2309
2310         &sensor_dev_attr_in2_input.dev_attr.attr,
2311         &sensor_dev_attr_in2_min.dev_attr.attr,
2312         &sensor_dev_attr_in2_max.dev_attr.attr,
2313         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2314         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2315
2316         &sensor_dev_attr_in3_input.dev_attr.attr,
2317         &sensor_dev_attr_in3_min.dev_attr.attr,
2318         &sensor_dev_attr_in3_max.dev_attr.attr,
2319         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2320         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2321
2322         &sensor_dev_attr_in4_input.dev_attr.attr,
2323         &sensor_dev_attr_in4_min.dev_attr.attr,
2324         &sensor_dev_attr_in4_max.dev_attr.attr,
2325         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2326         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2327
2328         &sensor_dev_attr_in5_input.dev_attr.attr,
2329         &sensor_dev_attr_in5_min.dev_attr.attr,
2330         &sensor_dev_attr_in5_max.dev_attr.attr,
2331         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2332         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2333
2334         &sensor_dev_attr_in6_input.dev_attr.attr,
2335         &sensor_dev_attr_in6_min.dev_attr.attr,
2336         &sensor_dev_attr_in6_max.dev_attr.attr,
2337         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2338         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2339
2340         &sensor_dev_attr_in7_input.dev_attr.attr,
2341         &sensor_dev_attr_in7_min.dev_attr.attr,
2342         &sensor_dev_attr_in7_max.dev_attr.attr,
2343         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2344         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2345
2346         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2347         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2348         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2349         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2350         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2351         NULL
2352 };
2353
2354 static const struct attribute_group it87_group_in = {
2355         .attrs = it87_attributes_in,
2356         .is_visible = it87_in_is_visible,
2357 };
2358
2359 static umode_t it87_temp_is_visible(struct kobject *kobj,
2360                                     struct attribute *attr, int index)
2361 {
2362         struct device *dev = container_of(kobj, struct device, kobj);
2363         struct it87_data *data = dev_get_drvdata(dev);
2364         int i = index / 7;      /* temperature index */
2365         int a = index % 7;      /* attribute index */
2366
2367         if (!(data->has_temp & BIT(i)))
2368                 return 0;
2369
2370         if (a && i >= data->num_temp_limit)
2371                 return 0;
2372
2373         if (a == 3) {
2374                 int type = get_temp_type(data, i);
2375
2376                 if (type == 0)
2377                         return 0;
2378                 if (has_bank_sel(data))
2379                         return 0444;
2380                 return attr->mode;
2381         }
2382
2383         if (a == 5 && !has_temp_offset(data))
2384                 return 0;
2385
2386         if (a == 6 && !data->has_beep)
2387                 return 0;
2388
2389         return attr->mode;
2390 }
2391
2392 static struct attribute *it87_attributes_temp[] = {
2393         &sensor_dev_attr_temp1_input.dev_attr.attr,
2394         &sensor_dev_attr_temp1_max.dev_attr.attr,
2395         &sensor_dev_attr_temp1_min.dev_attr.attr,
2396         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2397         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2398         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2399         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2400
2401         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2402         &sensor_dev_attr_temp2_max.dev_attr.attr,
2403         &sensor_dev_attr_temp2_min.dev_attr.attr,
2404         &sensor_dev_attr_temp2_type.dev_attr.attr,
2405         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2406         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2407         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2408
2409         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2410         &sensor_dev_attr_temp3_max.dev_attr.attr,
2411         &sensor_dev_attr_temp3_min.dev_attr.attr,
2412         &sensor_dev_attr_temp3_type.dev_attr.attr,
2413         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2414         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2415         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2416
2417         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2418         &sensor_dev_attr_temp4_max.dev_attr.attr,
2419         &sensor_dev_attr_temp4_min.dev_attr.attr,
2420         &sensor_dev_attr_temp4_type.dev_attr.attr,
2421         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2422         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2423         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2424
2425         &sensor_dev_attr_temp5_input.dev_attr.attr,
2426         &sensor_dev_attr_temp5_max.dev_attr.attr,
2427         &sensor_dev_attr_temp5_min.dev_attr.attr,
2428         &sensor_dev_attr_temp5_type.dev_attr.attr,
2429         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2430         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2431         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2432
2433         &sensor_dev_attr_temp6_input.dev_attr.attr,
2434         &sensor_dev_attr_temp6_max.dev_attr.attr,
2435         &sensor_dev_attr_temp6_min.dev_attr.attr,
2436         &sensor_dev_attr_temp6_type.dev_attr.attr,
2437         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2438         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2439         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2440         NULL
2441 };
2442
2443 static const struct attribute_group it87_group_temp = {
2444         .attrs = it87_attributes_temp,
2445         .is_visible = it87_temp_is_visible,
2446 };
2447
2448 static umode_t it87_is_visible(struct kobject *kobj,
2449                                struct attribute *attr, int index)
2450 {
2451         struct device *dev = container_of(kobj, struct device, kobj);
2452         struct it87_data *data = dev_get_drvdata(dev);
2453
2454         if ((index == 2 || index == 3) && !data->has_vid)
2455                 return 0;
2456
2457         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2458                 return 0;
2459
2460         return attr->mode;
2461 }
2462
2463 static struct attribute *it87_attributes[] = {
2464         &dev_attr_alarms.attr,
2465         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2466         &dev_attr_vrm.attr,                             /* 2 */
2467         &dev_attr_cpu0_vid.attr,                        /* 3 */
2468         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2469         &sensor_dev_attr_in7_label.dev_attr.attr,
2470         &sensor_dev_attr_in8_label.dev_attr.attr,
2471         &sensor_dev_attr_in9_label.dev_attr.attr,
2472         NULL
2473 };
2474
2475 static const struct attribute_group it87_group = {
2476         .attrs = it87_attributes,
2477         .is_visible = it87_is_visible,
2478 };
2479
2480 static umode_t it87_fan_is_visible(struct kobject *kobj,
2481                                    struct attribute *attr, int index)
2482 {
2483         struct device *dev = container_of(kobj, struct device, kobj);
2484         struct it87_data *data = dev_get_drvdata(dev);
2485         int i = index / 5;      /* fan index */
2486         int a = index % 5;      /* attribute index */
2487
2488         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2489                 i = (index - 15) / 4 + 3;
2490                 a = (index - 15) % 4;
2491         }
2492
2493         if (!(data->has_fan & BIT(i)))
2494                 return 0;
2495
2496         if (a == 3) {                           /* beep */
2497                 if (!data->has_beep)
2498                         return 0;
2499                 /* first fan beep attribute is writable */
2500                 if (i == __ffs(data->has_fan))
2501                         return attr->mode | S_IWUSR;
2502         }
2503
2504         if (a == 4 && has_16bit_fans(data))     /* divisor */
2505                 return 0;
2506
2507         return attr->mode;
2508 }
2509
2510 static struct attribute *it87_attributes_fan[] = {
2511         &sensor_dev_attr_fan1_input.dev_attr.attr,
2512         &sensor_dev_attr_fan1_min.dev_attr.attr,
2513         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2514         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2515         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2516
2517         &sensor_dev_attr_fan2_input.dev_attr.attr,
2518         &sensor_dev_attr_fan2_min.dev_attr.attr,
2519         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2520         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2521         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2522
2523         &sensor_dev_attr_fan3_input.dev_attr.attr,
2524         &sensor_dev_attr_fan3_min.dev_attr.attr,
2525         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2526         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2527         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2528
2529         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2530         &sensor_dev_attr_fan4_min.dev_attr.attr,
2531         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2532         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2533
2534         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2535         &sensor_dev_attr_fan5_min.dev_attr.attr,
2536         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2537         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2538
2539         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2540         &sensor_dev_attr_fan6_min.dev_attr.attr,
2541         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2542         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2543         NULL
2544 };
2545
2546 static const struct attribute_group it87_group_fan = {
2547         .attrs = it87_attributes_fan,
2548         .is_visible = it87_fan_is_visible,
2549 };
2550
2551 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2552                                    struct attribute *attr, int index)
2553 {
2554         struct device *dev = container_of(kobj, struct device, kobj);
2555         struct it87_data *data = dev_get_drvdata(dev);
2556         int i = index / 4;      /* pwm index */
2557         int a = index % 4;      /* attribute index */
2558
2559         if (!(data->has_pwm & BIT(i)))
2560                 return 0;
2561
2562         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2563         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2564                 return attr->mode | S_IWUSR;
2565
2566         /* pwm2_freq is writable if there are two pwm frequency selects */
2567         if (has_pwm_freq2(data) && i == 1 && a == 2)
2568                 return attr->mode | S_IWUSR;
2569
2570         return attr->mode;
2571 }
2572
2573 static struct attribute *it87_attributes_pwm[] = {
2574         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2575         &sensor_dev_attr_pwm1.dev_attr.attr,
2576         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2577         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2578
2579         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2580         &sensor_dev_attr_pwm2.dev_attr.attr,
2581         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2582         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2583
2584         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2585         &sensor_dev_attr_pwm3.dev_attr.attr,
2586         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2587         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2588
2589         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2590         &sensor_dev_attr_pwm4.dev_attr.attr,
2591         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2592         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2593
2594         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2595         &sensor_dev_attr_pwm5.dev_attr.attr,
2596         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2597         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2598
2599         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2600         &sensor_dev_attr_pwm6.dev_attr.attr,
2601         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2602         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2603
2604         NULL
2605 };
2606
2607 static const struct attribute_group it87_group_pwm = {
2608         .attrs = it87_attributes_pwm,
2609         .is_visible = it87_pwm_is_visible,
2610 };
2611
2612 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2613                                         struct attribute *attr, int index)
2614 {
2615         struct device *dev = container_of(kobj, struct device, kobj);
2616         struct it87_data *data = dev_get_drvdata(dev);
2617         int i = index / 11;     /* pwm index */
2618         int a = index % 11;     /* attribute index */
2619
2620         if (index >= 33) {      /* pwm 4..6 */
2621                 i = (index - 33) / 6 + 3;
2622                 a = (index - 33) % 6 + 4;
2623         }
2624
2625         if (!(data->has_pwm & BIT(i)))
2626                 return 0;
2627
2628         if (has_newer_autopwm(data)) {
2629                 if (a < 4)      /* no auto point pwm */
2630                         return 0;
2631                 if (a == 8)     /* no auto_point4 */
2632                         return 0;
2633         }
2634         if (has_old_autopwm(data)) {
2635                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2636                         return 0;
2637         }
2638
2639         return attr->mode;
2640 }
2641
2642 static struct attribute *it87_attributes_auto_pwm[] = {
2643         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2644         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2645         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2646         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2647         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2648         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2649         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2650         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2651         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2652         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2653         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2654
2655         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2656         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2657         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2658         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2659         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2660         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2661         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2662         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2663         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2664         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2665         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2666
2667         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2668         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2669         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2670         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2671         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2672         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2673         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2674         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2675         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2676         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2677         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2678
2679         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2680         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2681         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2682         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2683         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2684         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2685
2686         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2687         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2688         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2689         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2690         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2691         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2692
2693         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2694         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2695         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2696         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2697         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2698         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2699
2700         NULL,
2701 };
2702
2703 static const struct attribute_group it87_group_auto_pwm = {
2704         .attrs = it87_attributes_auto_pwm,
2705         .is_visible = it87_auto_pwm_is_visible,
2706 };
2707
2708 /* SuperIO detection - will change isa_address if a chip is found */
2709 static int __init it87_find(int sioaddr, unsigned short *address,
2710                             struct it87_sio_data *sio_data)
2711 {
2712         int err;
2713         u16 chip_type;
2714         const struct it87_devices *config;
2715
2716         err = superio_enter(sioaddr);
2717         if (err)
2718                 return err;
2719
2720         err = -ENODEV;
2721         chip_type = superio_inw(sioaddr, DEVID);
2722         if (chip_type == 0xffff)
2723                 goto exit;
2724
2725         if (force_id)
2726                 chip_type = force_id;
2727
2728         switch (chip_type) {
2729         case IT8705F_DEVID:
2730                 sio_data->type = it87;
2731                 break;
2732         case IT8712F_DEVID:
2733                 sio_data->type = it8712;
2734                 break;
2735         case IT8716F_DEVID:
2736         case IT8726F_DEVID:
2737                 sio_data->type = it8716;
2738                 break;
2739         case IT8718F_DEVID:
2740                 sio_data->type = it8718;
2741                 break;
2742         case IT8720F_DEVID:
2743                 sio_data->type = it8720;
2744                 break;
2745         case IT8721F_DEVID:
2746                 sio_data->type = it8721;
2747                 break;
2748         case IT8728F_DEVID:
2749                 sio_data->type = it8728;
2750                 break;
2751         case IT8732F_DEVID:
2752                 sio_data->type = it8732;
2753                 break;
2754         case IT8792E_DEVID:
2755                 sio_data->type = it8792;
2756                 break;
2757         case IT8771E_DEVID:
2758                 sio_data->type = it8771;
2759                 break;
2760         case IT8772E_DEVID:
2761                 sio_data->type = it8772;
2762                 break;
2763         case IT8781F_DEVID:
2764                 sio_data->type = it8781;
2765                 break;
2766         case IT8782F_DEVID:
2767                 sio_data->type = it8782;
2768                 break;
2769         case IT8783E_DEVID:
2770                 sio_data->type = it8783;
2771                 break;
2772         case IT8786E_DEVID:
2773                 sio_data->type = it8786;
2774                 break;
2775         case IT8790E_DEVID:
2776                 sio_data->type = it8790;
2777                 break;
2778         case IT8603E_DEVID:
2779         case IT8623E_DEVID:
2780                 sio_data->type = it8603;
2781                 break;
2782         case IT8607E_DEVID:
2783                 sio_data->type = it8607;
2784                 break;
2785         case IT8620E_DEVID:
2786                 sio_data->type = it8620;
2787                 break;
2788         case IT8622E_DEVID:
2789                 sio_data->type = it8622;
2790                 break;
2791         case IT8628E_DEVID:
2792                 sio_data->type = it8628;
2793                 break;
2794         case IT8655E_DEVID:
2795                 sio_data->type = it8655;
2796                 break;
2797         case IT8665E_DEVID:
2798                 sio_data->type = it8665;
2799                 break;
2800         case IT8686E_DEVID:
2801                 sio_data->type = it8686;
2802                 break;
2803         case 0xffff:    /* No device at all */
2804                 goto exit;
2805         default:
2806                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2807                 goto exit;
2808         }
2809
2810         superio_select(sioaddr, PME);
2811         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2812                 pr_info("Device not activated, skipping\n");
2813                 goto exit;
2814         }
2815
2816         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2817         if (*address == 0) {
2818                 pr_info("Base address not set, skipping\n");
2819                 goto exit;
2820         }
2821
2822         err = 0;
2823         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2824         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2825                 it87_devices[sio_data->type].suffix,
2826                 *address, sio_data->revision);
2827
2828         config = &it87_devices[sio_data->type];
2829
2830         /* in7 (VSB or VCCH5V) is always internal on some chips */
2831         if (has_in7_internal(config))
2832                 sio_data->internal |= BIT(1);
2833
2834         /* in8 (Vbat) is always internal */
2835         sio_data->internal |= BIT(2);
2836
2837         /* in9 (AVCC3), always internal if supported */
2838         if (has_avcc3(config))
2839                 sio_data->internal |= BIT(3); /* in9 is AVCC */
2840         else
2841                 sio_data->skip_in |= BIT(9);
2842
2843         if (!has_four_pwm(config))
2844                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2845         else if (!has_five_pwm(config))
2846                 sio_data->skip_pwm |= BIT(4) | BIT(5);
2847         else if (!has_six_pwm(config))
2848                 sio_data->skip_pwm |= BIT(5);
2849
2850         if (!has_vid(config))
2851                 sio_data->skip_vid = 1;
2852
2853         /* Read GPIO config and VID value from LDN 7 (GPIO) */
2854         if (sio_data->type == it87) {
2855                 /* The IT8705F has a different LD number for GPIO */
2856                 superio_select(sioaddr, 5);
2857                 sio_data->beep_pin = superio_inb(sioaddr,
2858                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2859         } else if (sio_data->type == it8783) {
2860                 int reg25, reg27, reg2a, reg2c, regef;
2861
2862                 superio_select(sioaddr, GPIO);
2863
2864                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2865                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2866                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2867                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2868                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2869
2870                 /* Check if fan3 is there or not */
2871                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2872                         sio_data->skip_fan |= BIT(2);
2873                 if ((reg25 & BIT(4)) ||
2874                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
2875                         sio_data->skip_pwm |= BIT(2);
2876
2877                 /* Check if fan2 is there or not */
2878                 if (reg27 & BIT(7))
2879                         sio_data->skip_fan |= BIT(1);
2880                 if (reg27 & BIT(3))
2881                         sio_data->skip_pwm |= BIT(1);
2882
2883                 /* VIN5 */
2884                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2885                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2886
2887                 /* VIN6 */
2888                 if (reg27 & BIT(1))
2889                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2890
2891                 /*
2892                  * VIN7
2893                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2894                  */
2895                 if (reg27 & BIT(2)) {
2896                         /*
2897                          * The data sheet is a bit unclear regarding the
2898                          * internal voltage divider for VCCH5V. It says
2899                          * "This bit enables and switches VIN7 (pin 91) to the
2900                          * internal voltage divider for VCCH5V".
2901                          * This is different to other chips, where the internal
2902                          * voltage divider would connect VIN7 to an internal
2903                          * voltage source. Maybe that is the case here as well.
2904                          *
2905                          * Since we don't know for sure, re-route it if that is
2906                          * not the case, and ask the user to report if the
2907                          * resulting voltage is sane.
2908                          */
2909                         if (!(reg2c & BIT(1))) {
2910                                 reg2c |= BIT(1);
2911                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2912                                              reg2c);
2913                                 pr_notice("Routing internal VCCH5V to in7.\n");
2914                         }
2915                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2916                         pr_notice("Please report if it displays a reasonable voltage.\n");
2917                 }
2918
2919                 if (reg2c & BIT(0))
2920                         sio_data->internal |= BIT(0);
2921                 if (reg2c & BIT(1))
2922                         sio_data->internal |= BIT(1);
2923
2924                 sio_data->beep_pin = superio_inb(sioaddr,
2925                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2926         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
2927                 int reg27, reg29;
2928
2929                 superio_select(sioaddr, GPIO);
2930
2931                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2932
2933                 /* Check if fan3 is there or not */
2934                 if (reg27 & BIT(6))
2935                         sio_data->skip_pwm |= BIT(2);
2936                 if (reg27 & BIT(7))
2937                         sio_data->skip_fan |= BIT(2);
2938
2939                 /* Check if fan2 is there or not */
2940                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2941                 if (reg29 & BIT(1))
2942                         sio_data->skip_pwm |= BIT(1);
2943                 if (reg29 & BIT(2))
2944                         sio_data->skip_fan |= BIT(1);
2945
2946                 if (sio_data->type == it8603) {
2947                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2948                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2949                 }
2950
2951                 sio_data->beep_pin = superio_inb(sioaddr,
2952                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2953         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
2954                    sio_data->type == it8686) {
2955                 int reg;
2956
2957                 superio_select(sioaddr, GPIO);
2958
2959                 /* Check for pwm5 */
2960                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2961                 if (reg & BIT(6))
2962                         sio_data->skip_pwm |= BIT(4);
2963
2964                 /* Check for fan4, fan5 */
2965                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2966                 if (!(reg & BIT(5)))
2967                         sio_data->skip_fan |= BIT(3);
2968                 if (!(reg & BIT(4)))
2969                         sio_data->skip_fan |= BIT(4);
2970
2971                 /* Check for pwm3, fan3 */
2972                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2973                 if (reg & BIT(6))
2974                         sio_data->skip_pwm |= BIT(2);
2975                 if (reg & BIT(7))
2976                         sio_data->skip_fan |= BIT(2);
2977
2978                 /* Check for pwm4 */
2979                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
2980                 if (reg & BIT(2))
2981                         sio_data->skip_pwm |= BIT(3);
2982
2983                 /* Check for pwm2, fan2 */
2984                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2985                 if (reg & BIT(1))
2986                         sio_data->skip_pwm |= BIT(1);
2987                 if (reg & BIT(2))
2988                         sio_data->skip_fan |= BIT(1);
2989                 /* Check for pwm6, fan6 */
2990                 if (!(reg & BIT(7))) {
2991                         sio_data->skip_pwm |= BIT(5);
2992                         sio_data->skip_fan |= BIT(5);
2993                 }
2994
2995                 /* Check if AVCC is on VIN3 */
2996                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2997                 if (reg & BIT(0)) {
2998                         /* For it8686, the bit just enables AVCC3 */
2999                         if (sio_data->type != it8686)
3000                                 sio_data->internal |= BIT(0);
3001                 } else {
3002                         sio_data->internal &= ~BIT(3);
3003                         sio_data->skip_in |= BIT(9);
3004                 }
3005
3006                 sio_data->beep_pin = superio_inb(sioaddr,
3007                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3008         } else if (sio_data->type == it8622) {
3009                 int reg;
3010
3011                 superio_select(sioaddr, GPIO);
3012
3013                 /* Check for pwm4, fan4 */
3014                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3015                 if (reg & BIT(6))
3016                         sio_data->skip_fan |= BIT(3);
3017                 if (reg & BIT(5))
3018                         sio_data->skip_pwm |= BIT(3);
3019
3020                 /* Check for pwm3, fan3, pwm5, fan5 */
3021                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3022                 if (reg & BIT(6))
3023                         sio_data->skip_pwm |= BIT(2);
3024                 if (reg & BIT(7))
3025                         sio_data->skip_fan |= BIT(2);
3026                 if (reg & BIT(3))
3027                         sio_data->skip_pwm |= BIT(4);
3028                 if (reg & BIT(1))
3029                         sio_data->skip_fan |= BIT(4);
3030
3031                 /* Check for pwm2, fan2 */
3032                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3033                 if (reg & BIT(1))
3034                         sio_data->skip_pwm |= BIT(1);
3035                 if (reg & BIT(2))
3036                         sio_data->skip_fan |= BIT(1);
3037
3038                 /* Check for AVCC */
3039                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3040                 if (!(reg & BIT(0)))
3041                         sio_data->skip_in |= BIT(9);
3042
3043                 sio_data->beep_pin = superio_inb(sioaddr,
3044                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3045         } else if (sio_data->type == it8732) {
3046                 int reg;
3047
3048                 superio_select(sioaddr, GPIO);
3049
3050                 /* Check for pwm2, fan2 */
3051                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3052                 if (reg & BIT(1))
3053                         sio_data->skip_pwm |= BIT(1);
3054                 if (reg & BIT(2))
3055                         sio_data->skip_fan |= BIT(1);
3056
3057                 /* Check for pwm3, fan3, fan4 */
3058                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3059                 if (reg & BIT(6))
3060                         sio_data->skip_pwm |= BIT(2);
3061                 if (reg & BIT(7))
3062                         sio_data->skip_fan |= BIT(2);
3063                 if (reg & BIT(5))
3064                         sio_data->skip_fan |= BIT(3);
3065
3066                 /* Check if AVCC is on VIN3 */
3067                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3068                 if (reg & BIT(0))
3069                         sio_data->internal |= BIT(0);
3070
3071                 sio_data->beep_pin = superio_inb(sioaddr,
3072                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3073         } else if (sio_data->type == it8655) {
3074                 int reg;
3075
3076                 superio_select(sioaddr, GPIO);
3077
3078                 /* Check for pwm2 */
3079                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3080                 if (reg & BIT(1))
3081                         sio_data->skip_pwm |= BIT(1);
3082
3083                 /* Check for fan2 */
3084                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3085                 if (reg & BIT(4))
3086                         sio_data->skip_fan |= BIT(1);
3087
3088                 /* Check for pwm3, fan3 */
3089                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3090                 if (reg & BIT(6))
3091                         sio_data->skip_pwm |= BIT(2);
3092                 if (reg & BIT(7))
3093                         sio_data->skip_fan |= BIT(2);
3094
3095                 sio_data->beep_pin = superio_inb(sioaddr,
3096                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3097         } else if (sio_data->type == it8665) {
3098                 int reg;
3099
3100                 superio_select(sioaddr, GPIO);
3101
3102                 /* Check for pwm2 */
3103                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3104                 if (reg & BIT(1))
3105                         sio_data->skip_pwm |= BIT(1);
3106
3107                 /* Check for fan2 */
3108                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3109                 if (reg & BIT(4))
3110                         sio_data->skip_fan |= BIT(1);
3111
3112                 /* Check for pwm3, fan3 */
3113                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3114                 if (reg & BIT(6))
3115                         sio_data->skip_pwm |= BIT(2);
3116                 if (reg & BIT(7))
3117                         sio_data->skip_fan |= BIT(2);
3118
3119                 /* Check for pwm5, fan5 */
3120                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3121                 if (reg & BIT(5))
3122                         sio_data->skip_pwm |= BIT(4);
3123                 if (!(reg & BIT(4)))
3124                         sio_data->skip_fan |= BIT(4);
3125
3126                 /* Check for pwm4, fan4, pwm6, fan6 */
3127                 reg = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3128                 if (reg & BIT(2))
3129                         sio_data->skip_pwm |= BIT(3);
3130                 if (reg & BIT(3))
3131                         sio_data->skip_fan |= BIT(3);
3132                 if (reg & BIT(0))
3133                         sio_data->skip_pwm |= BIT(5);
3134                 if (reg & BIT(1))
3135                         sio_data->skip_fan |= BIT(5);
3136
3137                 sio_data->beep_pin = superio_inb(sioaddr,
3138                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3139         } else {
3140                 int reg;
3141                 bool uart6;
3142
3143                 superio_select(sioaddr, GPIO);
3144
3145                 /* Check for fan4, fan5 */
3146                 if (has_five_fans(config)) {
3147                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3148                         switch (sio_data->type) {
3149                         case it8718:
3150                                 if (reg & BIT(5))
3151                                         sio_data->skip_fan |= BIT(3);
3152                                 if (reg & BIT(4))
3153                                         sio_data->skip_fan |= BIT(4);
3154                                 break;
3155                         case it8720:
3156                         case it8721:
3157                         case it8728:
3158                                 if (!(reg & BIT(5)))
3159                                         sio_data->skip_fan |= BIT(3);
3160                                 if (!(reg & BIT(4)))
3161                                         sio_data->skip_fan |= BIT(4);
3162                                 break;
3163                         default:
3164                                 break;
3165                         }
3166                 }
3167
3168                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3169                 if (!sio_data->skip_vid) {
3170                         /* We need at least 4 VID pins */
3171                         if (reg & 0x0f) {
3172                                 pr_info("VID is disabled (pins used for GPIO)\n");
3173                                 sio_data->skip_vid = 1;
3174                         }
3175                 }
3176
3177                 /* Check if fan3 is there or not */
3178                 if (reg & BIT(6))
3179                         sio_data->skip_pwm |= BIT(2);
3180                 if (reg & BIT(7))
3181                         sio_data->skip_fan |= BIT(2);
3182
3183                 /* Check if fan2 is there or not */
3184                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3185                 if (reg & BIT(1))
3186                         sio_data->skip_pwm |= BIT(1);
3187                 if (reg & BIT(2))
3188                         sio_data->skip_fan |= BIT(1);
3189
3190                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3191                     !(sio_data->skip_vid))
3192                         sio_data->vid_value = superio_inb(sioaddr,
3193                                                           IT87_SIO_VID_REG);
3194
3195                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3196
3197                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3198
3199                 /*
3200                  * The IT8720F has no VIN7 pin, so VCCH should always be
3201                  * routed internally to VIN7 with an internal divider.
3202                  * Curiously, there still is a configuration bit to control
3203                  * this, which means it can be set incorrectly. And even
3204                  * more curiously, many boards out there are improperly
3205                  * configured, even though the IT8720F datasheet claims
3206                  * that the internal routing of VCCH to VIN7 is the default
3207                  * setting. So we force the internal routing in this case.
3208                  *
3209                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3210                  * If UART6 is enabled, re-route VIN7 to the internal divider
3211                  * if that is not already the case.
3212                  */
3213                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3214                         reg |= BIT(1);
3215                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3216                         pr_notice("Routing internal VCCH to in7\n");
3217                 }
3218                 if (reg & BIT(0))
3219                         sio_data->internal |= BIT(0);
3220                 if (reg & BIT(1))
3221                         sio_data->internal |= BIT(1);
3222
3223                 /*
3224                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3225                  * While VIN7 can be routed to the internal voltage divider,
3226                  * VIN5 and VIN6 are not available if UART6 is enabled.
3227                  *
3228                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3229                  * is the temperature source. Since we can not read the
3230                  * temperature source here, skip_temp is preliminary.
3231                  */
3232                 if (uart6) {
3233                         sio_data->skip_in |= BIT(5) | BIT(6);
3234                         sio_data->skip_temp |= BIT(2);
3235                 }
3236
3237                 sio_data->beep_pin = superio_inb(sioaddr,
3238                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3239         }
3240         if (sio_data->beep_pin)
3241                 pr_info("Beeping is supported\n");
3242
3243 exit:
3244         superio_exit(sioaddr);
3245         return err;
3246 }
3247
3248 /* Called when we have found a new IT87. */
3249 static void it87_init_device(struct platform_device *pdev)
3250 {
3251         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3252         struct it87_data *data = platform_get_drvdata(pdev);
3253         int tmp, i;
3254         u8 mask;
3255
3256         /* Initialize chip specific register pointers */
3257         switch (data->type) {
3258         case it8686:
3259                 data->REG_FAN = IT87_REG_FAN;
3260                 data->REG_FANX = IT87_REG_FANX;
3261                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3262                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3263                 data->REG_PWM = IT87_REG_PWM;
3264                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3265                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3266                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3267                 break;
3268         case it8655:
3269         case it8665:
3270                 data->REG_FAN = IT87_REG_FAN_8665;
3271                 data->REG_FANX = IT87_REG_FANX_8665;
3272                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3273                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3274                 data->REG_PWM = IT87_REG_PWM_8665;
3275                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3276                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3277                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3278                 break;
3279         case it8622:
3280                 data->REG_FAN = IT87_REG_FAN;
3281                 data->REG_FANX = IT87_REG_FANX;
3282                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3283                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3284                 data->REG_PWM = IT87_REG_PWM_8665;
3285                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3286                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3287                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3288                 break;
3289         default:
3290                 data->REG_FAN = IT87_REG_FAN;
3291                 data->REG_FANX = IT87_REG_FANX;
3292                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3293                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3294                 data->REG_PWM = IT87_REG_PWM;
3295                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3296                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3297                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3298                 break;
3299         }
3300
3301         /*
3302          * For each PWM channel:
3303          * - If it is in automatic mode, setting to manual mode should set
3304          *   the fan to full speed by default.
3305          * - If it is in manual mode, we need a mapping to temperature
3306          *   channels to use when later setting to automatic mode later.
3307          *   Use a 1:1 mapping by default (we are clueless.)
3308          * In both cases, the value can (and should) be changed by the user
3309          * prior to switching to a different mode.
3310          * Note that this is no longer needed for the IT8721F and later, as
3311          * these have separate registers for the temperature mapping and the
3312          * manual duty cycle.
3313          */
3314         for (i = 0; i < NUM_AUTO_PWM; i++) {
3315                 data->pwm_temp_map[i] = i;
3316                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3317                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3318         }
3319
3320         /*
3321          * Some chips seem to have default value 0xff for all limit
3322          * registers. For low voltage limits it makes no sense and triggers
3323          * alarms, so change to 0 instead. For high temperature limits, it
3324          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3325          * but is still confusing, so change to 127 degrees C.
3326          */
3327         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3328                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3329                 if (tmp == 0xff)
3330                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3331         }
3332         for (i = 0; i < data->num_temp_limit; i++) {
3333                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3334                 if (tmp == 0xff)
3335                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3336         }
3337
3338         /*
3339          * Temperature channels are not forcibly enabled, as they can be
3340          * set to two different sensor types and we can't guess which one
3341          * is correct for a given system. These channels can be enabled at
3342          * run-time through the temp{1-3}_type sysfs accessors if needed.
3343          */
3344
3345         /* Check if voltage monitors are reset manually or by some reason */
3346         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3347         if ((tmp & 0xff) == 0) {
3348                 /* Enable all voltage monitors */
3349                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3350         }
3351
3352         /* Check if tachometers are reset manually or by some reason */
3353         mask = 0x70 & ~(sio_data->skip_fan << 4);
3354         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3355         if ((data->fan_main_ctrl & mask) == 0) {
3356                 /* Enable all fan tachometers */
3357                 data->fan_main_ctrl |= mask;
3358                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3359                                  data->fan_main_ctrl);
3360         }
3361         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3362
3363         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3364
3365         /* Set tachometers to 16-bit mode if needed */
3366         if (has_fan16_config(data)) {
3367                 if (~tmp & 0x07 & data->has_fan) {
3368                         dev_dbg(&pdev->dev,
3369                                 "Setting fan1-3 to 16-bit mode\n");
3370                         it87_write_value(data, IT87_REG_FAN_16BIT,
3371                                          tmp | 0x07);
3372                 }
3373         }
3374
3375         /* Check for additional fans */
3376         if (has_four_fans(data) && (tmp & BIT(4)))
3377                 data->has_fan |= BIT(3); /* fan4 enabled */
3378         if (has_five_fans(data) && (tmp & BIT(5)))
3379                 data->has_fan |= BIT(4); /* fan5 enabled */
3380         if (has_six_fans(data)) {
3381                 switch (data->type) {
3382                 case it8620:
3383                 case it8628:
3384                 case it8686:
3385                         if (tmp & BIT(2))
3386                                 data->has_fan |= BIT(5); /* fan6 enabled */
3387                         break;
3388                 case it8665:
3389                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3390                         if (tmp & BIT(3))
3391                                 data->has_fan |= BIT(5); /* fan6 enabled */
3392                         break;
3393                 default:
3394                         break;
3395                 }
3396         }
3397
3398         /* Fan input pins may be used for alternative functions */
3399         data->has_fan &= ~sio_data->skip_fan;
3400
3401         /* Check if pwm6 is enabled */
3402         if (has_six_pwm(data)) {
3403                 switch (data->type) {
3404                 case it8620:
3405                 case it8686:
3406                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3407                         if (!(tmp & BIT(3)))
3408                                 sio_data->skip_pwm |= BIT(5);
3409                         break;
3410                 default:
3411                         break;
3412                 }
3413         }
3414
3415         /* Start monitoring */
3416         it87_write_value(data, IT87_REG_CONFIG,
3417                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3418                          | (update_vbat ? 0x41 : 0x01));
3419 }
3420
3421 /* Return 1 if and only if the PWM interface is safe to use */
3422 static int it87_check_pwm(struct device *dev)
3423 {
3424         struct it87_data *data = dev_get_drvdata(dev);
3425         /*
3426          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3427          * and polarity set to active low is sign that this is the case so we
3428          * disable pwm control to protect the user.
3429          */
3430         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3431
3432         if ((tmp & 0x87) == 0) {
3433                 if (fix_pwm_polarity) {
3434                         /*
3435                          * The user asks us to attempt a chip reconfiguration.
3436                          * This means switching to active high polarity and
3437                          * inverting all fan speed values.
3438                          */
3439                         int i;
3440                         u8 pwm[3];
3441
3442                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3443                                 pwm[i] = it87_read_value(data,
3444                                                          data->REG_PWM[i]);
3445
3446                         /*
3447                          * If any fan is in automatic pwm mode, the polarity
3448                          * might be correct, as suspicious as it seems, so we
3449                          * better don't change anything (but still disable the
3450                          * PWM interface).
3451                          */
3452                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3453                                 dev_info(dev,
3454                                          "Reconfiguring PWM to active high polarity\n");
3455                                 it87_write_value(data, IT87_REG_FAN_CTL,
3456                                                  tmp | 0x87);
3457                                 for (i = 0; i < 3; i++)
3458                                         it87_write_value(data,
3459                                                          data->REG_PWM[i],
3460                                                          0x7f & ~pwm[i]);
3461                                 return 1;
3462                         }
3463
3464                         dev_info(dev,
3465                                  "PWM configuration is too broken to be fixed\n");
3466                 }
3467
3468                 dev_info(dev,
3469                          "Detected broken BIOS defaults, disabling PWM interface\n");
3470                 return 0;
3471         } else if (fix_pwm_polarity) {
3472                 dev_info(dev,
3473                          "PWM configuration looks sane, won't touch\n");
3474         }
3475
3476         return 1;
3477 }
3478
3479 static int it87_probe(struct platform_device *pdev)
3480 {
3481         struct it87_data *data;
3482         struct resource *res;
3483         struct device *dev = &pdev->dev;
3484         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3485         int enable_pwm_interface;
3486         struct device *hwmon_dev;
3487
3488         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3489         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3490                                  DRVNAME)) {
3491                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3492                         (unsigned long)res->start,
3493                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3494                 return -EBUSY;
3495         }
3496
3497         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3498         if (!data)
3499                 return -ENOMEM;
3500
3501         data->addr = res->start;
3502         data->type = sio_data->type;
3503         data->features = it87_devices[sio_data->type].features;
3504         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3505         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3506         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3507         data->bank = 0xff;
3508
3509         /*
3510          * IT8705F Datasheet 0.4.1, 3h == Version G.
3511          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3512          * These are the first revisions with 16-bit tachometer support.
3513          */
3514         switch (data->type) {
3515         case it87:
3516                 if (sio_data->revision >= 0x03) {
3517                         data->features &= ~FEAT_OLD_AUTOPWM;
3518                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3519                 }
3520                 break;
3521         case it8712:
3522                 if (sio_data->revision >= 0x08) {
3523                         data->features &= ~FEAT_OLD_AUTOPWM;
3524                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3525                                           FEAT_FIVE_FANS;
3526                 }
3527                 break;
3528         default:
3529                 break;
3530         }
3531
3532         /* Now, we do the remaining detection. */
3533         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3534             it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3535                 return -ENODEV;
3536
3537         platform_set_drvdata(pdev, data);
3538
3539         mutex_init(&data->update_lock);
3540
3541         /* Check PWM configuration */
3542         enable_pwm_interface = it87_check_pwm(dev);
3543
3544         /* Starting with IT8721F, we handle scaling of internal voltages */
3545         if (has_scaling(data)) {
3546                 if (sio_data->internal & BIT(0))
3547                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3548                 if (sio_data->internal & BIT(1))
3549                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3550                 if (sio_data->internal & BIT(2))
3551                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3552                 if (sio_data->internal & BIT(3))
3553                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3554         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3555                    sio_data->type == it8783) {
3556                 if (sio_data->internal & BIT(0))
3557                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3558                 if (sio_data->internal & BIT(1))
3559                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3560         }
3561
3562         data->has_temp = 0x07;
3563         if (sio_data->skip_temp & BIT(2)) {
3564                 if (sio_data->type == it8782 &&
3565                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3566                         data->has_temp &= ~BIT(2);
3567         }
3568
3569         data->in_internal = sio_data->internal;
3570         data->has_in = 0x3ff & ~sio_data->skip_in;
3571
3572         if (has_six_temp(data)) {
3573                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3574
3575                 /* Check for additional temperature sensors */
3576                 if ((reg & 0x03) >= 0x02)
3577                         data->has_temp |= BIT(3);
3578                 if (((reg >> 2) & 0x03) >= 0x02)
3579                         data->has_temp |= BIT(4);
3580                 if (((reg >> 4) & 0x03) >= 0x02)
3581                         data->has_temp |= BIT(5);
3582
3583                 /* Check for additional voltage sensors */
3584                 if ((reg & 0x03) == 0x01)
3585                         data->has_in |= BIT(10);
3586                 if (((reg >> 2) & 0x03) == 0x01)
3587                         data->has_in |= BIT(11);
3588                 if (((reg >> 4) & 0x03) == 0x01)
3589                         data->has_in |= BIT(12);
3590         }
3591
3592         data->has_beep = !!sio_data->beep_pin;
3593
3594         /* Initialize the IT87 chip */
3595         it87_init_device(pdev);
3596
3597         if (!sio_data->skip_vid) {
3598                 data->has_vid = true;
3599                 data->vrm = vid_which_vrm();
3600                 /* VID reading from Super-I/O config space if available */
3601                 data->vid = sio_data->vid_value;
3602         }
3603
3604         /* Prepare for sysfs hooks */
3605         data->groups[0] = &it87_group;
3606         data->groups[1] = &it87_group_in;
3607         data->groups[2] = &it87_group_temp;
3608         data->groups[3] = &it87_group_fan;
3609
3610         if (enable_pwm_interface) {
3611                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3612                 data->has_pwm &= ~sio_data->skip_pwm;
3613
3614                 data->groups[4] = &it87_group_pwm;
3615                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3616                         data->groups[5] = &it87_group_auto_pwm;
3617         }
3618
3619         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3620                                         it87_devices[sio_data->type].name,
3621                                         data, data->groups);
3622         return PTR_ERR_OR_ZERO(hwmon_dev);
3623 }
3624
3625 static struct platform_driver it87_driver = {
3626         .driver = {
3627                 .name   = DRVNAME,
3628         },
3629         .probe  = it87_probe,
3630 };
3631
3632 static int __init it87_device_add(int index, unsigned short address,
3633                                   const struct it87_sio_data *sio_data)
3634 {
3635         struct platform_device *pdev;
3636         struct resource res = {
3637                 .start  = address + IT87_EC_OFFSET,
3638                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3639                 .name   = DRVNAME,
3640                 .flags  = IORESOURCE_IO,
3641         };
3642         int err;
3643
3644         err = acpi_check_resource_conflict(&res);
3645         if (err)
3646                 return err;
3647
3648         pdev = platform_device_alloc(DRVNAME, address);
3649         if (!pdev)
3650                 return -ENOMEM;
3651
3652         err = platform_device_add_resources(pdev, &res, 1);
3653         if (err) {
3654                 pr_err("Device resource addition failed (%d)\n", err);
3655                 goto exit_device_put;
3656         }
3657
3658         err = platform_device_add_data(pdev, sio_data,
3659                                        sizeof(struct it87_sio_data));
3660         if (err) {
3661                 pr_err("Platform data allocation failed\n");
3662                 goto exit_device_put;
3663         }
3664
3665         err = platform_device_add(pdev);
3666         if (err) {
3667                 pr_err("Device addition failed (%d)\n", err);
3668                 goto exit_device_put;
3669         }
3670
3671         it87_pdev[index] = pdev;
3672         return 0;
3673
3674 exit_device_put:
3675         platform_device_put(pdev);
3676         return err;
3677 }
3678
3679 struct it87_dmi_data {
3680         bool sio4e_broken;      /* SIO accesses @ 0x4e are broken       */
3681         char *sio_mutex;        /* SIO ACPI mutex                       */
3682         u8 skip_pwm;            /* pwm channels to skip for this board  */
3683 };
3684
3685 /*
3686  * On Gigabyte AB350 boards, accesses to the Super-IO chip
3687  * at address 0x4e/0x4f can result in a system hang.
3688  * Accesses to address 0x2e/0x2f need to be mutex protected.
3689  */
3690 static struct it87_dmi_data gigabyte_ab350_gaming = {
3691         .sio4e_broken = true,
3692         .sio_mutex = "\\_SB.PCI0.SBRG.SIO1.MUT0",
3693 };
3694
3695 /*
3696  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3697  * connected to a fan, but to something else. One user
3698  * has reported instant system power-off when changing
3699  * the PWM2 duty cycle, so we disable it.
3700  * I use the board name string as the trigger in case
3701  * the same board is ever used in other systems.
3702  */
3703 static struct it87_dmi_data nvidia_fn68pt = {
3704         .skip_pwm = BIT(1),
3705 };
3706
3707 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3708         {
3709                 .matches = {
3710                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3711                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming-CF"),
3712                 },
3713                 .driver_data = &gigabyte_ab350_gaming,
3714         },
3715         {
3716                 .matches = {
3717                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3718                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming 3-CF"),
3719                 },
3720                 .driver_data = &gigabyte_ab350_gaming,
3721         },
3722         {
3723                 .matches = {
3724                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3725                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3726                 },
3727                 .driver_data = &nvidia_fn68pt,
3728         },
3729         { }
3730 };
3731
3732 static int __init sm_it87_init(void)
3733 {
3734         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3735         struct it87_dmi_data *dmi_data = NULL;
3736         int sioaddr[2] = { REG_2E, REG_4E };
3737         struct it87_sio_data sio_data;
3738         unsigned short isa_address;
3739         bool found = false;
3740         int i, err;
3741
3742         if (dmi)
3743                 dmi_data = dmi->driver_data;
3744
3745         if (dmi_data) {
3746                 it87_sio4e_broken = dmi_data->sio4e_broken;
3747 #ifdef __IT87_USE_ACPI_MUTEX
3748                 if (dmi_data->sio_mutex) {
3749                         static acpi_status status;
3750
3751                         status = acpi_get_handle(NULL, dmi_data->sio_mutex,
3752                                                  &it87_acpi_sio_handle);
3753                         if (ACPI_SUCCESS(status)) {
3754                                 it87_acpi_sio_mutex = dmi_data->sio_mutex;
3755                                 pr_debug("Found ACPI SIO mutex %s\n",
3756                                          dmi_data->sio_mutex);
3757                         } else {
3758                                 pr_warn("ACPI SIO mutex %s not found\n",
3759                                         dmi_data->sio_mutex);
3760                         }
3761                 }
3762 #endif /* __IT87_USE_ACPI_MUTEX */
3763         }
3764
3765         err = platform_driver_register(&it87_driver);
3766         if (err)
3767                 return err;
3768
3769         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3770                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3771                 isa_address = 0;
3772                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3773                 if (err || isa_address == 0)
3774                         continue;
3775
3776                 if (dmi_data)
3777                         sio_data.skip_pwm |= dmi_data->skip_pwm;
3778                 err = it87_device_add(i, isa_address, &sio_data);
3779                 if (err)
3780                         goto exit_dev_unregister;
3781                 found = true;
3782         }
3783
3784         if (!found) {
3785                 err = -ENODEV;
3786                 goto exit_unregister;
3787         }
3788         return 0;
3789
3790 exit_dev_unregister:
3791         /* NULL check handled by platform_device_unregister */
3792         platform_device_unregister(it87_pdev[0]);
3793 exit_unregister:
3794         platform_driver_unregister(&it87_driver);
3795         return err;
3796 }
3797
3798 static void __exit sm_it87_exit(void)
3799 {
3800         /* NULL check handled by platform_device_unregister */
3801         platform_device_unregister(it87_pdev[1]);
3802         platform_device_unregister(it87_pdev[0]);
3803         platform_driver_unregister(&it87_driver);
3804 }
3805
3806 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3807 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3808 module_param(update_vbat, bool, 0);
3809 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3810 module_param(fix_pwm_polarity, bool, 0);
3811 MODULE_PARM_DESC(fix_pwm_polarity,
3812                  "Force PWM polarity to active high (DANGEROUS)");
3813 MODULE_LICENSE("GPL");
3814
3815 module_init(sm_it87_init);
3816 module_exit(sm_it87_exit);