git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77
  78 #define DRVNAME "it87"
  79
  80 /* Necessary API not (yet) exported in upstream kernel */
  81 /* #define __IT87_USE_ACPI_MUTEX */
  82
  83 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  84              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  85              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  86              it8655, it8665, it8686 };
  87
  88 static unsigned short force_id;
  89 module_param(force_id, ushort, 0);
  90 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  91
  92 static unsigned short blacklist = 1;
  93 module_param(blacklist, ushort, 0);
  94 MODULE_PARM_DESC(blacklist,
  95                  "Enable/disable blacklist (1=enable, 0=disable, default 1)");
  96
  97 static struct platform_device *it87_pdev[2];
  98 static bool it87_sio4e_broken;
  99 #ifdef __IT87_USE_ACPI_MUTEX
 100 static acpi_handle it87_acpi_sio_handle;
 101 static char *it87_acpi_sio_mutex;
 102 #endif
 103
 104 #define REG_2E  0x2e    /* The register to read/write */
 105 #define REG_4E  0x4e    /* Secondary register to read/write */
 106
 107 #define DEV     0x07    /* Register: Logical device select */
 108 #define PME     0x04    /* The device with the fan registers in it */
 109
 110 /* The device with the IT8718F/IT8720F VID value in it */
 111 #define GPIO    0x07
 112
 113 #define DEVID   0x20    /* Register: Device ID */
 114 #define DEVREV  0x22    /* Register: Device Revision */
 115
 116 static inline void __superio_enter(int ioreg)
 117 {
 118         outb(0x87, ioreg);
 119         outb(0x01, ioreg);
 120         outb(0x55, ioreg);
 121         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 122 }
 123
 124 static inline int superio_inb(int ioreg, int reg)
 125 {
 126         int val;
 127
 128         outb(reg, ioreg);
 129         val = inb(ioreg + 1);
 130         if (it87_sio4e_broken && ioreg == 0x4e && val == 0xff) {
 131                 __superio_enter(ioreg);
 132                 outb(reg, ioreg);
 133                 val = inb(ioreg + 1);
 134                 pr_warn("Retry access 0x4e:0x%x -> 0x%x\n", reg, val);
 135         }
 136
 137         return val;
 138 }
 139
 140 static inline void superio_outb(int ioreg, int reg, int val)
 141 {
 142         outb(reg, ioreg);
 143         outb(val, ioreg + 1);
 144 }
 145
 146 static int superio_inw(int ioreg, int reg)
 147 {
 148         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 149 }
 150
 151 static inline void superio_select(int ioreg, int ldn)
 152 {
 153         outb(DEV, ioreg);
 154         outb(ldn, ioreg + 1);
 155 }
 156
 157 static inline int superio_enter(int ioreg)
 158 {
 159 #ifdef __IT87_USE_ACPI_MUTEX
 160         if (it87_acpi_sio_mutex) {
 161                 acpi_status status;
 162
 163                 status = acpi_acquire_mutex(NULL, it87_acpi_sio_mutex, 0x10);
 164                 if (ACPI_FAILURE(status)) {
 165                         pr_err("Failed to acquire ACPI mutex\n");
 166                         return -EBUSY;
 167                 }
 168         }
 169 #endif
 170         /*
 171          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 172          */
 173         if (!request_muxed_region(ioreg, 2, DRVNAME))
 174                 goto error;
 175
 176         __superio_enter(ioreg);
 177         return 0;
 178
 179 error:
 180 #ifdef __IT87_USE_ACPI_MUTEX
 181         if (it87_acpi_sio_mutex)
 182                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 183 #endif
 184         return -EBUSY;
 185 }
 186
 187 static inline void superio_exit(int ioreg)
 188 {
 189         if (!it87_sio4e_broken || ioreg != 0x4e) {
 190                 outb(0x02, ioreg);
 191                 outb(0x02, ioreg + 1);
 192         }
 193         release_region(ioreg, 2);
 194 #ifdef __IT87_USE_ACPI_MUTEX
 195         if (it87_acpi_sio_mutex)
 196                 acpi_release_mutex(it87_acpi_sio_handle, NULL);
 197 #endif
 198 }
 199
 200 /* Logical device 4 registers */
 201 #define IT8712F_DEVID 0x8712
 202 #define IT8705F_DEVID 0x8705
 203 #define IT8716F_DEVID 0x8716
 204 #define IT8718F_DEVID 0x8718
 205 #define IT8720F_DEVID 0x8720
 206 #define IT8721F_DEVID 0x8721
 207 #define IT8726F_DEVID 0x8726
 208 #define IT8728F_DEVID 0x8728
 209 #define IT8732F_DEVID 0x8732
 210 #define IT8792E_DEVID 0x8733
 211 #define IT8771E_DEVID 0x8771
 212 #define IT8772E_DEVID 0x8772
 213 #define IT8781F_DEVID 0x8781
 214 #define IT8782F_DEVID 0x8782
 215 #define IT8783E_DEVID 0x8783
 216 #define IT8786E_DEVID 0x8786
 217 #define IT8790E_DEVID 0x8790
 218 #define IT8603E_DEVID 0x8603
 219 #define IT8607E_DEVID 0x8607
 220 #define IT8613E_DEVID 0x8613
 221 #define IT8620E_DEVID 0x8620
 222 #define IT8622E_DEVID 0x8622
 223 #define IT8623E_DEVID 0x8623
 224 #define IT8625E_DEVID 0x8625
 225 #define IT8628E_DEVID 0x8628
 226 #define IT8655E_DEVID 0x8655
 227 #define IT8665E_DEVID 0x8665
 228 #define IT8686E_DEVID 0x8686
 229 #define IT87_ACT_REG  0x30
 230 #define IT87_BASE_REG 0x60
 231
 232 /* Logical device 7 registers (IT8712F and later) */
 233 #define IT87_SIO_GPIO1_REG      0x25
 234 #define IT87_SIO_GPIO2_REG      0x26
 235 #define IT87_SIO_GPIO3_REG      0x27
 236 #define IT87_SIO_GPIO4_REG      0x28
 237 #define IT87_SIO_GPIO5_REG      0x29
 238 #define IT87_SIO_GPIO9_REG      0xd3
 239 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 240 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 241 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 242 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 243 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 244 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 245
 246 /* Update battery voltage after every reading if true */
 247 static bool update_vbat;
 248
 249 /* Not all BIOSes properly configure the PWM registers */
 250 static bool fix_pwm_polarity;
 251
 252 /* Many IT87 constants specified below */
 253
 254 /* Length of ISA address segment */
 255 #define IT87_EXTENT 8
 256
 257 /* Length of ISA address segment for Environmental Controller */
 258 #define IT87_EC_EXTENT 2
 259
 260 /* Offset of EC registers from ISA base address */
 261 #define IT87_EC_OFFSET 5
 262
 263 /* Where are the ISA address/data registers relative to the EC base address */
 264 #define IT87_ADDR_REG_OFFSET 0
 265 #define IT87_DATA_REG_OFFSET 1
 266
 267 /*----- The IT87 registers -----*/
 268
 269 #define IT87_REG_CONFIG        0x00
 270
 271 #define IT87_REG_ALARM1        0x01
 272 #define IT87_REG_ALARM2        0x02
 273 #define IT87_REG_ALARM3        0x03
 274
 275 #define IT87_REG_BANK           0x06
 276
 277 /*
 278  * The IT8718F and IT8720F have the VID value in a different register, in
 279  * Super-I/O configuration space.
 280  */
 281 #define IT87_REG_VID           0x0a
 282 /*
 283  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 284  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 285  * mode.
 286  */
 287 #define IT87_REG_FAN_DIV       0x0b
 288 #define IT87_REG_FAN_16BIT     0x0c
 289
 290 /*
 291  * Monitors:
 292  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 293  * - up to 6 temp (1 to 6)
 294  * - up to 6 fan (1 to 6)
 295  */
 296
 297 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 298 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 299 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 300 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 301
 302 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 303 static const u8 IT87_REG_FAN_MIN_8665[] =
 304                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 305 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 306 static const u8 IT87_REG_FANX_MIN_8665[] =
 307                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 308
 309 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 310
 311 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 312
 313 #define IT87_REG_FAN_MAIN_CTRL 0x13
 314 #define IT87_REG_FAN_CTL       0x14
 315
 316 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 317 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 318
 319 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 320
 321 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 322                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 323
 324 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 325
 326 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 327 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 328
 329 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 330 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 331
 332 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 333                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 334 static const u8 IT87_REG_TEMP_LOW_8686[] =
 335                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 336
 337 #define IT87_REG_VIN_ENABLE    0x50
 338 #define IT87_REG_TEMP_ENABLE   0x51
 339 #define IT87_REG_TEMP_EXTRA    0x55
 340 #define IT87_REG_BEEP_ENABLE   0x5c
 341
 342 #define IT87_REG_CHIPID        0x58
 343
 344 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 345
 346 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 347 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 348
 349 #define IT87_REG_TEMP456_ENABLE 0x77
 350
 351 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 352 #define IT87_REG_TEMP_SRC2      0x23d
 353
 354 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 355 #define NUM_VIN_LIMIT           8
 356 #define NUM_TEMP                6
 357 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 358 #define NUM_FAN_DIV             3
 359 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 360 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 361
 362 struct it87_devices {
 363         const char *name;
 364         const char * const suffix;
 365         u32 features;
 366         u8 num_temp_limit;
 367         u8 num_temp_offset;
 368         u8 peci_mask;
 369         u8 old_peci_mask;
 370 };
 371
 372 #define FEAT_12MV_ADC           BIT(0)
 373 #define FEAT_NEWER_AUTOPWM      BIT(1)
 374 #define FEAT_OLD_AUTOPWM        BIT(2)
 375 #define FEAT_16BIT_FANS         BIT(3)
 376 #define FEAT_TEMP_OFFSET        BIT(4)
 377 #define FEAT_TEMP_PECI          BIT(5)
 378 #define FEAT_TEMP_OLD_PECI      BIT(6)
 379 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 380 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 381 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 382 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 383 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 384 #define FEAT_10_9MV_ADC         BIT(12)
 385 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 386 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 387 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 388 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 389 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 390 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 391 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 392 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 393 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 394 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 395 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 396 #define FEAT_11MV_ADC           BIT(24)
 397 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 398
 399 static const struct it87_devices it87_devices[] = {
 400         [it87] = {
 401                 .name = "it87",
 402                 .suffix = "F",
 403                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 404                                                 /* may need to overwrite */
 405                 .num_temp_limit = 3,
 406                 .num_temp_offset = 0,
 407         },
 408         [it8712] = {
 409                 .name = "it8712",
 410                 .suffix = "F",
 411                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 412                                                 /* may need to overwrite */
 413                 .num_temp_limit = 3,
 414                 .num_temp_offset = 0,
 415         },
 416         [it8716] = {
 417                 .name = "it8716",
 418                 .suffix = "F",
 419                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 420                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 421                   | FEAT_FANCTL_ONOFF,
 422                 .num_temp_limit = 3,
 423                 .num_temp_offset = 3,
 424         },
 425         [it8718] = {
 426                 .name = "it8718",
 427                 .suffix = "F",
 428                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 429                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 430                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 431                 .num_temp_limit = 3,
 432                 .num_temp_offset = 3,
 433                 .old_peci_mask = 0x4,
 434         },
 435         [it8720] = {
 436                 .name = "it8720",
 437                 .suffix = "F",
 438                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 439                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 440                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 441                 .num_temp_limit = 3,
 442                 .num_temp_offset = 3,
 443                 .old_peci_mask = 0x4,
 444         },
 445         [it8721] = {
 446                 .name = "it8721",
 447                 .suffix = "F",
 448                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 449                   | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 450                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 451                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 452                 .num_temp_limit = 3,
 453                 .num_temp_offset = 3,
 454                 .peci_mask = 0x05,
 455                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 456         },
 457         [it8728] = {
 458                 .name = "it8728",
 459                 .suffix = "F",
 460                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 461                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 462                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 463                   | FEAT_FANCTL_ONOFF,
 464                 .num_temp_limit = 6,
 465                 .num_temp_offset = 3,
 466                 .peci_mask = 0x07,
 467         },
 468         [it8732] = {
 469                 .name = "it8732",
 470                 .suffix = "F",
 471                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 472                   | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 473                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 474                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 475                 .num_temp_limit = 3,
 476                 .num_temp_offset = 3,
 477                 .peci_mask = 0x07,
 478                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 479         },
 480         [it8771] = {
 481                 .name = "it8771",
 482                 .suffix = "E",
 483                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 484                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 485                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 486                                 /* PECI: guesswork */
 487                                 /* 12mV ADC (OHM) */
 488                                 /* 16 bit fans (OHM) */
 489                                 /* three fans, always 16 bit (guesswork) */
 490                 .num_temp_limit = 3,
 491                 .num_temp_offset = 3,
 492                 .peci_mask = 0x07,
 493         },
 494         [it8772] = {
 495                 .name = "it8772",
 496                 .suffix = "E",
 497                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 498                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 499                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 500                                 /* PECI (coreboot) */
 501                                 /* 12mV ADC (HWSensors4, OHM) */
 502                                 /* 16 bit fans (HWSensors4, OHM) */
 503                                 /* three fans, always 16 bit (datasheet) */
 504                 .num_temp_limit = 3,
 505                 .num_temp_offset = 3,
 506                 .peci_mask = 0x07,
 507         },
 508         [it8781] = {
 509                 .name = "it8781",
 510                 .suffix = "F",
 511                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 512                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 513                   | FEAT_FANCTL_ONOFF,
 514                 .num_temp_limit = 3,
 515                 .num_temp_offset = 3,
 516                 .old_peci_mask = 0x4,
 517         },
 518         [it8782] = {
 519                 .name = "it8782",
 520                 .suffix = "F",
 521                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 522                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 523                   | FEAT_FANCTL_ONOFF,
 524                 .num_temp_limit = 3,
 525                 .num_temp_offset = 3,
 526                 .old_peci_mask = 0x4,
 527         },
 528         [it8783] = {
 529                 .name = "it8783",
 530                 .suffix = "E/F",
 531                 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 532                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 533                   | FEAT_FANCTL_ONOFF,
 534                 .num_temp_limit = 3,
 535                 .num_temp_offset = 3,
 536                 .old_peci_mask = 0x4,
 537         },
 538         [it8786] = {
 539                 .name = "it8786",
 540                 .suffix = "E",
 541                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 542                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 543                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 544                 .num_temp_limit = 3,
 545                 .num_temp_offset = 3,
 546                 .peci_mask = 0x07,
 547         },
 548         [it8790] = {
 549                 .name = "it8790",
 550                 .suffix = "E",
 551                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 552                   | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
 553                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 554                 .num_temp_limit = 3,
 555                 .num_temp_offset = 3,
 556                 .peci_mask = 0x07,
 557         },
 558         [it8792] = {
 559                 .name = "it8792",
 560                 .suffix = "E",
 561                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 562                   | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
 563                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 564                 .num_temp_limit = 3,
 565                 .num_temp_offset = 3,
 566                 .peci_mask = 0x07,
 567         },
 568         [it8603] = {
 569                 .name = "it8603",
 570                 .suffix = "E",
 571                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 572                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 573                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 574                 .num_temp_limit = 3,
 575                 .num_temp_offset = 3,
 576                 .peci_mask = 0x07,
 577         },
 578         [it8607] = {
 579                 .name = "it8607",
 580                 .suffix = "E",
 581                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 582                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 583                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 584                   | FEAT_FANCTL_ONOFF,
 585                 .num_temp_limit = 3,
 586                 .num_temp_offset = 3,
 587                 .peci_mask = 0x07,
 588         },
 589         [it8613] = {
 590                 .name = "it8613",
 591                 .suffix = "E",
 592                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 593                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 594                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 595                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 596                 .num_temp_limit = 6,
 597                 .num_temp_offset = 6,
 598                 .peci_mask = 0x07,
 599         },
 600         [it8620] = {
 601                 .name = "it8620",
 602                 .suffix = "E",
 603                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 604                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 605                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 606                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 607                   | FEAT_FANCTL_ONOFF,
 608                 .num_temp_limit = 3,
 609                 .num_temp_offset = 3,
 610                 .peci_mask = 0x07,
 611         },
 612         [it8622] = {
 613                 .name = "it8622",
 614                 .suffix = "E",
 615                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 616                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 617                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 618                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 619                 .num_temp_limit = 3,
 620                 .num_temp_offset = 3,
 621                 .peci_mask = 0x07,
 622         },
 623         [it8625] = {
 624                 .name = "it8625",
 625                 .suffix = "E",
 626                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 627                   | FEAT_TEMP_OFFSET | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 628                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 629                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 630                 .num_temp_limit = 6,
 631                 .num_temp_offset = 6,
 632         },
 633         [it8628] = {
 634                 .name = "it8628",
 635                 .suffix = "E",
 636                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 637                   | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 638                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 639                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 640                   | FEAT_FANCTL_ONOFF,
 641                 .num_temp_limit = 6,
 642                 .num_temp_offset = 3,
 643                 .peci_mask = 0x07,
 644         },
 645         [it8655] = {
 646                 .name = "it8655",
 647                 .suffix = "E",
 648                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 649                   | FEAT_TEMP_OFFSET | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 650                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 651                 .num_temp_limit = 6,
 652                 .num_temp_offset = 6,
 653         },
 654         [it8665] = {
 655                 .name = "it8665",
 656                 .suffix = "E",
 657                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 658                   | FEAT_TEMP_OFFSET | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 659                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 660                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 661                 .num_temp_limit = 6,
 662                 .num_temp_offset = 6,
 663         },
 664         [it8686] = {
 665                 .name = "it8686",
 666                 .suffix = "E",
 667                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 668                   | FEAT_TEMP_OFFSET | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 669                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 670                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 671                 .num_temp_limit = 6,
 672                 .num_temp_offset = 6,
 673         },
 674 };
 675
 676 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 677 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 678 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 679 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 680 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 681 #define has_temp_offset(data)   ((data)->features & FEAT_TEMP_OFFSET)
 682 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 683                                  ((data)->peci_mask & BIT(nr)))
 684 #define has_temp_old_peci(data, nr) \
 685                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 686                                  ((data)->old_peci_mask & BIT(nr)))
 687 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 688 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 689                                                      FEAT_SIX_FANS))
 690 #define has_vid(data)           ((data)->features & FEAT_VID)
 691 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 692 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 693 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 694 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 695                                                      | FEAT_SIX_PWM))
 696 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 697 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 698 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 699 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 700 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 701                                                      FEAT_FIVE_FANS | \
 702                                                      FEAT_SIX_FANS))
 703 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 704                                                      FEAT_FIVE_PWM \
 705                                                      | FEAT_SIX_PWM))
 706 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 707 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 708 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 709 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 710 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 711
 712 struct it87_sio_data {
 713         enum chips type;
 714         /* Values read from Super-I/O config space */
 715         u8 revision;
 716         u8 vid_value;
 717         u8 beep_pin;
 718         u8 internal;    /* Internal sensors can be labeled */
 719         /* Features skipped based on config or DMI */
 720         u16 skip_in;
 721         u8 skip_vid;
 722         u8 skip_fan;
 723         u8 skip_pwm;
 724         u8 skip_temp;
 725 };
 726
 727 /*
 728  * For each registered chip, we need to keep some data in memory.
 729  * The structure is dynamically allocated.
 730  */
 731 struct it87_data {
 732         const struct attribute_group *groups[7];
 733         enum chips type;
 734         u32 features;
 735         u8 bank;
 736         u8 peci_mask;
 737         u8 old_peci_mask;
 738
 739         const u8 *REG_FAN;
 740         const u8 *REG_FANX;
 741         const u8 *REG_FAN_MIN;
 742         const u8 *REG_FANX_MIN;
 743
 744         const u8 *REG_PWM;
 745
 746         const u8 *REG_TEMP_OFFSET;
 747         const u8 *REG_TEMP_LOW;
 748         const u8 *REG_TEMP_HIGH;
 749
 750         unsigned short addr;
 751         const char *name;
 752         struct mutex update_lock;
 753         char valid;             /* !=0 if following fields are valid */
 754         unsigned long last_updated;     /* In jiffies */
 755
 756         u16 in_scaled;          /* Internal voltage sensors are scaled */
 757         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 758         u16 has_in;             /* Bitfield, voltage sensors enabled */
 759         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 760         u8 has_fan;             /* Bitfield, fans enabled */
 761         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 762         u8 has_temp;            /* Bitfield, temp sensors enabled */
 763         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 764         u8 num_temp_limit;      /* Number of temperature limit registers */
 765         u8 num_temp_offset;     /* Number of temperature offset registers */
 766         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 767         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 768         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 769         bool has_vid;           /* True if VID supported */
 770         u8 vid;                 /* Register encoding, combined */
 771         u8 vrm;
 772         u32 alarms;             /* Register encoding, combined */
 773         bool has_beep;          /* true if beep supported */
 774         u8 beeps;               /* Register encoding */
 775         u8 fan_main_ctrl;       /* Register value */
 776         u8 fan_ctl;             /* Register value */
 777
 778         /*
 779          * The following 3 arrays correspond to the same registers up to
 780          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 781          * 7, and we want to preserve settings on mode changes, so we have
 782          * to track all values separately.
 783          * Starting with the IT8721F, the manual PWM duty cycles are stored
 784          * in separate registers (8-bit values), so the separate tracking
 785          * is no longer needed, but it is still done to keep the driver
 786          * simple.
 787          */
 788         u8 has_pwm;             /* Bitfield, pwm control enabled */
 789         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 790         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 791         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 792
 793         /* Automatic fan speed control registers */
 794         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 795         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 796 };
 797
 798 static int adc_lsb(const struct it87_data *data, int nr)
 799 {
 800         int lsb;
 801
 802         if (has_12mv_adc(data))
 803                 lsb = 120;
 804         else if (has_10_9mv_adc(data))
 805                 lsb = 109;
 806         else if (has_11mv_adc(data))
 807                 lsb = 110;
 808         else
 809                 lsb = 160;
 810         if (data->in_scaled & BIT(nr))
 811                 lsb <<= 1;
 812         return lsb;
 813 }
 814
 815 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 816 {
 817         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 818         return clamp_val(val, 0, 255);
 819 }
 820
 821 static int in_from_reg(const struct it87_data *data, int nr, int val)
 822 {
 823         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 824 }
 825
 826 static inline u8 FAN_TO_REG(long rpm, int div)
 827 {
 828         if (rpm == 0)
 829                 return 255;
 830         rpm = clamp_val(rpm, 1, 1000000);
 831         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 832 }
 833
 834 static inline u16 FAN16_TO_REG(long rpm)
 835 {
 836         if (rpm == 0)
 837                 return 0xffff;
 838         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 839 }
 840
 841 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 842                                 1350000 / ((val) * (div)))
 843 /* The divider is fixed to 2 in 16-bit mode */
 844 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 845                              1350000 / ((val) * 2))
 846
 847 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 848                                     ((val) + 500) / 1000), -128, 127))
 849 #define TEMP_FROM_REG(val) ((val) * 1000)
 850
 851 static u8 pwm_to_reg(const struct it87_data *data, long val)
 852 {
 853         if (has_newer_autopwm(data))
 854                 return val;
 855         else
 856                 return val >> 1;
 857 }
 858
 859 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 860 {
 861         if (has_newer_autopwm(data))
 862                 return reg;
 863         else
 864                 return (reg & 0x7f) << 1;
 865 }
 866
 867 static int DIV_TO_REG(int val)
 868 {
 869         int answer = 0;
 870
 871         while (answer < 7 && (val >>= 1))
 872                 answer++;
 873         return answer;
 874 }
 875
 876 #define DIV_FROM_REG(val) BIT(val)
 877
 878 /*
 879  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 880  * depending on the chip type, to calculate the actual PWM frequency.
 881  *
 882  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 883  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 884  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 885  * sometimes just one. It is unknown if this is a datasheet error or real,
 886  * so this is ignored for now.
 887  */
 888 static const unsigned int pwm_freq[8] = {
 889         48000000,
 890         24000000,
 891         12000000,
 892         8000000,
 893         6000000,
 894         3000000,
 895         1500000,
 896         750000,
 897 };
 898
 899 static int _it87_read_value(struct it87_data *data, u8 reg)
 900 {
 901         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 902         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 903 }
 904
 905 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 906 {
 907         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 908         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 909 }
 910
 911 static void it87_set_bank(struct it87_data *data, u8 bank)
 912 {
 913         if (has_bank_sel(data) && bank != data->bank) {
 914                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 915
 916                 breg &= 0x1f;
 917                 breg |= (bank << 5);
 918                 data->bank = bank;
 919                 _it87_write_value(data, IT87_REG_BANK, breg);
 920         }
 921 }
 922
 923 /*
 924  * Must be called with data->update_lock held, except during initialization.
 925  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 926  * would slow down the IT87 access and should not be necessary.
 927  */
 928 static int it87_read_value(struct it87_data *data, u16 reg)
 929 {
 930         it87_set_bank(data, reg >> 8);
 931         return _it87_read_value(data, reg & 0xff);
 932 }
 933
 934 /*
 935  * Must be called with data->update_lock held, except during initialization.
 936  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 937  * would slow down the IT87 access and should not be necessary.
 938  */
 939 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
 940 {
 941         it87_set_bank(data, reg >> 8);
 942         _it87_write_value(data, reg & 0xff, value);
 943 }
 944
 945 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 946 {
 947         data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]);
 948         if (has_newer_autopwm(data)) {
 949                 if (has_new_tempmap(data))
 950                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x38;
 951                 else
 952                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 953                 data->pwm_duty[nr] = it87_read_value(data,
 954                                                      IT87_REG_PWM_DUTY[nr]);
 955         } else {
 956                 if (data->pwm_ctrl[nr] & 0x80)  /* Automatic mode */
 957                         data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 958                 else                            /* Manual mode */
 959                         data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
 960         }
 961
 962         if (has_old_autopwm(data)) {
 963                 int i;
 964
 965                 for (i = 0; i < 5 ; i++)
 966                         data->auto_temp[nr][i] = it87_read_value(data,
 967                                                 IT87_REG_AUTO_TEMP(nr, i));
 968                 for (i = 0; i < 3 ; i++)
 969                         data->auto_pwm[nr][i] = it87_read_value(data,
 970                                                 IT87_REG_AUTO_PWM(nr, i));
 971         } else if (has_newer_autopwm(data)) {
 972                 int i;
 973
 974                 /*
 975                  * 0: temperature hysteresis (base + 5)
 976                  * 1: fan off temperature (base + 0)
 977                  * 2: fan start temperature (base + 1)
 978                  * 3: fan max temperature (base + 2)
 979                  */
 980                 data->auto_temp[nr][0] =
 981                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
 982
 983                 for (i = 0; i < 3 ; i++)
 984                         data->auto_temp[nr][i + 1] =
 985                                 it87_read_value(data,
 986                                                 IT87_REG_AUTO_TEMP(nr, i));
 987                 /*
 988                  * 0: start pwm value (base + 3)
 989                  * 1: pwm slope (base + 4, 1/8th pwm)
 990                  */
 991                 data->auto_pwm[nr][0] =
 992                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
 993                 data->auto_pwm[nr][1] =
 994                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
 995         }
 996 }
 997
 998 static struct it87_data *it87_update_device(struct device *dev)
 999 {
1000         struct it87_data *data = dev_get_drvdata(dev);
1001         int i;
1002
1003         mutex_lock(&data->update_lock);
1004
1005         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1006             !data->valid) {
1007                 if (update_vbat) {
1008                         /*
1009                          * Cleared after each update, so reenable.  Value
1010                          * returned by this read will be previous value
1011                          */
1012                         it87_write_value(data, IT87_REG_CONFIG,
1013                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1014                 }
1015                 for (i = 0; i < NUM_VIN; i++) {
1016                         if (!(data->has_in & BIT(i)))
1017                                 continue;
1018
1019                         data->in[i][0] =
1020                                 it87_read_value(data, IT87_REG_VIN[i]);
1021
1022                         /* VBAT and AVCC don't have limit registers */
1023                         if (i >= NUM_VIN_LIMIT)
1024                                 continue;
1025
1026                         data->in[i][1] =
1027                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
1028                         data->in[i][2] =
1029                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
1030                 }
1031
1032                 for (i = 0; i < NUM_FAN; i++) {
1033                         /* Skip disabled fans */
1034                         if (!(data->has_fan & BIT(i)))
1035                                 continue;
1036
1037                         data->fan[i][1] =
1038                                 it87_read_value(data, data->REG_FAN_MIN[i]);
1039                         data->fan[i][0] = it87_read_value(data,
1040                                        data->REG_FAN[i]);
1041                         /* Add high byte if in 16-bit mode */
1042                         if (has_16bit_fans(data)) {
1043                                 data->fan[i][0] |= it87_read_value(data,
1044                                                 data->REG_FANX[i]) << 8;
1045                                 data->fan[i][1] |= it87_read_value(data,
1046                                                 data->REG_FANX_MIN[i]) << 8;
1047                         }
1048                 }
1049                 for (i = 0; i < NUM_TEMP; i++) {
1050                         if (!(data->has_temp & BIT(i)))
1051                                 continue;
1052                         data->temp[i][0] =
1053                                 it87_read_value(data, IT87_REG_TEMP(i));
1054
1055                         if (i >= data->num_temp_limit)
1056                                 continue;
1057
1058                         if (has_temp_offset(data) && i < data->num_temp_offset)
1059                                 data->temp[i][3] =
1060                                   it87_read_value(data,
1061                                                   data->REG_TEMP_OFFSET[i]);
1062
1063                         data->temp[i][1] =
1064                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1065                         data->temp[i][2] =
1066                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1067                 }
1068
1069                 /* Newer chips don't have clock dividers */
1070                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1071                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1072                         data->fan_div[0] = i & 0x07;
1073                         data->fan_div[1] = (i >> 3) & 0x07;
1074                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1075                 }
1076
1077                 data->alarms =
1078                         it87_read_value(data, IT87_REG_ALARM1) |
1079                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1080                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1081                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1082
1083                 data->fan_main_ctrl = it87_read_value(data,
1084                                 IT87_REG_FAN_MAIN_CTRL);
1085                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1086                 for (i = 0; i < NUM_PWM; i++) {
1087                         if (!(data->has_pwm & BIT(i)))
1088                                 continue;
1089                         it87_update_pwm_ctrl(data, i);
1090                 }
1091
1092                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1093                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1094                 /*
1095                  * The IT8705F does not have VID capability.
1096                  * The IT8718F and later don't use IT87_REG_VID for the
1097                  * same purpose.
1098                  */
1099                 if (data->type == it8712 || data->type == it8716) {
1100                         data->vid = it87_read_value(data, IT87_REG_VID);
1101                         /*
1102                          * The older IT8712F revisions had only 5 VID pins,
1103                          * but we assume it is always safe to read 6 bits.
1104                          */
1105                         data->vid &= 0x3f;
1106                 }
1107                 data->last_updated = jiffies;
1108                 data->valid = 1;
1109         }
1110
1111         mutex_unlock(&data->update_lock);
1112
1113         return data;
1114 }
1115
1116 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1117                        char *buf)
1118 {
1119         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1120         struct it87_data *data = it87_update_device(dev);
1121         int index = sattr->index;
1122         int nr = sattr->nr;
1123
1124         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1125 }
1126
1127 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1128                       const char *buf, size_t count)
1129 {
1130         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1131         struct it87_data *data = dev_get_drvdata(dev);
1132         int index = sattr->index;
1133         int nr = sattr->nr;
1134         unsigned long val;
1135
1136         if (kstrtoul(buf, 10, &val) < 0)
1137                 return -EINVAL;
1138
1139         mutex_lock(&data->update_lock);
1140         data->in[nr][index] = in_to_reg(data, nr, val);
1141         it87_write_value(data,
1142                          index == 1 ? IT87_REG_VIN_MIN(nr)
1143                                     : IT87_REG_VIN_MAX(nr),
1144                          data->in[nr][index]);
1145         mutex_unlock(&data->update_lock);
1146         return count;
1147 }
1148
1149 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1150 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1151                             0, 1);
1152 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1153                             0, 2);
1154
1155 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1156 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1157                             1, 1);
1158 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1159                             1, 2);
1160
1161 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1162 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1163                             2, 1);
1164 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1165                             2, 2);
1166
1167 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1168 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1169                             3, 1);
1170 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1171                             3, 2);
1172
1173 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1174 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1175                             4, 1);
1176 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1177                             4, 2);
1178
1179 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1180 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1181                             5, 1);
1182 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1183                             5, 2);
1184
1185 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1186 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1187                             6, 1);
1188 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1189                             6, 2);
1190
1191 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1192 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1193                             7, 1);
1194 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1195                             7, 2);
1196
1197 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1198 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1199 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1200 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1201 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1202
1203 /* Up to 6 temperatures */
1204 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1205                          char *buf)
1206 {
1207         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1208         int nr = sattr->nr;
1209         int index = sattr->index;
1210         struct it87_data *data = it87_update_device(dev);
1211
1212         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1213 }
1214
1215 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1216                         const char *buf, size_t count)
1217 {
1218         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1219         int nr = sattr->nr;
1220         int index = sattr->index;
1221         struct it87_data *data = dev_get_drvdata(dev);
1222         long val;
1223         u8 reg, regval;
1224
1225         if (kstrtol(buf, 10, &val) < 0)
1226                 return -EINVAL;
1227
1228         mutex_lock(&data->update_lock);
1229
1230         switch (index) {
1231         default:
1232         case 1:
1233                 reg = data->REG_TEMP_LOW[nr];
1234                 break;
1235         case 2:
1236                 reg = data->REG_TEMP_HIGH[nr];
1237                 break;
1238         case 3:
1239                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1240                 if (!(regval & 0x80)) {
1241                         regval |= 0x80;
1242                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1243                 }
1244                 data->valid = 0;
1245                 reg = data->REG_TEMP_OFFSET[nr];
1246                 break;
1247         }
1248
1249         data->temp[nr][index] = TEMP_TO_REG(val);
1250         it87_write_value(data, reg, data->temp[nr][index]);
1251         mutex_unlock(&data->update_lock);
1252         return count;
1253 }
1254
1255 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1256 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1257                             0, 1);
1258 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1259                             0, 2);
1260 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1261                             set_temp, 0, 3);
1262 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1263 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1264                             1, 1);
1265 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1266                             1, 2);
1267 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1268                             set_temp, 1, 3);
1269 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1270 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1271                             2, 1);
1272 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1273                             2, 2);
1274 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1275                             set_temp, 2, 3);
1276 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1277 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1278                             3, 1);
1279 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1280                             3, 2);
1281 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1282                             set_temp, 3, 3);
1283 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1284 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1285                             4, 1);
1286 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1287                             4, 2);
1288 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1289                             set_temp, 4, 3);
1290 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1291 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1292                             5, 1);
1293 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1294                             5, 2);
1295 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1296                             set_temp, 5, 3);
1297
1298 static int get_temp_type(struct it87_data *data, int index)
1299 {
1300         u8 reg, extra;
1301         int type = 0;
1302
1303         if (has_bank_sel(data)) {
1304                 int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
1305                 u8 src1, src2;
1306
1307                 src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
1308                 src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
1309
1310                 switch (data->type) {
1311                 case it8686:
1312                         switch (src1) {
1313                         case 0:
1314                                 if (index >= 3)
1315                                         return 4;
1316                                 break;
1317                         case 1:
1318                                 if (index == 1 || index == 2 ||
1319                                           index == 4 || index == 5)
1320                                         return 6;
1321                                 break;
1322                         case 2:
1323                                 if (index == 2 || index == 6)
1324                                         return 5;
1325                                 break;
1326                         default:
1327                                 break;
1328                         }
1329                         break;
1330                 case it8625:
1331                         if (index < 3)
1332                                 break;
1333                 case it8655:
1334                 case it8665:
1335                         if (src1 < 3) {
1336                                 index = src1;
1337                                 break;
1338                         }
1339                         switch(src1) {
1340                         case 3:
1341                                 type = (src2 & BIT(index)) ? 6 : 5;
1342                                 break;
1343                         case 4 ... 8:
1344                                 type = (src2 & BIT(index)) ? 4 : 6;
1345                                 break;
1346                         case 9:
1347                                 type = (src2 & BIT(index)) ? 5 : 0;
1348                                 break;
1349                         default:
1350                                 break;
1351                         }
1352                         return type;
1353                 default:
1354                         return 0;
1355                 }
1356         }
1357         if (index >= 3)
1358                 return 0;
1359
1360         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1361         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1362
1363         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1364             (has_temp_old_peci(data, index) && (extra & 0x80)))
1365                 type = 6;               /* Intel PECI */
1366         if (reg & BIT(index))
1367                 type = 3;               /* thermal diode */
1368         else if (reg & BIT(index + 3))
1369                 type = 4;               /* thermistor */
1370
1371         return type;
1372 }
1373
1374 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1375                               char *buf)
1376 {
1377         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1378         struct it87_data *data = it87_update_device(dev);
1379         int type = get_temp_type(data, sensor_attr->index);
1380
1381         return sprintf(buf, "%d\n", type);
1382 }
1383
1384 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1385                              const char *buf, size_t count)
1386 {
1387         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1388         int nr = sensor_attr->index;
1389
1390         struct it87_data *data = dev_get_drvdata(dev);
1391         long val;
1392         u8 reg, extra;
1393
1394         if (kstrtol(buf, 10, &val) < 0)
1395                 return -EINVAL;
1396
1397         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1398         reg &= ~(1 << nr);
1399         reg &= ~(8 << nr);
1400         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1401                 reg &= 0x3f;
1402         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1403         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1404                 extra &= 0x7f;
1405         if (val == 2) { /* backwards compatibility */
1406                 dev_warn(dev,
1407                          "Sensor type 2 is deprecated, please use 4 instead\n");
1408                 val = 4;
1409         }
1410         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1411         if (val == 3)
1412                 reg |= 1 << nr;
1413         else if (val == 4)
1414                 reg |= 8 << nr;
1415         else if (has_temp_peci(data, nr) && val == 6)
1416                 reg |= (nr + 1) << 6;
1417         else if (has_temp_old_peci(data, nr) && val == 6)
1418                 extra |= 0x80;
1419         else if (val != 0)
1420                 return -EINVAL;
1421
1422         mutex_lock(&data->update_lock);
1423         data->sensor = reg;
1424         data->extra = extra;
1425         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1426         if (has_temp_old_peci(data, nr))
1427                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1428         data->valid = 0;        /* Force cache refresh */
1429         mutex_unlock(&data->update_lock);
1430         return count;
1431 }
1432
1433 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1434                           set_temp_type, 0);
1435 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1436                           set_temp_type, 1);
1437 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1438                           set_temp_type, 2);
1439 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1440                           set_temp_type, 3);
1441 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1442                           set_temp_type, 4);
1443 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1444                           set_temp_type, 5);
1445
1446 /* 6 Fans */
1447
1448 static int pwm_mode(const struct it87_data *data, int nr)
1449 {
1450         if (has_fanctl_onoff(data) && nr < 3 &&
1451             !(data->fan_main_ctrl & BIT(nr)))
1452                 return 0;                               /* Full speed */
1453         if (data->pwm_ctrl[nr] & 0x80)
1454                 return 2;                               /* Automatic mode */
1455         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1456             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1457                 return 0;                       /* Full speed */
1458
1459         return 1;                               /* Manual mode */
1460 }
1461
1462 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1463                         char *buf)
1464 {
1465         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1466         int nr = sattr->nr;
1467         int index = sattr->index;
1468         int speed;
1469         struct it87_data *data = it87_update_device(dev);
1470
1471         speed = has_16bit_fans(data) ?
1472                 FAN16_FROM_REG(data->fan[nr][index]) :
1473                 FAN_FROM_REG(data->fan[nr][index],
1474                              DIV_FROM_REG(data->fan_div[nr]));
1475         return sprintf(buf, "%d\n", speed);
1476 }
1477
1478 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1479                             char *buf)
1480 {
1481         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1482         struct it87_data *data = it87_update_device(dev);
1483         int nr = sensor_attr->index;
1484
1485         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1486 }
1487
1488 static ssize_t show_pwm_enable(struct device *dev,
1489                                struct device_attribute *attr, char *buf)
1490 {
1491         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1492         struct it87_data *data = it87_update_device(dev);
1493         int nr = sensor_attr->index;
1494
1495         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1496 }
1497
1498 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1499                         char *buf)
1500 {
1501         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1502         struct it87_data *data = it87_update_device(dev);
1503         int nr = sensor_attr->index;
1504
1505         return sprintf(buf, "%d\n",
1506                        pwm_from_reg(data, data->pwm_duty[nr]));
1507 }
1508
1509 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1510                              char *buf)
1511 {
1512         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1513         struct it87_data *data = it87_update_device(dev);
1514         int nr = sensor_attr->index;
1515         unsigned int freq;
1516         int index;
1517
1518         if (has_pwm_freq2(data) && nr == 1)
1519                 index = (data->extra >> 4) & 0x07;
1520         else
1521                 index = (data->fan_ctl >> 4) & 0x07;
1522
1523         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1524
1525         return sprintf(buf, "%u\n", freq);
1526 }
1527
1528 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1529                        const char *buf, size_t count)
1530 {
1531         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1532         int nr = sattr->nr;
1533         int index = sattr->index;
1534
1535         struct it87_data *data = dev_get_drvdata(dev);
1536         long val;
1537         u8 reg;
1538
1539         if (kstrtol(buf, 10, &val) < 0)
1540                 return -EINVAL;
1541
1542         mutex_lock(&data->update_lock);
1543
1544         if (has_16bit_fans(data)) {
1545                 data->fan[nr][index] = FAN16_TO_REG(val);
1546                 it87_write_value(data, data->REG_FAN_MIN[nr],
1547                                  data->fan[nr][index] & 0xff);
1548                 it87_write_value(data, data->REG_FANX_MIN[nr],
1549                                  data->fan[nr][index] >> 8);
1550         } else {
1551                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1552                 switch (nr) {
1553                 case 0:
1554                         data->fan_div[nr] = reg & 0x07;
1555                         break;
1556                 case 1:
1557                         data->fan_div[nr] = (reg >> 3) & 0x07;
1558                         break;
1559                 case 2:
1560                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1561                         break;
1562                 }
1563                 data->fan[nr][index] =
1564                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1565                 it87_write_value(data, data->REG_FAN_MIN[nr],
1566                                  data->fan[nr][index]);
1567         }
1568
1569         mutex_unlock(&data->update_lock);
1570         return count;
1571 }
1572
1573 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1574                            const char *buf, size_t count)
1575 {
1576         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1577         struct it87_data *data = dev_get_drvdata(dev);
1578         int nr = sensor_attr->index;
1579         unsigned long val;
1580         int min;
1581         u8 old;
1582
1583         if (kstrtoul(buf, 10, &val) < 0)
1584                 return -EINVAL;
1585
1586         mutex_lock(&data->update_lock);
1587         old = it87_read_value(data, IT87_REG_FAN_DIV);
1588
1589         /* Save fan min limit */
1590         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1591
1592         switch (nr) {
1593         case 0:
1594         case 1:
1595                 data->fan_div[nr] = DIV_TO_REG(val);
1596                 break;
1597         case 2:
1598                 if (val < 8)
1599                         data->fan_div[nr] = 1;
1600                 else
1601                         data->fan_div[nr] = 3;
1602         }
1603         val = old & 0x80;
1604         val |= (data->fan_div[0] & 0x07);
1605         val |= (data->fan_div[1] & 0x07) << 3;
1606         if (data->fan_div[2] == 3)
1607                 val |= 0x1 << 6;
1608         it87_write_value(data, IT87_REG_FAN_DIV, val);
1609
1610         /* Restore fan min limit */
1611         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1612         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1613
1614         mutex_unlock(&data->update_lock);
1615         return count;
1616 }
1617
1618 /* Returns 0 if OK, -EINVAL otherwise */
1619 static int check_trip_points(struct device *dev, int nr)
1620 {
1621         const struct it87_data *data = dev_get_drvdata(dev);
1622         int i, err = 0;
1623
1624         if (has_old_autopwm(data)) {
1625                 for (i = 0; i < 3; i++) {
1626                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1627                                 err = -EINVAL;
1628                 }
1629                 for (i = 0; i < 2; i++) {
1630                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1631                                 err = -EINVAL;
1632                 }
1633         } else if (has_newer_autopwm(data)) {
1634                 for (i = 1; i < 3; i++) {
1635                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1636                                 err = -EINVAL;
1637                 }
1638         }
1639
1640         if (err) {
1641                 dev_err(dev,
1642                         "Inconsistent trip points, not switching to automatic mode\n");
1643                 dev_err(dev, "Adjust the trip points and try again\n");
1644         }
1645         return err;
1646 }
1647
1648 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1649                               const char *buf, size_t count)
1650 {
1651         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1652         struct it87_data *data = dev_get_drvdata(dev);
1653         int nr = sensor_attr->index;
1654         long val;
1655
1656         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1657                 return -EINVAL;
1658
1659         /* Check trip points before switching to automatic mode */
1660         if (val == 2) {
1661                 if (check_trip_points(dev, nr) < 0)
1662                         return -EINVAL;
1663         }
1664
1665         mutex_lock(&data->update_lock);
1666
1667         if (val == 0) {
1668                 if (nr < 3 && has_fanctl_onoff(data)) {
1669                         int tmp;
1670                         /* make sure the fan is on when in on/off mode */
1671                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1672                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1673                         /* set on/off mode */
1674                         data->fan_main_ctrl &= ~BIT(nr);
1675                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1676                                          data->fan_main_ctrl);
1677                 } else {
1678                         u8 ctrl;
1679
1680                         /* No on/off mode, set maximum pwm value */
1681                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1682                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1683                                          data->pwm_duty[nr]);
1684                         /* and set manual mode */
1685                         if (has_newer_autopwm(data)) {
1686                                 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1687                                         data->pwm_temp_map[nr];
1688                         } else {
1689                                 ctrl = data->pwm_duty[nr];
1690                         }
1691                         data->pwm_ctrl[nr] = ctrl;
1692                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1693                 }
1694         } else {
1695                 u8 ctrl;
1696
1697                 if (has_newer_autopwm(data)) {
1698                         ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1699                                 data->pwm_temp_map[nr];
1700                         if (val != 1)
1701                                 ctrl |= 0x80;
1702                 } else {
1703                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1704                 }
1705                 data->pwm_ctrl[nr] = ctrl;
1706                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1707
1708                 if (has_fanctl_onoff(data) && nr < 3) {
1709                         /* set SmartGuardian mode */
1710                         data->fan_main_ctrl |= BIT(nr);
1711                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1712                                          data->fan_main_ctrl);
1713                 }
1714         }
1715
1716         mutex_unlock(&data->update_lock);
1717         return count;
1718 }
1719
1720 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1721                        const char *buf, size_t count)
1722 {
1723         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1724         struct it87_data *data = dev_get_drvdata(dev);
1725         int nr = sensor_attr->index;
1726         long val;
1727
1728         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1729                 return -EINVAL;
1730
1731         mutex_lock(&data->update_lock);
1732         it87_update_pwm_ctrl(data, nr);
1733         if (has_newer_autopwm(data)) {
1734                 /*
1735                  * If we are in automatic mode, the PWM duty cycle register
1736                  * is read-only so we can't write the value.
1737                  */
1738                 if (data->pwm_ctrl[nr] & 0x80) {
1739                         mutex_unlock(&data->update_lock);
1740                         return -EBUSY;
1741                 }
1742                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1743                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1744                                  data->pwm_duty[nr]);
1745         } else {
1746                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1747                 /*
1748                  * If we are in manual mode, write the duty cycle immediately;
1749                  * otherwise, just store it for later use.
1750                  */
1751                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1752                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1753                         it87_write_value(data, data->REG_PWM[nr],
1754                                          data->pwm_ctrl[nr]);
1755                 }
1756         }
1757         mutex_unlock(&data->update_lock);
1758         return count;
1759 }
1760
1761 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1762                             const char *buf, size_t count)
1763 {
1764         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1765         struct it87_data *data = dev_get_drvdata(dev);
1766         int nr = sensor_attr->index;
1767         unsigned long val;
1768         int i;
1769
1770         if (kstrtoul(buf, 10, &val) < 0)
1771                 return -EINVAL;
1772
1773         val = clamp_val(val, 0, 1000000);
1774         val *= has_newer_autopwm(data) ? 256 : 128;
1775
1776         /* Search for the nearest available frequency */
1777         for (i = 0; i < 7; i++) {
1778                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1779                         break;
1780         }
1781
1782         mutex_lock(&data->update_lock);
1783         if (nr == 0) {
1784                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1785                 data->fan_ctl |= i << 4;
1786                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1787         } else {
1788                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1789                 data->extra |= i << 4;
1790                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1791         }
1792         mutex_unlock(&data->update_lock);
1793
1794         return count;
1795 }
1796
1797 static ssize_t show_pwm_temp_map(struct device *dev,
1798                                  struct device_attribute *attr, char *buf)
1799 {
1800         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1801         struct it87_data *data = it87_update_device(dev);
1802         int nr = sensor_attr->index;
1803         int map;
1804
1805         map = data->pwm_temp_map[nr];
1806         if (has_new_tempmap(data)) {
1807                 map >>= 3;
1808                 if (map >= 6)
1809                         map = 0;        /* Should never happen */
1810         } else {
1811                 if (map >= 3)
1812                         map = 0;        /* Should never happen */
1813                 if (nr >= 3)            /* pwm channels 3..6 map to temp4..6 */
1814                         map += 3;
1815         }
1816
1817         return sprintf(buf, "%d\n", (int)BIT(map));
1818 }
1819
1820 static ssize_t set_pwm_temp_map(struct device *dev,
1821                                 struct device_attribute *attr, const char *buf,
1822                                 size_t count)
1823 {
1824         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1825         struct it87_data *data = dev_get_drvdata(dev);
1826         int nr = sensor_attr->index;
1827         long val;
1828         u8 reg;
1829
1830         if (kstrtol(buf, 10, &val) < 0)
1831                 return -EINVAL;
1832
1833         if (nr >= 3 && !has_new_tempmap(data))
1834                 val -= 3;
1835
1836         switch (val) {
1837         case BIT(0):
1838                 reg = 0x00;
1839                 break;
1840         case BIT(1):
1841                 reg = 0x01;
1842                 break;
1843         case BIT(2):
1844                 reg = 0x02;
1845                 break;
1846         case BIT(3):
1847                 reg = 0x03;
1848                 break;
1849         case BIT(4):
1850                 reg = 0x04;
1851                 break;
1852         case BIT(5):
1853                 reg = 0x05;
1854                 break;
1855         case BIT(6):
1856                 reg = 0x06;
1857                 break;
1858         default:
1859                 return -EINVAL;
1860         }
1861
1862         if (has_new_tempmap(data))
1863                 reg <<= 3;
1864         else if (reg > 0x02)
1865                 return -EINVAL;
1866
1867         mutex_lock(&data->update_lock);
1868         it87_update_pwm_ctrl(data, nr);
1869         data->pwm_temp_map[nr] = reg;
1870         /*
1871          * If we are in automatic mode, write the temp mapping immediately;
1872          * otherwise, just store it for later use.
1873          */
1874         if (data->pwm_ctrl[nr] & 0x80) {
1875                 u8 mask = has_new_tempmap(data) ? 0xc7 : 0xfc;
1876
1877                 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & mask) |
1878                                                 data->pwm_temp_map[nr];
1879                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1880         }
1881         mutex_unlock(&data->update_lock);
1882         return count;
1883 }
1884
1885 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1886                              char *buf)
1887 {
1888         struct it87_data *data = it87_update_device(dev);
1889         struct sensor_device_attribute_2 *sensor_attr =
1890                         to_sensor_dev_attr_2(attr);
1891         int nr = sensor_attr->nr;
1892         int point = sensor_attr->index;
1893
1894         return sprintf(buf, "%d\n",
1895                        pwm_from_reg(data, data->auto_pwm[nr][point]));
1896 }
1897
1898 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1899                             const char *buf, size_t count)
1900 {
1901         struct it87_data *data = dev_get_drvdata(dev);
1902         struct sensor_device_attribute_2 *sensor_attr =
1903                         to_sensor_dev_attr_2(attr);
1904         int nr = sensor_attr->nr;
1905         int point = sensor_attr->index;
1906         int regaddr;
1907         long val;
1908
1909         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1910                 return -EINVAL;
1911
1912         mutex_lock(&data->update_lock);
1913         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1914         if (has_newer_autopwm(data))
1915                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1916         else
1917                 regaddr = IT87_REG_AUTO_PWM(nr, point);
1918         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1919         mutex_unlock(&data->update_lock);
1920         return count;
1921 }
1922
1923 static ssize_t show_auto_pwm_slope(struct device *dev,
1924                                    struct device_attribute *attr, char *buf)
1925 {
1926         struct it87_data *data = it87_update_device(dev);
1927         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1928         int nr = sensor_attr->index;
1929
1930         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1931 }
1932
1933 static ssize_t set_auto_pwm_slope(struct device *dev,
1934                                   struct device_attribute *attr,
1935                                   const char *buf, size_t count)
1936 {
1937         struct it87_data *data = dev_get_drvdata(dev);
1938         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1939         int nr = sensor_attr->index;
1940         unsigned long val;
1941
1942         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1943                 return -EINVAL;
1944
1945         mutex_lock(&data->update_lock);
1946         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1947         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1948                          data->auto_pwm[nr][1]);
1949         mutex_unlock(&data->update_lock);
1950         return count;
1951 }
1952
1953 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1954                               char *buf)
1955 {
1956         struct it87_data *data = it87_update_device(dev);
1957         struct sensor_device_attribute_2 *sensor_attr =
1958                         to_sensor_dev_attr_2(attr);
1959         int nr = sensor_attr->nr;
1960         int point = sensor_attr->index;
1961         int reg;
1962
1963         if (has_old_autopwm(data) || point)
1964                 reg = data->auto_temp[nr][point];
1965         else
1966                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1967
1968         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1969 }
1970
1971 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1972                              const char *buf, size_t count)
1973 {
1974         struct it87_data *data = dev_get_drvdata(dev);
1975         struct sensor_device_attribute_2 *sensor_attr =
1976                         to_sensor_dev_attr_2(attr);
1977         int nr = sensor_attr->nr;
1978         int point = sensor_attr->index;
1979         long val;
1980         int reg;
1981
1982         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1983                 return -EINVAL;
1984
1985         mutex_lock(&data->update_lock);
1986         if (has_newer_autopwm(data) && !point) {
1987                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1988                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1989                 data->auto_temp[nr][0] = reg;
1990                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1991         } else {
1992                 reg = TEMP_TO_REG(val);
1993                 data->auto_temp[nr][point] = reg;
1994                 if (has_newer_autopwm(data))
1995                         point--;
1996                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1997         }
1998         mutex_unlock(&data->update_lock);
1999         return count;
2000 }
2001
2002 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
2003 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2004                             0, 1);
2005 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
2006                           set_fan_div, 0);
2007
2008 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
2009 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2010                             1, 1);
2011 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
2012                           set_fan_div, 1);
2013
2014 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
2015 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2016                             2, 1);
2017 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
2018                           set_fan_div, 2);
2019
2020 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2021 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2022                             3, 1);
2023
2024 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2025 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2026                             4, 1);
2027
2028 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2029 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2030                             5, 1);
2031
2032 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2033                           show_pwm_enable, set_pwm_enable, 0);
2034 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2035 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2036                           set_pwm_freq, 0);
2037 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2038                           show_pwm_temp_map, set_pwm_temp_map, 0);
2039 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2040                             show_auto_pwm, set_auto_pwm, 0, 0);
2041 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2042                             show_auto_pwm, set_auto_pwm, 0, 1);
2043 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2044                             show_auto_pwm, set_auto_pwm, 0, 2);
2045 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2046                             show_auto_pwm, NULL, 0, 3);
2047 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2048                             show_auto_temp, set_auto_temp, 0, 1);
2049 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2050                             show_auto_temp, set_auto_temp, 0, 0);
2051 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2052                             show_auto_temp, set_auto_temp, 0, 2);
2053 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2054                             show_auto_temp, set_auto_temp, 0, 3);
2055 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2056                             show_auto_temp, set_auto_temp, 0, 4);
2057 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2058                             show_auto_pwm, set_auto_pwm, 0, 0);
2059 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2060                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2061
2062 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2063                           show_pwm_enable, set_pwm_enable, 1);
2064 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2065 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2066 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2067                           show_pwm_temp_map, set_pwm_temp_map, 1);
2068 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2069                             show_auto_pwm, set_auto_pwm, 1, 0);
2070 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2071                             show_auto_pwm, set_auto_pwm, 1, 1);
2072 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2073                             show_auto_pwm, set_auto_pwm, 1, 2);
2074 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2075                             show_auto_pwm, NULL, 1, 3);
2076 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2077                             show_auto_temp, set_auto_temp, 1, 1);
2078 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2079                             show_auto_temp, set_auto_temp, 1, 0);
2080 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2081                             show_auto_temp, set_auto_temp, 1, 2);
2082 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2083                             show_auto_temp, set_auto_temp, 1, 3);
2084 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2085                             show_auto_temp, set_auto_temp, 1, 4);
2086 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2087                             show_auto_pwm, set_auto_pwm, 1, 0);
2088 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2089                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2090
2091 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2092                           show_pwm_enable, set_pwm_enable, 2);
2093 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2094 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2095 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2096                           show_pwm_temp_map, set_pwm_temp_map, 2);
2097 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2098                             show_auto_pwm, set_auto_pwm, 2, 0);
2099 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2100                             show_auto_pwm, set_auto_pwm, 2, 1);
2101 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2102                             show_auto_pwm, set_auto_pwm, 2, 2);
2103 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2104                             show_auto_pwm, NULL, 2, 3);
2105 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2106                             show_auto_temp, set_auto_temp, 2, 1);
2107 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2108                             show_auto_temp, set_auto_temp, 2, 0);
2109 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2110                             show_auto_temp, set_auto_temp, 2, 2);
2111 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2112                             show_auto_temp, set_auto_temp, 2, 3);
2113 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2114                             show_auto_temp, set_auto_temp, 2, 4);
2115 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2116                             show_auto_pwm, set_auto_pwm, 2, 0);
2117 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2118                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2119
2120 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2121                           show_pwm_enable, set_pwm_enable, 3);
2122 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2123 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2124 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2125                           show_pwm_temp_map, set_pwm_temp_map, 3);
2126 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2127                             show_auto_temp, set_auto_temp, 2, 1);
2128 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2129                             show_auto_temp, set_auto_temp, 2, 0);
2130 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2131                             show_auto_temp, set_auto_temp, 2, 2);
2132 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2133                             show_auto_temp, set_auto_temp, 2, 3);
2134 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2135                             show_auto_pwm, set_auto_pwm, 3, 0);
2136 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2137                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2138
2139 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2140                           show_pwm_enable, set_pwm_enable, 4);
2141 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2142 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2143 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2144                           show_pwm_temp_map, set_pwm_temp_map, 4);
2145 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2146                             show_auto_temp, set_auto_temp, 2, 1);
2147 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2148                             show_auto_temp, set_auto_temp, 2, 0);
2149 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2150                             show_auto_temp, set_auto_temp, 2, 2);
2151 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2152                             show_auto_temp, set_auto_temp, 2, 3);
2153 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2154                             show_auto_pwm, set_auto_pwm, 4, 0);
2155 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2156                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2157
2158 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2159                           show_pwm_enable, set_pwm_enable, 5);
2160 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2161 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2162 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2163                           show_pwm_temp_map, set_pwm_temp_map, 5);
2164 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2165                             show_auto_temp, set_auto_temp, 2, 1);
2166 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2167                             show_auto_temp, set_auto_temp, 2, 0);
2168 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2169                             show_auto_temp, set_auto_temp, 2, 2);
2170 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2171                             show_auto_temp, set_auto_temp, 2, 3);
2172 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2173                             show_auto_pwm, set_auto_pwm, 5, 0);
2174 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2175                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2176
2177 /* Alarms */
2178 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2179                            char *buf)
2180 {
2181         struct it87_data *data = it87_update_device(dev);
2182
2183         return sprintf(buf, "%u\n", data->alarms);
2184 }
2185 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2186
2187 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2188                           char *buf)
2189 {
2190         struct it87_data *data = it87_update_device(dev);
2191         int bitnr = to_sensor_dev_attr(attr)->index;
2192
2193         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2194 }
2195
2196 static ssize_t clear_intrusion(struct device *dev,
2197                                struct device_attribute *attr, const char *buf,
2198                                size_t count)
2199 {
2200         struct it87_data *data = dev_get_drvdata(dev);
2201         int config;
2202         long val;
2203
2204         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2205                 return -EINVAL;
2206
2207         mutex_lock(&data->update_lock);
2208         config = it87_read_value(data, IT87_REG_CONFIG);
2209         if (config < 0) {
2210                 count = config;
2211         } else {
2212                 config |= BIT(5);
2213                 it87_write_value(data, IT87_REG_CONFIG, config);
2214                 /* Invalidate cache to force re-read */
2215                 data->valid = 0;
2216         }
2217         mutex_unlock(&data->update_lock);
2218
2219         return count;
2220 }
2221
2222 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2223 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2224 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2225 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2226 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2227 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2228 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2229 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2230 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2231 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2232 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2233 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2234 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2235 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2236 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2237 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2238 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2239 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2240 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2241 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2242 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2243                           show_alarm, clear_intrusion, 4);
2244
2245 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2246                          char *buf)
2247 {
2248         struct it87_data *data = it87_update_device(dev);
2249         int bitnr = to_sensor_dev_attr(attr)->index;
2250
2251         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2252 }
2253
2254 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2255                         const char *buf, size_t count)
2256 {
2257         int bitnr = to_sensor_dev_attr(attr)->index;
2258         struct it87_data *data = dev_get_drvdata(dev);
2259         long val;
2260
2261         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2262                 return -EINVAL;
2263
2264         mutex_lock(&data->update_lock);
2265         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2266         if (val)
2267                 data->beeps |= BIT(bitnr);
2268         else
2269                 data->beeps &= ~BIT(bitnr);
2270         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2271         mutex_unlock(&data->update_lock);
2272         return count;
2273 }
2274
2275 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2276                           show_beep, set_beep, 1);
2277 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2278 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2279 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2280 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2281 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2282 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2283 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2284 /* fanX_beep writability is set later */
2285 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2286 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2287 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2288 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2289 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2290 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2291 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2292                           show_beep, set_beep, 2);
2293 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2294 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2295 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2296 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2297 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2298
2299 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2300                             char *buf)
2301 {
2302         struct it87_data *data = dev_get_drvdata(dev);
2303
2304         return sprintf(buf, "%u\n", data->vrm);
2305 }
2306
2307 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2308                              const char *buf, size_t count)
2309 {
2310         struct it87_data *data = dev_get_drvdata(dev);
2311         unsigned long val;
2312
2313         if (kstrtoul(buf, 10, &val) < 0)
2314                 return -EINVAL;
2315
2316         data->vrm = val;
2317
2318         return count;
2319 }
2320 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2321
2322 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2323                             char *buf)
2324 {
2325         struct it87_data *data = it87_update_device(dev);
2326
2327         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2328 }
2329 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2330
2331 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2332                           char *buf)
2333 {
2334         static const char * const labels[] = {
2335                 "+5V",
2336                 "5VSB",
2337                 "Vbat",
2338                 "AVCC",
2339         };
2340         static const char * const labels_it8721[] = {
2341                 "+3.3V",
2342                 "3VSB",
2343                 "Vbat",
2344                 "+3.3V",
2345         };
2346         struct it87_data *data = dev_get_drvdata(dev);
2347         int nr = to_sensor_dev_attr(attr)->index;
2348         const char *label;
2349
2350         if (has_vin3_5v(data) && nr == 0)
2351                 label = labels[0];
2352         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2353                  has_11mv_adc(data))
2354                 label = labels_it8721[nr];
2355         else
2356                 label = labels[nr];
2357
2358         return sprintf(buf, "%s\n", label);
2359 }
2360 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2361 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2362 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2363 /* AVCC3 */
2364 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2365
2366 static umode_t it87_in_is_visible(struct kobject *kobj,
2367                                   struct attribute *attr, int index)
2368 {
2369         struct device *dev = container_of(kobj, struct device, kobj);
2370         struct it87_data *data = dev_get_drvdata(dev);
2371         int i = index / 5;      /* voltage index */
2372         int a = index % 5;      /* attribute index */
2373
2374         if (index >= 40) {      /* in8 and higher only have input attributes */
2375                 i = index - 40 + 8;
2376                 a = 0;
2377         }
2378
2379         if (!(data->has_in & BIT(i)))
2380                 return 0;
2381
2382         if (a == 4 && !data->has_beep)
2383                 return 0;
2384
2385         return attr->mode;
2386 }
2387
2388 static struct attribute *it87_attributes_in[] = {
2389         &sensor_dev_attr_in0_input.dev_attr.attr,
2390         &sensor_dev_attr_in0_min.dev_attr.attr,
2391         &sensor_dev_attr_in0_max.dev_attr.attr,
2392         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2393         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2394
2395         &sensor_dev_attr_in1_input.dev_attr.attr,
2396         &sensor_dev_attr_in1_min.dev_attr.attr,
2397         &sensor_dev_attr_in1_max.dev_attr.attr,
2398         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2399         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2400
2401         &sensor_dev_attr_in2_input.dev_attr.attr,
2402         &sensor_dev_attr_in2_min.dev_attr.attr,
2403         &sensor_dev_attr_in2_max.dev_attr.attr,
2404         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2405         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2406
2407         &sensor_dev_attr_in3_input.dev_attr.attr,
2408         &sensor_dev_attr_in3_min.dev_attr.attr,
2409         &sensor_dev_attr_in3_max.dev_attr.attr,
2410         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2411         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2412
2413         &sensor_dev_attr_in4_input.dev_attr.attr,
2414         &sensor_dev_attr_in4_min.dev_attr.attr,
2415         &sensor_dev_attr_in4_max.dev_attr.attr,
2416         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2417         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2418
2419         &sensor_dev_attr_in5_input.dev_attr.attr,
2420         &sensor_dev_attr_in5_min.dev_attr.attr,
2421         &sensor_dev_attr_in5_max.dev_attr.attr,
2422         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2423         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2424
2425         &sensor_dev_attr_in6_input.dev_attr.attr,
2426         &sensor_dev_attr_in6_min.dev_attr.attr,
2427         &sensor_dev_attr_in6_max.dev_attr.attr,
2428         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2429         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2430
2431         &sensor_dev_attr_in7_input.dev_attr.attr,
2432         &sensor_dev_attr_in7_min.dev_attr.attr,
2433         &sensor_dev_attr_in7_max.dev_attr.attr,
2434         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2435         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2436
2437         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2438         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2439         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2440         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2441         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2442         NULL
2443 };
2444
2445 static const struct attribute_group it87_group_in = {
2446         .attrs = it87_attributes_in,
2447         .is_visible = it87_in_is_visible,
2448 };
2449
2450 static umode_t it87_temp_is_visible(struct kobject *kobj,
2451                                     struct attribute *attr, int index)
2452 {
2453         struct device *dev = container_of(kobj, struct device, kobj);
2454         struct it87_data *data = dev_get_drvdata(dev);
2455         int i = index / 7;      /* temperature index */
2456         int a = index % 7;      /* attribute index */
2457
2458         if (!(data->has_temp & BIT(i)))
2459                 return 0;
2460
2461         if (a && i >= data->num_temp_limit)
2462                 return 0;
2463
2464         if (a == 3) {
2465                 int type = get_temp_type(data, i);
2466
2467                 if (type == 0)
2468                         return 0;
2469                 if (has_bank_sel(data))
2470                         return 0444;
2471                 return attr->mode;
2472         }
2473
2474         if (a == 5 && (!has_temp_offset(data) || i >= data->num_temp_offset))
2475                 return 0;
2476
2477         if (a == 6 && !data->has_beep)
2478                 return 0;
2479
2480         return attr->mode;
2481 }
2482
2483 static struct attribute *it87_attributes_temp[] = {
2484         &sensor_dev_attr_temp1_input.dev_attr.attr,
2485         &sensor_dev_attr_temp1_max.dev_attr.attr,
2486         &sensor_dev_attr_temp1_min.dev_attr.attr,
2487         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2488         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2489         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2490         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2491
2492         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2493         &sensor_dev_attr_temp2_max.dev_attr.attr,
2494         &sensor_dev_attr_temp2_min.dev_attr.attr,
2495         &sensor_dev_attr_temp2_type.dev_attr.attr,
2496         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2497         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2498         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2499
2500         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2501         &sensor_dev_attr_temp3_max.dev_attr.attr,
2502         &sensor_dev_attr_temp3_min.dev_attr.attr,
2503         &sensor_dev_attr_temp3_type.dev_attr.attr,
2504         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2505         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2506         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2507
2508         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2509         &sensor_dev_attr_temp4_max.dev_attr.attr,
2510         &sensor_dev_attr_temp4_min.dev_attr.attr,
2511         &sensor_dev_attr_temp4_type.dev_attr.attr,
2512         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2513         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2514         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2515
2516         &sensor_dev_attr_temp5_input.dev_attr.attr,
2517         &sensor_dev_attr_temp5_max.dev_attr.attr,
2518         &sensor_dev_attr_temp5_min.dev_attr.attr,
2519         &sensor_dev_attr_temp5_type.dev_attr.attr,
2520         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2521         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2522         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2523
2524         &sensor_dev_attr_temp6_input.dev_attr.attr,
2525         &sensor_dev_attr_temp6_max.dev_attr.attr,
2526         &sensor_dev_attr_temp6_min.dev_attr.attr,
2527         &sensor_dev_attr_temp6_type.dev_attr.attr,
2528         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2529         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2530         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2531         NULL
2532 };
2533
2534 static const struct attribute_group it87_group_temp = {
2535         .attrs = it87_attributes_temp,
2536         .is_visible = it87_temp_is_visible,
2537 };
2538
2539 static umode_t it87_is_visible(struct kobject *kobj,
2540                                struct attribute *attr, int index)
2541 {
2542         struct device *dev = container_of(kobj, struct device, kobj);
2543         struct it87_data *data = dev_get_drvdata(dev);
2544
2545         if ((index == 2 || index == 3) && !data->has_vid)
2546                 return 0;
2547
2548         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2549                 return 0;
2550
2551         return attr->mode;
2552 }
2553
2554 static struct attribute *it87_attributes[] = {
2555         &dev_attr_alarms.attr,
2556         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2557         &dev_attr_vrm.attr,                             /* 2 */
2558         &dev_attr_cpu0_vid.attr,                        /* 3 */
2559         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2560         &sensor_dev_attr_in7_label.dev_attr.attr,
2561         &sensor_dev_attr_in8_label.dev_attr.attr,
2562         &sensor_dev_attr_in9_label.dev_attr.attr,
2563         NULL
2564 };
2565
2566 static const struct attribute_group it87_group = {
2567         .attrs = it87_attributes,
2568         .is_visible = it87_is_visible,
2569 };
2570
2571 static umode_t it87_fan_is_visible(struct kobject *kobj,
2572                                    struct attribute *attr, int index)
2573 {
2574         struct device *dev = container_of(kobj, struct device, kobj);
2575         struct it87_data *data = dev_get_drvdata(dev);
2576         int i = index / 5;      /* fan index */
2577         int a = index % 5;      /* attribute index */
2578
2579         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2580                 i = (index - 15) / 4 + 3;
2581                 a = (index - 15) % 4;
2582         }
2583
2584         if (!(data->has_fan & BIT(i)))
2585                 return 0;
2586
2587         if (a == 3) {                           /* beep */
2588                 if (!data->has_beep)
2589                         return 0;
2590                 /* first fan beep attribute is writable */
2591                 if (i == __ffs(data->has_fan))
2592                         return attr->mode | S_IWUSR;
2593         }
2594
2595         if (a == 4 && has_16bit_fans(data))     /* divisor */
2596                 return 0;
2597
2598         return attr->mode;
2599 }
2600
2601 static struct attribute *it87_attributes_fan[] = {
2602         &sensor_dev_attr_fan1_input.dev_attr.attr,
2603         &sensor_dev_attr_fan1_min.dev_attr.attr,
2604         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2605         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2606         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2607
2608         &sensor_dev_attr_fan2_input.dev_attr.attr,
2609         &sensor_dev_attr_fan2_min.dev_attr.attr,
2610         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2611         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2612         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2613
2614         &sensor_dev_attr_fan3_input.dev_attr.attr,
2615         &sensor_dev_attr_fan3_min.dev_attr.attr,
2616         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2617         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2618         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2619
2620         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2621         &sensor_dev_attr_fan4_min.dev_attr.attr,
2622         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2623         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2624
2625         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2626         &sensor_dev_attr_fan5_min.dev_attr.attr,
2627         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2628         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2629
2630         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2631         &sensor_dev_attr_fan6_min.dev_attr.attr,
2632         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2633         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2634         NULL
2635 };
2636
2637 static const struct attribute_group it87_group_fan = {
2638         .attrs = it87_attributes_fan,
2639         .is_visible = it87_fan_is_visible,
2640 };
2641
2642 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2643                                    struct attribute *attr, int index)
2644 {
2645         struct device *dev = container_of(kobj, struct device, kobj);
2646         struct it87_data *data = dev_get_drvdata(dev);
2647         int i = index / 4;      /* pwm index */
2648         int a = index % 4;      /* attribute index */
2649
2650         if (!(data->has_pwm & BIT(i)))
2651                 return 0;
2652
2653         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2654         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2655                 return attr->mode | S_IWUSR;
2656
2657         /* pwm2_freq is writable if there are two pwm frequency selects */
2658         if (has_pwm_freq2(data) && i == 1 && a == 2)
2659                 return attr->mode | S_IWUSR;
2660
2661         return attr->mode;
2662 }
2663
2664 static struct attribute *it87_attributes_pwm[] = {
2665         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2666         &sensor_dev_attr_pwm1.dev_attr.attr,
2667         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2668         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2669
2670         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2671         &sensor_dev_attr_pwm2.dev_attr.attr,
2672         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2673         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2674
2675         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2676         &sensor_dev_attr_pwm3.dev_attr.attr,
2677         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2678         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2679
2680         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2681         &sensor_dev_attr_pwm4.dev_attr.attr,
2682         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2683         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2684
2685         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2686         &sensor_dev_attr_pwm5.dev_attr.attr,
2687         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2688         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2689
2690         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2691         &sensor_dev_attr_pwm6.dev_attr.attr,
2692         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2693         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2694
2695         NULL
2696 };
2697
2698 static const struct attribute_group it87_group_pwm = {
2699         .attrs = it87_attributes_pwm,
2700         .is_visible = it87_pwm_is_visible,
2701 };
2702
2703 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2704                                         struct attribute *attr, int index)
2705 {
2706         struct device *dev = container_of(kobj, struct device, kobj);
2707         struct it87_data *data = dev_get_drvdata(dev);
2708         int i = index / 11;     /* pwm index */
2709         int a = index % 11;     /* attribute index */
2710
2711         if (index >= 33) {      /* pwm 4..6 */
2712                 i = (index - 33) / 6 + 3;
2713                 a = (index - 33) % 6 + 4;
2714         }
2715
2716         if (!(data->has_pwm & BIT(i)))
2717                 return 0;
2718
2719         if (has_newer_autopwm(data)) {
2720                 if (a < 4)      /* no auto point pwm */
2721                         return 0;
2722                 if (a == 8)     /* no auto_point4 */
2723                         return 0;
2724         }
2725         if (has_old_autopwm(data)) {
2726                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2727                         return 0;
2728         }
2729
2730         return attr->mode;
2731 }
2732
2733 static struct attribute *it87_attributes_auto_pwm[] = {
2734         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2735         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2736         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2737         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2738         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2739         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2740         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2741         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2742         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2743         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2744         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2745
2746         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2747         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2748         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2749         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2750         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2751         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2752         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2753         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2754         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2755         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2756         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2757
2758         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2759         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2760         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2761         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2762         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2763         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2764         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2765         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2766         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2767         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2768         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2769
2770         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2771         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2772         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2773         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2774         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2775         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2776
2777         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2778         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2779         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2780         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2781         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2782         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2783
2784         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2785         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2786         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2787         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2788         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2789         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2790
2791         NULL,
2792 };
2793
2794 static const struct attribute_group it87_group_auto_pwm = {
2795         .attrs = it87_attributes_auto_pwm,
2796         .is_visible = it87_auto_pwm_is_visible,
2797 };
2798
2799 /* SuperIO detection - will change isa_address if a chip is found */
2800 static int __init it87_find(int sioaddr, unsigned short *address,
2801                             struct it87_sio_data *sio_data)
2802 {
2803         int err;
2804         u16 chip_type;
2805         const struct it87_devices *config;
2806
2807         err = superio_enter(sioaddr);
2808         if (err)
2809                 return err;
2810
2811         err = -ENODEV;
2812         chip_type = superio_inw(sioaddr, DEVID);
2813         if (chip_type == 0xffff)
2814                 goto exit;
2815
2816         if (force_id)
2817                 chip_type = force_id;
2818
2819         switch (chip_type) {
2820         case IT8705F_DEVID:
2821                 sio_data->type = it87;
2822                 break;
2823         case IT8712F_DEVID:
2824                 sio_data->type = it8712;
2825                 break;
2826         case IT8716F_DEVID:
2827         case IT8726F_DEVID:
2828                 sio_data->type = it8716;
2829                 break;
2830         case IT8718F_DEVID:
2831                 sio_data->type = it8718;
2832                 break;
2833         case IT8720F_DEVID:
2834                 sio_data->type = it8720;
2835                 break;
2836         case IT8721F_DEVID:
2837                 sio_data->type = it8721;
2838                 break;
2839         case IT8728F_DEVID:
2840                 sio_data->type = it8728;
2841                 break;
2842         case IT8732F_DEVID:
2843                 sio_data->type = it8732;
2844                 break;
2845         case IT8792E_DEVID:
2846                 sio_data->type = it8792;
2847                 break;
2848         case IT8771E_DEVID:
2849                 sio_data->type = it8771;
2850                 break;
2851         case IT8772E_DEVID:
2852                 sio_data->type = it8772;
2853                 break;
2854         case IT8781F_DEVID:
2855                 sio_data->type = it8781;
2856                 break;
2857         case IT8782F_DEVID:
2858                 sio_data->type = it8782;
2859                 break;
2860         case IT8783E_DEVID:
2861                 sio_data->type = it8783;
2862                 break;
2863         case IT8786E_DEVID:
2864                 sio_data->type = it8786;
2865                 break;
2866         case IT8790E_DEVID:
2867                 sio_data->type = it8790;
2868                 break;
2869         case IT8603E_DEVID:
2870         case IT8623E_DEVID:
2871                 sio_data->type = it8603;
2872                 break;
2873         case IT8607E_DEVID:
2874                 sio_data->type = it8607;
2875                 break;
2876         case IT8613E_DEVID:
2877                 sio_data->type = it8613;
2878                 break;
2879         case IT8620E_DEVID:
2880                 sio_data->type = it8620;
2881                 break;
2882         case IT8622E_DEVID:
2883                 sio_data->type = it8622;
2884                 break;
2885         case IT8625E_DEVID:
2886                 sio_data->type = it8625;
2887                 break;
2888         case IT8628E_DEVID:
2889                 sio_data->type = it8628;
2890                 break;
2891         case IT8655E_DEVID:
2892                 sio_data->type = it8655;
2893                 break;
2894         case IT8665E_DEVID:
2895                 sio_data->type = it8665;
2896                 break;
2897         case IT8686E_DEVID:
2898                 sio_data->type = it8686;
2899                 break;
2900         case 0xffff:    /* No device at all */
2901                 goto exit;
2902         default:
2903                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2904                 goto exit;
2905         }
2906
2907         superio_select(sioaddr, PME);
2908         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2909                 pr_info("Device not activated, skipping\n");
2910                 goto exit;
2911         }
2912
2913         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2914         if (*address == 0) {
2915                 pr_info("Base address not set, skipping\n");
2916                 goto exit;
2917         }
2918
2919         err = 0;
2920         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2921         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2922                 it87_devices[sio_data->type].suffix,
2923                 *address, sio_data->revision);
2924
2925         config = &it87_devices[sio_data->type];
2926
2927         /* in7 (VSB or VCCH5V) is always internal on some chips */
2928         if (has_in7_internal(config))
2929                 sio_data->internal |= BIT(1);
2930
2931         /* in8 (Vbat) is always internal */
2932         sio_data->internal |= BIT(2);
2933
2934         /* in9 (AVCC3), always internal if supported */
2935         if (has_avcc3(config))
2936                 sio_data->internal |= BIT(3); /* in9 is AVCC */
2937         else
2938                 sio_data->skip_in |= BIT(9);
2939
2940         if (!has_four_pwm(config))
2941                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2942         else if (!has_five_pwm(config))
2943                 sio_data->skip_pwm |= BIT(4) | BIT(5);
2944         else if (!has_six_pwm(config))
2945                 sio_data->skip_pwm |= BIT(5);
2946
2947         if (!has_vid(config))
2948                 sio_data->skip_vid = 1;
2949
2950         /* Read GPIO config and VID value from LDN 7 (GPIO) */
2951         if (sio_data->type == it87) {
2952                 /* The IT8705F has a different LD number for GPIO */
2953                 superio_select(sioaddr, 5);
2954                 sio_data->beep_pin = superio_inb(sioaddr,
2955                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2956         } else if (sio_data->type == it8783) {
2957                 int reg25, reg27, reg2a, reg2c, regef;
2958
2959                 superio_select(sioaddr, GPIO);
2960
2961                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2962                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2963                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2964                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2965                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2966
2967                 /* Check if fan3 is there or not */
2968                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2969                         sio_data->skip_fan |= BIT(2);
2970                 if ((reg25 & BIT(4)) ||
2971                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
2972                         sio_data->skip_pwm |= BIT(2);
2973
2974                 /* Check if fan2 is there or not */
2975                 if (reg27 & BIT(7))
2976                         sio_data->skip_fan |= BIT(1);
2977                 if (reg27 & BIT(3))
2978                         sio_data->skip_pwm |= BIT(1);
2979
2980                 /* VIN5 */
2981                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2982                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2983
2984                 /* VIN6 */
2985                 if (reg27 & BIT(1))
2986                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2987
2988                 /*
2989                  * VIN7
2990                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2991                  */
2992                 if (reg27 & BIT(2)) {
2993                         /*
2994                          * The data sheet is a bit unclear regarding the
2995                          * internal voltage divider for VCCH5V. It says
2996                          * "This bit enables and switches VIN7 (pin 91) to the
2997                          * internal voltage divider for VCCH5V".
2998                          * This is different to other chips, where the internal
2999                          * voltage divider would connect VIN7 to an internal
3000                          * voltage source. Maybe that is the case here as well.
3001                          *
3002                          * Since we don't know for sure, re-route it if that is
3003                          * not the case, and ask the user to report if the
3004                          * resulting voltage is sane.
3005                          */
3006                         if (!(reg2c & BIT(1))) {
3007                                 reg2c |= BIT(1);
3008                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3009                                              reg2c);
3010                                 pr_notice("Routing internal VCCH5V to in7.\n");
3011                         }
3012                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3013                         pr_notice("Please report if it displays a reasonable voltage.\n");
3014                 }
3015
3016                 if (reg2c & BIT(0))
3017                         sio_data->internal |= BIT(0);
3018                 if (reg2c & BIT(1))
3019                         sio_data->internal |= BIT(1);
3020
3021                 sio_data->beep_pin = superio_inb(sioaddr,
3022                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3023         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3024                 int reg27, reg29;
3025
3026                 superio_select(sioaddr, GPIO);
3027
3028                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3029
3030                 /* Check if fan3 is there or not */
3031                 if (reg27 & BIT(6))
3032                         sio_data->skip_pwm |= BIT(2);
3033                 if (reg27 & BIT(7))
3034                         sio_data->skip_fan |= BIT(2);
3035
3036                 /* Check if fan2 is there or not */
3037                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3038                 if (reg29 & BIT(1))
3039                         sio_data->skip_pwm |= BIT(1);
3040                 if (reg29 & BIT(2))
3041                         sio_data->skip_fan |= BIT(1);
3042
3043                 if (sio_data->type == it8603) {
3044                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3045                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3046                 }
3047
3048                 sio_data->beep_pin = superio_inb(sioaddr,
3049                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3050         } else if (sio_data->type == it8613) {
3051                 int reg27, reg29, reg2a;
3052
3053                 superio_select(sioaddr, GPIO);
3054
3055                 /* Check for pwm3, fan3, pwm5, fan5 */
3056                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3057                 if (reg27 & BIT(1))
3058                         sio_data->skip_fan |= BIT(4);
3059                 if (reg27 & BIT(3))
3060                         sio_data->skip_pwm |= BIT(4);
3061                 if (reg27 & BIT(6))
3062                         sio_data->skip_pwm |= BIT(2);
3063                 if (reg27 & BIT(7))
3064                         sio_data->skip_fan |= BIT(2);
3065
3066                 /* Check for pwm2, fan2 */
3067                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3068                 if (reg29 & BIT(1))
3069                         sio_data->skip_pwm |= BIT(1);
3070                 if (reg29 & BIT(2))
3071                         sio_data->skip_fan |= BIT(1);
3072
3073                 /* Check for pwm4, fan4 */
3074                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3075                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3076                         sio_data->skip_fan |= BIT(3);
3077                         sio_data->skip_pwm |= BIT(3);
3078                 }
3079
3080                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3081                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3082                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3083                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3084
3085                 sio_data->beep_pin = superio_inb(sioaddr,
3086                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3087         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3088                    sio_data->type == it8686) {
3089                 int reg;
3090
3091                 superio_select(sioaddr, GPIO);
3092
3093                 /* Check for pwm5 */
3094                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3095                 if (reg & BIT(6))
3096                         sio_data->skip_pwm |= BIT(4);
3097
3098                 /* Check for fan4, fan5 */
3099                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3100                 if (!(reg & BIT(5)))
3101                         sio_data->skip_fan |= BIT(3);
3102                 if (!(reg & BIT(4)))
3103                         sio_data->skip_fan |= BIT(4);
3104
3105                 /* Check for pwm3, fan3 */
3106                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3107                 if (reg & BIT(6))
3108                         sio_data->skip_pwm |= BIT(2);
3109                 if (reg & BIT(7))
3110                         sio_data->skip_fan |= BIT(2);
3111
3112                 /* Check for pwm4 */
3113                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3114                 if (reg & BIT(2))
3115                         sio_data->skip_pwm |= BIT(3);
3116
3117                 /* Check for pwm2, fan2 */
3118                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3119                 if (reg & BIT(1))
3120                         sio_data->skip_pwm |= BIT(1);
3121                 if (reg & BIT(2))
3122                         sio_data->skip_fan |= BIT(1);
3123                 /* Check for pwm6, fan6 */
3124                 if (!(reg & BIT(7))) {
3125                         sio_data->skip_pwm |= BIT(5);
3126                         sio_data->skip_fan |= BIT(5);
3127                 }
3128
3129                 /* Check if AVCC is on VIN3 */
3130                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3131                 if (reg & BIT(0)) {
3132                         /* For it8686, the bit just enables AVCC3 */
3133                         if (sio_data->type != it8686)
3134                                 sio_data->internal |= BIT(0);
3135                 } else {
3136                         sio_data->internal &= ~BIT(3);
3137                         sio_data->skip_in |= BIT(9);
3138                 }
3139
3140                 sio_data->beep_pin = superio_inb(sioaddr,
3141                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3142         } else if (sio_data->type == it8622) {
3143                 int reg;
3144
3145                 superio_select(sioaddr, GPIO);
3146
3147                 /* Check for pwm4, fan4 */
3148                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3149                 if (reg & BIT(6))
3150                         sio_data->skip_fan |= BIT(3);
3151                 if (reg & BIT(5))
3152                         sio_data->skip_pwm |= BIT(3);
3153
3154                 /* Check for pwm3, fan3, pwm5, fan5 */
3155                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3156                 if (reg & BIT(6))
3157                         sio_data->skip_pwm |= BIT(2);
3158                 if (reg & BIT(7))
3159                         sio_data->skip_fan |= BIT(2);
3160                 if (reg & BIT(3))
3161                         sio_data->skip_pwm |= BIT(4);
3162                 if (reg & BIT(1))
3163                         sio_data->skip_fan |= BIT(4);
3164
3165                 /* Check for pwm2, fan2 */
3166                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3167                 if (reg & BIT(1))
3168                         sio_data->skip_pwm |= BIT(1);
3169                 if (reg & BIT(2))
3170                         sio_data->skip_fan |= BIT(1);
3171
3172                 /* Check for AVCC */
3173                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3174                 if (!(reg & BIT(0)))
3175                         sio_data->skip_in |= BIT(9);
3176
3177                 sio_data->beep_pin = superio_inb(sioaddr,
3178                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3179         } else if (sio_data->type == it8732) {
3180                 int reg;
3181
3182                 superio_select(sioaddr, GPIO);
3183
3184                 /* Check for pwm2, fan2 */
3185                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3186                 if (reg & BIT(1))
3187                         sio_data->skip_pwm |= BIT(1);
3188                 if (reg & BIT(2))
3189                         sio_data->skip_fan |= BIT(1);
3190
3191                 /* Check for pwm3, fan3, fan4 */
3192                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3193                 if (reg & BIT(6))
3194                         sio_data->skip_pwm |= BIT(2);
3195                 if (reg & BIT(7))
3196                         sio_data->skip_fan |= BIT(2);
3197                 if (reg & BIT(5))
3198                         sio_data->skip_fan |= BIT(3);
3199
3200                 /* Check if AVCC is on VIN3 */
3201                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3202                 if (reg & BIT(0))
3203                         sio_data->internal |= BIT(0);
3204
3205                 sio_data->beep_pin = superio_inb(sioaddr,
3206                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3207         } else if (sio_data->type == it8655) {
3208                 int reg;
3209
3210                 superio_select(sioaddr, GPIO);
3211
3212                 /* Check for pwm2 */
3213                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3214                 if (reg & BIT(1))
3215                         sio_data->skip_pwm |= BIT(1);
3216
3217                 /* Check for fan2 */
3218                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3219                 if (reg & BIT(4))
3220                         sio_data->skip_fan |= BIT(1);
3221
3222                 /* Check for pwm3, fan3 */
3223                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3224                 if (reg & BIT(6))
3225                         sio_data->skip_pwm |= BIT(2);
3226                 if (reg & BIT(7))
3227                         sio_data->skip_fan |= BIT(2);
3228
3229                 sio_data->beep_pin = superio_inb(sioaddr,
3230                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3231         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3232                 int reg27, reg29, reg2d, regd3;
3233
3234                 superio_select(sioaddr, GPIO);
3235
3236                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3237                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3238                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3239                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3240
3241                 /* Check for pwm2, fan2 */
3242                 if (reg29 & BIT(1))
3243                         sio_data->skip_pwm |= BIT(1);
3244                 if (reg2d & BIT(4))
3245                         sio_data->skip_fan |= BIT(1);
3246
3247                 /* Check for pwm3, fan3 */
3248                 if (reg27 & BIT(6))
3249                         sio_data->skip_pwm |= BIT(2);
3250                 if (reg27 & BIT(7))
3251                         sio_data->skip_fan |= BIT(2);
3252
3253                 /* Check for pwm4, fan4, pwm5, fan5 */
3254                 if (sio_data->type == it8625) {
3255                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3256
3257                         if (reg25 & BIT(6))
3258                                 sio_data->skip_fan |= BIT(3);
3259                         if (reg25 & BIT(5))
3260                                 sio_data->skip_pwm |= BIT(3);
3261                         if (reg27 & BIT(3))
3262                                 sio_data->skip_pwm |= BIT(4);
3263                         if (reg27 & BIT(1))
3264                                 sio_data->skip_fan |= BIT(4);
3265                 } else {
3266                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3267
3268                         if (regd3 & BIT(2))
3269                                 sio_data->skip_pwm |= BIT(3);
3270                         if (regd3 & BIT(3))
3271                                 sio_data->skip_fan |= BIT(3);
3272                         if (reg26 & BIT(5))
3273                                 sio_data->skip_pwm |= BIT(4);
3274                         if (!(reg26 & BIT(4)))
3275                                 sio_data->skip_fan |= BIT(4);
3276                 }
3277
3278                 /* Check for pwm6, fan6 */
3279                 if (regd3 & BIT(0))
3280                         sio_data->skip_pwm |= BIT(5);
3281                 if (regd3 & BIT(1))
3282                         sio_data->skip_fan |= BIT(5);
3283
3284                 sio_data->beep_pin = superio_inb(sioaddr,
3285                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3286         } else {
3287                 int reg;
3288                 bool uart6;
3289
3290                 superio_select(sioaddr, GPIO);
3291
3292                 /* Check for fan4, fan5 */
3293                 if (has_five_fans(config)) {
3294                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3295                         switch (sio_data->type) {
3296                         case it8718:
3297                                 if (reg & BIT(5))
3298                                         sio_data->skip_fan |= BIT(3);
3299                                 if (reg & BIT(4))
3300                                         sio_data->skip_fan |= BIT(4);
3301                                 break;
3302                         case it8720:
3303                         case it8721:
3304                         case it8728:
3305                                 if (!(reg & BIT(5)))
3306                                         sio_data->skip_fan |= BIT(3);
3307                                 if (!(reg & BIT(4)))
3308                                         sio_data->skip_fan |= BIT(4);
3309                                 break;
3310                         default:
3311                                 break;
3312                         }
3313                 }
3314
3315                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3316                 if (!sio_data->skip_vid) {
3317                         /* We need at least 4 VID pins */
3318                         if (reg & 0x0f) {
3319                                 pr_info("VID is disabled (pins used for GPIO)\n");
3320                                 sio_data->skip_vid = 1;
3321                         }
3322                 }
3323
3324                 /* Check if fan3 is there or not */
3325                 if (reg & BIT(6))
3326                         sio_data->skip_pwm |= BIT(2);
3327                 if (reg & BIT(7))
3328                         sio_data->skip_fan |= BIT(2);
3329
3330                 /* Check if fan2 is there or not */
3331                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3332                 if (reg & BIT(1))
3333                         sio_data->skip_pwm |= BIT(1);
3334                 if (reg & BIT(2))
3335                         sio_data->skip_fan |= BIT(1);
3336
3337                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3338                     !(sio_data->skip_vid))
3339                         sio_data->vid_value = superio_inb(sioaddr,
3340                                                           IT87_SIO_VID_REG);
3341
3342                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3343
3344                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3345
3346                 /*
3347                  * The IT8720F has no VIN7 pin, so VCCH should always be
3348                  * routed internally to VIN7 with an internal divider.
3349                  * Curiously, there still is a configuration bit to control
3350                  * this, which means it can be set incorrectly. And even
3351                  * more curiously, many boards out there are improperly
3352                  * configured, even though the IT8720F datasheet claims
3353                  * that the internal routing of VCCH to VIN7 is the default
3354                  * setting. So we force the internal routing in this case.
3355                  *
3356                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3357                  * If UART6 is enabled, re-route VIN7 to the internal divider
3358                  * if that is not already the case.
3359                  */
3360                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3361                         reg |= BIT(1);
3362                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3363                         pr_notice("Routing internal VCCH to in7\n");
3364                 }
3365                 if (reg & BIT(0))
3366                         sio_data->internal |= BIT(0);
3367                 if (reg & BIT(1))
3368                         sio_data->internal |= BIT(1);
3369
3370                 /*
3371                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3372                  * While VIN7 can be routed to the internal voltage divider,
3373                  * VIN5 and VIN6 are not available if UART6 is enabled.
3374                  *
3375                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3376                  * is the temperature source. Since we can not read the
3377                  * temperature source here, skip_temp is preliminary.
3378                  */
3379                 if (uart6) {
3380                         sio_data->skip_in |= BIT(5) | BIT(6);
3381                         sio_data->skip_temp |= BIT(2);
3382                 }
3383
3384                 sio_data->beep_pin = superio_inb(sioaddr,
3385                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3386         }
3387         if (sio_data->beep_pin)
3388                 pr_info("Beeping is supported\n");
3389
3390 exit:
3391         superio_exit(sioaddr);
3392         return err;
3393 }
3394
3395 static void it87_init_regs(struct platform_device *pdev)
3396 {
3397         struct it87_data *data = platform_get_drvdata(pdev);
3398
3399         /* Initialize chip specific register pointers */
3400         switch (data->type) {
3401         case it8628:
3402         case it8686:
3403                 data->REG_FAN = IT87_REG_FAN;
3404                 data->REG_FANX = IT87_REG_FANX;
3405                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3406                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3407                 data->REG_PWM = IT87_REG_PWM;
3408                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3409                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3410                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3411                 break;
3412         case it8625:
3413         case it8655:
3414         case it8665:
3415                 data->REG_FAN = IT87_REG_FAN_8665;
3416                 data->REG_FANX = IT87_REG_FANX_8665;
3417                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3418                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3419                 data->REG_PWM = IT87_REG_PWM_8665;
3420                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3421                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3422                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3423                 break;
3424         case it8622:
3425                 data->REG_FAN = IT87_REG_FAN;
3426                 data->REG_FANX = IT87_REG_FANX;
3427                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3428                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3429                 data->REG_PWM = IT87_REG_PWM_8665;
3430                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3431                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3432                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3433                 break;
3434         case it8613:
3435                 data->REG_FAN = IT87_REG_FAN;
3436                 data->REG_FANX = IT87_REG_FANX;
3437                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3438                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3439                 data->REG_PWM = IT87_REG_PWM_8665;
3440                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3441                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3442                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3443                 break;
3444         default:
3445                 data->REG_FAN = IT87_REG_FAN;
3446                 data->REG_FANX = IT87_REG_FANX;
3447                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3448                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3449                 data->REG_PWM = IT87_REG_PWM;
3450                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3451                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3452                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3453                 break;
3454         }
3455 }
3456
3457 /* Called when we have found a new IT87. */
3458 static void it87_init_device(struct platform_device *pdev)
3459 {
3460         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3461         struct it87_data *data = platform_get_drvdata(pdev);
3462         int tmp, i;
3463         u8 mask;
3464
3465         /*
3466          * For each PWM channel:
3467          * - If it is in automatic mode, setting to manual mode should set
3468          *   the fan to full speed by default.
3469          * - If it is in manual mode, we need a mapping to temperature
3470          *   channels to use when later setting to automatic mode later.
3471          *   Use a 1:1 mapping by default (we are clueless.)
3472          * In both cases, the value can (and should) be changed by the user
3473          * prior to switching to a different mode.
3474          * Note that this is no longer needed for the IT8721F and later, as
3475          * these have separate registers for the temperature mapping and the
3476          * manual duty cycle.
3477          */
3478         for (i = 0; i < NUM_AUTO_PWM; i++) {
3479                 data->pwm_temp_map[i] = i;
3480                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3481                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3482         }
3483
3484         /*
3485          * Some chips seem to have default value 0xff for all limit
3486          * registers. For low voltage limits it makes no sense and triggers
3487          * alarms, so change to 0 instead. For high temperature limits, it
3488          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3489          * but is still confusing, so change to 127 degrees C.
3490          */
3491         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3492                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3493                 if (tmp == 0xff)
3494                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3495         }
3496         for (i = 0; i < data->num_temp_limit; i++) {
3497                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3498                 if (tmp == 0xff)
3499                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3500         }
3501
3502         /*
3503          * Temperature channels are not forcibly enabled, as they can be
3504          * set to two different sensor types and we can't guess which one
3505          * is correct for a given system. These channels can be enabled at
3506          * run-time through the temp{1-3}_type sysfs accessors if needed.
3507          */
3508
3509         /* Check if voltage monitors are reset manually or by some reason */
3510         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3511         if ((tmp & 0xff) == 0) {
3512                 /* Enable all voltage monitors */
3513                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3514         }
3515
3516         /* Check if tachometers are reset manually or by some reason */
3517         mask = 0x70 & ~(sio_data->skip_fan << 4);
3518         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3519         if ((data->fan_main_ctrl & mask) == 0) {
3520                 /* Enable all fan tachometers */
3521                 data->fan_main_ctrl |= mask;
3522                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3523                                  data->fan_main_ctrl);
3524         }
3525         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3526
3527         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3528
3529         /* Set tachometers to 16-bit mode if needed */
3530         if (has_fan16_config(data)) {
3531                 if (~tmp & 0x07 & data->has_fan) {
3532                         dev_dbg(&pdev->dev,
3533                                 "Setting fan1-3 to 16-bit mode\n");
3534                         it87_write_value(data, IT87_REG_FAN_16BIT,
3535                                          tmp | 0x07);
3536                 }
3537         }
3538
3539         /* Check for additional fans */
3540         if (has_four_fans(data) && (tmp & BIT(4)))
3541                 data->has_fan |= BIT(3); /* fan4 enabled */
3542         if (has_five_fans(data) && (tmp & BIT(5)))
3543                 data->has_fan |= BIT(4); /* fan5 enabled */
3544         if (has_six_fans(data)) {
3545                 switch (data->type) {
3546                 case it8620:
3547                 case it8628:
3548                 case it8686:
3549                         if (tmp & BIT(2))
3550                                 data->has_fan |= BIT(5); /* fan6 enabled */
3551                         break;
3552                 case it8625:
3553                 case it8665:
3554                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3555                         if (tmp & BIT(3))
3556                                 data->has_fan |= BIT(5); /* fan6 enabled */
3557                         break;
3558                 default:
3559                         break;
3560                 }
3561         }
3562
3563         /* Fan input pins may be used for alternative functions */
3564         data->has_fan &= ~sio_data->skip_fan;
3565
3566         /* Check if pwm6 is enabled */
3567         if (has_six_pwm(data)) {
3568                 switch (data->type) {
3569                 case it8620:
3570                 case it8686:
3571                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3572                         if (!(tmp & BIT(3)))
3573                                 sio_data->skip_pwm |= BIT(5);
3574                         break;
3575                 default:
3576                         break;
3577                 }
3578         }
3579
3580         /* Start monitoring */
3581         it87_write_value(data, IT87_REG_CONFIG,
3582                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3583                          | (update_vbat ? 0x41 : 0x01));
3584 }
3585
3586 /* Return 1 if and only if the PWM interface is safe to use */
3587 static int it87_check_pwm(struct device *dev)
3588 {
3589         struct it87_data *data = dev_get_drvdata(dev);
3590         /*
3591          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3592          * and polarity set to active low is sign that this is the case so we
3593          * disable pwm control to protect the user.
3594          */
3595         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3596
3597         if ((tmp & 0x87) == 0) {
3598                 if (fix_pwm_polarity) {
3599                         /*
3600                          * The user asks us to attempt a chip reconfiguration.
3601                          * This means switching to active high polarity and
3602                          * inverting all fan speed values.
3603                          */
3604                         int i;
3605                         u8 pwm[3];
3606
3607                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3608                                 pwm[i] = it87_read_value(data,
3609                                                          data->REG_PWM[i]);
3610
3611                         /*
3612                          * If any fan is in automatic pwm mode, the polarity
3613                          * might be correct, as suspicious as it seems, so we
3614                          * better don't change anything (but still disable the
3615                          * PWM interface).
3616                          */
3617                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3618                                 dev_info(dev,
3619                                          "Reconfiguring PWM to active high polarity\n");
3620                                 it87_write_value(data, IT87_REG_FAN_CTL,
3621                                                  tmp | 0x87);
3622                                 for (i = 0; i < 3; i++)
3623                                         it87_write_value(data,
3624                                                          data->REG_PWM[i],
3625                                                          0x7f & ~pwm[i]);
3626                                 return 1;
3627                         }
3628
3629                         dev_info(dev,
3630                                  "PWM configuration is too broken to be fixed\n");
3631                 }
3632
3633                 dev_info(dev,
3634                          "Detected broken BIOS defaults, disabling PWM interface\n");
3635                 return 0;
3636         } else if (fix_pwm_polarity) {
3637                 dev_info(dev,
3638                          "PWM configuration looks sane, won't touch\n");
3639         }
3640
3641         return 1;
3642 }
3643
3644 static int it87_probe(struct platform_device *pdev)
3645 {
3646         struct it87_data *data;
3647         struct resource *res;
3648         struct device *dev = &pdev->dev;
3649         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3650         int enable_pwm_interface;
3651         struct device *hwmon_dev;
3652
3653         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3654         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3655                                  DRVNAME)) {
3656                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3657                         (unsigned long)res->start,
3658                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3659                 return -EBUSY;
3660         }
3661
3662         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3663         if (!data)
3664                 return -ENOMEM;
3665
3666         data->addr = res->start;
3667         data->type = sio_data->type;
3668         data->features = it87_devices[sio_data->type].features;
3669         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3670         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3671         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3672         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3673         data->bank = 0xff;
3674
3675         /*
3676          * IT8705F Datasheet 0.4.1, 3h == Version G.
3677          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3678          * These are the first revisions with 16-bit tachometer support.
3679          */
3680         switch (data->type) {
3681         case it87:
3682                 if (sio_data->revision >= 0x03) {
3683                         data->features &= ~FEAT_OLD_AUTOPWM;
3684                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3685                 }
3686                 break;
3687         case it8712:
3688                 if (sio_data->revision >= 0x08) {
3689                         data->features &= ~FEAT_OLD_AUTOPWM;
3690                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3691                                           FEAT_FIVE_FANS;
3692                 }
3693                 break;
3694         default:
3695                 break;
3696         }
3697
3698         /* Now, we do the remaining detection. */
3699         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3700             it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3701                 return -ENODEV;
3702
3703         platform_set_drvdata(pdev, data);
3704
3705         mutex_init(&data->update_lock);
3706
3707         /* Initialize register pointers */
3708         it87_init_regs(pdev);
3709
3710         /* Check PWM configuration */
3711         enable_pwm_interface = it87_check_pwm(dev);
3712
3713         /* Starting with IT8721F, we handle scaling of internal voltages */
3714         if (has_scaling(data)) {
3715                 if (sio_data->internal & BIT(0))
3716                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3717                 if (sio_data->internal & BIT(1))
3718                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3719                 if (sio_data->internal & BIT(2))
3720                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3721                 if (sio_data->internal & BIT(3))
3722                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3723         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3724                    sio_data->type == it8783) {
3725                 if (sio_data->internal & BIT(0))
3726                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3727                 if (sio_data->internal & BIT(1))
3728                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3729         }
3730
3731         data->has_temp = 0x07;
3732         if (sio_data->skip_temp & BIT(2)) {
3733                 if (sio_data->type == it8782 &&
3734                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3735                         data->has_temp &= ~BIT(2);
3736         }
3737
3738         data->in_internal = sio_data->internal;
3739         data->has_in = 0x3ff & ~sio_data->skip_in;
3740
3741         if (has_six_temp(data)) {
3742                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3743
3744                 /* Check for additional temperature sensors */
3745                 if ((reg & 0x03) >= 0x02)
3746                         data->has_temp |= BIT(3);
3747                 if (((reg >> 2) & 0x03) >= 0x02)
3748                         data->has_temp |= BIT(4);
3749                 if (((reg >> 4) & 0x03) >= 0x02)
3750                         data->has_temp |= BIT(5);
3751
3752                 /* Check for additional voltage sensors */
3753                 if ((reg & 0x03) == 0x01)
3754                         data->has_in |= BIT(10);
3755                 if (((reg >> 2) & 0x03) == 0x01)
3756                         data->has_in |= BIT(11);
3757                 if (((reg >> 4) & 0x03) == 0x01)
3758                         data->has_in |= BIT(12);
3759         }
3760
3761         data->has_beep = !!sio_data->beep_pin;
3762
3763         /* Initialize the IT87 chip */
3764         it87_init_device(pdev);
3765
3766         if (!sio_data->skip_vid) {
3767                 data->has_vid = true;
3768                 data->vrm = vid_which_vrm();
3769                 /* VID reading from Super-I/O config space if available */
3770                 data->vid = sio_data->vid_value;
3771         }
3772
3773         /* Prepare for sysfs hooks */
3774         data->groups[0] = &it87_group;
3775         data->groups[1] = &it87_group_in;
3776         data->groups[2] = &it87_group_temp;
3777         data->groups[3] = &it87_group_fan;
3778
3779         if (enable_pwm_interface) {
3780                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3781                 data->has_pwm &= ~sio_data->skip_pwm;
3782
3783                 data->groups[4] = &it87_group_pwm;
3784                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3785                         data->groups[5] = &it87_group_auto_pwm;
3786         }
3787
3788         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3789                                         it87_devices[sio_data->type].name,
3790                                         data, data->groups);
3791         return PTR_ERR_OR_ZERO(hwmon_dev);
3792 }
3793
3794 static struct platform_driver it87_driver = {
3795         .driver = {
3796                 .name   = DRVNAME,
3797         },
3798         .probe  = it87_probe,
3799 };
3800
3801 static int __init it87_device_add(int index, unsigned short address,
3802                                   const struct it87_sio_data *sio_data)
3803 {
3804         struct platform_device *pdev;
3805         struct resource res = {
3806                 .start  = address + IT87_EC_OFFSET,
3807                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3808                 .name   = DRVNAME,
3809                 .flags  = IORESOURCE_IO,
3810         };
3811         int err;
3812
3813         err = acpi_check_resource_conflict(&res);
3814         if (err)
3815                 return err;
3816
3817         pdev = platform_device_alloc(DRVNAME, address);
3818         if (!pdev)
3819                 return -ENOMEM;
3820
3821         err = platform_device_add_resources(pdev, &res, 1);
3822         if (err) {
3823                 pr_err("Device resource addition failed (%d)\n", err);
3824                 goto exit_device_put;
3825         }
3826
3827         err = platform_device_add_data(pdev, sio_data,
3828                                        sizeof(struct it87_sio_data));
3829         if (err) {
3830                 pr_err("Platform data allocation failed\n");
3831                 goto exit_device_put;
3832         }
3833
3834         err = platform_device_add(pdev);
3835         if (err) {
3836                 pr_err("Device addition failed (%d)\n", err);
3837                 goto exit_device_put;
3838         }
3839
3840         it87_pdev[index] = pdev;
3841         return 0;
3842
3843 exit_device_put:
3844         platform_device_put(pdev);
3845         return err;
3846 }
3847
3848 struct it87_dmi_data {
3849         bool sio4e_broken;      /* SIO accesses @ 0x4e are broken       */
3850         char *sio_mutex;        /* SIO ACPI mutex                       */
3851         u8 skip_pwm;            /* pwm channels to skip for this board  */
3852 };
3853
3854 /*
3855  * On Gigabyte AB350 and AX370 boards, accesses to the Super-IO chip
3856  * at address 0x4e/0x4f can result in a system hang.
3857  * Accesses to address 0x2e/0x2f need to be mutex protected.
3858  */
3859 static struct it87_dmi_data gigabyte_ab350_gaming = {
3860         .sio4e_broken = true,
3861         .sio_mutex = "\\_SB.PCI0.SBRG.SIO1.MUT0",
3862 };
3863
3864 /*
3865  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3866  * connected to a fan, but to something else. One user
3867  * has reported instant system power-off when changing
3868  * the PWM2 duty cycle, so we disable it.
3869  * I use the board name string as the trigger in case
3870  * the same board is ever used in other systems.
3871  */
3872 static struct it87_dmi_data nvidia_fn68pt = {
3873         .skip_pwm = BIT(1),
3874 };
3875
3876 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3877         {
3878                 .matches = {
3879                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3880                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming-CF"),
3881                 },
3882                 .driver_data = &gigabyte_ab350_gaming,
3883         },
3884         {
3885                 .matches = {
3886                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3887                         DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming 3-CF"),
3888                 },
3889                 .driver_data = &gigabyte_ab350_gaming,
3890         },
3891         {
3892                 .matches = {
3893                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3894                         DMI_MATCH(DMI_BOARD_NAME, "AB350M-D3H-CF"),
3895                 },
3896                 .driver_data = &gigabyte_ab350_gaming,
3897         },
3898         {
3899                 .matches = {
3900                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3901                         DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming K7"),
3902                 },
3903                 .driver_data = &gigabyte_ab350_gaming,
3904         },
3905         {
3906                 .matches = {
3907                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3908                         DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming 5"),
3909                 },
3910                 .driver_data = &gigabyte_ab350_gaming,
3911         },
3912         {
3913                 .matches = {
3914                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3915                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3916                 },
3917                 .driver_data = &nvidia_fn68pt,
3918         },
3919         { }
3920 };
3921
3922 static int __init sm_it87_init(void)
3923 {
3924         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3925         struct it87_dmi_data *dmi_data = NULL;
3926         int sioaddr[2] = { REG_2E, REG_4E };
3927         struct it87_sio_data sio_data;
3928         unsigned short isa_address;
3929         bool found = false;
3930         int i, err;
3931
3932         if (dmi)
3933                 dmi_data = dmi->driver_data;
3934
3935         if (dmi_data) {
3936                 it87_sio4e_broken = dmi_data->sio4e_broken;
3937 #ifdef __IT87_USE_ACPI_MUTEX
3938                 if (dmi_data->sio_mutex) {
3939                         static acpi_status status;
3940
3941                         status = acpi_get_handle(NULL, dmi_data->sio_mutex,
3942                                                  &it87_acpi_sio_handle);
3943                         if (ACPI_SUCCESS(status)) {
3944                                 it87_acpi_sio_mutex = dmi_data->sio_mutex;
3945                                 pr_debug("Found ACPI SIO mutex %s\n",
3946                                          dmi_data->sio_mutex);
3947                         } else {
3948                                 pr_warn("ACPI SIO mutex %s not found\n",
3949                                         dmi_data->sio_mutex);
3950                         }
3951                 }
3952 #endif /* __IT87_USE_ACPI_MUTEX */
3953         }
3954
3955         err = platform_driver_register(&it87_driver);
3956         if (err)
3957                 return err;
3958
3959         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3960                 /*
3961                  * Accessing the second Super-IO chip can result in board
3962                  * hangs. Disable until we figure out what is going on.
3963                  */
3964                 if (blacklist && it87_sio4e_broken && sioaddr[i] == 0x4e)
3965                         continue;
3966                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3967                 isa_address = 0;
3968                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3969                 if (err || isa_address == 0)
3970                         continue;
3971
3972                 if (dmi_data)
3973                         sio_data.skip_pwm |= dmi_data->skip_pwm;
3974                 err = it87_device_add(i, isa_address, &sio_data);
3975                 if (err)
3976                         goto exit_dev_unregister;
3977                 found = true;
3978         }
3979
3980         if (!found) {
3981                 err = -ENODEV;
3982                 goto exit_unregister;
3983         }
3984         return 0;
3985
3986 exit_dev_unregister:
3987         /* NULL check handled by platform_device_unregister */
3988         platform_device_unregister(it87_pdev[0]);
3989 exit_unregister:
3990         platform_driver_unregister(&it87_driver);
3991         return err;
3992 }
3993
3994 static void __exit sm_it87_exit(void)
3995 {
3996         /* NULL check handled by platform_device_unregister */
3997         platform_device_unregister(it87_pdev[1]);
3998         platform_device_unregister(it87_pdev[0]);
3999         platform_driver_unregister(&it87_driver);
4000 }
4001
4002 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4003 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4004 module_param(update_vbat, bool, 0);
4005 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4006 module_param(fix_pwm_polarity, bool, 0);
4007 MODULE_PARM_DESC(fix_pwm_polarity,
4008                  "Force PWM polarity to active high (DANGEROUS)");
4009 MODULE_LICENSE("GPL");
4010
4011 module_init(sm_it87_init);
4012 module_exit(sm_it87_exit);