git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77
  78 #define DRVNAME "it87"
  79
  80 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  81              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  82              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  83              it8655, it8665, it8686 };
  84
  85 static unsigned short force_id;
  86 module_param(force_id, ushort, 0);
  87 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  88
  89 static bool ignore_resource_conflict;
  90 module_param(ignore_resource_conflict, bool, 0);
  91 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
  92
  93 static struct platform_device *it87_pdev[2];
  94
  95 #define REG_2E  0x2e    /* The register to read/write */
  96 #define REG_4E  0x4e    /* Secondary register to read/write */
  97
  98 #define DEV     0x07    /* Register: Logical device select */
  99 #define PME     0x04    /* The device with the fan registers in it */
 100
 101 /* The device with the IT8718F/IT8720F VID value in it */
 102 #define GPIO    0x07
 103
 104 #define DEVID   0x20    /* Register: Device ID */
 105 #define DEVREV  0x22    /* Register: Device Revision */
 106
 107 static inline void __superio_enter(int ioreg)
 108 {
 109         outb(0x87, ioreg);
 110         outb(0x01, ioreg);
 111         outb(0x55, ioreg);
 112         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 113 }
 114
 115 static inline int superio_inb(int ioreg, int reg)
 116 {
 117         int val;
 118
 119         outb(reg, ioreg);
 120         val = inb(ioreg + 1);
 121
 122         return val;
 123 }
 124
 125 static inline void superio_outb(int ioreg, int reg, int val)
 126 {
 127         outb(reg, ioreg);
 128         outb(val, ioreg + 1);
 129 }
 130
 131 static int superio_inw(int ioreg, int reg)
 132 {
 133         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 134 }
 135
 136 static inline void superio_select(int ioreg, int ldn)
 137 {
 138         outb(DEV, ioreg);
 139         outb(ldn, ioreg + 1);
 140 }
 141
 142 static inline int superio_enter(int ioreg)
 143 {
 144         /*
 145          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 146          */
 147         if (!request_muxed_region(ioreg, 2, DRVNAME))
 148                 goto error;
 149
 150         __superio_enter(ioreg);
 151         return 0;
 152
 153 error:
 154         return -EBUSY;
 155 }
 156
 157 static inline void superio_exit(int ioreg, bool doexit)
 158 {
 159         if (doexit) {
 160                 outb(0x02, ioreg);
 161                 outb(0x02, ioreg + 1);
 162         }
 163         release_region(ioreg, 2);
 164 }
 165
 166 /* Logical device 4 registers */
 167 #define IT8712F_DEVID 0x8712
 168 #define IT8705F_DEVID 0x8705
 169 #define IT8716F_DEVID 0x8716
 170 #define IT8718F_DEVID 0x8718
 171 #define IT8720F_DEVID 0x8720
 172 #define IT8721F_DEVID 0x8721
 173 #define IT8726F_DEVID 0x8726
 174 #define IT8728F_DEVID 0x8728
 175 #define IT8732F_DEVID 0x8732
 176 #define IT8792E_DEVID 0x8733
 177 #define IT8771E_DEVID 0x8771
 178 #define IT8772E_DEVID 0x8772
 179 #define IT8781F_DEVID 0x8781
 180 #define IT8782F_DEVID 0x8782
 181 #define IT8783E_DEVID 0x8783
 182 #define IT8786E_DEVID 0x8786
 183 #define IT8790E_DEVID 0x8790
 184 #define IT8603E_DEVID 0x8603
 185 #define IT8607E_DEVID 0x8607
 186 #define IT8613E_DEVID 0x8613
 187 #define IT8620E_DEVID 0x8620
 188 #define IT8622E_DEVID 0x8622
 189 #define IT8623E_DEVID 0x8623
 190 #define IT8625E_DEVID 0x8625
 191 #define IT8628E_DEVID 0x8628
 192 #define IT8655E_DEVID 0x8655
 193 #define IT8665E_DEVID 0x8665
 194 #define IT8686E_DEVID 0x8686
 195 #define IT87_ACT_REG  0x30
 196 #define IT87_BASE_REG 0x60
 197
 198 /* Logical device 7 registers (IT8712F and later) */
 199 #define IT87_SIO_GPIO1_REG      0x25
 200 #define IT87_SIO_GPIO2_REG      0x26
 201 #define IT87_SIO_GPIO3_REG      0x27
 202 #define IT87_SIO_GPIO4_REG      0x28
 203 #define IT87_SIO_GPIO5_REG      0x29
 204 #define IT87_SIO_GPIO9_REG      0xd3
 205 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 206 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 207 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 208 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 209 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 210 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 211
 212 /* Update battery voltage after every reading if true */
 213 static bool update_vbat;
 214
 215 /* Not all BIOSes properly configure the PWM registers */
 216 static bool fix_pwm_polarity;
 217
 218 /* Many IT87 constants specified below */
 219
 220 /* Length of ISA address segment */
 221 #define IT87_EXTENT 8
 222
 223 /* Length of ISA address segment for Environmental Controller */
 224 #define IT87_EC_EXTENT 2
 225
 226 /* Offset of EC registers from ISA base address */
 227 #define IT87_EC_OFFSET 5
 228
 229 /* Where are the ISA address/data registers relative to the EC base address */
 230 #define IT87_ADDR_REG_OFFSET 0
 231 #define IT87_DATA_REG_OFFSET 1
 232
 233 /*----- The IT87 registers -----*/
 234
 235 #define IT87_REG_CONFIG        0x00
 236
 237 #define IT87_REG_ALARM1        0x01
 238 #define IT87_REG_ALARM2        0x02
 239 #define IT87_REG_ALARM3        0x03
 240
 241 #define IT87_REG_BANK           0x06
 242
 243 /*
 244  * The IT8718F and IT8720F have the VID value in a different register, in
 245  * Super-I/O configuration space.
 246  */
 247 #define IT87_REG_VID           0x0a
 248 /*
 249  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 250  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 251  * mode.
 252  */
 253 #define IT87_REG_FAN_DIV       0x0b
 254 #define IT87_REG_FAN_16BIT     0x0c
 255
 256 /*
 257  * Monitors:
 258  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 259  * - up to 6 temp (1 to 6)
 260  * - up to 6 fan (1 to 6)
 261  */
 262
 263 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 264 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 265 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 266 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 267
 268 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 269 static const u8 IT87_REG_FAN_MIN_8665[] =
 270                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 271 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 272 static const u8 IT87_REG_FANX_MIN_8665[] =
 273                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 274
 275 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 276
 277 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 278
 279 #define IT87_REG_FAN_MAIN_CTRL 0x13
 280 #define IT87_REG_FAN_CTL       0x14
 281
 282 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 283 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 284
 285 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 286
 287 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 288                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 289
 290 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 291
 292 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 293 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 294
 295 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 296 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 297
 298 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 299                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 300 static const u8 IT87_REG_TEMP_LOW_8686[] =
 301                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 302
 303 #define IT87_REG_VIN_ENABLE    0x50
 304 #define IT87_REG_TEMP_ENABLE   0x51
 305 #define IT87_REG_TEMP_EXTRA    0x55
 306 #define IT87_REG_BEEP_ENABLE   0x5c
 307
 308 #define IT87_REG_CHIPID        0x58
 309
 310 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 311
 312 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 313 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 314
 315 #define IT87_REG_TEMP456_ENABLE 0x77
 316
 317 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 318 #define IT87_REG_TEMP_SRC2      0x23d
 319
 320 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 321 #define NUM_VIN_LIMIT           8
 322 #define NUM_TEMP                6
 323 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 324 #define NUM_FAN_DIV             3
 325 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 326 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 327
 328 struct it87_devices {
 329         const char *name;
 330         const char * const suffix;
 331         u32 features;
 332         u8 num_temp_limit;
 333         u8 num_temp_offset;
 334         u8 num_temp_map;        /* Number of temperature sources for pwm */
 335         u8 peci_mask;
 336         u8 old_peci_mask;
 337 };
 338
 339 #define FEAT_12MV_ADC           BIT(0)
 340 #define FEAT_NEWER_AUTOPWM      BIT(1)
 341 #define FEAT_OLD_AUTOPWM        BIT(2)
 342 #define FEAT_16BIT_FANS         BIT(3)
 343 #define FEAT_TEMP_PECI          BIT(5)
 344 #define FEAT_TEMP_OLD_PECI      BIT(6)
 345 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 346 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 347 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 348 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 349 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 350 #define FEAT_10_9MV_ADC         BIT(12)
 351 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 352 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 353 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 354 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 355 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 356 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 357 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 358 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 359 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 360 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 361 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 362 #define FEAT_11MV_ADC           BIT(24)
 363 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 364
 365 static const struct it87_devices it87_devices[] = {
 366         [it87] = {
 367                 .name = "it87",
 368                 .suffix = "F",
 369                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 370                                                 /* may need to overwrite */
 371                 .num_temp_limit = 3,
 372                 .num_temp_offset = 0,
 373                 .num_temp_map = 3,
 374         },
 375         [it8712] = {
 376                 .name = "it8712",
 377                 .suffix = "F",
 378                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 379                                                 /* may need to overwrite */
 380                 .num_temp_limit = 3,
 381                 .num_temp_offset = 0,
 382                 .num_temp_map = 3,
 383         },
 384         [it8716] = {
 385                 .name = "it8716",
 386                 .suffix = "F",
 387                 .features = FEAT_16BIT_FANS | FEAT_VID
 388                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 389                   | FEAT_FANCTL_ONOFF,
 390                 .num_temp_limit = 3,
 391                 .num_temp_offset = 3,
 392                 .num_temp_map = 3,
 393         },
 394         [it8718] = {
 395                 .name = "it8718",
 396                 .suffix = "F",
 397                 .features = FEAT_16BIT_FANS | FEAT_VID
 398                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 399                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 400                 .num_temp_limit = 3,
 401                 .num_temp_offset = 3,
 402                 .num_temp_map = 3,
 403                 .old_peci_mask = 0x4,
 404         },
 405         [it8720] = {
 406                 .name = "it8720",
 407                 .suffix = "F",
 408                 .features = FEAT_16BIT_FANS | FEAT_VID
 409                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 410                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 411                 .num_temp_limit = 3,
 412                 .num_temp_offset = 3,
 413                 .num_temp_map = 3,
 414                 .old_peci_mask = 0x4,
 415         },
 416         [it8721] = {
 417                 .name = "it8721",
 418                 .suffix = "F",
 419                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 420                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 421                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 422                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 423                 .num_temp_limit = 3,
 424                 .num_temp_offset = 3,
 425                 .num_temp_map = 3,
 426                 .peci_mask = 0x05,
 427                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 428         },
 429         [it8728] = {
 430                 .name = "it8728",
 431                 .suffix = "F",
 432                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 433                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 434                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 435                   | FEAT_FANCTL_ONOFF,
 436                 .num_temp_limit = 6,
 437                 .num_temp_offset = 3,
 438                 .num_temp_map = 3,
 439                 .peci_mask = 0x07,
 440         },
 441         [it8732] = {
 442                 .name = "it8732",
 443                 .suffix = "F",
 444                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 445                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 446                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 447                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 448                 .num_temp_limit = 3,
 449                 .num_temp_offset = 3,
 450                 .num_temp_map = 3,
 451                 .peci_mask = 0x07,
 452                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 453         },
 454         [it8771] = {
 455                 .name = "it8771",
 456                 .suffix = "E",
 457                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 458                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 459                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 460                                 /* PECI: guesswork */
 461                                 /* 12mV ADC (OHM) */
 462                                 /* 16 bit fans (OHM) */
 463                                 /* three fans, always 16 bit (guesswork) */
 464                 .num_temp_limit = 3,
 465                 .num_temp_offset = 3,
 466                 .num_temp_map = 3,
 467                 .peci_mask = 0x07,
 468         },
 469         [it8772] = {
 470                 .name = "it8772",
 471                 .suffix = "E",
 472                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 473                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 474                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 475                                 /* PECI (coreboot) */
 476                                 /* 12mV ADC (HWSensors4, OHM) */
 477                                 /* 16 bit fans (HWSensors4, OHM) */
 478                                 /* three fans, always 16 bit (datasheet) */
 479                 .num_temp_limit = 3,
 480                 .num_temp_offset = 3,
 481                 .num_temp_map = 3,
 482                 .peci_mask = 0x07,
 483         },
 484         [it8781] = {
 485                 .name = "it8781",
 486                 .suffix = "F",
 487                 .features = FEAT_16BIT_FANS
 488                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 489                   | FEAT_FANCTL_ONOFF,
 490                 .num_temp_limit = 3,
 491                 .num_temp_offset = 3,
 492                 .num_temp_map = 3,
 493                 .old_peci_mask = 0x4,
 494         },
 495         [it8782] = {
 496                 .name = "it8782",
 497                 .suffix = "F",
 498                 .features = FEAT_16BIT_FANS
 499                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 500                   | FEAT_FANCTL_ONOFF,
 501                 .num_temp_limit = 3,
 502                 .num_temp_offset = 3,
 503                 .num_temp_map = 3,
 504                 .old_peci_mask = 0x4,
 505         },
 506         [it8783] = {
 507                 .name = "it8783",
 508                 .suffix = "E/F",
 509                 .features = FEAT_16BIT_FANS
 510                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 511                   | FEAT_FANCTL_ONOFF,
 512                 .num_temp_limit = 3,
 513                 .num_temp_offset = 3,
 514                 .num_temp_map = 3,
 515                 .old_peci_mask = 0x4,
 516         },
 517         [it8786] = {
 518                 .name = "it8786",
 519                 .suffix = "E",
 520                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 521                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 522                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 523                 .num_temp_limit = 3,
 524                 .num_temp_offset = 3,
 525                 .num_temp_map = 3,
 526                 .peci_mask = 0x07,
 527         },
 528         [it8790] = {
 529                 .name = "it8790",
 530                 .suffix = "E",
 531                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 532                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 533                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 534                 .num_temp_limit = 3,
 535                 .num_temp_offset = 3,
 536                 .num_temp_map = 3,
 537                 .peci_mask = 0x07,
 538         },
 539         [it8792] = {
 540                 .name = "it8792",
 541                 .suffix = "E",
 542                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 543                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 544                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 545                 .num_temp_limit = 3,
 546                 .num_temp_offset = 3,
 547                 .num_temp_map = 3,
 548                 .peci_mask = 0x07,
 549         },
 550         [it8603] = {
 551                 .name = "it8603",
 552                 .suffix = "E",
 553                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 554                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 555                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 556                 .num_temp_limit = 3,
 557                 .num_temp_offset = 3,
 558                 .num_temp_map = 4,
 559                 .peci_mask = 0x07,
 560         },
 561         [it8607] = {
 562                 .name = "it8607",
 563                 .suffix = "E",
 564                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 565                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 566                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 567                   | FEAT_FANCTL_ONOFF,
 568                 .num_temp_limit = 3,
 569                 .num_temp_offset = 3,
 570                 .num_temp_map = 6,
 571                 .peci_mask = 0x07,
 572         },
 573         [it8613] = {
 574                 .name = "it8613",
 575                 .suffix = "E",
 576                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 577                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 578                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 579                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 580                 .num_temp_limit = 6,
 581                 .num_temp_offset = 6,
 582                 .num_temp_map = 6,
 583                 .peci_mask = 0x07,
 584         },
 585         [it8620] = {
 586                 .name = "it8620",
 587                 .suffix = "E",
 588                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 589                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 590                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 591                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 592                   | FEAT_FANCTL_ONOFF,
 593                 .num_temp_limit = 3,
 594                 .num_temp_offset = 3,
 595                 .num_temp_map = 3,
 596                 .peci_mask = 0x07,
 597         },
 598         [it8622] = {
 599                 .name = "it8622",
 600                 .suffix = "E",
 601                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 602                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 603                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 604                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 605                 .num_temp_limit = 3,
 606                 .num_temp_offset = 3,
 607                 .num_temp_map = 4,
 608                 .peci_mask = 0x07,
 609         },
 610         [it8625] = {
 611                 .name = "it8625",
 612                 .suffix = "E",
 613                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 614                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 615                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 616                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 617                 .num_temp_limit = 6,
 618                 .num_temp_offset = 6,
 619                 .num_temp_map = 6,
 620         },
 621         [it8628] = {
 622                 .name = "it8628",
 623                 .suffix = "E",
 624                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 625                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 626                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 627                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 628                   | FEAT_FANCTL_ONOFF,
 629                 .num_temp_limit = 6,
 630                 .num_temp_offset = 3,
 631                 .num_temp_map = 3,
 632                 .peci_mask = 0x07,
 633         },
 634         [it8655] = {
 635                 .name = "it8655",
 636                 .suffix = "E",
 637                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 638                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 639                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 640                 .num_temp_limit = 6,
 641                 .num_temp_offset = 6,
 642                 .num_temp_map = 6,
 643         },
 644         [it8665] = {
 645                 .name = "it8665",
 646                 .suffix = "E",
 647                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 648                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 649                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 650                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 651                 .num_temp_limit = 6,
 652                 .num_temp_offset = 6,
 653                 .num_temp_map = 6,
 654         },
 655         [it8686] = {
 656                 .name = "it8686",
 657                 .suffix = "E",
 658                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 659                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 660                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 661                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 662                 .num_temp_limit = 6,
 663                 .num_temp_offset = 6,
 664                 .num_temp_map = 7,
 665         },
 666 };
 667
 668 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 669 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 670 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 671 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 672 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 673 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 674                                  ((data)->peci_mask & BIT(nr)))
 675 #define has_temp_old_peci(data, nr) \
 676                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 677                                  ((data)->old_peci_mask & BIT(nr)))
 678 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 679 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 680                                                      FEAT_SIX_FANS))
 681 #define has_vid(data)           ((data)->features & FEAT_VID)
 682 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 683 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 684 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 685 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 686                                                      | FEAT_SIX_PWM))
 687 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 688 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 689 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 690 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 691 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 692                                                      FEAT_FIVE_FANS | \
 693                                                      FEAT_SIX_FANS))
 694 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 695                                                      FEAT_FIVE_PWM \
 696                                                      | FEAT_SIX_PWM))
 697 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 698 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 699 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 700 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 701 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 702
 703 struct it87_sio_data {
 704         enum chips type;
 705         /* Values read from Super-I/O config space */
 706         u8 revision;
 707         u8 vid_value;
 708         u8 beep_pin;
 709         u8 internal;    /* Internal sensors can be labeled */
 710         /* Features skipped based on config or DMI */
 711         u16 skip_in;
 712         u8 skip_vid;
 713         u8 skip_fan;
 714         u8 skip_pwm;
 715         u8 skip_temp;
 716 };
 717
 718 /*
 719  * For each registered chip, we need to keep some data in memory.
 720  * The structure is dynamically allocated.
 721  */
 722 struct it87_data {
 723         const struct attribute_group *groups[7];
 724         enum chips type;
 725         u32 features;
 726         u8 bank;
 727         u8 peci_mask;
 728         u8 old_peci_mask;
 729
 730         const u8 *REG_FAN;
 731         const u8 *REG_FANX;
 732         const u8 *REG_FAN_MIN;
 733         const u8 *REG_FANX_MIN;
 734
 735         const u8 *REG_PWM;
 736
 737         const u8 *REG_TEMP_OFFSET;
 738         const u8 *REG_TEMP_LOW;
 739         const u8 *REG_TEMP_HIGH;
 740
 741         unsigned short addr;
 742         const char *name;
 743         struct mutex update_lock;
 744         char valid;             /* !=0 if following fields are valid */
 745         unsigned long last_updated;     /* In jiffies */
 746
 747         u16 in_scaled;          /* Internal voltage sensors are scaled */
 748         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 749         u16 has_in;             /* Bitfield, voltage sensors enabled */
 750         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 751         u8 has_fan;             /* Bitfield, fans enabled */
 752         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 753         u8 has_temp;            /* Bitfield, temp sensors enabled */
 754         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 755         u8 num_temp_limit;      /* Number of temperature limit registers */
 756         u8 num_temp_offset;     /* Number of temperature offset registers */
 757         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 758         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 759         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 760         bool has_vid;           /* True if VID supported */
 761         u8 vid;                 /* Register encoding, combined */
 762         u8 vrm;
 763         u32 alarms;             /* Register encoding, combined */
 764         bool has_beep;          /* true if beep supported */
 765         u8 beeps;               /* Register encoding */
 766         u8 fan_main_ctrl;       /* Register value */
 767         u8 fan_ctl;             /* Register value */
 768
 769         /*
 770          * The following 3 arrays correspond to the same registers up to
 771          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 772          * 7, and we want to preserve settings on mode changes, so we have
 773          * to track all values separately.
 774          * Starting with the IT8721F, the manual PWM duty cycles are stored
 775          * in separate registers (8-bit values), so the separate tracking
 776          * is no longer needed, but it is still done to keep the driver
 777          * simple.
 778          */
 779         u8 has_pwm;             /* Bitfield, pwm control enabled */
 780         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 781         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 782         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 783         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 784         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 785         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 786
 787         /* Automatic fan speed control registers */
 788         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 789         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 790 };
 791
 792 static int adc_lsb(const struct it87_data *data, int nr)
 793 {
 794         int lsb;
 795
 796         if (has_12mv_adc(data))
 797                 lsb = 120;
 798         else if (has_10_9mv_adc(data))
 799                 lsb = 109;
 800         else if (has_11mv_adc(data))
 801                 lsb = 110;
 802         else
 803                 lsb = 160;
 804         if (data->in_scaled & BIT(nr))
 805                 lsb <<= 1;
 806         return lsb;
 807 }
 808
 809 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 810 {
 811         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 812         return clamp_val(val, 0, 255);
 813 }
 814
 815 static int in_from_reg(const struct it87_data *data, int nr, int val)
 816 {
 817         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 818 }
 819
 820 static inline u8 FAN_TO_REG(long rpm, int div)
 821 {
 822         if (rpm == 0)
 823                 return 255;
 824         rpm = clamp_val(rpm, 1, 1000000);
 825         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 826 }
 827
 828 static inline u16 FAN16_TO_REG(long rpm)
 829 {
 830         if (rpm == 0)
 831                 return 0xffff;
 832         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 833 }
 834
 835 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 836                                 1350000 / ((val) * (div)))
 837 /* The divider is fixed to 2 in 16-bit mode */
 838 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 839                              1350000 / ((val) * 2))
 840
 841 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 842                                     ((val) + 500) / 1000), -128, 127))
 843 #define TEMP_FROM_REG(val) ((val) * 1000)
 844
 845 static u8 pwm_to_reg(const struct it87_data *data, long val)
 846 {
 847         if (has_newer_autopwm(data))
 848                 return val;
 849         else
 850                 return val >> 1;
 851 }
 852
 853 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 854 {
 855         if (has_newer_autopwm(data))
 856                 return reg;
 857         else
 858                 return (reg & 0x7f) << 1;
 859 }
 860
 861 static int DIV_TO_REG(int val)
 862 {
 863         int answer = 0;
 864
 865         while (answer < 7 && (val >>= 1))
 866                 answer++;
 867         return answer;
 868 }
 869
 870 #define DIV_FROM_REG(val) BIT(val)
 871
 872 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 873 {
 874         u8 map;
 875
 876         map  = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 877         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 878                 map = 0;
 879
 880         return map;
 881 }
 882
 883 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 884 {
 885         u8 ctrl = data->pwm_ctrl[nr];
 886
 887         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 888                (map << data->pwm_temp_map_shift);
 889 }
 890
 891 /*
 892  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 893  * depending on the chip type, to calculate the actual PWM frequency.
 894  *
 895  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 896  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 897  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 898  * sometimes just one. It is unknown if this is a datasheet error or real,
 899  * so this is ignored for now.
 900  */
 901 static const unsigned int pwm_freq[8] = {
 902         48000000,
 903         24000000,
 904         12000000,
 905         8000000,
 906         6000000,
 907         3000000,
 908         1500000,
 909         750000,
 910 };
 911
 912 static int _it87_read_value(struct it87_data *data, u8 reg)
 913 {
 914         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 915         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 916 }
 917
 918 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 919 {
 920         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 921         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 922 }
 923
 924 static void it87_set_bank(struct it87_data *data, u8 bank)
 925 {
 926         if (has_bank_sel(data) && bank != data->bank) {
 927                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 928
 929                 breg &= 0x1f;
 930                 breg |= (bank << 5);
 931                 data->bank = bank;
 932                 _it87_write_value(data, IT87_REG_BANK, breg);
 933         }
 934 }
 935
 936 /*
 937  * Must be called with data->update_lock held, except during initialization.
 938  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 939  * would slow down the IT87 access and should not be necessary.
 940  */
 941 static int it87_read_value(struct it87_data *data, u16 reg)
 942 {
 943         it87_set_bank(data, reg >> 8);
 944         return _it87_read_value(data, reg & 0xff);
 945 }
 946
 947 /*
 948  * Must be called with data->update_lock held, except during initialization.
 949  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 950  * would slow down the IT87 access and should not be necessary.
 951  */
 952 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
 953 {
 954         it87_set_bank(data, reg >> 8);
 955         _it87_write_value(data, reg & 0xff, value);
 956 }
 957
 958 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 959 {
 960         u8 ctrl;
 961
 962         ctrl = it87_read_value(data, data->REG_PWM[nr]);
 963         data->pwm_ctrl[nr] = ctrl;
 964         if (has_newer_autopwm(data)) {
 965                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
 966                 data->pwm_duty[nr] = it87_read_value(data,
 967                                                      IT87_REG_PWM_DUTY[nr]);
 968         } else {
 969                 if (ctrl & 0x80)        /* Automatic mode */
 970                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
 971                 else                            /* Manual mode */
 972                         data->pwm_duty[nr] = ctrl & 0x7f;
 973         }
 974
 975         if (has_old_autopwm(data)) {
 976                 int i;
 977
 978                 for (i = 0; i < 5 ; i++)
 979                         data->auto_temp[nr][i] = it87_read_value(data,
 980                                                 IT87_REG_AUTO_TEMP(nr, i));
 981                 for (i = 0; i < 3 ; i++)
 982                         data->auto_pwm[nr][i] = it87_read_value(data,
 983                                                 IT87_REG_AUTO_PWM(nr, i));
 984         } else if (has_newer_autopwm(data)) {
 985                 int i;
 986
 987                 /*
 988                  * 0: temperature hysteresis (base + 5)
 989                  * 1: fan off temperature (base + 0)
 990                  * 2: fan start temperature (base + 1)
 991                  * 3: fan max temperature (base + 2)
 992                  */
 993                 data->auto_temp[nr][0] =
 994                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
 995
 996                 for (i = 0; i < 3 ; i++)
 997                         data->auto_temp[nr][i + 1] =
 998                                 it87_read_value(data,
 999                                                 IT87_REG_AUTO_TEMP(nr, i));
1000                 /*
1001                  * 0: start pwm value (base + 3)
1002                  * 1: pwm slope (base + 4, 1/8th pwm)
1003                  */
1004                 data->auto_pwm[nr][0] =
1005                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
1006                 data->auto_pwm[nr][1] =
1007                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
1008         }
1009 }
1010
1011 static struct it87_data *it87_update_device(struct device *dev)
1012 {
1013         struct it87_data *data = dev_get_drvdata(dev);
1014         int i;
1015
1016         mutex_lock(&data->update_lock);
1017
1018         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1019             !data->valid) {
1020                 if (update_vbat) {
1021                         /*
1022                          * Cleared after each update, so reenable.  Value
1023                          * returned by this read will be previous value
1024                          */
1025                         it87_write_value(data, IT87_REG_CONFIG,
1026                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1027                 }
1028                 for (i = 0; i < NUM_VIN; i++) {
1029                         if (!(data->has_in & BIT(i)))
1030                                 continue;
1031
1032                         data->in[i][0] =
1033                                 it87_read_value(data, IT87_REG_VIN[i]);
1034
1035                         /* VBAT and AVCC don't have limit registers */
1036                         if (i >= NUM_VIN_LIMIT)
1037                                 continue;
1038
1039                         data->in[i][1] =
1040                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
1041                         data->in[i][2] =
1042                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
1043                 }
1044
1045                 for (i = 0; i < NUM_FAN; i++) {
1046                         /* Skip disabled fans */
1047                         if (!(data->has_fan & BIT(i)))
1048                                 continue;
1049
1050                         data->fan[i][1] =
1051                                 it87_read_value(data, data->REG_FAN_MIN[i]);
1052                         data->fan[i][0] = it87_read_value(data,
1053                                        data->REG_FAN[i]);
1054                         /* Add high byte if in 16-bit mode */
1055                         if (has_16bit_fans(data)) {
1056                                 data->fan[i][0] |= it87_read_value(data,
1057                                                 data->REG_FANX[i]) << 8;
1058                                 data->fan[i][1] |= it87_read_value(data,
1059                                                 data->REG_FANX_MIN[i]) << 8;
1060                         }
1061                 }
1062                 for (i = 0; i < NUM_TEMP; i++) {
1063                         if (!(data->has_temp & BIT(i)))
1064                                 continue;
1065                         data->temp[i][0] =
1066                                 it87_read_value(data, IT87_REG_TEMP(i));
1067
1068                         if (i >= data->num_temp_limit)
1069                                 continue;
1070
1071                         if (i < data->num_temp_offset)
1072                                 data->temp[i][3] =
1073                                   it87_read_value(data,
1074                                                   data->REG_TEMP_OFFSET[i]);
1075
1076                         data->temp[i][1] =
1077                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1078                         data->temp[i][2] =
1079                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1080                 }
1081
1082                 /* Newer chips don't have clock dividers */
1083                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1084                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1085                         data->fan_div[0] = i & 0x07;
1086                         data->fan_div[1] = (i >> 3) & 0x07;
1087                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1088                 }
1089
1090                 data->alarms =
1091                         it87_read_value(data, IT87_REG_ALARM1) |
1092                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1093                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1094                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1095
1096                 data->fan_main_ctrl = it87_read_value(data,
1097                                 IT87_REG_FAN_MAIN_CTRL);
1098                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1099                 for (i = 0; i < NUM_PWM; i++) {
1100                         if (!(data->has_pwm & BIT(i)))
1101                                 continue;
1102                         it87_update_pwm_ctrl(data, i);
1103                 }
1104
1105                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1106                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1107                 /*
1108                  * The IT8705F does not have VID capability.
1109                  * The IT8718F and later don't use IT87_REG_VID for the
1110                  * same purpose.
1111                  */
1112                 if (data->type == it8712 || data->type == it8716) {
1113                         data->vid = it87_read_value(data, IT87_REG_VID);
1114                         /*
1115                          * The older IT8712F revisions had only 5 VID pins,
1116                          * but we assume it is always safe to read 6 bits.
1117                          */
1118                         data->vid &= 0x3f;
1119                 }
1120                 data->last_updated = jiffies;
1121                 data->valid = 1;
1122         }
1123
1124         mutex_unlock(&data->update_lock);
1125
1126         return data;
1127 }
1128
1129 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1130                        char *buf)
1131 {
1132         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1133         struct it87_data *data = it87_update_device(dev);
1134         int index = sattr->index;
1135         int nr = sattr->nr;
1136
1137         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1138 }
1139
1140 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1141                       const char *buf, size_t count)
1142 {
1143         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1144         struct it87_data *data = dev_get_drvdata(dev);
1145         int index = sattr->index;
1146         int nr = sattr->nr;
1147         unsigned long val;
1148
1149         if (kstrtoul(buf, 10, &val) < 0)
1150                 return -EINVAL;
1151
1152         mutex_lock(&data->update_lock);
1153         data->in[nr][index] = in_to_reg(data, nr, val);
1154         it87_write_value(data,
1155                          index == 1 ? IT87_REG_VIN_MIN(nr)
1156                                     : IT87_REG_VIN_MAX(nr),
1157                          data->in[nr][index]);
1158         mutex_unlock(&data->update_lock);
1159         return count;
1160 }
1161
1162 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1163 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1164                             0, 1);
1165 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1166                             0, 2);
1167
1168 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1169 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1170                             1, 1);
1171 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1172                             1, 2);
1173
1174 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1175 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1176                             2, 1);
1177 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1178                             2, 2);
1179
1180 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1181 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1182                             3, 1);
1183 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1184                             3, 2);
1185
1186 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1187 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1188                             4, 1);
1189 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1190                             4, 2);
1191
1192 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1193 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1194                             5, 1);
1195 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1196                             5, 2);
1197
1198 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1199 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1200                             6, 1);
1201 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1202                             6, 2);
1203
1204 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1205 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1206                             7, 1);
1207 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1208                             7, 2);
1209
1210 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1211 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1212 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1213 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1214 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1215
1216 /* Up to 6 temperatures */
1217 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1218                          char *buf)
1219 {
1220         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1221         int nr = sattr->nr;
1222         int index = sattr->index;
1223         struct it87_data *data = it87_update_device(dev);
1224
1225         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1226 }
1227
1228 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1229                         const char *buf, size_t count)
1230 {
1231         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1232         int nr = sattr->nr;
1233         int index = sattr->index;
1234         struct it87_data *data = dev_get_drvdata(dev);
1235         long val;
1236         u8 reg, regval;
1237
1238         if (kstrtol(buf, 10, &val) < 0)
1239                 return -EINVAL;
1240
1241         mutex_lock(&data->update_lock);
1242
1243         switch (index) {
1244         default:
1245         case 1:
1246                 reg = data->REG_TEMP_LOW[nr];
1247                 break;
1248         case 2:
1249                 reg = data->REG_TEMP_HIGH[nr];
1250                 break;
1251         case 3:
1252                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1253                 if (!(regval & 0x80)) {
1254                         regval |= 0x80;
1255                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1256                 }
1257                 data->valid = 0;
1258                 reg = data->REG_TEMP_OFFSET[nr];
1259                 break;
1260         }
1261
1262         data->temp[nr][index] = TEMP_TO_REG(val);
1263         it87_write_value(data, reg, data->temp[nr][index]);
1264         mutex_unlock(&data->update_lock);
1265         return count;
1266 }
1267
1268 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1269 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1270                             0, 1);
1271 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1272                             0, 2);
1273 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1274                             set_temp, 0, 3);
1275 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1276 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1277                             1, 1);
1278 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1279                             1, 2);
1280 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1281                             set_temp, 1, 3);
1282 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1283 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1284                             2, 1);
1285 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1286                             2, 2);
1287 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1288                             set_temp, 2, 3);
1289 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1290 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1291                             3, 1);
1292 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1293                             3, 2);
1294 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1295                             set_temp, 3, 3);
1296 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1297 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1298                             4, 1);
1299 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1300                             4, 2);
1301 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1302                             set_temp, 4, 3);
1303 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1304 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1305                             5, 1);
1306 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1307                             5, 2);
1308 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1309                             set_temp, 5, 3);
1310
1311 static int get_temp_type(struct it87_data *data, int index)
1312 {
1313         u8 reg, extra;
1314         int type = 0;
1315
1316         if (has_bank_sel(data)) {
1317                 int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
1318                 u8 src1, src2;
1319
1320                 src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
1321                 src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
1322
1323                 switch (data->type) {
1324                 case it8686:
1325                         switch (src1) {
1326                         case 0:
1327                                 if (index >= 3)
1328                                         return 4;
1329                                 break;
1330                         case 1:
1331                                 if (index == 1 || index == 2 ||
1332                                           index == 4 || index == 5)
1333                                         return 6;
1334                                 break;
1335                         case 2:
1336                                 if (index == 2 || index == 6)
1337                                         return 5;
1338                                 break;
1339                         default:
1340                                 break;
1341                         }
1342                         break;
1343                 case it8625:
1344                         if (index < 3)
1345                                 break;
1346                 case it8655:
1347                 case it8665:
1348                         if (src1 < 3) {
1349                                 index = src1;
1350                                 break;
1351                         }
1352                         switch(src1) {
1353                         case 3:
1354                                 type = (src2 & BIT(index)) ? 6 : 5;
1355                                 break;
1356                         case 4 ... 8:
1357                                 type = (src2 & BIT(index)) ? 4 : 6;
1358                                 break;
1359                         case 9:
1360                                 type = (src2 & BIT(index)) ? 5 : 0;
1361                                 break;
1362                         default:
1363                                 break;
1364                         }
1365                         return type;
1366                 default:
1367                         return 0;
1368                 }
1369         }
1370         if (index >= 3)
1371                 return 0;
1372
1373         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1374         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1375
1376         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1377             (has_temp_old_peci(data, index) && (extra & 0x80)))
1378                 type = 6;               /* Intel PECI */
1379         if (reg & BIT(index))
1380                 type = 3;               /* thermal diode */
1381         else if (reg & BIT(index + 3))
1382                 type = 4;               /* thermistor */
1383
1384         return type;
1385 }
1386
1387 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1388                               char *buf)
1389 {
1390         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1391         struct it87_data *data = it87_update_device(dev);
1392         int type = get_temp_type(data, sensor_attr->index);
1393
1394         return sprintf(buf, "%d\n", type);
1395 }
1396
1397 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1398                              const char *buf, size_t count)
1399 {
1400         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1401         int nr = sensor_attr->index;
1402
1403         struct it87_data *data = dev_get_drvdata(dev);
1404         long val;
1405         u8 reg, extra;
1406
1407         if (kstrtol(buf, 10, &val) < 0)
1408                 return -EINVAL;
1409
1410         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1411         reg &= ~(1 << nr);
1412         reg &= ~(8 << nr);
1413         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1414                 reg &= 0x3f;
1415         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1416         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1417                 extra &= 0x7f;
1418         if (val == 2) { /* backwards compatibility */
1419                 dev_warn(dev,
1420                          "Sensor type 2 is deprecated, please use 4 instead\n");
1421                 val = 4;
1422         }
1423         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1424         if (val == 3)
1425                 reg |= 1 << nr;
1426         else if (val == 4)
1427                 reg |= 8 << nr;
1428         else if (has_temp_peci(data, nr) && val == 6)
1429                 reg |= (nr + 1) << 6;
1430         else if (has_temp_old_peci(data, nr) && val == 6)
1431                 extra |= 0x80;
1432         else if (val != 0)
1433                 return -EINVAL;
1434
1435         mutex_lock(&data->update_lock);
1436         data->sensor = reg;
1437         data->extra = extra;
1438         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1439         if (has_temp_old_peci(data, nr))
1440                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1441         data->valid = 0;        /* Force cache refresh */
1442         mutex_unlock(&data->update_lock);
1443         return count;
1444 }
1445
1446 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1447                           set_temp_type, 0);
1448 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1449                           set_temp_type, 1);
1450 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1451                           set_temp_type, 2);
1452 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1453                           set_temp_type, 3);
1454 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1455                           set_temp_type, 4);
1456 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1457                           set_temp_type, 5);
1458
1459 /* 6 Fans */
1460
1461 static int pwm_mode(const struct it87_data *data, int nr)
1462 {
1463         if (has_fanctl_onoff(data) && nr < 3 &&
1464             !(data->fan_main_ctrl & BIT(nr)))
1465                 return 0;                               /* Full speed */
1466         if (data->pwm_ctrl[nr] & 0x80)
1467                 return 2;                               /* Automatic mode */
1468         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1469             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1470                 return 0;                       /* Full speed */
1471
1472         return 1;                               /* Manual mode */
1473 }
1474
1475 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1476                         char *buf)
1477 {
1478         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1479         int nr = sattr->nr;
1480         int index = sattr->index;
1481         int speed;
1482         struct it87_data *data = it87_update_device(dev);
1483
1484         speed = has_16bit_fans(data) ?
1485                 FAN16_FROM_REG(data->fan[nr][index]) :
1486                 FAN_FROM_REG(data->fan[nr][index],
1487                              DIV_FROM_REG(data->fan_div[nr]));
1488         return sprintf(buf, "%d\n", speed);
1489 }
1490
1491 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1492                             char *buf)
1493 {
1494         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1495         struct it87_data *data = it87_update_device(dev);
1496         int nr = sensor_attr->index;
1497
1498         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1499 }
1500
1501 static ssize_t show_pwm_enable(struct device *dev,
1502                                struct device_attribute *attr, char *buf)
1503 {
1504         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1505         struct it87_data *data = it87_update_device(dev);
1506         int nr = sensor_attr->index;
1507
1508         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1509 }
1510
1511 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1512                         char *buf)
1513 {
1514         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1515         struct it87_data *data = it87_update_device(dev);
1516         int nr = sensor_attr->index;
1517
1518         return sprintf(buf, "%d\n",
1519                        pwm_from_reg(data, data->pwm_duty[nr]));
1520 }
1521
1522 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1523                              char *buf)
1524 {
1525         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1526         struct it87_data *data = it87_update_device(dev);
1527         int nr = sensor_attr->index;
1528         unsigned int freq;
1529         int index;
1530
1531         if (has_pwm_freq2(data) && nr == 1)
1532                 index = (data->extra >> 4) & 0x07;
1533         else
1534                 index = (data->fan_ctl >> 4) & 0x07;
1535
1536         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1537
1538         return sprintf(buf, "%u\n", freq);
1539 }
1540
1541 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1542                        const char *buf, size_t count)
1543 {
1544         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1545         int nr = sattr->nr;
1546         int index = sattr->index;
1547
1548         struct it87_data *data = dev_get_drvdata(dev);
1549         long val;
1550         u8 reg;
1551
1552         if (kstrtol(buf, 10, &val) < 0)
1553                 return -EINVAL;
1554
1555         mutex_lock(&data->update_lock);
1556
1557         if (has_16bit_fans(data)) {
1558                 data->fan[nr][index] = FAN16_TO_REG(val);
1559                 it87_write_value(data, data->REG_FAN_MIN[nr],
1560                                  data->fan[nr][index] & 0xff);
1561                 it87_write_value(data, data->REG_FANX_MIN[nr],
1562                                  data->fan[nr][index] >> 8);
1563         } else {
1564                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1565                 switch (nr) {
1566                 case 0:
1567                         data->fan_div[nr] = reg & 0x07;
1568                         break;
1569                 case 1:
1570                         data->fan_div[nr] = (reg >> 3) & 0x07;
1571                         break;
1572                 case 2:
1573                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1574                         break;
1575                 }
1576                 data->fan[nr][index] =
1577                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1578                 it87_write_value(data, data->REG_FAN_MIN[nr],
1579                                  data->fan[nr][index]);
1580         }
1581
1582         mutex_unlock(&data->update_lock);
1583         return count;
1584 }
1585
1586 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1587                            const char *buf, size_t count)
1588 {
1589         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1590         struct it87_data *data = dev_get_drvdata(dev);
1591         int nr = sensor_attr->index;
1592         unsigned long val;
1593         int min;
1594         u8 old;
1595
1596         if (kstrtoul(buf, 10, &val) < 0)
1597                 return -EINVAL;
1598
1599         mutex_lock(&data->update_lock);
1600         old = it87_read_value(data, IT87_REG_FAN_DIV);
1601
1602         /* Save fan min limit */
1603         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1604
1605         switch (nr) {
1606         case 0:
1607         case 1:
1608                 data->fan_div[nr] = DIV_TO_REG(val);
1609                 break;
1610         case 2:
1611                 if (val < 8)
1612                         data->fan_div[nr] = 1;
1613                 else
1614                         data->fan_div[nr] = 3;
1615         }
1616         val = old & 0x80;
1617         val |= (data->fan_div[0] & 0x07);
1618         val |= (data->fan_div[1] & 0x07) << 3;
1619         if (data->fan_div[2] == 3)
1620                 val |= 0x1 << 6;
1621         it87_write_value(data, IT87_REG_FAN_DIV, val);
1622
1623         /* Restore fan min limit */
1624         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1625         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1626
1627         mutex_unlock(&data->update_lock);
1628         return count;
1629 }
1630
1631 /* Returns 0 if OK, -EINVAL otherwise */
1632 static int check_trip_points(struct device *dev, int nr)
1633 {
1634         const struct it87_data *data = dev_get_drvdata(dev);
1635         int i, err = 0;
1636
1637         if (has_old_autopwm(data)) {
1638                 for (i = 0; i < 3; i++) {
1639                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1640                                 err = -EINVAL;
1641                 }
1642                 for (i = 0; i < 2; i++) {
1643                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1644                                 err = -EINVAL;
1645                 }
1646         } else if (has_newer_autopwm(data)) {
1647                 for (i = 1; i < 3; i++) {
1648                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1649                                 err = -EINVAL;
1650                 }
1651         }
1652
1653         if (err) {
1654                 dev_err(dev,
1655                         "Inconsistent trip points, not switching to automatic mode\n");
1656                 dev_err(dev, "Adjust the trip points and try again\n");
1657         }
1658         return err;
1659 }
1660
1661 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1662                               const char *buf, size_t count)
1663 {
1664         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1665         struct it87_data *data = dev_get_drvdata(dev);
1666         int nr = sensor_attr->index;
1667         long val;
1668
1669         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1670                 return -EINVAL;
1671
1672         /* Check trip points before switching to automatic mode */
1673         if (val == 2) {
1674                 if (check_trip_points(dev, nr) < 0)
1675                         return -EINVAL;
1676         }
1677
1678         mutex_lock(&data->update_lock);
1679         it87_update_pwm_ctrl(data, nr);
1680
1681         if (val == 0) {
1682                 if (nr < 3 && has_fanctl_onoff(data)) {
1683                         int tmp;
1684                         /* make sure the fan is on when in on/off mode */
1685                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1686                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1687                         /* set on/off mode */
1688                         data->fan_main_ctrl &= ~BIT(nr);
1689                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1690                                          data->fan_main_ctrl);
1691                 } else {
1692                         u8 ctrl;
1693
1694                         /* No on/off mode, set maximum pwm value */
1695                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1696                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1697                                          data->pwm_duty[nr]);
1698                         /* and set manual mode */
1699                         if (has_newer_autopwm(data)) {
1700                                 ctrl = temp_map_to_reg(data, nr,
1701                                                        data->pwm_temp_map[nr]);
1702                                 ctrl &= 0x7f;
1703                         } else {
1704                                 ctrl = data->pwm_duty[nr];
1705                         }
1706                         data->pwm_ctrl[nr] = ctrl;
1707                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1708                 }
1709         } else {
1710                 u8 ctrl;
1711
1712                 if (has_newer_autopwm(data)) {
1713                         ctrl = temp_map_to_reg(data, nr,
1714                                                data->pwm_temp_map[nr]);
1715                         if (val == 1)
1716                                 ctrl &= 0x7f;
1717                         else
1718                                 ctrl |= 0x80;
1719                 } else {
1720                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1721                 }
1722                 data->pwm_ctrl[nr] = ctrl;
1723                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1724
1725                 if (has_fanctl_onoff(data) && nr < 3) {
1726                         /* set SmartGuardian mode */
1727                         data->fan_main_ctrl |= BIT(nr);
1728                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1729                                          data->fan_main_ctrl);
1730                 }
1731         }
1732
1733         mutex_unlock(&data->update_lock);
1734         return count;
1735 }
1736
1737 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1738                        const char *buf, size_t count)
1739 {
1740         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1741         struct it87_data *data = dev_get_drvdata(dev);
1742         int nr = sensor_attr->index;
1743         long val;
1744
1745         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1746                 return -EINVAL;
1747
1748         mutex_lock(&data->update_lock);
1749         it87_update_pwm_ctrl(data, nr);
1750         if (has_newer_autopwm(data)) {
1751                 /*
1752                  * If we are in automatic mode, the PWM duty cycle register
1753                  * is read-only so we can't write the value.
1754                  */
1755                 if (data->pwm_ctrl[nr] & 0x80) {
1756                         mutex_unlock(&data->update_lock);
1757                         return -EBUSY;
1758                 }
1759                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1760                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1761                                  data->pwm_duty[nr]);
1762         } else {
1763                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1764                 /*
1765                  * If we are in manual mode, write the duty cycle immediately;
1766                  * otherwise, just store it for later use.
1767                  */
1768                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1769                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1770                         it87_write_value(data, data->REG_PWM[nr],
1771                                          data->pwm_ctrl[nr]);
1772                 }
1773         }
1774         mutex_unlock(&data->update_lock);
1775         return count;
1776 }
1777
1778 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1779                             const char *buf, size_t count)
1780 {
1781         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1782         struct it87_data *data = dev_get_drvdata(dev);
1783         int nr = sensor_attr->index;
1784         unsigned long val;
1785         int i;
1786
1787         if (kstrtoul(buf, 10, &val) < 0)
1788                 return -EINVAL;
1789
1790         val = clamp_val(val, 0, 1000000);
1791         val *= has_newer_autopwm(data) ? 256 : 128;
1792
1793         /* Search for the nearest available frequency */
1794         for (i = 0; i < 7; i++) {
1795                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1796                         break;
1797         }
1798
1799         mutex_lock(&data->update_lock);
1800         if (nr == 0) {
1801                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1802                 data->fan_ctl |= i << 4;
1803                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1804         } else {
1805                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1806                 data->extra |= i << 4;
1807                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1808         }
1809         mutex_unlock(&data->update_lock);
1810
1811         return count;
1812 }
1813
1814 static ssize_t show_pwm_temp_map(struct device *dev,
1815                                  struct device_attribute *attr, char *buf)
1816 {
1817         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1818         struct it87_data *data = it87_update_device(dev);
1819         int nr = sensor_attr->index;
1820
1821         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1822 }
1823
1824 static ssize_t set_pwm_temp_map(struct device *dev,
1825                                 struct device_attribute *attr, const char *buf,
1826                                 size_t count)
1827 {
1828         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1829         struct it87_data *data = dev_get_drvdata(dev);
1830         int nr = sensor_attr->index;
1831         unsigned long val;
1832         u8 map;
1833
1834         if (kstrtoul(buf, 10, &val) < 0)
1835                 return -EINVAL;
1836
1837         if (!val || val > data->pwm_num_temp_map)
1838                 return -EINVAL;
1839
1840         map = val - 1;
1841
1842         mutex_lock(&data->update_lock);
1843         it87_update_pwm_ctrl(data, nr);
1844         data->pwm_temp_map[nr] = map;
1845         /*
1846          * If we are in automatic mode, write the temp mapping immediately;
1847          * otherwise, just store it for later use.
1848          */
1849         if (data->pwm_ctrl[nr] & 0x80) {
1850                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
1851                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1852         }
1853         mutex_unlock(&data->update_lock);
1854         return count;
1855 }
1856
1857 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1858                              char *buf)
1859 {
1860         struct it87_data *data = it87_update_device(dev);
1861         struct sensor_device_attribute_2 *sensor_attr =
1862                         to_sensor_dev_attr_2(attr);
1863         int nr = sensor_attr->nr;
1864         int point = sensor_attr->index;
1865
1866         return sprintf(buf, "%d\n",
1867                        pwm_from_reg(data, data->auto_pwm[nr][point]));
1868 }
1869
1870 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1871                             const char *buf, size_t count)
1872 {
1873         struct it87_data *data = dev_get_drvdata(dev);
1874         struct sensor_device_attribute_2 *sensor_attr =
1875                         to_sensor_dev_attr_2(attr);
1876         int nr = sensor_attr->nr;
1877         int point = sensor_attr->index;
1878         int regaddr;
1879         long val;
1880
1881         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1882                 return -EINVAL;
1883
1884         mutex_lock(&data->update_lock);
1885         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1886         if (has_newer_autopwm(data))
1887                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1888         else
1889                 regaddr = IT87_REG_AUTO_PWM(nr, point);
1890         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1891         mutex_unlock(&data->update_lock);
1892         return count;
1893 }
1894
1895 static ssize_t show_auto_pwm_slope(struct device *dev,
1896                                    struct device_attribute *attr, char *buf)
1897 {
1898         struct it87_data *data = it87_update_device(dev);
1899         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1900         int nr = sensor_attr->index;
1901
1902         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1903 }
1904
1905 static ssize_t set_auto_pwm_slope(struct device *dev,
1906                                   struct device_attribute *attr,
1907                                   const char *buf, size_t count)
1908 {
1909         struct it87_data *data = dev_get_drvdata(dev);
1910         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1911         int nr = sensor_attr->index;
1912         unsigned long val;
1913
1914         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1915                 return -EINVAL;
1916
1917         mutex_lock(&data->update_lock);
1918         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1919         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1920                          data->auto_pwm[nr][1]);
1921         mutex_unlock(&data->update_lock);
1922         return count;
1923 }
1924
1925 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1926                               char *buf)
1927 {
1928         struct it87_data *data = it87_update_device(dev);
1929         struct sensor_device_attribute_2 *sensor_attr =
1930                         to_sensor_dev_attr_2(attr);
1931         int nr = sensor_attr->nr;
1932         int point = sensor_attr->index;
1933         int reg;
1934
1935         if (has_old_autopwm(data) || point)
1936                 reg = data->auto_temp[nr][point];
1937         else
1938                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1939
1940         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1941 }
1942
1943 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1944                              const char *buf, size_t count)
1945 {
1946         struct it87_data *data = dev_get_drvdata(dev);
1947         struct sensor_device_attribute_2 *sensor_attr =
1948                         to_sensor_dev_attr_2(attr);
1949         int nr = sensor_attr->nr;
1950         int point = sensor_attr->index;
1951         long val;
1952         int reg;
1953
1954         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1955                 return -EINVAL;
1956
1957         mutex_lock(&data->update_lock);
1958         if (has_newer_autopwm(data) && !point) {
1959                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1960                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1961                 data->auto_temp[nr][0] = reg;
1962                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1963         } else {
1964                 reg = TEMP_TO_REG(val);
1965                 data->auto_temp[nr][point] = reg;
1966                 if (has_newer_autopwm(data))
1967                         point--;
1968                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1969         }
1970         mutex_unlock(&data->update_lock);
1971         return count;
1972 }
1973
1974 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1975 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1976                             0, 1);
1977 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1978                           set_fan_div, 0);
1979
1980 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1981 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1982                             1, 1);
1983 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1984                           set_fan_div, 1);
1985
1986 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1987 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1988                             2, 1);
1989 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1990                           set_fan_div, 2);
1991
1992 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1993 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1994                             3, 1);
1995
1996 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1997 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1998                             4, 1);
1999
2000 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2001 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2002                             5, 1);
2003
2004 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2005                           show_pwm_enable, set_pwm_enable, 0);
2006 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2007 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2008                           set_pwm_freq, 0);
2009 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2010                           show_pwm_temp_map, set_pwm_temp_map, 0);
2011 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2012                             show_auto_pwm, set_auto_pwm, 0, 0);
2013 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2014                             show_auto_pwm, set_auto_pwm, 0, 1);
2015 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2016                             show_auto_pwm, set_auto_pwm, 0, 2);
2017 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2018                             show_auto_pwm, NULL, 0, 3);
2019 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2020                             show_auto_temp, set_auto_temp, 0, 1);
2021 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2022                             show_auto_temp, set_auto_temp, 0, 0);
2023 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2024                             show_auto_temp, set_auto_temp, 0, 2);
2025 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2026                             show_auto_temp, set_auto_temp, 0, 3);
2027 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2028                             show_auto_temp, set_auto_temp, 0, 4);
2029 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2030                             show_auto_pwm, set_auto_pwm, 0, 0);
2031 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2032                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2033
2034 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2035                           show_pwm_enable, set_pwm_enable, 1);
2036 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2037 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2038 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2039                           show_pwm_temp_map, set_pwm_temp_map, 1);
2040 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2041                             show_auto_pwm, set_auto_pwm, 1, 0);
2042 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2043                             show_auto_pwm, set_auto_pwm, 1, 1);
2044 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2045                             show_auto_pwm, set_auto_pwm, 1, 2);
2046 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2047                             show_auto_pwm, NULL, 1, 3);
2048 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2049                             show_auto_temp, set_auto_temp, 1, 1);
2050 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2051                             show_auto_temp, set_auto_temp, 1, 0);
2052 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2053                             show_auto_temp, set_auto_temp, 1, 2);
2054 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2055                             show_auto_temp, set_auto_temp, 1, 3);
2056 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2057                             show_auto_temp, set_auto_temp, 1, 4);
2058 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2059                             show_auto_pwm, set_auto_pwm, 1, 0);
2060 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2061                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2062
2063 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2064                           show_pwm_enable, set_pwm_enable, 2);
2065 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2066 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2067 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2068                           show_pwm_temp_map, set_pwm_temp_map, 2);
2069 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2070                             show_auto_pwm, set_auto_pwm, 2, 0);
2071 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2072                             show_auto_pwm, set_auto_pwm, 2, 1);
2073 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2074                             show_auto_pwm, set_auto_pwm, 2, 2);
2075 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2076                             show_auto_pwm, NULL, 2, 3);
2077 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2078                             show_auto_temp, set_auto_temp, 2, 1);
2079 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2080                             show_auto_temp, set_auto_temp, 2, 0);
2081 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2082                             show_auto_temp, set_auto_temp, 2, 2);
2083 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2084                             show_auto_temp, set_auto_temp, 2, 3);
2085 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2086                             show_auto_temp, set_auto_temp, 2, 4);
2087 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2088                             show_auto_pwm, set_auto_pwm, 2, 0);
2089 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2090                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2091
2092 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2093                           show_pwm_enable, set_pwm_enable, 3);
2094 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2095 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2096 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2097                           show_pwm_temp_map, set_pwm_temp_map, 3);
2098 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2099                             show_auto_temp, set_auto_temp, 2, 1);
2100 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2101                             show_auto_temp, set_auto_temp, 2, 0);
2102 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2103                             show_auto_temp, set_auto_temp, 2, 2);
2104 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2105                             show_auto_temp, set_auto_temp, 2, 3);
2106 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2107                             show_auto_pwm, set_auto_pwm, 3, 0);
2108 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2109                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2110
2111 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2112                           show_pwm_enable, set_pwm_enable, 4);
2113 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2114 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2115 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2116                           show_pwm_temp_map, set_pwm_temp_map, 4);
2117 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2118                             show_auto_temp, set_auto_temp, 2, 1);
2119 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2120                             show_auto_temp, set_auto_temp, 2, 0);
2121 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2122                             show_auto_temp, set_auto_temp, 2, 2);
2123 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2124                             show_auto_temp, set_auto_temp, 2, 3);
2125 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2126                             show_auto_pwm, set_auto_pwm, 4, 0);
2127 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2128                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2129
2130 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2131                           show_pwm_enable, set_pwm_enable, 5);
2132 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2133 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2134 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2135                           show_pwm_temp_map, set_pwm_temp_map, 5);
2136 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2137                             show_auto_temp, set_auto_temp, 2, 1);
2138 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2139                             show_auto_temp, set_auto_temp, 2, 0);
2140 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2141                             show_auto_temp, set_auto_temp, 2, 2);
2142 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2143                             show_auto_temp, set_auto_temp, 2, 3);
2144 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2145                             show_auto_pwm, set_auto_pwm, 5, 0);
2146 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2147                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2148
2149 /* Alarms */
2150 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2151                            char *buf)
2152 {
2153         struct it87_data *data = it87_update_device(dev);
2154
2155         return sprintf(buf, "%u\n", data->alarms);
2156 }
2157 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2158
2159 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2160                           char *buf)
2161 {
2162         struct it87_data *data = it87_update_device(dev);
2163         int bitnr = to_sensor_dev_attr(attr)->index;
2164
2165         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2166 }
2167
2168 static ssize_t clear_intrusion(struct device *dev,
2169                                struct device_attribute *attr, const char *buf,
2170                                size_t count)
2171 {
2172         struct it87_data *data = dev_get_drvdata(dev);
2173         int config;
2174         long val;
2175
2176         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2177                 return -EINVAL;
2178
2179         mutex_lock(&data->update_lock);
2180         config = it87_read_value(data, IT87_REG_CONFIG);
2181         if (config < 0) {
2182                 count = config;
2183         } else {
2184                 config |= BIT(5);
2185                 it87_write_value(data, IT87_REG_CONFIG, config);
2186                 /* Invalidate cache to force re-read */
2187                 data->valid = 0;
2188         }
2189         mutex_unlock(&data->update_lock);
2190
2191         return count;
2192 }
2193
2194 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2195 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2196 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2197 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2198 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2199 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2200 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2201 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2202 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2203 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2204 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2205 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2206 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2207 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2208 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2209 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2210 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2211 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2212 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2213 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2214 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2215                           show_alarm, clear_intrusion, 4);
2216
2217 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2218                          char *buf)
2219 {
2220         struct it87_data *data = it87_update_device(dev);
2221         int bitnr = to_sensor_dev_attr(attr)->index;
2222
2223         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2224 }
2225
2226 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2227                         const char *buf, size_t count)
2228 {
2229         int bitnr = to_sensor_dev_attr(attr)->index;
2230         struct it87_data *data = dev_get_drvdata(dev);
2231         long val;
2232
2233         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2234                 return -EINVAL;
2235
2236         mutex_lock(&data->update_lock);
2237         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2238         if (val)
2239                 data->beeps |= BIT(bitnr);
2240         else
2241                 data->beeps &= ~BIT(bitnr);
2242         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2243         mutex_unlock(&data->update_lock);
2244         return count;
2245 }
2246
2247 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2248                           show_beep, set_beep, 1);
2249 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2250 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2251 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2252 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2253 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2254 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2255 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2256 /* fanX_beep writability is set later */
2257 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2258 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2259 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2260 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2261 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2262 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2263 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2264                           show_beep, set_beep, 2);
2265 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2266 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2267 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2268 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2269 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2270
2271 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2272                             char *buf)
2273 {
2274         struct it87_data *data = dev_get_drvdata(dev);
2275
2276         return sprintf(buf, "%u\n", data->vrm);
2277 }
2278
2279 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2280                              const char *buf, size_t count)
2281 {
2282         struct it87_data *data = dev_get_drvdata(dev);
2283         unsigned long val;
2284
2285         if (kstrtoul(buf, 10, &val) < 0)
2286                 return -EINVAL;
2287
2288         data->vrm = val;
2289
2290         return count;
2291 }
2292 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2293
2294 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2295                             char *buf)
2296 {
2297         struct it87_data *data = it87_update_device(dev);
2298
2299         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2300 }
2301 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2302
2303 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2304                           char *buf)
2305 {
2306         static const char * const labels[] = {
2307                 "+5V",
2308                 "5VSB",
2309                 "Vbat",
2310                 "AVCC",
2311         };
2312         static const char * const labels_it8721[] = {
2313                 "+3.3V",
2314                 "3VSB",
2315                 "Vbat",
2316                 "+3.3V",
2317         };
2318         struct it87_data *data = dev_get_drvdata(dev);
2319         int nr = to_sensor_dev_attr(attr)->index;
2320         const char *label;
2321
2322         if (has_vin3_5v(data) && nr == 0)
2323                 label = labels[0];
2324         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2325                  has_11mv_adc(data))
2326                 label = labels_it8721[nr];
2327         else
2328                 label = labels[nr];
2329
2330         return sprintf(buf, "%s\n", label);
2331 }
2332 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2333 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2334 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2335 /* AVCC3 */
2336 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2337
2338 static umode_t it87_in_is_visible(struct kobject *kobj,
2339                                   struct attribute *attr, int index)
2340 {
2341         struct device *dev = container_of(kobj, struct device, kobj);
2342         struct it87_data *data = dev_get_drvdata(dev);
2343         int i = index / 5;      /* voltage index */
2344         int a = index % 5;      /* attribute index */
2345
2346         if (index >= 40) {      /* in8 and higher only have input attributes */
2347                 i = index - 40 + 8;
2348                 a = 0;
2349         }
2350
2351         if (!(data->has_in & BIT(i)))
2352                 return 0;
2353
2354         if (a == 4 && !data->has_beep)
2355                 return 0;
2356
2357         return attr->mode;
2358 }
2359
2360 static struct attribute *it87_attributes_in[] = {
2361         &sensor_dev_attr_in0_input.dev_attr.attr,
2362         &sensor_dev_attr_in0_min.dev_attr.attr,
2363         &sensor_dev_attr_in0_max.dev_attr.attr,
2364         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2365         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2366
2367         &sensor_dev_attr_in1_input.dev_attr.attr,
2368         &sensor_dev_attr_in1_min.dev_attr.attr,
2369         &sensor_dev_attr_in1_max.dev_attr.attr,
2370         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2371         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2372
2373         &sensor_dev_attr_in2_input.dev_attr.attr,
2374         &sensor_dev_attr_in2_min.dev_attr.attr,
2375         &sensor_dev_attr_in2_max.dev_attr.attr,
2376         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2377         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2378
2379         &sensor_dev_attr_in3_input.dev_attr.attr,
2380         &sensor_dev_attr_in3_min.dev_attr.attr,
2381         &sensor_dev_attr_in3_max.dev_attr.attr,
2382         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2383         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2384
2385         &sensor_dev_attr_in4_input.dev_attr.attr,
2386         &sensor_dev_attr_in4_min.dev_attr.attr,
2387         &sensor_dev_attr_in4_max.dev_attr.attr,
2388         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2389         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2390
2391         &sensor_dev_attr_in5_input.dev_attr.attr,
2392         &sensor_dev_attr_in5_min.dev_attr.attr,
2393         &sensor_dev_attr_in5_max.dev_attr.attr,
2394         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2395         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2396
2397         &sensor_dev_attr_in6_input.dev_attr.attr,
2398         &sensor_dev_attr_in6_min.dev_attr.attr,
2399         &sensor_dev_attr_in6_max.dev_attr.attr,
2400         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2401         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2402
2403         &sensor_dev_attr_in7_input.dev_attr.attr,
2404         &sensor_dev_attr_in7_min.dev_attr.attr,
2405         &sensor_dev_attr_in7_max.dev_attr.attr,
2406         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2407         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2408
2409         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2410         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2411         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2412         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2413         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2414         NULL
2415 };
2416
2417 static const struct attribute_group it87_group_in = {
2418         .attrs = it87_attributes_in,
2419         .is_visible = it87_in_is_visible,
2420 };
2421
2422 static umode_t it87_temp_is_visible(struct kobject *kobj,
2423                                     struct attribute *attr, int index)
2424 {
2425         struct device *dev = container_of(kobj, struct device, kobj);
2426         struct it87_data *data = dev_get_drvdata(dev);
2427         int i = index / 7;      /* temperature index */
2428         int a = index % 7;      /* attribute index */
2429
2430         if (!(data->has_temp & BIT(i)))
2431                 return 0;
2432
2433         if (a && i >= data->num_temp_limit)
2434                 return 0;
2435
2436         if (a == 3) {
2437                 int type = get_temp_type(data, i);
2438
2439                 if (type == 0)
2440                         return 0;
2441                 if (has_bank_sel(data))
2442                         return 0444;
2443                 return attr->mode;
2444         }
2445
2446         if (a == 5 && i >= data->num_temp_offset)
2447                 return 0;
2448
2449         if (a == 6 && !data->has_beep)
2450                 return 0;
2451
2452         return attr->mode;
2453 }
2454
2455 static struct attribute *it87_attributes_temp[] = {
2456         &sensor_dev_attr_temp1_input.dev_attr.attr,
2457         &sensor_dev_attr_temp1_max.dev_attr.attr,
2458         &sensor_dev_attr_temp1_min.dev_attr.attr,
2459         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2460         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2461         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2462         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2463
2464         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2465         &sensor_dev_attr_temp2_max.dev_attr.attr,
2466         &sensor_dev_attr_temp2_min.dev_attr.attr,
2467         &sensor_dev_attr_temp2_type.dev_attr.attr,
2468         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2469         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2470         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2471
2472         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2473         &sensor_dev_attr_temp3_max.dev_attr.attr,
2474         &sensor_dev_attr_temp3_min.dev_attr.attr,
2475         &sensor_dev_attr_temp3_type.dev_attr.attr,
2476         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2477         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2478         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2479
2480         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2481         &sensor_dev_attr_temp4_max.dev_attr.attr,
2482         &sensor_dev_attr_temp4_min.dev_attr.attr,
2483         &sensor_dev_attr_temp4_type.dev_attr.attr,
2484         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2485         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2486         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2487
2488         &sensor_dev_attr_temp5_input.dev_attr.attr,
2489         &sensor_dev_attr_temp5_max.dev_attr.attr,
2490         &sensor_dev_attr_temp5_min.dev_attr.attr,
2491         &sensor_dev_attr_temp5_type.dev_attr.attr,
2492         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2493         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2494         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2495
2496         &sensor_dev_attr_temp6_input.dev_attr.attr,
2497         &sensor_dev_attr_temp6_max.dev_attr.attr,
2498         &sensor_dev_attr_temp6_min.dev_attr.attr,
2499         &sensor_dev_attr_temp6_type.dev_attr.attr,
2500         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2501         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2502         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2503         NULL
2504 };
2505
2506 static const struct attribute_group it87_group_temp = {
2507         .attrs = it87_attributes_temp,
2508         .is_visible = it87_temp_is_visible,
2509 };
2510
2511 static umode_t it87_is_visible(struct kobject *kobj,
2512                                struct attribute *attr, int index)
2513 {
2514         struct device *dev = container_of(kobj, struct device, kobj);
2515         struct it87_data *data = dev_get_drvdata(dev);
2516
2517         if ((index == 2 || index == 3) && !data->has_vid)
2518                 return 0;
2519
2520         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2521                 return 0;
2522
2523         return attr->mode;
2524 }
2525
2526 static struct attribute *it87_attributes[] = {
2527         &dev_attr_alarms.attr,
2528         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2529         &dev_attr_vrm.attr,                             /* 2 */
2530         &dev_attr_cpu0_vid.attr,                        /* 3 */
2531         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2532         &sensor_dev_attr_in7_label.dev_attr.attr,
2533         &sensor_dev_attr_in8_label.dev_attr.attr,
2534         &sensor_dev_attr_in9_label.dev_attr.attr,
2535         NULL
2536 };
2537
2538 static const struct attribute_group it87_group = {
2539         .attrs = it87_attributes,
2540         .is_visible = it87_is_visible,
2541 };
2542
2543 static umode_t it87_fan_is_visible(struct kobject *kobj,
2544                                    struct attribute *attr, int index)
2545 {
2546         struct device *dev = container_of(kobj, struct device, kobj);
2547         struct it87_data *data = dev_get_drvdata(dev);
2548         int i = index / 5;      /* fan index */
2549         int a = index % 5;      /* attribute index */
2550
2551         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2552                 i = (index - 15) / 4 + 3;
2553                 a = (index - 15) % 4;
2554         }
2555
2556         if (!(data->has_fan & BIT(i)))
2557                 return 0;
2558
2559         if (a == 3) {                           /* beep */
2560                 if (!data->has_beep)
2561                         return 0;
2562                 /* first fan beep attribute is writable */
2563                 if (i == __ffs(data->has_fan))
2564                         return attr->mode | S_IWUSR;
2565         }
2566
2567         if (a == 4 && has_16bit_fans(data))     /* divisor */
2568                 return 0;
2569
2570         return attr->mode;
2571 }
2572
2573 static struct attribute *it87_attributes_fan[] = {
2574         &sensor_dev_attr_fan1_input.dev_attr.attr,
2575         &sensor_dev_attr_fan1_min.dev_attr.attr,
2576         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2577         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2578         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2579
2580         &sensor_dev_attr_fan2_input.dev_attr.attr,
2581         &sensor_dev_attr_fan2_min.dev_attr.attr,
2582         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2583         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2584         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2585
2586         &sensor_dev_attr_fan3_input.dev_attr.attr,
2587         &sensor_dev_attr_fan3_min.dev_attr.attr,
2588         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2589         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2590         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2591
2592         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2593         &sensor_dev_attr_fan4_min.dev_attr.attr,
2594         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2595         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2596
2597         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2598         &sensor_dev_attr_fan5_min.dev_attr.attr,
2599         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2600         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2601
2602         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2603         &sensor_dev_attr_fan6_min.dev_attr.attr,
2604         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2605         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2606         NULL
2607 };
2608
2609 static const struct attribute_group it87_group_fan = {
2610         .attrs = it87_attributes_fan,
2611         .is_visible = it87_fan_is_visible,
2612 };
2613
2614 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2615                                    struct attribute *attr, int index)
2616 {
2617         struct device *dev = container_of(kobj, struct device, kobj);
2618         struct it87_data *data = dev_get_drvdata(dev);
2619         int i = index / 4;      /* pwm index */
2620         int a = index % 4;      /* attribute index */
2621
2622         if (!(data->has_pwm & BIT(i)))
2623                 return 0;
2624
2625         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2626         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2627                 return attr->mode | S_IWUSR;
2628
2629         /* pwm2_freq is writable if there are two pwm frequency selects */
2630         if (has_pwm_freq2(data) && i == 1 && a == 2)
2631                 return attr->mode | S_IWUSR;
2632
2633         return attr->mode;
2634 }
2635
2636 static struct attribute *it87_attributes_pwm[] = {
2637         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2638         &sensor_dev_attr_pwm1.dev_attr.attr,
2639         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2640         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2641
2642         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2643         &sensor_dev_attr_pwm2.dev_attr.attr,
2644         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2645         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2646
2647         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2648         &sensor_dev_attr_pwm3.dev_attr.attr,
2649         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2650         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2651
2652         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2653         &sensor_dev_attr_pwm4.dev_attr.attr,
2654         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2655         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2656
2657         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2658         &sensor_dev_attr_pwm5.dev_attr.attr,
2659         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2660         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2661
2662         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2663         &sensor_dev_attr_pwm6.dev_attr.attr,
2664         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2665         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2666
2667         NULL
2668 };
2669
2670 static const struct attribute_group it87_group_pwm = {
2671         .attrs = it87_attributes_pwm,
2672         .is_visible = it87_pwm_is_visible,
2673 };
2674
2675 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2676                                         struct attribute *attr, int index)
2677 {
2678         struct device *dev = container_of(kobj, struct device, kobj);
2679         struct it87_data *data = dev_get_drvdata(dev);
2680         int i = index / 11;     /* pwm index */
2681         int a = index % 11;     /* attribute index */
2682
2683         if (index >= 33) {      /* pwm 4..6 */
2684                 i = (index - 33) / 6 + 3;
2685                 a = (index - 33) % 6 + 4;
2686         }
2687
2688         if (!(data->has_pwm & BIT(i)))
2689                 return 0;
2690
2691         if (has_newer_autopwm(data)) {
2692                 if (a < 4)      /* no auto point pwm */
2693                         return 0;
2694                 if (a == 8)     /* no auto_point4 */
2695                         return 0;
2696         }
2697         if (has_old_autopwm(data)) {
2698                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2699                         return 0;
2700         }
2701
2702         return attr->mode;
2703 }
2704
2705 static struct attribute *it87_attributes_auto_pwm[] = {
2706         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2707         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2708         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2709         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2710         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2711         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2712         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2713         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2714         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2715         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2716         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2717
2718         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2719         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2720         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2721         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2722         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2723         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2724         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2725         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2726         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2727         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2728         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2729
2730         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2731         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2732         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2733         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2734         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2735         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2736         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2737         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2738         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2739         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2740         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2741
2742         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2743         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2744         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2745         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2746         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2747         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2748
2749         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2750         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2751         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2752         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2753         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2754         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2755
2756         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2757         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2758         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2759         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2760         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2761         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2762
2763         NULL,
2764 };
2765
2766 static const struct attribute_group it87_group_auto_pwm = {
2767         .attrs = it87_attributes_auto_pwm,
2768         .is_visible = it87_auto_pwm_is_visible,
2769 };
2770
2771 /* SuperIO detection - will change isa_address if a chip is found */
2772 static int __init it87_find(int sioaddr, unsigned short *address,
2773                             struct it87_sio_data *sio_data)
2774 {
2775         const struct it87_devices *config;
2776         bool doexit = true;
2777         u16 chip_type;
2778         int err;
2779
2780         err = superio_enter(sioaddr);
2781         if (err)
2782                 return err;
2783
2784         err = -ENODEV;
2785         chip_type = superio_inw(sioaddr, DEVID);
2786         if (chip_type == 0xffff)
2787                 goto exit;
2788
2789         if (force_id)
2790                 chip_type = force_id;
2791
2792         switch (chip_type) {
2793         case IT8705F_DEVID:
2794                 sio_data->type = it87;
2795                 break;
2796         case IT8712F_DEVID:
2797                 sio_data->type = it8712;
2798                 break;
2799         case IT8716F_DEVID:
2800         case IT8726F_DEVID:
2801                 sio_data->type = it8716;
2802                 break;
2803         case IT8718F_DEVID:
2804                 sio_data->type = it8718;
2805                 break;
2806         case IT8720F_DEVID:
2807                 sio_data->type = it8720;
2808                 break;
2809         case IT8721F_DEVID:
2810                 sio_data->type = it8721;
2811                 break;
2812         case IT8728F_DEVID:
2813                 sio_data->type = it8728;
2814                 break;
2815         case IT8732F_DEVID:
2816                 sio_data->type = it8732;
2817                 break;
2818         case IT8792E_DEVID:
2819                 sio_data->type = it8792;
2820                 /*
2821                  * Disabling configuration mode on IT8792E can result in system
2822                  * hang-ups and access failures to the Super-IO chip at the
2823                  * second SIO address. Never exit configuration mode on this
2824                  * chip to avoid the problem.
2825                  */
2826                 doexit = false;
2827                 break;
2828         case IT8771E_DEVID:
2829                 sio_data->type = it8771;
2830                 break;
2831         case IT8772E_DEVID:
2832                 sio_data->type = it8772;
2833                 break;
2834         case IT8781F_DEVID:
2835                 sio_data->type = it8781;
2836                 break;
2837         case IT8782F_DEVID:
2838                 sio_data->type = it8782;
2839                 break;
2840         case IT8783E_DEVID:
2841                 sio_data->type = it8783;
2842                 break;
2843         case IT8786E_DEVID:
2844                 sio_data->type = it8786;
2845                 break;
2846         case IT8790E_DEVID:
2847                 sio_data->type = it8790;
2848                 doexit = false;         /* See IT8792E comment above */
2849                 break;
2850         case IT8603E_DEVID:
2851         case IT8623E_DEVID:
2852                 sio_data->type = it8603;
2853                 break;
2854         case IT8607E_DEVID:
2855                 sio_data->type = it8607;
2856                 break;
2857         case IT8613E_DEVID:
2858                 sio_data->type = it8613;
2859                 break;
2860         case IT8620E_DEVID:
2861                 sio_data->type = it8620;
2862                 break;
2863         case IT8622E_DEVID:
2864                 sio_data->type = it8622;
2865                 break;
2866         case IT8625E_DEVID:
2867                 sio_data->type = it8625;
2868                 break;
2869         case IT8628E_DEVID:
2870                 sio_data->type = it8628;
2871                 break;
2872         case IT8655E_DEVID:
2873                 sio_data->type = it8655;
2874                 break;
2875         case IT8665E_DEVID:
2876                 sio_data->type = it8665;
2877                 break;
2878         case IT8686E_DEVID:
2879                 sio_data->type = it8686;
2880                 break;
2881         case 0xffff:    /* No device at all */
2882                 goto exit;
2883         default:
2884                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2885                 goto exit;
2886         }
2887
2888         superio_select(sioaddr, PME);
2889         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2890                 pr_info("Device not activated, skipping\n");
2891                 goto exit;
2892         }
2893
2894         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2895         if (*address == 0) {
2896                 pr_info("Base address not set, skipping\n");
2897                 goto exit;
2898         }
2899
2900         err = 0;
2901         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2902         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2903                 it87_devices[sio_data->type].suffix,
2904                 *address, sio_data->revision);
2905
2906         config = &it87_devices[sio_data->type];
2907
2908         /* in7 (VSB or VCCH5V) is always internal on some chips */
2909         if (has_in7_internal(config))
2910                 sio_data->internal |= BIT(1);
2911
2912         /* in8 (Vbat) is always internal */
2913         sio_data->internal |= BIT(2);
2914
2915         /* in9 (AVCC3), always internal if supported */
2916         if (has_avcc3(config))
2917                 sio_data->internal |= BIT(3); /* in9 is AVCC */
2918         else
2919                 sio_data->skip_in |= BIT(9);
2920
2921         if (!has_four_pwm(config))
2922                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2923         else if (!has_five_pwm(config))
2924                 sio_data->skip_pwm |= BIT(4) | BIT(5);
2925         else if (!has_six_pwm(config))
2926                 sio_data->skip_pwm |= BIT(5);
2927
2928         if (!has_vid(config))
2929                 sio_data->skip_vid = 1;
2930
2931         /* Read GPIO config and VID value from LDN 7 (GPIO) */
2932         if (sio_data->type == it87) {
2933                 /* The IT8705F has a different LD number for GPIO */
2934                 superio_select(sioaddr, 5);
2935                 sio_data->beep_pin = superio_inb(sioaddr,
2936                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2937         } else if (sio_data->type == it8783) {
2938                 int reg25, reg27, reg2a, reg2c, regef;
2939
2940                 superio_select(sioaddr, GPIO);
2941
2942                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2943                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2944                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2945                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2946                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2947
2948                 /* Check if fan3 is there or not */
2949                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2950                         sio_data->skip_fan |= BIT(2);
2951                 if ((reg25 & BIT(4)) ||
2952                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
2953                         sio_data->skip_pwm |= BIT(2);
2954
2955                 /* Check if fan2 is there or not */
2956                 if (reg27 & BIT(7))
2957                         sio_data->skip_fan |= BIT(1);
2958                 if (reg27 & BIT(3))
2959                         sio_data->skip_pwm |= BIT(1);
2960
2961                 /* VIN5 */
2962                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2963                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2964
2965                 /* VIN6 */
2966                 if (reg27 & BIT(1))
2967                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2968
2969                 /*
2970                  * VIN7
2971                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2972                  */
2973                 if (reg27 & BIT(2)) {
2974                         /*
2975                          * The data sheet is a bit unclear regarding the
2976                          * internal voltage divider for VCCH5V. It says
2977                          * "This bit enables and switches VIN7 (pin 91) to the
2978                          * internal voltage divider for VCCH5V".
2979                          * This is different to other chips, where the internal
2980                          * voltage divider would connect VIN7 to an internal
2981                          * voltage source. Maybe that is the case here as well.
2982                          *
2983                          * Since we don't know for sure, re-route it if that is
2984                          * not the case, and ask the user to report if the
2985                          * resulting voltage is sane.
2986                          */
2987                         if (!(reg2c & BIT(1))) {
2988                                 reg2c |= BIT(1);
2989                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2990                                              reg2c);
2991                                 pr_notice("Routing internal VCCH5V to in7.\n");
2992                         }
2993                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2994                         pr_notice("Please report if it displays a reasonable voltage.\n");
2995                 }
2996
2997                 if (reg2c & BIT(0))
2998                         sio_data->internal |= BIT(0);
2999                 if (reg2c & BIT(1))
3000                         sio_data->internal |= BIT(1);
3001
3002                 sio_data->beep_pin = superio_inb(sioaddr,
3003                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3004         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3005                 int reg27, reg29;
3006
3007                 superio_select(sioaddr, GPIO);
3008
3009                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3010
3011                 /* Check if fan3 is there or not */
3012                 if (reg27 & BIT(6))
3013                         sio_data->skip_pwm |= BIT(2);
3014                 if (reg27 & BIT(7))
3015                         sio_data->skip_fan |= BIT(2);
3016
3017                 /* Check if fan2 is there or not */
3018                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3019                 if (reg29 & BIT(1))
3020                         sio_data->skip_pwm |= BIT(1);
3021                 if (reg29 & BIT(2))
3022                         sio_data->skip_fan |= BIT(1);
3023
3024                 switch (sio_data->type) {
3025                 case it8603:
3026                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3027                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3028                         break;
3029                 case it8607:
3030                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3031                         sio_data->skip_fan |= BIT(0);
3032                 default:
3033                         break;
3034                 }
3035
3036                 sio_data->beep_pin = superio_inb(sioaddr,
3037                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3038         } else if (sio_data->type == it8613) {
3039                 int reg27, reg29, reg2a;
3040
3041                 superio_select(sioaddr, GPIO);
3042
3043                 /* Check for pwm3, fan3, pwm5, fan5 */
3044                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3045                 if (reg27 & BIT(1))
3046                         sio_data->skip_fan |= BIT(4);
3047                 if (reg27 & BIT(3))
3048                         sio_data->skip_pwm |= BIT(4);
3049                 if (reg27 & BIT(6))
3050                         sio_data->skip_pwm |= BIT(2);
3051                 if (reg27 & BIT(7))
3052                         sio_data->skip_fan |= BIT(2);
3053
3054                 /* Check for pwm2, fan2 */
3055                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3056                 if (reg29 & BIT(1))
3057                         sio_data->skip_pwm |= BIT(1);
3058                 if (reg29 & BIT(2))
3059                         sio_data->skip_fan |= BIT(1);
3060
3061                 /* Check for pwm4, fan4 */
3062                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3063                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3064                         sio_data->skip_fan |= BIT(3);
3065                         sio_data->skip_pwm |= BIT(3);
3066                 }
3067
3068                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3069                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3070                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3071                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3072
3073                 sio_data->beep_pin = superio_inb(sioaddr,
3074                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3075         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3076                    sio_data->type == it8686) {
3077                 int reg;
3078
3079                 superio_select(sioaddr, GPIO);
3080
3081                 /* Check for pwm5 */
3082                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3083                 if (reg & BIT(6))
3084                         sio_data->skip_pwm |= BIT(4);
3085
3086                 /* Check for fan4, fan5 */
3087                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3088                 if (!(reg & BIT(5)))
3089                         sio_data->skip_fan |= BIT(3);
3090                 if (!(reg & BIT(4)))
3091                         sio_data->skip_fan |= BIT(4);
3092
3093                 /* Check for pwm3, fan3 */
3094                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3095                 if (reg & BIT(6))
3096                         sio_data->skip_pwm |= BIT(2);
3097                 if (reg & BIT(7))
3098                         sio_data->skip_fan |= BIT(2);
3099
3100                 /* Check for pwm4 */
3101                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3102                 if (reg & BIT(2))
3103                         sio_data->skip_pwm |= BIT(3);
3104
3105                 /* Check for pwm2, fan2 */
3106                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3107                 if (reg & BIT(1))
3108                         sio_data->skip_pwm |= BIT(1);
3109                 if (reg & BIT(2))
3110                         sio_data->skip_fan |= BIT(1);
3111                 /* Check for pwm6, fan6 */
3112                 if (!(reg & BIT(7))) {
3113                         sio_data->skip_pwm |= BIT(5);
3114                         sio_data->skip_fan |= BIT(5);
3115                 }
3116
3117                 /* Check if AVCC is on VIN3 */
3118                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3119                 if (reg & BIT(0)) {
3120                         /* For it8686, the bit just enables AVCC3 */
3121                         if (sio_data->type != it8686)
3122                                 sio_data->internal |= BIT(0);
3123                 } else {
3124                         sio_data->internal &= ~BIT(3);
3125                         sio_data->skip_in |= BIT(9);
3126                 }
3127
3128                 sio_data->beep_pin = superio_inb(sioaddr,
3129                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3130         } else if (sio_data->type == it8622) {
3131                 int reg;
3132
3133                 superio_select(sioaddr, GPIO);
3134
3135                 /* Check for pwm4, fan4 */
3136                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3137                 if (reg & BIT(6))
3138                         sio_data->skip_fan |= BIT(3);
3139                 if (reg & BIT(5))
3140                         sio_data->skip_pwm |= BIT(3);
3141
3142                 /* Check for pwm3, fan3, pwm5, fan5 */
3143                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3144                 if (reg & BIT(6))
3145                         sio_data->skip_pwm |= BIT(2);
3146                 if (reg & BIT(7))
3147                         sio_data->skip_fan |= BIT(2);
3148                 if (reg & BIT(3))
3149                         sio_data->skip_pwm |= BIT(4);
3150                 if (reg & BIT(1))
3151                         sio_data->skip_fan |= BIT(4);
3152
3153                 /* Check for pwm2, fan2 */
3154                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3155                 if (reg & BIT(1))
3156                         sio_data->skip_pwm |= BIT(1);
3157                 if (reg & BIT(2))
3158                         sio_data->skip_fan |= BIT(1);
3159
3160                 /* Check for AVCC */
3161                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3162                 if (!(reg & BIT(0)))
3163                         sio_data->skip_in |= BIT(9);
3164
3165                 sio_data->beep_pin = superio_inb(sioaddr,
3166                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3167         } else if (sio_data->type == it8732) {
3168                 int reg;
3169
3170                 superio_select(sioaddr, GPIO);
3171
3172                 /* Check for pwm2, fan2 */
3173                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3174                 if (reg & BIT(1))
3175                         sio_data->skip_pwm |= BIT(1);
3176                 if (reg & BIT(2))
3177                         sio_data->skip_fan |= BIT(1);
3178
3179                 /* Check for pwm3, fan3, fan4 */
3180                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3181                 if (reg & BIT(6))
3182                         sio_data->skip_pwm |= BIT(2);
3183                 if (reg & BIT(7))
3184                         sio_data->skip_fan |= BIT(2);
3185                 if (reg & BIT(5))
3186                         sio_data->skip_fan |= BIT(3);
3187
3188                 /* Check if AVCC is on VIN3 */
3189                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3190                 if (reg & BIT(0))
3191                         sio_data->internal |= BIT(0);
3192
3193                 sio_data->beep_pin = superio_inb(sioaddr,
3194                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3195         } else if (sio_data->type == it8655) {
3196                 int reg;
3197
3198                 superio_select(sioaddr, GPIO);
3199
3200                 /* Check for pwm2 */
3201                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3202                 if (reg & BIT(1))
3203                         sio_data->skip_pwm |= BIT(1);
3204
3205                 /* Check for fan2 */
3206                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3207                 if (reg & BIT(4))
3208                         sio_data->skip_fan |= BIT(1);
3209
3210                 /* Check for pwm3, fan3 */
3211                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3212                 if (reg & BIT(6))
3213                         sio_data->skip_pwm |= BIT(2);
3214                 if (reg & BIT(7))
3215                         sio_data->skip_fan |= BIT(2);
3216
3217                 sio_data->beep_pin = superio_inb(sioaddr,
3218                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3219         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3220                 int reg27, reg29, reg2d, regd3;
3221
3222                 superio_select(sioaddr, GPIO);
3223
3224                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3225                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3226                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3227                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3228
3229                 /* Check for pwm2, fan2 */
3230                 if (reg29 & BIT(1))
3231                         sio_data->skip_pwm |= BIT(1);
3232                 if (reg2d & BIT(4))
3233                         sio_data->skip_fan |= BIT(1);
3234
3235                 /* Check for pwm3, fan3 */
3236                 if (reg27 & BIT(6))
3237                         sio_data->skip_pwm |= BIT(2);
3238                 if (reg27 & BIT(7))
3239                         sio_data->skip_fan |= BIT(2);
3240
3241                 /* Check for pwm4, fan4, pwm5, fan5 */
3242                 if (sio_data->type == it8625) {
3243                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3244
3245                         if (reg25 & BIT(6))
3246                                 sio_data->skip_fan |= BIT(3);
3247                         if (reg25 & BIT(5))
3248                                 sio_data->skip_pwm |= BIT(3);
3249                         if (reg27 & BIT(3))
3250                                 sio_data->skip_pwm |= BIT(4);
3251                         if (reg27 & BIT(1))
3252                                 sio_data->skip_fan |= BIT(4);
3253                 } else {
3254                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3255
3256                         if (regd3 & BIT(2))
3257                                 sio_data->skip_pwm |= BIT(3);
3258                         if (regd3 & BIT(3))
3259                                 sio_data->skip_fan |= BIT(3);
3260                         if (reg26 & BIT(5))
3261                                 sio_data->skip_pwm |= BIT(4);
3262                         if (!(reg26 & BIT(4)))
3263                                 sio_data->skip_fan |= BIT(4);
3264                 }
3265
3266                 /* Check for pwm6, fan6 */
3267                 if (regd3 & BIT(0))
3268                         sio_data->skip_pwm |= BIT(5);
3269                 if (regd3 & BIT(1))
3270                         sio_data->skip_fan |= BIT(5);
3271
3272                 sio_data->beep_pin = superio_inb(sioaddr,
3273                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3274         } else {
3275                 int reg;
3276                 bool uart6;
3277
3278                 superio_select(sioaddr, GPIO);
3279
3280                 /* Check for fan4, fan5 */
3281                 if (has_five_fans(config)) {
3282                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3283                         switch (sio_data->type) {
3284                         case it8718:
3285                                 if (reg & BIT(5))
3286                                         sio_data->skip_fan |= BIT(3);
3287                                 if (reg & BIT(4))
3288                                         sio_data->skip_fan |= BIT(4);
3289                                 break;
3290                         case it8720:
3291                         case it8721:
3292                         case it8728:
3293                                 if (!(reg & BIT(5)))
3294                                         sio_data->skip_fan |= BIT(3);
3295                                 if (!(reg & BIT(4)))
3296                                         sio_data->skip_fan |= BIT(4);
3297                                 break;
3298                         default:
3299                                 break;
3300                         }
3301                 }
3302
3303                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3304                 if (!sio_data->skip_vid) {
3305                         /* We need at least 4 VID pins */
3306                         if (reg & 0x0f) {
3307                                 pr_info("VID is disabled (pins used for GPIO)\n");
3308                                 sio_data->skip_vid = 1;
3309                         }
3310                 }
3311
3312                 /* Check if fan3 is there or not */
3313                 if (reg & BIT(6))
3314                         sio_data->skip_pwm |= BIT(2);
3315                 if (reg & BIT(7))
3316                         sio_data->skip_fan |= BIT(2);
3317
3318                 /* Check if fan2 is there or not */
3319                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3320                 if (reg & BIT(1))
3321                         sio_data->skip_pwm |= BIT(1);
3322                 if (reg & BIT(2))
3323                         sio_data->skip_fan |= BIT(1);
3324
3325                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3326                     !(sio_data->skip_vid))
3327                         sio_data->vid_value = superio_inb(sioaddr,
3328                                                           IT87_SIO_VID_REG);
3329
3330                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3331
3332                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3333
3334                 /*
3335                  * The IT8720F has no VIN7 pin, so VCCH should always be
3336                  * routed internally to VIN7 with an internal divider.
3337                  * Curiously, there still is a configuration bit to control
3338                  * this, which means it can be set incorrectly. And even
3339                  * more curiously, many boards out there are improperly
3340                  * configured, even though the IT8720F datasheet claims
3341                  * that the internal routing of VCCH to VIN7 is the default
3342                  * setting. So we force the internal routing in this case.
3343                  *
3344                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3345                  * If UART6 is enabled, re-route VIN7 to the internal divider
3346                  * if that is not already the case.
3347                  */
3348                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3349                         reg |= BIT(1);
3350                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3351                         pr_notice("Routing internal VCCH to in7\n");
3352                 }
3353                 if (reg & BIT(0))
3354                         sio_data->internal |= BIT(0);
3355                 if (reg & BIT(1))
3356                         sio_data->internal |= BIT(1);
3357
3358                 /*
3359                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3360                  * While VIN7 can be routed to the internal voltage divider,
3361                  * VIN5 and VIN6 are not available if UART6 is enabled.
3362                  *
3363                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3364                  * is the temperature source. Since we can not read the
3365                  * temperature source here, skip_temp is preliminary.
3366                  */
3367                 if (uart6) {
3368                         sio_data->skip_in |= BIT(5) | BIT(6);
3369                         sio_data->skip_temp |= BIT(2);
3370                 }
3371
3372                 sio_data->beep_pin = superio_inb(sioaddr,
3373                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3374         }
3375         if (sio_data->beep_pin)
3376                 pr_info("Beeping is supported\n");
3377
3378 exit:
3379         superio_exit(sioaddr, doexit);
3380         return err;
3381 }
3382
3383 static void it87_init_regs(struct platform_device *pdev)
3384 {
3385         struct it87_data *data = platform_get_drvdata(pdev);
3386
3387         /* Initialize chip specific register pointers */
3388         switch (data->type) {
3389         case it8628:
3390         case it8686:
3391                 data->REG_FAN = IT87_REG_FAN;
3392                 data->REG_FANX = IT87_REG_FANX;
3393                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3394                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3395                 data->REG_PWM = IT87_REG_PWM;
3396                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3397                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3398                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3399                 break;
3400         case it8625:
3401         case it8655:
3402         case it8665:
3403                 data->REG_FAN = IT87_REG_FAN_8665;
3404                 data->REG_FANX = IT87_REG_FANX_8665;
3405                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3406                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3407                 data->REG_PWM = IT87_REG_PWM_8665;
3408                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3409                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3410                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3411                 break;
3412         case it8622:
3413                 data->REG_FAN = IT87_REG_FAN;
3414                 data->REG_FANX = IT87_REG_FANX;
3415                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3416                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3417                 data->REG_PWM = IT87_REG_PWM_8665;
3418                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3419                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3420                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3421                 break;
3422         case it8613:
3423                 data->REG_FAN = IT87_REG_FAN;
3424                 data->REG_FANX = IT87_REG_FANX;
3425                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3426                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3427                 data->REG_PWM = IT87_REG_PWM_8665;
3428                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3429                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3430                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3431                 break;
3432         default:
3433                 data->REG_FAN = IT87_REG_FAN;
3434                 data->REG_FANX = IT87_REG_FANX;
3435                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3436                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3437                 data->REG_PWM = IT87_REG_PWM;
3438                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3439                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3440                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3441                 break;
3442         }
3443 }
3444
3445 /* Called when we have found a new IT87. */
3446 static void it87_init_device(struct platform_device *pdev)
3447 {
3448         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3449         struct it87_data *data = platform_get_drvdata(pdev);
3450         int tmp, i;
3451         u8 mask;
3452
3453         if (has_new_tempmap(data)) {
3454                 data->pwm_temp_map_shift = 3;
3455                 data->pwm_temp_map_mask = 0x07;
3456         } else {
3457                 data->pwm_temp_map_shift = 0;
3458                 data->pwm_temp_map_mask = 0x03;
3459         }
3460
3461         /*
3462          * For each PWM channel:
3463          * - If it is in automatic mode, setting to manual mode should set
3464          *   the fan to full speed by default.
3465          * - If it is in manual mode, we need a mapping to temperature
3466          *   channels to use when later setting to automatic mode later.
3467          *   Map to the first sensor by default (we are clueless.)
3468          * In both cases, the value can (and should) be changed by the user
3469          * prior to switching to a different mode.
3470          * Note that this is no longer needed for the IT8721F and later, as
3471          * these have separate registers for the temperature mapping and the
3472          * manual duty cycle.
3473          */
3474         for (i = 0; i < NUM_AUTO_PWM; i++) {
3475                 data->pwm_temp_map[i] = 0;
3476                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3477                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3478         }
3479
3480         /*
3481          * Some chips seem to have default value 0xff for all limit
3482          * registers. For low voltage limits it makes no sense and triggers
3483          * alarms, so change to 0 instead. For high temperature limits, it
3484          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3485          * but is still confusing, so change to 127 degrees C.
3486          */
3487         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3488                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3489                 if (tmp == 0xff)
3490                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3491         }
3492         for (i = 0; i < data->num_temp_limit; i++) {
3493                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3494                 if (tmp == 0xff)
3495                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3496         }
3497
3498         /*
3499          * Temperature channels are not forcibly enabled, as they can be
3500          * set to two different sensor types and we can't guess which one
3501          * is correct for a given system. These channels can be enabled at
3502          * run-time through the temp{1-3}_type sysfs accessors if needed.
3503          */
3504
3505         /* Check if voltage monitors are reset manually or by some reason */
3506         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3507         if ((tmp & 0xff) == 0) {
3508                 /* Enable all voltage monitors */
3509                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3510         }
3511
3512         /* Check if tachometers are reset manually or by some reason */
3513         mask = 0x70 & ~(sio_data->skip_fan << 4);
3514         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3515         if ((data->fan_main_ctrl & mask) == 0) {
3516                 /* Enable all fan tachometers */
3517                 data->fan_main_ctrl |= mask;
3518                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3519                                  data->fan_main_ctrl);
3520         }
3521         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3522
3523         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3524
3525         /* Set tachometers to 16-bit mode if needed */
3526         if (has_fan16_config(data)) {
3527                 if (~tmp & 0x07 & data->has_fan) {
3528                         dev_dbg(&pdev->dev,
3529                                 "Setting fan1-3 to 16-bit mode\n");
3530                         it87_write_value(data, IT87_REG_FAN_16BIT,
3531                                          tmp | 0x07);
3532                 }
3533         }
3534
3535         /* Check for additional fans */
3536         if (has_four_fans(data) && (tmp & BIT(4)))
3537                 data->has_fan |= BIT(3); /* fan4 enabled */
3538         if (has_five_fans(data) && (tmp & BIT(5)))
3539                 data->has_fan |= BIT(4); /* fan5 enabled */
3540         if (has_six_fans(data)) {
3541                 switch (data->type) {
3542                 case it8620:
3543                 case it8628:
3544                 case it8686:
3545                         if (tmp & BIT(2))
3546                                 data->has_fan |= BIT(5); /* fan6 enabled */
3547                         break;
3548                 case it8625:
3549                 case it8665:
3550                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3551                         if (tmp & BIT(3))
3552                                 data->has_fan |= BIT(5); /* fan6 enabled */
3553                         break;
3554                 default:
3555                         break;
3556                 }
3557         }
3558
3559         /* Fan input pins may be used for alternative functions */
3560         data->has_fan &= ~sio_data->skip_fan;
3561
3562         /* Check if pwm6 is enabled */
3563         if (has_six_pwm(data)) {
3564                 switch (data->type) {
3565                 case it8620:
3566                 case it8686:
3567                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3568                         if (!(tmp & BIT(3)))
3569                                 sio_data->skip_pwm |= BIT(5);
3570                         break;
3571                 default:
3572                         break;
3573                 }
3574         }
3575
3576         /* Start monitoring */
3577         it87_write_value(data, IT87_REG_CONFIG,
3578                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3579                          | (update_vbat ? 0x41 : 0x01));
3580 }
3581
3582 /* Return 1 if and only if the PWM interface is safe to use */
3583 static int it87_check_pwm(struct device *dev)
3584 {
3585         struct it87_data *data = dev_get_drvdata(dev);
3586         /*
3587          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3588          * and polarity set to active low is sign that this is the case so we
3589          * disable pwm control to protect the user.
3590          */
3591         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3592
3593         if ((tmp & 0x87) == 0) {
3594                 if (fix_pwm_polarity) {
3595                         /*
3596                          * The user asks us to attempt a chip reconfiguration.
3597                          * This means switching to active high polarity and
3598                          * inverting all fan speed values.
3599                          */
3600                         int i;
3601                         u8 pwm[3];
3602
3603                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3604                                 pwm[i] = it87_read_value(data,
3605                                                          data->REG_PWM[i]);
3606
3607                         /*
3608                          * If any fan is in automatic pwm mode, the polarity
3609                          * might be correct, as suspicious as it seems, so we
3610                          * better don't change anything (but still disable the
3611                          * PWM interface).
3612                          */
3613                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3614                                 dev_info(dev,
3615                                          "Reconfiguring PWM to active high polarity\n");
3616                                 it87_write_value(data, IT87_REG_FAN_CTL,
3617                                                  tmp | 0x87);
3618                                 for (i = 0; i < 3; i++)
3619                                         it87_write_value(data,
3620                                                          data->REG_PWM[i],
3621                                                          0x7f & ~pwm[i]);
3622                                 return 1;
3623                         }
3624
3625                         dev_info(dev,
3626                                  "PWM configuration is too broken to be fixed\n");
3627                 }
3628
3629                 dev_info(dev,
3630                          "Detected broken BIOS defaults, disabling PWM interface\n");
3631                 return 0;
3632         } else if (fix_pwm_polarity) {
3633                 dev_info(dev,
3634                          "PWM configuration looks sane, won't touch\n");
3635         }
3636
3637         return 1;
3638 }
3639
3640 static int it87_probe(struct platform_device *pdev)
3641 {
3642         struct it87_data *data;
3643         struct resource *res;
3644         struct device *dev = &pdev->dev;
3645         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3646         int enable_pwm_interface;
3647         struct device *hwmon_dev;
3648
3649         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3650         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3651                                  DRVNAME)) {
3652                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3653                         (unsigned long)res->start,
3654                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3655                 return -EBUSY;
3656         }
3657
3658         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3659         if (!data)
3660                 return -ENOMEM;
3661
3662         data->addr = res->start;
3663         data->type = sio_data->type;
3664         data->features = it87_devices[sio_data->type].features;
3665         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3666         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3667         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3668         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3669         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3670         data->bank = 0xff;
3671
3672         /*
3673          * IT8705F Datasheet 0.4.1, 3h == Version G.
3674          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3675          * These are the first revisions with 16-bit tachometer support.
3676          */
3677         switch (data->type) {
3678         case it87:
3679                 if (sio_data->revision >= 0x03) {
3680                         data->features &= ~FEAT_OLD_AUTOPWM;
3681                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3682                 }
3683                 break;
3684         case it8712:
3685                 if (sio_data->revision >= 0x08) {
3686                         data->features &= ~FEAT_OLD_AUTOPWM;
3687                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3688                                           FEAT_FIVE_FANS;
3689                 }
3690                 break;
3691         default:
3692                 break;
3693         }
3694
3695         /* Now, we do the remaining detection. */
3696         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3697             it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3698                 return -ENODEV;
3699
3700         platform_set_drvdata(pdev, data);
3701
3702         mutex_init(&data->update_lock);
3703
3704         /* Initialize register pointers */
3705         it87_init_regs(pdev);
3706
3707         /* Check PWM configuration */
3708         enable_pwm_interface = it87_check_pwm(dev);
3709
3710         /* Starting with IT8721F, we handle scaling of internal voltages */
3711         if (has_scaling(data)) {
3712                 if (sio_data->internal & BIT(0))
3713                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3714                 if (sio_data->internal & BIT(1))
3715                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3716                 if (sio_data->internal & BIT(2))
3717                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3718                 if (sio_data->internal & BIT(3))
3719                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3720         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3721                    sio_data->type == it8783) {
3722                 if (sio_data->internal & BIT(0))
3723                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3724                 if (sio_data->internal & BIT(1))
3725                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3726         }
3727
3728         data->has_temp = 0x07;
3729         if (sio_data->skip_temp & BIT(2)) {
3730                 if (sio_data->type == it8782 &&
3731                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3732                         data->has_temp &= ~BIT(2);
3733         }
3734
3735         data->in_internal = sio_data->internal;
3736         data->has_in = 0x3ff & ~sio_data->skip_in;
3737
3738         if (has_six_temp(data)) {
3739                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3740
3741                 /* Check for additional temperature sensors */
3742                 if ((reg & 0x03) >= 0x02)
3743                         data->has_temp |= BIT(3);
3744                 if (((reg >> 2) & 0x03) >= 0x02)
3745                         data->has_temp |= BIT(4);
3746                 if (((reg >> 4) & 0x03) >= 0x02)
3747                         data->has_temp |= BIT(5);
3748
3749                 /* Check for additional voltage sensors */
3750                 if ((reg & 0x03) == 0x01)
3751                         data->has_in |= BIT(10);
3752                 if (((reg >> 2) & 0x03) == 0x01)
3753                         data->has_in |= BIT(11);
3754                 if (((reg >> 4) & 0x03) == 0x01)
3755                         data->has_in |= BIT(12);
3756         }
3757
3758         data->has_beep = !!sio_data->beep_pin;
3759
3760         /* Initialize the IT87 chip */
3761         it87_init_device(pdev);
3762
3763         if (!sio_data->skip_vid) {
3764                 data->has_vid = true;
3765                 data->vrm = vid_which_vrm();
3766                 /* VID reading from Super-I/O config space if available */
3767                 data->vid = sio_data->vid_value;
3768         }
3769
3770         /* Prepare for sysfs hooks */
3771         data->groups[0] = &it87_group;
3772         data->groups[1] = &it87_group_in;
3773         data->groups[2] = &it87_group_temp;
3774         data->groups[3] = &it87_group_fan;
3775
3776         if (enable_pwm_interface) {
3777                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3778                 data->has_pwm &= ~sio_data->skip_pwm;
3779
3780                 data->groups[4] = &it87_group_pwm;
3781                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3782                         data->groups[5] = &it87_group_auto_pwm;
3783         }
3784
3785         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3786                                         it87_devices[sio_data->type].name,
3787                                         data, data->groups);
3788         return PTR_ERR_OR_ZERO(hwmon_dev);
3789 }
3790
3791 static struct platform_driver it87_driver = {
3792         .driver = {
3793                 .name   = DRVNAME,
3794         },
3795         .probe  = it87_probe,
3796 };
3797
3798 static int __init it87_device_add(int index, unsigned short address,
3799                                   const struct it87_sio_data *sio_data)
3800 {
3801         struct platform_device *pdev;
3802         struct resource res = {
3803                 .start  = address + IT87_EC_OFFSET,
3804                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3805                 .name   = DRVNAME,
3806                 .flags  = IORESOURCE_IO,
3807         };
3808         int err;
3809
3810         err = acpi_check_resource_conflict(&res);
3811         if (err) {
3812                 if (!ignore_resource_conflict)
3813                         return err;
3814         }
3815
3816         pdev = platform_device_alloc(DRVNAME, address);
3817         if (!pdev)
3818                 return -ENOMEM;
3819
3820         err = platform_device_add_resources(pdev, &res, 1);
3821         if (err) {
3822                 pr_err("Device resource addition failed (%d)\n", err);
3823                 goto exit_device_put;
3824         }
3825
3826         err = platform_device_add_data(pdev, sio_data,
3827                                        sizeof(struct it87_sio_data));
3828         if (err) {
3829                 pr_err("Platform data allocation failed\n");
3830                 goto exit_device_put;
3831         }
3832
3833         err = platform_device_add(pdev);
3834         if (err) {
3835                 pr_err("Device addition failed (%d)\n", err);
3836                 goto exit_device_put;
3837         }
3838
3839         it87_pdev[index] = pdev;
3840         return 0;
3841
3842 exit_device_put:
3843         platform_device_put(pdev);
3844         return err;
3845 }
3846
3847 struct it87_dmi_data {
3848         bool sio2_force_config; /* force sio2 into configuration mode   */
3849         u8 skip_pwm;            /* pwm channels to skip for this board  */
3850 };
3851
3852 /*
3853  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
3854  * (IT8792E) needs to be in configuration mode before accessing the first
3855  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
3856  * This needs to be done before accessing the first Super-IO chip since
3857  * the second chip may have been accessed prior to loading this driver.
3858  *
3859  * The problem is also reported to affect IT8795E, which is used on X299 boards
3860  * and has the same chip ID as IT9792E (0x8733). It also appears to affect
3861  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
3862  * Z87X-OC.
3863  * DMI entries for those systems will be added as they become available and
3864  * as the problem is confirmed to affect those boards.
3865  */
3866 static struct it87_dmi_data gigabyte_sio2_force = {
3867         .sio2_force_config = true,
3868 };
3869
3870 /*
3871  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3872  * connected to a fan, but to something else. One user
3873  * has reported instant system power-off when changing
3874  * the PWM2 duty cycle, so we disable it.
3875  * I use the board name string as the trigger in case
3876  * the same board is ever used in other systems.
3877  */
3878 static struct it87_dmi_data nvidia_fn68pt = {
3879         .skip_pwm = BIT(1),
3880 };
3881
3882 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3883         {
3884                 .matches = {
3885                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3886                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
3887                 },
3888                 .driver_data = &gigabyte_sio2_force,
3889         },
3890         {
3891                 .matches = {
3892                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3893                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
3894                 },
3895                 .driver_data = &gigabyte_sio2_force,
3896         },
3897         {
3898                 .matches = {
3899                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3900                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
3901                 },
3902                 .driver_data = &gigabyte_sio2_force,
3903         },
3904         {
3905                 .matches = {
3906                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3907                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3908                 },
3909                 .driver_data = &nvidia_fn68pt,
3910         },
3911         { }
3912 };
3913
3914 static int __init sm_it87_init(void)
3915 {
3916         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3917         struct it87_dmi_data *dmi_data = NULL;
3918         int sioaddr[2] = { REG_2E, REG_4E };
3919         struct it87_sio_data sio_data;
3920         unsigned short isa_address;
3921         bool found = false;
3922         int i, err;
3923
3924         if (dmi)
3925                 dmi_data = dmi->driver_data;
3926
3927         err = platform_driver_register(&it87_driver);
3928         if (err)
3929                 return err;
3930
3931         if (dmi_data && dmi_data->sio2_force_config)
3932                 __superio_enter(REG_4E);
3933
3934         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3935                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3936                 isa_address = 0;
3937                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3938                 if (err || isa_address == 0)
3939                         continue;
3940
3941                 if (dmi_data)
3942                         sio_data.skip_pwm |= dmi_data->skip_pwm;
3943                 err = it87_device_add(i, isa_address, &sio_data);
3944                 if (err)
3945                         goto exit_dev_unregister;
3946                 found = true;
3947         }
3948
3949         if (!found) {
3950                 err = -ENODEV;
3951                 goto exit_unregister;
3952         }
3953         return 0;
3954
3955 exit_dev_unregister:
3956         /* NULL check handled by platform_device_unregister */
3957         platform_device_unregister(it87_pdev[0]);
3958 exit_unregister:
3959         platform_driver_unregister(&it87_driver);
3960         return err;
3961 }
3962
3963 static void __exit sm_it87_exit(void)
3964 {
3965         /* NULL check handled by platform_device_unregister */
3966         platform_device_unregister(it87_pdev[1]);
3967         platform_device_unregister(it87_pdev[0]);
3968         platform_driver_unregister(&it87_driver);
3969 }
3970
3971 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3972 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3973 module_param(update_vbat, bool, 0);
3974 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3975 module_param(fix_pwm_polarity, bool, 0);
3976 MODULE_PARM_DESC(fix_pwm_polarity,
3977                  "Force PWM polarity to active high (DANGEROUS)");
3978 MODULE_LICENSE("GPL");
3979
3980 module_init(sm_it87_init);
3981 module_exit(sm_it87_exit);