git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77
  78 #define DRVNAME "it87"
  79
  80 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  81              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  82              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  83              it8655, it8665, it8686 };
  84
  85 static unsigned short force_id;
  86 module_param(force_id, ushort, 0);
  87 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  88
  89 static bool ignore_resource_conflict;
  90 module_param(ignore_resource_conflict, bool, 0);
  91 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
  92
  93 static struct platform_device *it87_pdev[2];
  94
  95 #define REG_2E  0x2e    /* The register to read/write */
  96 #define REG_4E  0x4e    /* Secondary register to read/write */
  97
  98 #define DEV     0x07    /* Register: Logical device select */
  99 #define PME     0x04    /* The device with the fan registers in it */
 100
 101 /* The device with the IT8718F/IT8720F VID value in it */
 102 #define GPIO    0x07
 103
 104 #define DEVID   0x20    /* Register: Device ID */
 105 #define DEVREV  0x22    /* Register: Device Revision */
 106
 107 static inline void __superio_enter(int ioreg)
 108 {
 109         outb(0x87, ioreg);
 110         outb(0x01, ioreg);
 111         outb(0x55, ioreg);
 112         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 113 }
 114
 115 static inline int superio_inb(int ioreg, int reg)
 116 {
 117         int val;
 118
 119         outb(reg, ioreg);
 120         val = inb(ioreg + 1);
 121
 122         return val;
 123 }
 124
 125 static inline void superio_outb(int ioreg, int reg, int val)
 126 {
 127         outb(reg, ioreg);
 128         outb(val, ioreg + 1);
 129 }
 130
 131 static int superio_inw(int ioreg, int reg)
 132 {
 133         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 134 }
 135
 136 static inline void superio_select(int ioreg, int ldn)
 137 {
 138         outb(DEV, ioreg);
 139         outb(ldn, ioreg + 1);
 140 }
 141
 142 static inline int superio_enter(int ioreg)
 143 {
 144         /*
 145          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 146          */
 147         if (!request_muxed_region(ioreg, 2, DRVNAME))
 148                 goto error;
 149
 150         __superio_enter(ioreg);
 151         return 0;
 152
 153 error:
 154         return -EBUSY;
 155 }
 156
 157 static inline void superio_exit(int ioreg, bool doexit)
 158 {
 159         if (doexit) {
 160                 outb(0x02, ioreg);
 161                 outb(0x02, ioreg + 1);
 162         }
 163         release_region(ioreg, 2);
 164 }
 165
 166 /* Logical device 4 registers */
 167 #define IT8712F_DEVID 0x8712
 168 #define IT8705F_DEVID 0x8705
 169 #define IT8716F_DEVID 0x8716
 170 #define IT8718F_DEVID 0x8718
 171 #define IT8720F_DEVID 0x8720
 172 #define IT8721F_DEVID 0x8721
 173 #define IT8726F_DEVID 0x8726
 174 #define IT8728F_DEVID 0x8728
 175 #define IT8732F_DEVID 0x8732
 176 #define IT8792E_DEVID 0x8733
 177 #define IT8771E_DEVID 0x8771
 178 #define IT8772E_DEVID 0x8772
 179 #define IT8781F_DEVID 0x8781
 180 #define IT8782F_DEVID 0x8782
 181 #define IT8783E_DEVID 0x8783
 182 #define IT8786E_DEVID 0x8786
 183 #define IT8790E_DEVID 0x8790
 184 #define IT8603E_DEVID 0x8603
 185 #define IT8607E_DEVID 0x8607
 186 #define IT8613E_DEVID 0x8613
 187 #define IT8620E_DEVID 0x8620
 188 #define IT8622E_DEVID 0x8622
 189 #define IT8623E_DEVID 0x8623
 190 #define IT8625E_DEVID 0x8625
 191 #define IT8628E_DEVID 0x8628
 192 #define IT8655E_DEVID 0x8655
 193 #define IT8665E_DEVID 0x8665
 194 #define IT8686E_DEVID 0x8686
 195 #define IT87_ACT_REG  0x30
 196 #define IT87_BASE_REG 0x60
 197
 198 /* Logical device 7 registers (IT8712F and later) */
 199 #define IT87_SIO_GPIO1_REG      0x25
 200 #define IT87_SIO_GPIO2_REG      0x26
 201 #define IT87_SIO_GPIO3_REG      0x27
 202 #define IT87_SIO_GPIO4_REG      0x28
 203 #define IT87_SIO_GPIO5_REG      0x29
 204 #define IT87_SIO_GPIO9_REG      0xd3
 205 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 206 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 207 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 208 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 209 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 210 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 211
 212 /* Update battery voltage after every reading if true */
 213 static bool update_vbat;
 214
 215 /* Not all BIOSes properly configure the PWM registers */
 216 static bool fix_pwm_polarity;
 217
 218 /* Many IT87 constants specified below */
 219
 220 /* Length of ISA address segment */
 221 #define IT87_EXTENT 8
 222
 223 /* Length of ISA address segment for Environmental Controller */
 224 #define IT87_EC_EXTENT 2
 225
 226 /* Offset of EC registers from ISA base address */
 227 #define IT87_EC_OFFSET 5
 228
 229 /* Where are the ISA address/data registers relative to the EC base address */
 230 #define IT87_ADDR_REG_OFFSET 0
 231 #define IT87_DATA_REG_OFFSET 1
 232
 233 /*----- The IT87 registers -----*/
 234
 235 #define IT87_REG_CONFIG        0x00
 236
 237 #define IT87_REG_ALARM1        0x01
 238 #define IT87_REG_ALARM2        0x02
 239 #define IT87_REG_ALARM3        0x03
 240
 241 #define IT87_REG_BANK           0x06
 242
 243 /*
 244  * The IT8718F and IT8720F have the VID value in a different register, in
 245  * Super-I/O configuration space.
 246  */
 247 #define IT87_REG_VID           0x0a
 248 /*
 249  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 250  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 251  * mode.
 252  */
 253 #define IT87_REG_FAN_DIV       0x0b
 254 #define IT87_REG_FAN_16BIT     0x0c
 255
 256 /*
 257  * Monitors:
 258  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 259  * - up to 6 temp (1 to 6)
 260  * - up to 6 fan (1 to 6)
 261  */
 262
 263 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 264 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 265 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 266 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 267
 268 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 269 static const u8 IT87_REG_FAN_MIN_8665[] =
 270                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 271 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 272 static const u8 IT87_REG_FANX_MIN_8665[] =
 273                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 274
 275 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 276
 277 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 278
 279 #define IT87_REG_FAN_MAIN_CTRL 0x13
 280 #define IT87_REG_FAN_CTL       0x14
 281
 282 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 283 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 284
 285 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 286
 287 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 288                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 289
 290 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 291
 292 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 293 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 294
 295 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 296 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 297
 298 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 299                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 300 static const u8 IT87_REG_TEMP_LOW_8686[] =
 301                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 302
 303 #define IT87_REG_VIN_ENABLE    0x50
 304 #define IT87_REG_TEMP_ENABLE   0x51
 305 #define IT87_REG_TEMP_EXTRA    0x55
 306 #define IT87_REG_BEEP_ENABLE   0x5c
 307
 308 #define IT87_REG_CHIPID        0x58
 309
 310 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 311
 312 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 313 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 314
 315 #define IT87_REG_TEMP456_ENABLE 0x77
 316
 317 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 318 #define IT87_REG_TEMP_SRC2      0x23d
 319
 320 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 321 #define NUM_VIN_LIMIT           8
 322 #define NUM_TEMP                6
 323 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 324 #define NUM_FAN_DIV             3
 325 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 326 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 327
 328 struct it87_devices {
 329         const char *name;
 330         const char * const suffix;
 331         u32 features;
 332         u8 num_temp_limit;
 333         u8 num_temp_offset;
 334         u8 num_temp_map;        /* Number of temperature sources for pwm */
 335         u8 peci_mask;
 336         u8 old_peci_mask;
 337 };
 338
 339 #define FEAT_12MV_ADC           BIT(0)
 340 #define FEAT_NEWER_AUTOPWM      BIT(1)
 341 #define FEAT_OLD_AUTOPWM        BIT(2)
 342 #define FEAT_16BIT_FANS         BIT(3)
 343 #define FEAT_TEMP_PECI          BIT(5)
 344 #define FEAT_TEMP_OLD_PECI      BIT(6)
 345 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 346 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 347 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 348 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 349 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 350 #define FEAT_10_9MV_ADC         BIT(12)
 351 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 352 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 353 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 354 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 355 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 356 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 357 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 358 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 359 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 360 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 361 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 362 #define FEAT_11MV_ADC           BIT(24)
 363 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 364
 365 static const struct it87_devices it87_devices[] = {
 366         [it87] = {
 367                 .name = "it87",
 368                 .suffix = "F",
 369                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 370                                                 /* may need to overwrite */
 371                 .num_temp_limit = 3,
 372                 .num_temp_offset = 0,
 373                 .num_temp_map = 3,
 374         },
 375         [it8712] = {
 376                 .name = "it8712",
 377                 .suffix = "F",
 378                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 379                                                 /* may need to overwrite */
 380                 .num_temp_limit = 3,
 381                 .num_temp_offset = 0,
 382                 .num_temp_map = 3,
 383         },
 384         [it8716] = {
 385                 .name = "it8716",
 386                 .suffix = "F",
 387                 .features = FEAT_16BIT_FANS | FEAT_VID
 388                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 389                   | FEAT_FANCTL_ONOFF,
 390                 .num_temp_limit = 3,
 391                 .num_temp_offset = 3,
 392                 .num_temp_map = 3,
 393         },
 394         [it8718] = {
 395                 .name = "it8718",
 396                 .suffix = "F",
 397                 .features = FEAT_16BIT_FANS | FEAT_VID
 398                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 399                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 400                 .num_temp_limit = 3,
 401                 .num_temp_offset = 3,
 402                 .num_temp_map = 3,
 403                 .old_peci_mask = 0x4,
 404         },
 405         [it8720] = {
 406                 .name = "it8720",
 407                 .suffix = "F",
 408                 .features = FEAT_16BIT_FANS | FEAT_VID
 409                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 410                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 411                 .num_temp_limit = 3,
 412                 .num_temp_offset = 3,
 413                 .num_temp_map = 3,
 414                 .old_peci_mask = 0x4,
 415         },
 416         [it8721] = {
 417                 .name = "it8721",
 418                 .suffix = "F",
 419                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 420                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 421                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 422                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 423                 .num_temp_limit = 3,
 424                 .num_temp_offset = 3,
 425                 .num_temp_map = 3,
 426                 .peci_mask = 0x05,
 427                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 428         },
 429         [it8728] = {
 430                 .name = "it8728",
 431                 .suffix = "F",
 432                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 433                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 434                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 435                   | FEAT_FANCTL_ONOFF,
 436                 .num_temp_limit = 6,
 437                 .num_temp_offset = 3,
 438                 .num_temp_map = 3,
 439                 .peci_mask = 0x07,
 440         },
 441         [it8732] = {
 442                 .name = "it8732",
 443                 .suffix = "F",
 444                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 445                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 446                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 447                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 448                 .num_temp_limit = 3,
 449                 .num_temp_offset = 3,
 450                 .num_temp_map = 3,
 451                 .peci_mask = 0x07,
 452                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 453         },
 454         [it8771] = {
 455                 .name = "it8771",
 456                 .suffix = "E",
 457                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 458                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 459                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 460                                 /* PECI: guesswork */
 461                                 /* 12mV ADC (OHM) */
 462                                 /* 16 bit fans (OHM) */
 463                                 /* three fans, always 16 bit (guesswork) */
 464                 .num_temp_limit = 3,
 465                 .num_temp_offset = 3,
 466                 .num_temp_map = 3,
 467                 .peci_mask = 0x07,
 468         },
 469         [it8772] = {
 470                 .name = "it8772",
 471                 .suffix = "E",
 472                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 473                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 474                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 475                                 /* PECI (coreboot) */
 476                                 /* 12mV ADC (HWSensors4, OHM) */
 477                                 /* 16 bit fans (HWSensors4, OHM) */
 478                                 /* three fans, always 16 bit (datasheet) */
 479                 .num_temp_limit = 3,
 480                 .num_temp_offset = 3,
 481                 .num_temp_map = 3,
 482                 .peci_mask = 0x07,
 483         },
 484         [it8781] = {
 485                 .name = "it8781",
 486                 .suffix = "F",
 487                 .features = FEAT_16BIT_FANS
 488                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 489                   | FEAT_FANCTL_ONOFF,
 490                 .num_temp_limit = 3,
 491                 .num_temp_offset = 3,
 492                 .num_temp_map = 3,
 493                 .old_peci_mask = 0x4,
 494         },
 495         [it8782] = {
 496                 .name = "it8782",
 497                 .suffix = "F",
 498                 .features = FEAT_16BIT_FANS
 499                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 500                   | FEAT_FANCTL_ONOFF,
 501                 .num_temp_limit = 3,
 502                 .num_temp_offset = 3,
 503                 .num_temp_map = 3,
 504                 .old_peci_mask = 0x4,
 505         },
 506         [it8783] = {
 507                 .name = "it8783",
 508                 .suffix = "E/F",
 509                 .features = FEAT_16BIT_FANS
 510                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 511                   | FEAT_FANCTL_ONOFF,
 512                 .num_temp_limit = 3,
 513                 .num_temp_offset = 3,
 514                 .num_temp_map = 3,
 515                 .old_peci_mask = 0x4,
 516         },
 517         [it8786] = {
 518                 .name = "it8786",
 519                 .suffix = "E",
 520                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 521                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 522                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 523                 .num_temp_limit = 3,
 524                 .num_temp_offset = 3,
 525                 .num_temp_map = 3,
 526                 .peci_mask = 0x07,
 527         },
 528         [it8790] = {
 529                 .name = "it8790",
 530                 .suffix = "E",
 531                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 532                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 533                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 534                 .num_temp_limit = 3,
 535                 .num_temp_offset = 3,
 536                 .num_temp_map = 3,
 537                 .peci_mask = 0x07,
 538         },
 539         [it8792] = {
 540                 .name = "it8792",
 541                 .suffix = "E",
 542                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 543                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 544                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 545                 .num_temp_limit = 3,
 546                 .num_temp_offset = 3,
 547                 .num_temp_map = 3,
 548                 .peci_mask = 0x07,
 549         },
 550         [it8603] = {
 551                 .name = "it8603",
 552                 .suffix = "E",
 553                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 554                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 555                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 556                 .num_temp_limit = 3,
 557                 .num_temp_offset = 3,
 558                 .num_temp_map = 4,
 559                 .peci_mask = 0x07,
 560         },
 561         [it8607] = {
 562                 .name = "it8607",
 563                 .suffix = "E",
 564                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 565                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 566                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 567                   | FEAT_FANCTL_ONOFF,
 568                 .num_temp_limit = 3,
 569                 .num_temp_offset = 3,
 570                 .num_temp_map = 6,
 571                 .peci_mask = 0x07,
 572         },
 573         [it8613] = {
 574                 .name = "it8613",
 575                 .suffix = "E",
 576                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 577                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 578                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 579                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 580                 .num_temp_limit = 6,
 581                 .num_temp_offset = 6,
 582                 .num_temp_map = 6,
 583                 .peci_mask = 0x07,
 584         },
 585         [it8620] = {
 586                 .name = "it8620",
 587                 .suffix = "E",
 588                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 589                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 590                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 591                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 592                   | FEAT_FANCTL_ONOFF,
 593                 .num_temp_limit = 3,
 594                 .num_temp_offset = 3,
 595                 .num_temp_map = 3,
 596                 .peci_mask = 0x07,
 597         },
 598         [it8622] = {
 599                 .name = "it8622",
 600                 .suffix = "E",
 601                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 602                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 603                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 604                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 605                 .num_temp_limit = 3,
 606                 .num_temp_offset = 3,
 607                 .num_temp_map = 4,
 608                 .peci_mask = 0x07,
 609         },
 610         [it8625] = {
 611                 .name = "it8625",
 612                 .suffix = "E",
 613                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 614                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 615                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 616                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 617                 .num_temp_limit = 6,
 618                 .num_temp_offset = 6,
 619                 .num_temp_map = 6,
 620         },
 621         [it8628] = {
 622                 .name = "it8628",
 623                 .suffix = "E",
 624                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 625                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 626                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 627                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 628                   | FEAT_FANCTL_ONOFF,
 629                 .num_temp_limit = 6,
 630                 .num_temp_offset = 3,
 631                 .num_temp_map = 3,
 632                 .peci_mask = 0x07,
 633         },
 634         [it8655] = {
 635                 .name = "it8655",
 636                 .suffix = "E",
 637                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 638                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 639                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
 640                 .num_temp_limit = 6,
 641                 .num_temp_offset = 6,
 642                 .num_temp_map = 6,
 643         },
 644         [it8665] = {
 645                 .name = "it8665",
 646                 .suffix = "E",
 647                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 648                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 649                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 650                   | FEAT_SIX_PWM | FEAT_BANK_SEL,
 651                 .num_temp_limit = 6,
 652                 .num_temp_offset = 6,
 653                 .num_temp_map = 6,
 654         },
 655         [it8686] = {
 656                 .name = "it8686",
 657                 .suffix = "E",
 658                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 659                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 660                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 661                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 662                 .num_temp_limit = 6,
 663                 .num_temp_offset = 6,
 664                 .num_temp_map = 7,
 665         },
 666 };
 667
 668 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 669 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 670 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 671 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 672 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 673 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 674                                  ((data)->peci_mask & BIT(nr)))
 675 #define has_temp_old_peci(data, nr) \
 676                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 677                                  ((data)->old_peci_mask & BIT(nr)))
 678 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 679 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 680                                                      FEAT_SIX_FANS))
 681 #define has_vid(data)           ((data)->features & FEAT_VID)
 682 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 683 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 684 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 685 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 686                                                      | FEAT_SIX_PWM))
 687 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 688 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 689 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 690 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 691 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 692                                                      FEAT_FIVE_FANS | \
 693                                                      FEAT_SIX_FANS))
 694 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 695                                                      FEAT_FIVE_PWM \
 696                                                      | FEAT_SIX_PWM))
 697 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 698 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 699 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 700 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 701 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 702
 703 struct it87_sio_data {
 704         enum chips type;
 705         /* Values read from Super-I/O config space */
 706         u8 revision;
 707         u8 vid_value;
 708         u8 beep_pin;
 709         u8 internal;    /* Internal sensors can be labeled */
 710         /* Features skipped based on config or DMI */
 711         u16 skip_in;
 712         u8 skip_vid;
 713         u8 skip_fan;
 714         u8 skip_pwm;
 715         u8 skip_temp;
 716 };
 717
 718 /*
 719  * For each registered chip, we need to keep some data in memory.
 720  * The structure is dynamically allocated.
 721  */
 722 struct it87_data {
 723         const struct attribute_group *groups[7];
 724         enum chips type;
 725         u32 features;
 726         u8 peci_mask;
 727         u8 old_peci_mask;
 728
 729         const u8 *REG_FAN;
 730         const u8 *REG_FANX;
 731         const u8 *REG_FAN_MIN;
 732         const u8 *REG_FANX_MIN;
 733
 734         const u8 *REG_PWM;
 735
 736         const u8 *REG_TEMP_OFFSET;
 737         const u8 *REG_TEMP_LOW;
 738         const u8 *REG_TEMP_HIGH;
 739
 740         unsigned short addr;
 741         const char *name;
 742         struct mutex update_lock;
 743         char valid;             /* !=0 if following fields are valid */
 744         unsigned long last_updated;     /* In jiffies */
 745
 746         u16 in_scaled;          /* Internal voltage sensors are scaled */
 747         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 748         u16 has_in;             /* Bitfield, voltage sensors enabled */
 749         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 750         u8 has_fan;             /* Bitfield, fans enabled */
 751         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 752         u8 has_temp;            /* Bitfield, temp sensors enabled */
 753         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 754         u8 num_temp_limit;      /* Number of temperature limit registers */
 755         u8 num_temp_offset;     /* Number of temperature offset registers */
 756         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 757         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 758         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 759         bool has_vid;           /* True if VID supported */
 760         u8 vid;                 /* Register encoding, combined */
 761         u8 vrm;
 762         u32 alarms;             /* Register encoding, combined */
 763         bool has_beep;          /* true if beep supported */
 764         u8 beeps;               /* Register encoding */
 765         u8 fan_main_ctrl;       /* Register value */
 766         u8 fan_ctl;             /* Register value */
 767
 768         /*
 769          * The following 3 arrays correspond to the same registers up to
 770          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 771          * 7, and we want to preserve settings on mode changes, so we have
 772          * to track all values separately.
 773          * Starting with the IT8721F, the manual PWM duty cycles are stored
 774          * in separate registers (8-bit values), so the separate tracking
 775          * is no longer needed, but it is still done to keep the driver
 776          * simple.
 777          */
 778         u8 has_pwm;             /* Bitfield, pwm control enabled */
 779         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 780         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 781         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 782         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 783         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 784         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 785
 786         /* Automatic fan speed control registers */
 787         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 788         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 789 };
 790
 791 static int adc_lsb(const struct it87_data *data, int nr)
 792 {
 793         int lsb;
 794
 795         if (has_12mv_adc(data))
 796                 lsb = 120;
 797         else if (has_10_9mv_adc(data))
 798                 lsb = 109;
 799         else if (has_11mv_adc(data))
 800                 lsb = 110;
 801         else
 802                 lsb = 160;
 803         if (data->in_scaled & BIT(nr))
 804                 lsb <<= 1;
 805         return lsb;
 806 }
 807
 808 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 809 {
 810         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 811         return clamp_val(val, 0, 255);
 812 }
 813
 814 static int in_from_reg(const struct it87_data *data, int nr, int val)
 815 {
 816         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 817 }
 818
 819 static inline u8 FAN_TO_REG(long rpm, int div)
 820 {
 821         if (rpm == 0)
 822                 return 255;
 823         rpm = clamp_val(rpm, 1, 1000000);
 824         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 825 }
 826
 827 static inline u16 FAN16_TO_REG(long rpm)
 828 {
 829         if (rpm == 0)
 830                 return 0xffff;
 831         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 832 }
 833
 834 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 835                                 1350000 / ((val) * (div)))
 836 /* The divider is fixed to 2 in 16-bit mode */
 837 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 838                              1350000 / ((val) * 2))
 839
 840 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 841                                     ((val) + 500) / 1000), -128, 127))
 842 #define TEMP_FROM_REG(val) ((val) * 1000)
 843
 844 static u8 pwm_to_reg(const struct it87_data *data, long val)
 845 {
 846         if (has_newer_autopwm(data))
 847                 return val;
 848         else
 849                 return val >> 1;
 850 }
 851
 852 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 853 {
 854         if (has_newer_autopwm(data))
 855                 return reg;
 856         else
 857                 return (reg & 0x7f) << 1;
 858 }
 859
 860 static int DIV_TO_REG(int val)
 861 {
 862         int answer = 0;
 863
 864         while (answer < 7 && (val >>= 1))
 865                 answer++;
 866         return answer;
 867 }
 868
 869 #define DIV_FROM_REG(val) BIT(val)
 870
 871 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 872 {
 873         u8 map;
 874
 875         map  = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 876         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 877                 map = 0;
 878
 879         return map;
 880 }
 881
 882 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 883 {
 884         u8 ctrl = data->pwm_ctrl[nr];
 885
 886         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 887                (map << data->pwm_temp_map_shift);
 888 }
 889
 890 /*
 891  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 892  * depending on the chip type, to calculate the actual PWM frequency.
 893  *
 894  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 895  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 896  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 897  * sometimes just one. It is unknown if this is a datasheet error or real,
 898  * so this is ignored for now.
 899  */
 900 static const unsigned int pwm_freq[8] = {
 901         48000000,
 902         24000000,
 903         12000000,
 904         8000000,
 905         6000000,
 906         3000000,
 907         1500000,
 908         750000,
 909 };
 910
 911 static int _it87_read_value(struct it87_data *data, u8 reg)
 912 {
 913         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 914         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 915 }
 916
 917 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
 918 {
 919         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 920         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 921 }
 922
 923 static u8 it87_set_bank(struct it87_data *data, u8 bank)
 924 {
 925         u8 _bank = bank;
 926
 927         if (has_bank_sel(data)) {
 928                 u8 breg = _it87_read_value(data, IT87_REG_BANK);
 929
 930                 _bank = breg >> 5;
 931                 if (bank != _bank) {
 932                         breg &= 0x1f;
 933                         breg |= (bank << 5);
 934                         _it87_write_value(data, IT87_REG_BANK, breg);
 935                 }
 936         }
 937         return _bank;
 938 }
 939
 940 /*
 941  * Must be called with data->update_lock held, except during initialization.
 942  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 943  * would slow down the IT87 access and should not be necessary.
 944  */
 945 static int it87_read_value(struct it87_data *data, u16 reg)
 946 {
 947         u8 bank;
 948         int val;
 949
 950         bank = it87_set_bank(data, reg >> 8);
 951         val = _it87_read_value(data, reg & 0xff);
 952         it87_set_bank(data, bank);
 953
 954         return val;
 955 }
 956
 957 /*
 958  * Must be called with data->update_lock held, except during initialization.
 959  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 960  * would slow down the IT87 access and should not be necessary.
 961  */
 962 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
 963 {
 964         u8 bank;
 965
 966         bank = it87_set_bank(data, reg >> 8);
 967         _it87_write_value(data, reg & 0xff, value);
 968         it87_set_bank(data, bank);
 969 }
 970
 971 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 972 {
 973         u8 ctrl;
 974
 975         ctrl = it87_read_value(data, data->REG_PWM[nr]);
 976         data->pwm_ctrl[nr] = ctrl;
 977         if (has_newer_autopwm(data)) {
 978                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
 979                 data->pwm_duty[nr] = it87_read_value(data,
 980                                                      IT87_REG_PWM_DUTY[nr]);
 981         } else {
 982                 if (ctrl & 0x80)        /* Automatic mode */
 983                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
 984                 else                            /* Manual mode */
 985                         data->pwm_duty[nr] = ctrl & 0x7f;
 986         }
 987
 988         if (has_old_autopwm(data)) {
 989                 int i;
 990
 991                 for (i = 0; i < 5 ; i++)
 992                         data->auto_temp[nr][i] = it87_read_value(data,
 993                                                 IT87_REG_AUTO_TEMP(nr, i));
 994                 for (i = 0; i < 3 ; i++)
 995                         data->auto_pwm[nr][i] = it87_read_value(data,
 996                                                 IT87_REG_AUTO_PWM(nr, i));
 997         } else if (has_newer_autopwm(data)) {
 998                 int i;
 999
1000                 /*
1001                  * 0: temperature hysteresis (base + 5)
1002                  * 1: fan off temperature (base + 0)
1003                  * 2: fan start temperature (base + 1)
1004                  * 3: fan max temperature (base + 2)
1005                  */
1006                 data->auto_temp[nr][0] =
1007                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
1008
1009                 for (i = 0; i < 3 ; i++)
1010                         data->auto_temp[nr][i + 1] =
1011                                 it87_read_value(data,
1012                                                 IT87_REG_AUTO_TEMP(nr, i));
1013                 /*
1014                  * 0: start pwm value (base + 3)
1015                  * 1: pwm slope (base + 4, 1/8th pwm)
1016                  */
1017                 data->auto_pwm[nr][0] =
1018                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
1019                 data->auto_pwm[nr][1] =
1020                         it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
1021         }
1022 }
1023
1024 static struct it87_data *it87_update_device(struct device *dev)
1025 {
1026         struct it87_data *data = dev_get_drvdata(dev);
1027         int i;
1028
1029         mutex_lock(&data->update_lock);
1030
1031         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1032             !data->valid) {
1033                 if (update_vbat) {
1034                         /*
1035                          * Cleared after each update, so reenable.  Value
1036                          * returned by this read will be previous value
1037                          */
1038                         it87_write_value(data, IT87_REG_CONFIG,
1039                                 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1040                 }
1041                 for (i = 0; i < NUM_VIN; i++) {
1042                         if (!(data->has_in & BIT(i)))
1043                                 continue;
1044
1045                         data->in[i][0] =
1046                                 it87_read_value(data, IT87_REG_VIN[i]);
1047
1048                         /* VBAT and AVCC don't have limit registers */
1049                         if (i >= NUM_VIN_LIMIT)
1050                                 continue;
1051
1052                         data->in[i][1] =
1053                                 it87_read_value(data, IT87_REG_VIN_MIN(i));
1054                         data->in[i][2] =
1055                                 it87_read_value(data, IT87_REG_VIN_MAX(i));
1056                 }
1057
1058                 for (i = 0; i < NUM_FAN; i++) {
1059                         /* Skip disabled fans */
1060                         if (!(data->has_fan & BIT(i)))
1061                                 continue;
1062
1063                         data->fan[i][1] =
1064                                 it87_read_value(data, data->REG_FAN_MIN[i]);
1065                         data->fan[i][0] = it87_read_value(data,
1066                                        data->REG_FAN[i]);
1067                         /* Add high byte if in 16-bit mode */
1068                         if (has_16bit_fans(data)) {
1069                                 data->fan[i][0] |= it87_read_value(data,
1070                                                 data->REG_FANX[i]) << 8;
1071                                 data->fan[i][1] |= it87_read_value(data,
1072                                                 data->REG_FANX_MIN[i]) << 8;
1073                         }
1074                 }
1075                 for (i = 0; i < NUM_TEMP; i++) {
1076                         if (!(data->has_temp & BIT(i)))
1077                                 continue;
1078                         data->temp[i][0] =
1079                                 it87_read_value(data, IT87_REG_TEMP(i));
1080
1081                         if (i >= data->num_temp_limit)
1082                                 continue;
1083
1084                         if (i < data->num_temp_offset)
1085                                 data->temp[i][3] =
1086                                   it87_read_value(data,
1087                                                   data->REG_TEMP_OFFSET[i]);
1088
1089                         data->temp[i][1] =
1090                                 it87_read_value(data, data->REG_TEMP_LOW[i]);
1091                         data->temp[i][2] =
1092                                 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1093                 }
1094
1095                 /* Newer chips don't have clock dividers */
1096                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1097                         i = it87_read_value(data, IT87_REG_FAN_DIV);
1098                         data->fan_div[0] = i & 0x07;
1099                         data->fan_div[1] = (i >> 3) & 0x07;
1100                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1101                 }
1102
1103                 data->alarms =
1104                         it87_read_value(data, IT87_REG_ALARM1) |
1105                         (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1106                         (it87_read_value(data, IT87_REG_ALARM3) << 16);
1107                 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1108
1109                 data->fan_main_ctrl = it87_read_value(data,
1110                                 IT87_REG_FAN_MAIN_CTRL);
1111                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1112                 for (i = 0; i < NUM_PWM; i++) {
1113                         if (!(data->has_pwm & BIT(i)))
1114                                 continue;
1115                         it87_update_pwm_ctrl(data, i);
1116                 }
1117
1118                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1119                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1120                 /*
1121                  * The IT8705F does not have VID capability.
1122                  * The IT8718F and later don't use IT87_REG_VID for the
1123                  * same purpose.
1124                  */
1125                 if (data->type == it8712 || data->type == it8716) {
1126                         data->vid = it87_read_value(data, IT87_REG_VID);
1127                         /*
1128                          * The older IT8712F revisions had only 5 VID pins,
1129                          * but we assume it is always safe to read 6 bits.
1130                          */
1131                         data->vid &= 0x3f;
1132                 }
1133                 data->last_updated = jiffies;
1134                 data->valid = 1;
1135         }
1136
1137         mutex_unlock(&data->update_lock);
1138
1139         return data;
1140 }
1141
1142 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1143                        char *buf)
1144 {
1145         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1146         struct it87_data *data = it87_update_device(dev);
1147         int index = sattr->index;
1148         int nr = sattr->nr;
1149
1150         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1151 }
1152
1153 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1154                       const char *buf, size_t count)
1155 {
1156         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1157         struct it87_data *data = dev_get_drvdata(dev);
1158         int index = sattr->index;
1159         int nr = sattr->nr;
1160         unsigned long val;
1161
1162         if (kstrtoul(buf, 10, &val) < 0)
1163                 return -EINVAL;
1164
1165         mutex_lock(&data->update_lock);
1166         data->in[nr][index] = in_to_reg(data, nr, val);
1167         it87_write_value(data,
1168                          index == 1 ? IT87_REG_VIN_MIN(nr)
1169                                     : IT87_REG_VIN_MAX(nr),
1170                          data->in[nr][index]);
1171         mutex_unlock(&data->update_lock);
1172         return count;
1173 }
1174
1175 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1176 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1177                             0, 1);
1178 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1179                             0, 2);
1180
1181 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1182 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1183                             1, 1);
1184 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1185                             1, 2);
1186
1187 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1188 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1189                             2, 1);
1190 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1191                             2, 2);
1192
1193 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1194 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1195                             3, 1);
1196 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1197                             3, 2);
1198
1199 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1200 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1201                             4, 1);
1202 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1203                             4, 2);
1204
1205 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1206 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1207                             5, 1);
1208 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1209                             5, 2);
1210
1211 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1212 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1213                             6, 1);
1214 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1215                             6, 2);
1216
1217 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1218 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1219                             7, 1);
1220 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1221                             7, 2);
1222
1223 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1224 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1225 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1226 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1227 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1228
1229 /* Up to 6 temperatures */
1230 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1231                          char *buf)
1232 {
1233         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1234         int nr = sattr->nr;
1235         int index = sattr->index;
1236         struct it87_data *data = it87_update_device(dev);
1237
1238         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1239 }
1240
1241 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1242                         const char *buf, size_t count)
1243 {
1244         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1245         int nr = sattr->nr;
1246         int index = sattr->index;
1247         struct it87_data *data = dev_get_drvdata(dev);
1248         long val;
1249         u8 reg, regval;
1250
1251         if (kstrtol(buf, 10, &val) < 0)
1252                 return -EINVAL;
1253
1254         mutex_lock(&data->update_lock);
1255
1256         switch (index) {
1257         default:
1258         case 1:
1259                 reg = data->REG_TEMP_LOW[nr];
1260                 break;
1261         case 2:
1262                 reg = data->REG_TEMP_HIGH[nr];
1263                 break;
1264         case 3:
1265                 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1266                 if (!(regval & 0x80)) {
1267                         regval |= 0x80;
1268                         it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1269                 }
1270                 data->valid = 0;
1271                 reg = data->REG_TEMP_OFFSET[nr];
1272                 break;
1273         }
1274
1275         data->temp[nr][index] = TEMP_TO_REG(val);
1276         it87_write_value(data, reg, data->temp[nr][index]);
1277         mutex_unlock(&data->update_lock);
1278         return count;
1279 }
1280
1281 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1282 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1283                             0, 1);
1284 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1285                             0, 2);
1286 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1287                             set_temp, 0, 3);
1288 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1289 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1290                             1, 1);
1291 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1292                             1, 2);
1293 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1294                             set_temp, 1, 3);
1295 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1296 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1297                             2, 1);
1298 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1299                             2, 2);
1300 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1301                             set_temp, 2, 3);
1302 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1303 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1304                             3, 1);
1305 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1306                             3, 2);
1307 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1308                             set_temp, 3, 3);
1309 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1310 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1311                             4, 1);
1312 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1313                             4, 2);
1314 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1315                             set_temp, 4, 3);
1316 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1317 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1318                             5, 1);
1319 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1320                             5, 2);
1321 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1322                             set_temp, 5, 3);
1323
1324 static const u8 temp_types_8686[NUM_TEMP][9] = {
1325         { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1326         { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1327         { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1328         { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1329         { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1330         { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1331 };
1332
1333 static int get_temp_type(struct it87_data *data, int index)
1334 {
1335         u8 reg, extra;
1336         int type = 0;
1337
1338         if (has_bank_sel(data)) {
1339                 int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
1340                 u8 src1, src2;
1341
1342                 src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
1343
1344                 switch (data->type) {
1345                 case it8686:
1346                         if (src1 < 9)
1347                                 type = temp_types_8686[index][src1];
1348                         break;
1349                 case it8625:
1350                         if (index < 3)
1351                                 break;
1352                 case it8655:
1353                 case it8665:
1354                         if (src1 < 3) {
1355                                 index = src1;
1356                                 break;
1357                         }
1358                         src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
1359                         switch(src1) {
1360                         case 3:
1361                                 type = (src2 & BIT(index)) ? 6 : 5;
1362                                 break;
1363                         case 4 ... 8:
1364                                 type = (src2 & BIT(index)) ? 4 : 6;
1365                                 break;
1366                         case 9:
1367                                 type = (src2 & BIT(index)) ? 5 : 0;
1368                                 break;
1369                         default:
1370                                 break;
1371                         }
1372                         return type;
1373                 default:
1374                         return 0;
1375                 }
1376         }
1377         if (type || index >= 3)
1378                 return type;
1379
1380         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1381         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1382
1383         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1384             (has_temp_old_peci(data, index) && (extra & 0x80)))
1385                 type = 6;               /* Intel PECI */
1386         if (reg & BIT(index))
1387                 type = 3;               /* thermal diode */
1388         else if (reg & BIT(index + 3))
1389                 type = 4;               /* thermistor */
1390
1391         return type;
1392 }
1393
1394 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1395                               char *buf)
1396 {
1397         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1398         struct it87_data *data = it87_update_device(dev);
1399         int type = get_temp_type(data, sensor_attr->index);
1400
1401         return sprintf(buf, "%d\n", type);
1402 }
1403
1404 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1405                              const char *buf, size_t count)
1406 {
1407         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1408         int nr = sensor_attr->index;
1409
1410         struct it87_data *data = dev_get_drvdata(dev);
1411         long val;
1412         u8 reg, extra;
1413
1414         if (kstrtol(buf, 10, &val) < 0)
1415                 return -EINVAL;
1416
1417         reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1418         reg &= ~(1 << nr);
1419         reg &= ~(8 << nr);
1420         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1421                 reg &= 0x3f;
1422         extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1423         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1424                 extra &= 0x7f;
1425         if (val == 2) { /* backwards compatibility */
1426                 dev_warn(dev,
1427                          "Sensor type 2 is deprecated, please use 4 instead\n");
1428                 val = 4;
1429         }
1430         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1431         if (val == 3)
1432                 reg |= 1 << nr;
1433         else if (val == 4)
1434                 reg |= 8 << nr;
1435         else if (has_temp_peci(data, nr) && val == 6)
1436                 reg |= (nr + 1) << 6;
1437         else if (has_temp_old_peci(data, nr) && val == 6)
1438                 extra |= 0x80;
1439         else if (val != 0)
1440                 return -EINVAL;
1441
1442         mutex_lock(&data->update_lock);
1443         data->sensor = reg;
1444         data->extra = extra;
1445         it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1446         if (has_temp_old_peci(data, nr))
1447                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1448         data->valid = 0;        /* Force cache refresh */
1449         mutex_unlock(&data->update_lock);
1450         return count;
1451 }
1452
1453 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1454                           set_temp_type, 0);
1455 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1456                           set_temp_type, 1);
1457 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1458                           set_temp_type, 2);
1459 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1460                           set_temp_type, 3);
1461 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1462                           set_temp_type, 4);
1463 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1464                           set_temp_type, 5);
1465
1466 /* 6 Fans */
1467
1468 static int pwm_mode(const struct it87_data *data, int nr)
1469 {
1470         if (has_fanctl_onoff(data) && nr < 3 &&
1471             !(data->fan_main_ctrl & BIT(nr)))
1472                 return 0;                               /* Full speed */
1473         if (data->pwm_ctrl[nr] & 0x80)
1474                 return 2;                               /* Automatic mode */
1475         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1476             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1477                 return 0;                       /* Full speed */
1478
1479         return 1;                               /* Manual mode */
1480 }
1481
1482 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1483                         char *buf)
1484 {
1485         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1486         int nr = sattr->nr;
1487         int index = sattr->index;
1488         int speed;
1489         struct it87_data *data = it87_update_device(dev);
1490
1491         speed = has_16bit_fans(data) ?
1492                 FAN16_FROM_REG(data->fan[nr][index]) :
1493                 FAN_FROM_REG(data->fan[nr][index],
1494                              DIV_FROM_REG(data->fan_div[nr]));
1495         return sprintf(buf, "%d\n", speed);
1496 }
1497
1498 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1499                             char *buf)
1500 {
1501         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1502         struct it87_data *data = it87_update_device(dev);
1503         int nr = sensor_attr->index;
1504
1505         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1506 }
1507
1508 static ssize_t show_pwm_enable(struct device *dev,
1509                                struct device_attribute *attr, char *buf)
1510 {
1511         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1512         struct it87_data *data = it87_update_device(dev);
1513         int nr = sensor_attr->index;
1514
1515         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1516 }
1517
1518 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1519                         char *buf)
1520 {
1521         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1522         struct it87_data *data = it87_update_device(dev);
1523         int nr = sensor_attr->index;
1524
1525         return sprintf(buf, "%d\n",
1526                        pwm_from_reg(data, data->pwm_duty[nr]));
1527 }
1528
1529 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1530                              char *buf)
1531 {
1532         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1533         struct it87_data *data = it87_update_device(dev);
1534         int nr = sensor_attr->index;
1535         unsigned int freq;
1536         int index;
1537
1538         if (has_pwm_freq2(data) && nr == 1)
1539                 index = (data->extra >> 4) & 0x07;
1540         else
1541                 index = (data->fan_ctl >> 4) & 0x07;
1542
1543         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1544
1545         return sprintf(buf, "%u\n", freq);
1546 }
1547
1548 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1549                        const char *buf, size_t count)
1550 {
1551         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1552         int nr = sattr->nr;
1553         int index = sattr->index;
1554
1555         struct it87_data *data = dev_get_drvdata(dev);
1556         long val;
1557         u8 reg;
1558
1559         if (kstrtol(buf, 10, &val) < 0)
1560                 return -EINVAL;
1561
1562         mutex_lock(&data->update_lock);
1563
1564         if (has_16bit_fans(data)) {
1565                 data->fan[nr][index] = FAN16_TO_REG(val);
1566                 it87_write_value(data, data->REG_FAN_MIN[nr],
1567                                  data->fan[nr][index] & 0xff);
1568                 it87_write_value(data, data->REG_FANX_MIN[nr],
1569                                  data->fan[nr][index] >> 8);
1570         } else {
1571                 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1572                 switch (nr) {
1573                 case 0:
1574                         data->fan_div[nr] = reg & 0x07;
1575                         break;
1576                 case 1:
1577                         data->fan_div[nr] = (reg >> 3) & 0x07;
1578                         break;
1579                 case 2:
1580                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1581                         break;
1582                 }
1583                 data->fan[nr][index] =
1584                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1585                 it87_write_value(data, data->REG_FAN_MIN[nr],
1586                                  data->fan[nr][index]);
1587         }
1588
1589         mutex_unlock(&data->update_lock);
1590         return count;
1591 }
1592
1593 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1594                            const char *buf, size_t count)
1595 {
1596         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1597         struct it87_data *data = dev_get_drvdata(dev);
1598         int nr = sensor_attr->index;
1599         unsigned long val;
1600         int min;
1601         u8 old;
1602
1603         if (kstrtoul(buf, 10, &val) < 0)
1604                 return -EINVAL;
1605
1606         mutex_lock(&data->update_lock);
1607         old = it87_read_value(data, IT87_REG_FAN_DIV);
1608
1609         /* Save fan min limit */
1610         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1611
1612         switch (nr) {
1613         case 0:
1614         case 1:
1615                 data->fan_div[nr] = DIV_TO_REG(val);
1616                 break;
1617         case 2:
1618                 if (val < 8)
1619                         data->fan_div[nr] = 1;
1620                 else
1621                         data->fan_div[nr] = 3;
1622         }
1623         val = old & 0x80;
1624         val |= (data->fan_div[0] & 0x07);
1625         val |= (data->fan_div[1] & 0x07) << 3;
1626         if (data->fan_div[2] == 3)
1627                 val |= 0x1 << 6;
1628         it87_write_value(data, IT87_REG_FAN_DIV, val);
1629
1630         /* Restore fan min limit */
1631         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1632         it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1633
1634         mutex_unlock(&data->update_lock);
1635         return count;
1636 }
1637
1638 /* Returns 0 if OK, -EINVAL otherwise */
1639 static int check_trip_points(struct device *dev, int nr)
1640 {
1641         const struct it87_data *data = dev_get_drvdata(dev);
1642         int i, err = 0;
1643
1644         if (has_old_autopwm(data)) {
1645                 for (i = 0; i < 3; i++) {
1646                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1647                                 err = -EINVAL;
1648                 }
1649                 for (i = 0; i < 2; i++) {
1650                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1651                                 err = -EINVAL;
1652                 }
1653         } else if (has_newer_autopwm(data)) {
1654                 for (i = 1; i < 3; i++) {
1655                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1656                                 err = -EINVAL;
1657                 }
1658         }
1659
1660         if (err) {
1661                 dev_err(dev,
1662                         "Inconsistent trip points, not switching to automatic mode\n");
1663                 dev_err(dev, "Adjust the trip points and try again\n");
1664         }
1665         return err;
1666 }
1667
1668 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1669                               const char *buf, size_t count)
1670 {
1671         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1672         struct it87_data *data = dev_get_drvdata(dev);
1673         int nr = sensor_attr->index;
1674         long val;
1675
1676         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1677                 return -EINVAL;
1678
1679         /* Check trip points before switching to automatic mode */
1680         if (val == 2) {
1681                 if (check_trip_points(dev, nr) < 0)
1682                         return -EINVAL;
1683         }
1684
1685         mutex_lock(&data->update_lock);
1686         it87_update_pwm_ctrl(data, nr);
1687
1688         if (val == 0) {
1689                 if (nr < 3 && has_fanctl_onoff(data)) {
1690                         int tmp;
1691                         /* make sure the fan is on when in on/off mode */
1692                         tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1693                         it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1694                         /* set on/off mode */
1695                         data->fan_main_ctrl &= ~BIT(nr);
1696                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1697                                          data->fan_main_ctrl);
1698                 } else {
1699                         u8 ctrl;
1700
1701                         /* No on/off mode, set maximum pwm value */
1702                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1703                         it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1704                                          data->pwm_duty[nr]);
1705                         /* and set manual mode */
1706                         if (has_newer_autopwm(data)) {
1707                                 ctrl = temp_map_to_reg(data, nr,
1708                                                        data->pwm_temp_map[nr]);
1709                                 ctrl &= 0x7f;
1710                         } else {
1711                                 ctrl = data->pwm_duty[nr];
1712                         }
1713                         data->pwm_ctrl[nr] = ctrl;
1714                         it87_write_value(data, data->REG_PWM[nr], ctrl);
1715                 }
1716         } else {
1717                 u8 ctrl;
1718
1719                 if (has_newer_autopwm(data)) {
1720                         ctrl = temp_map_to_reg(data, nr,
1721                                                data->pwm_temp_map[nr]);
1722                         if (val == 1)
1723                                 ctrl &= 0x7f;
1724                         else
1725                                 ctrl |= 0x80;
1726                 } else {
1727                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1728                 }
1729                 data->pwm_ctrl[nr] = ctrl;
1730                 it87_write_value(data, data->REG_PWM[nr], ctrl);
1731
1732                 if (has_fanctl_onoff(data) && nr < 3) {
1733                         /* set SmartGuardian mode */
1734                         data->fan_main_ctrl |= BIT(nr);
1735                         it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1736                                          data->fan_main_ctrl);
1737                 }
1738         }
1739
1740         mutex_unlock(&data->update_lock);
1741         return count;
1742 }
1743
1744 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1745                        const char *buf, size_t count)
1746 {
1747         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1748         struct it87_data *data = dev_get_drvdata(dev);
1749         int nr = sensor_attr->index;
1750         long val;
1751
1752         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1753                 return -EINVAL;
1754
1755         mutex_lock(&data->update_lock);
1756         it87_update_pwm_ctrl(data, nr);
1757         if (has_newer_autopwm(data)) {
1758                 /*
1759                  * If we are in automatic mode, the PWM duty cycle register
1760                  * is read-only so we can't write the value.
1761                  */
1762                 if (data->pwm_ctrl[nr] & 0x80) {
1763                         mutex_unlock(&data->update_lock);
1764                         return -EBUSY;
1765                 }
1766                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1767                 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1768                                  data->pwm_duty[nr]);
1769         } else {
1770                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1771                 /*
1772                  * If we are in manual mode, write the duty cycle immediately;
1773                  * otherwise, just store it for later use.
1774                  */
1775                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1776                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1777                         it87_write_value(data, data->REG_PWM[nr],
1778                                          data->pwm_ctrl[nr]);
1779                 }
1780         }
1781         mutex_unlock(&data->update_lock);
1782         return count;
1783 }
1784
1785 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1786                             const char *buf, size_t count)
1787 {
1788         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1789         struct it87_data *data = dev_get_drvdata(dev);
1790         int nr = sensor_attr->index;
1791         unsigned long val;
1792         int i;
1793
1794         if (kstrtoul(buf, 10, &val) < 0)
1795                 return -EINVAL;
1796
1797         val = clamp_val(val, 0, 1000000);
1798         val *= has_newer_autopwm(data) ? 256 : 128;
1799
1800         /* Search for the nearest available frequency */
1801         for (i = 0; i < 7; i++) {
1802                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1803                         break;
1804         }
1805
1806         mutex_lock(&data->update_lock);
1807         if (nr == 0) {
1808                 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1809                 data->fan_ctl |= i << 4;
1810                 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1811         } else {
1812                 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1813                 data->extra |= i << 4;
1814                 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1815         }
1816         mutex_unlock(&data->update_lock);
1817
1818         return count;
1819 }
1820
1821 static ssize_t show_pwm_temp_map(struct device *dev,
1822                                  struct device_attribute *attr, char *buf)
1823 {
1824         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1825         struct it87_data *data = it87_update_device(dev);
1826         int nr = sensor_attr->index;
1827
1828         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1829 }
1830
1831 static ssize_t set_pwm_temp_map(struct device *dev,
1832                                 struct device_attribute *attr, const char *buf,
1833                                 size_t count)
1834 {
1835         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1836         struct it87_data *data = dev_get_drvdata(dev);
1837         int nr = sensor_attr->index;
1838         unsigned long val;
1839         u8 map;
1840
1841         if (kstrtoul(buf, 10, &val) < 0)
1842                 return -EINVAL;
1843
1844         if (!val || val > data->pwm_num_temp_map)
1845                 return -EINVAL;
1846
1847         map = val - 1;
1848
1849         mutex_lock(&data->update_lock);
1850         it87_update_pwm_ctrl(data, nr);
1851         data->pwm_temp_map[nr] = map;
1852         /*
1853          * If we are in automatic mode, write the temp mapping immediately;
1854          * otherwise, just store it for later use.
1855          */
1856         if (data->pwm_ctrl[nr] & 0x80) {
1857                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
1858                 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1859         }
1860         mutex_unlock(&data->update_lock);
1861         return count;
1862 }
1863
1864 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1865                              char *buf)
1866 {
1867         struct it87_data *data = it87_update_device(dev);
1868         struct sensor_device_attribute_2 *sensor_attr =
1869                         to_sensor_dev_attr_2(attr);
1870         int nr = sensor_attr->nr;
1871         int point = sensor_attr->index;
1872
1873         return sprintf(buf, "%d\n",
1874                        pwm_from_reg(data, data->auto_pwm[nr][point]));
1875 }
1876
1877 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1878                             const char *buf, size_t count)
1879 {
1880         struct it87_data *data = dev_get_drvdata(dev);
1881         struct sensor_device_attribute_2 *sensor_attr =
1882                         to_sensor_dev_attr_2(attr);
1883         int nr = sensor_attr->nr;
1884         int point = sensor_attr->index;
1885         int regaddr;
1886         long val;
1887
1888         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1889                 return -EINVAL;
1890
1891         mutex_lock(&data->update_lock);
1892         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1893         if (has_newer_autopwm(data))
1894                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1895         else
1896                 regaddr = IT87_REG_AUTO_PWM(nr, point);
1897         it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1898         mutex_unlock(&data->update_lock);
1899         return count;
1900 }
1901
1902 static ssize_t show_auto_pwm_slope(struct device *dev,
1903                                    struct device_attribute *attr, char *buf)
1904 {
1905         struct it87_data *data = it87_update_device(dev);
1906         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1907         int nr = sensor_attr->index;
1908
1909         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1910 }
1911
1912 static ssize_t set_auto_pwm_slope(struct device *dev,
1913                                   struct device_attribute *attr,
1914                                   const char *buf, size_t count)
1915 {
1916         struct it87_data *data = dev_get_drvdata(dev);
1917         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1918         int nr = sensor_attr->index;
1919         unsigned long val;
1920
1921         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1922                 return -EINVAL;
1923
1924         mutex_lock(&data->update_lock);
1925         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1926         it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1927                          data->auto_pwm[nr][1]);
1928         mutex_unlock(&data->update_lock);
1929         return count;
1930 }
1931
1932 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1933                               char *buf)
1934 {
1935         struct it87_data *data = it87_update_device(dev);
1936         struct sensor_device_attribute_2 *sensor_attr =
1937                         to_sensor_dev_attr_2(attr);
1938         int nr = sensor_attr->nr;
1939         int point = sensor_attr->index;
1940         int reg;
1941
1942         if (has_old_autopwm(data) || point)
1943                 reg = data->auto_temp[nr][point];
1944         else
1945                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1946
1947         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1948 }
1949
1950 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1951                              const char *buf, size_t count)
1952 {
1953         struct it87_data *data = dev_get_drvdata(dev);
1954         struct sensor_device_attribute_2 *sensor_attr =
1955                         to_sensor_dev_attr_2(attr);
1956         int nr = sensor_attr->nr;
1957         int point = sensor_attr->index;
1958         long val;
1959         int reg;
1960
1961         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1962                 return -EINVAL;
1963
1964         mutex_lock(&data->update_lock);
1965         if (has_newer_autopwm(data) && !point) {
1966                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1967                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1968                 data->auto_temp[nr][0] = reg;
1969                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1970         } else {
1971                 reg = TEMP_TO_REG(val);
1972                 data->auto_temp[nr][point] = reg;
1973                 if (has_newer_autopwm(data))
1974                         point--;
1975                 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1976         }
1977         mutex_unlock(&data->update_lock);
1978         return count;
1979 }
1980
1981 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1982 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1983                             0, 1);
1984 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1985                           set_fan_div, 0);
1986
1987 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1988 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1989                             1, 1);
1990 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1991                           set_fan_div, 1);
1992
1993 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1994 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1995                             2, 1);
1996 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1997                           set_fan_div, 2);
1998
1999 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2000 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2001                             3, 1);
2002
2003 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2004 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2005                             4, 1);
2006
2007 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2008 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2009                             5, 1);
2010
2011 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2012                           show_pwm_enable, set_pwm_enable, 0);
2013 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2014 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2015                           set_pwm_freq, 0);
2016 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2017                           show_pwm_temp_map, set_pwm_temp_map, 0);
2018 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2019                             show_auto_pwm, set_auto_pwm, 0, 0);
2020 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2021                             show_auto_pwm, set_auto_pwm, 0, 1);
2022 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2023                             show_auto_pwm, set_auto_pwm, 0, 2);
2024 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2025                             show_auto_pwm, NULL, 0, 3);
2026 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2027                             show_auto_temp, set_auto_temp, 0, 1);
2028 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2029                             show_auto_temp, set_auto_temp, 0, 0);
2030 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2031                             show_auto_temp, set_auto_temp, 0, 2);
2032 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2033                             show_auto_temp, set_auto_temp, 0, 3);
2034 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2035                             show_auto_temp, set_auto_temp, 0, 4);
2036 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2037                             show_auto_pwm, set_auto_pwm, 0, 0);
2038 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2039                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2040
2041 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2042                           show_pwm_enable, set_pwm_enable, 1);
2043 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2044 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2045 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2046                           show_pwm_temp_map, set_pwm_temp_map, 1);
2047 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2048                             show_auto_pwm, set_auto_pwm, 1, 0);
2049 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2050                             show_auto_pwm, set_auto_pwm, 1, 1);
2051 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2052                             show_auto_pwm, set_auto_pwm, 1, 2);
2053 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2054                             show_auto_pwm, NULL, 1, 3);
2055 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2056                             show_auto_temp, set_auto_temp, 1, 1);
2057 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2058                             show_auto_temp, set_auto_temp, 1, 0);
2059 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2060                             show_auto_temp, set_auto_temp, 1, 2);
2061 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2062                             show_auto_temp, set_auto_temp, 1, 3);
2063 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2064                             show_auto_temp, set_auto_temp, 1, 4);
2065 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2066                             show_auto_pwm, set_auto_pwm, 1, 0);
2067 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2068                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2069
2070 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2071                           show_pwm_enable, set_pwm_enable, 2);
2072 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2073 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2074 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2075                           show_pwm_temp_map, set_pwm_temp_map, 2);
2076 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2077                             show_auto_pwm, set_auto_pwm, 2, 0);
2078 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2079                             show_auto_pwm, set_auto_pwm, 2, 1);
2080 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2081                             show_auto_pwm, set_auto_pwm, 2, 2);
2082 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2083                             show_auto_pwm, NULL, 2, 3);
2084 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2085                             show_auto_temp, set_auto_temp, 2, 1);
2086 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2087                             show_auto_temp, set_auto_temp, 2, 0);
2088 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2089                             show_auto_temp, set_auto_temp, 2, 2);
2090 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2091                             show_auto_temp, set_auto_temp, 2, 3);
2092 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2093                             show_auto_temp, set_auto_temp, 2, 4);
2094 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2095                             show_auto_pwm, set_auto_pwm, 2, 0);
2096 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2097                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2098
2099 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2100                           show_pwm_enable, set_pwm_enable, 3);
2101 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2102 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2103 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2104                           show_pwm_temp_map, set_pwm_temp_map, 3);
2105 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2106                             show_auto_temp, set_auto_temp, 2, 1);
2107 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2108                             show_auto_temp, set_auto_temp, 2, 0);
2109 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2110                             show_auto_temp, set_auto_temp, 2, 2);
2111 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2112                             show_auto_temp, set_auto_temp, 2, 3);
2113 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2114                             show_auto_pwm, set_auto_pwm, 3, 0);
2115 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2116                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2117
2118 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2119                           show_pwm_enable, set_pwm_enable, 4);
2120 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2121 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2122 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2123                           show_pwm_temp_map, set_pwm_temp_map, 4);
2124 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2125                             show_auto_temp, set_auto_temp, 2, 1);
2126 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2127                             show_auto_temp, set_auto_temp, 2, 0);
2128 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2129                             show_auto_temp, set_auto_temp, 2, 2);
2130 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2131                             show_auto_temp, set_auto_temp, 2, 3);
2132 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2133                             show_auto_pwm, set_auto_pwm, 4, 0);
2134 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2135                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2136
2137 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2138                           show_pwm_enable, set_pwm_enable, 5);
2139 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2140 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2141 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2142                           show_pwm_temp_map, set_pwm_temp_map, 5);
2143 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2144                             show_auto_temp, set_auto_temp, 2, 1);
2145 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2146                             show_auto_temp, set_auto_temp, 2, 0);
2147 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2148                             show_auto_temp, set_auto_temp, 2, 2);
2149 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2150                             show_auto_temp, set_auto_temp, 2, 3);
2151 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2152                             show_auto_pwm, set_auto_pwm, 5, 0);
2153 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2154                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2155
2156 /* Alarms */
2157 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2158                            char *buf)
2159 {
2160         struct it87_data *data = it87_update_device(dev);
2161
2162         return sprintf(buf, "%u\n", data->alarms);
2163 }
2164 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2165
2166 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2167                           char *buf)
2168 {
2169         struct it87_data *data = it87_update_device(dev);
2170         int bitnr = to_sensor_dev_attr(attr)->index;
2171
2172         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2173 }
2174
2175 static ssize_t clear_intrusion(struct device *dev,
2176                                struct device_attribute *attr, const char *buf,
2177                                size_t count)
2178 {
2179         struct it87_data *data = dev_get_drvdata(dev);
2180         int config;
2181         long val;
2182
2183         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2184                 return -EINVAL;
2185
2186         mutex_lock(&data->update_lock);
2187         config = it87_read_value(data, IT87_REG_CONFIG);
2188         if (config < 0) {
2189                 count = config;
2190         } else {
2191                 config |= BIT(5);
2192                 it87_write_value(data, IT87_REG_CONFIG, config);
2193                 /* Invalidate cache to force re-read */
2194                 data->valid = 0;
2195         }
2196         mutex_unlock(&data->update_lock);
2197
2198         return count;
2199 }
2200
2201 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2202 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2203 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2204 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2205 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2206 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2207 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2208 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2209 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2210 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2211 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2212 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2213 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2214 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2215 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2216 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2217 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2218 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2219 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2220 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2221 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2222                           show_alarm, clear_intrusion, 4);
2223
2224 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2225                          char *buf)
2226 {
2227         struct it87_data *data = it87_update_device(dev);
2228         int bitnr = to_sensor_dev_attr(attr)->index;
2229
2230         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2231 }
2232
2233 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2234                         const char *buf, size_t count)
2235 {
2236         int bitnr = to_sensor_dev_attr(attr)->index;
2237         struct it87_data *data = dev_get_drvdata(dev);
2238         long val;
2239
2240         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2241                 return -EINVAL;
2242
2243         mutex_lock(&data->update_lock);
2244         data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2245         if (val)
2246                 data->beeps |= BIT(bitnr);
2247         else
2248                 data->beeps &= ~BIT(bitnr);
2249         it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2250         mutex_unlock(&data->update_lock);
2251         return count;
2252 }
2253
2254 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2255                           show_beep, set_beep, 1);
2256 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2257 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2258 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2259 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2260 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2261 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2262 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2263 /* fanX_beep writability is set later */
2264 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2265 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2266 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2267 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2268 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2269 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2270 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2271                           show_beep, set_beep, 2);
2272 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2273 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2274 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2275 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2276 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2277
2278 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2279                             char *buf)
2280 {
2281         struct it87_data *data = dev_get_drvdata(dev);
2282
2283         return sprintf(buf, "%u\n", data->vrm);
2284 }
2285
2286 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2287                              const char *buf, size_t count)
2288 {
2289         struct it87_data *data = dev_get_drvdata(dev);
2290         unsigned long val;
2291
2292         if (kstrtoul(buf, 10, &val) < 0)
2293                 return -EINVAL;
2294
2295         data->vrm = val;
2296
2297         return count;
2298 }
2299 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2300
2301 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2302                             char *buf)
2303 {
2304         struct it87_data *data = it87_update_device(dev);
2305
2306         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2307 }
2308 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2309
2310 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2311                           char *buf)
2312 {
2313         static const char * const labels[] = {
2314                 "+5V",
2315                 "5VSB",
2316                 "Vbat",
2317                 "AVCC",
2318         };
2319         static const char * const labels_it8721[] = {
2320                 "+3.3V",
2321                 "3VSB",
2322                 "Vbat",
2323                 "+3.3V",
2324         };
2325         struct it87_data *data = dev_get_drvdata(dev);
2326         int nr = to_sensor_dev_attr(attr)->index;
2327         const char *label;
2328
2329         if (has_vin3_5v(data) && nr == 0)
2330                 label = labels[0];
2331         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2332                  has_11mv_adc(data))
2333                 label = labels_it8721[nr];
2334         else
2335                 label = labels[nr];
2336
2337         return sprintf(buf, "%s\n", label);
2338 }
2339 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2340 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2341 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2342 /* AVCC3 */
2343 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2344
2345 static umode_t it87_in_is_visible(struct kobject *kobj,
2346                                   struct attribute *attr, int index)
2347 {
2348         struct device *dev = container_of(kobj, struct device, kobj);
2349         struct it87_data *data = dev_get_drvdata(dev);
2350         int i = index / 5;      /* voltage index */
2351         int a = index % 5;      /* attribute index */
2352
2353         if (index >= 40) {      /* in8 and higher only have input attributes */
2354                 i = index - 40 + 8;
2355                 a = 0;
2356         }
2357
2358         if (!(data->has_in & BIT(i)))
2359                 return 0;
2360
2361         if (a == 4 && !data->has_beep)
2362                 return 0;
2363
2364         return attr->mode;
2365 }
2366
2367 static struct attribute *it87_attributes_in[] = {
2368         &sensor_dev_attr_in0_input.dev_attr.attr,
2369         &sensor_dev_attr_in0_min.dev_attr.attr,
2370         &sensor_dev_attr_in0_max.dev_attr.attr,
2371         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2372         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2373
2374         &sensor_dev_attr_in1_input.dev_attr.attr,
2375         &sensor_dev_attr_in1_min.dev_attr.attr,
2376         &sensor_dev_attr_in1_max.dev_attr.attr,
2377         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2378         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2379
2380         &sensor_dev_attr_in2_input.dev_attr.attr,
2381         &sensor_dev_attr_in2_min.dev_attr.attr,
2382         &sensor_dev_attr_in2_max.dev_attr.attr,
2383         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2384         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2385
2386         &sensor_dev_attr_in3_input.dev_attr.attr,
2387         &sensor_dev_attr_in3_min.dev_attr.attr,
2388         &sensor_dev_attr_in3_max.dev_attr.attr,
2389         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2390         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2391
2392         &sensor_dev_attr_in4_input.dev_attr.attr,
2393         &sensor_dev_attr_in4_min.dev_attr.attr,
2394         &sensor_dev_attr_in4_max.dev_attr.attr,
2395         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2396         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2397
2398         &sensor_dev_attr_in5_input.dev_attr.attr,
2399         &sensor_dev_attr_in5_min.dev_attr.attr,
2400         &sensor_dev_attr_in5_max.dev_attr.attr,
2401         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2402         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2403
2404         &sensor_dev_attr_in6_input.dev_attr.attr,
2405         &sensor_dev_attr_in6_min.dev_attr.attr,
2406         &sensor_dev_attr_in6_max.dev_attr.attr,
2407         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2408         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2409
2410         &sensor_dev_attr_in7_input.dev_attr.attr,
2411         &sensor_dev_attr_in7_min.dev_attr.attr,
2412         &sensor_dev_attr_in7_max.dev_attr.attr,
2413         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2414         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2415
2416         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2417         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2418         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2419         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2420         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2421         NULL
2422 };
2423
2424 static const struct attribute_group it87_group_in = {
2425         .attrs = it87_attributes_in,
2426         .is_visible = it87_in_is_visible,
2427 };
2428
2429 static umode_t it87_temp_is_visible(struct kobject *kobj,
2430                                     struct attribute *attr, int index)
2431 {
2432         struct device *dev = container_of(kobj, struct device, kobj);
2433         struct it87_data *data = dev_get_drvdata(dev);
2434         int i = index / 7;      /* temperature index */
2435         int a = index % 7;      /* attribute index */
2436
2437         if (!(data->has_temp & BIT(i)))
2438                 return 0;
2439
2440         if (a && i >= data->num_temp_limit)
2441                 return 0;
2442
2443         if (a == 3) {
2444                 int type = get_temp_type(data, i);
2445
2446                 if (type == 0)
2447                         return 0;
2448                 if (has_bank_sel(data))
2449                         return 0444;
2450                 return attr->mode;
2451         }
2452
2453         if (a == 5 && i >= data->num_temp_offset)
2454                 return 0;
2455
2456         if (a == 6 && !data->has_beep)
2457                 return 0;
2458
2459         return attr->mode;
2460 }
2461
2462 static struct attribute *it87_attributes_temp[] = {
2463         &sensor_dev_attr_temp1_input.dev_attr.attr,
2464         &sensor_dev_attr_temp1_max.dev_attr.attr,
2465         &sensor_dev_attr_temp1_min.dev_attr.attr,
2466         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2467         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2468         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2469         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2470
2471         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2472         &sensor_dev_attr_temp2_max.dev_attr.attr,
2473         &sensor_dev_attr_temp2_min.dev_attr.attr,
2474         &sensor_dev_attr_temp2_type.dev_attr.attr,
2475         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2476         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2477         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2478
2479         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2480         &sensor_dev_attr_temp3_max.dev_attr.attr,
2481         &sensor_dev_attr_temp3_min.dev_attr.attr,
2482         &sensor_dev_attr_temp3_type.dev_attr.attr,
2483         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2484         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2485         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2486
2487         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2488         &sensor_dev_attr_temp4_max.dev_attr.attr,
2489         &sensor_dev_attr_temp4_min.dev_attr.attr,
2490         &sensor_dev_attr_temp4_type.dev_attr.attr,
2491         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2492         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2493         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2494
2495         &sensor_dev_attr_temp5_input.dev_attr.attr,
2496         &sensor_dev_attr_temp5_max.dev_attr.attr,
2497         &sensor_dev_attr_temp5_min.dev_attr.attr,
2498         &sensor_dev_attr_temp5_type.dev_attr.attr,
2499         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2500         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2501         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2502
2503         &sensor_dev_attr_temp6_input.dev_attr.attr,
2504         &sensor_dev_attr_temp6_max.dev_attr.attr,
2505         &sensor_dev_attr_temp6_min.dev_attr.attr,
2506         &sensor_dev_attr_temp6_type.dev_attr.attr,
2507         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2508         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2509         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2510         NULL
2511 };
2512
2513 static const struct attribute_group it87_group_temp = {
2514         .attrs = it87_attributes_temp,
2515         .is_visible = it87_temp_is_visible,
2516 };
2517
2518 static umode_t it87_is_visible(struct kobject *kobj,
2519                                struct attribute *attr, int index)
2520 {
2521         struct device *dev = container_of(kobj, struct device, kobj);
2522         struct it87_data *data = dev_get_drvdata(dev);
2523
2524         if ((index == 2 || index == 3) && !data->has_vid)
2525                 return 0;
2526
2527         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2528                 return 0;
2529
2530         return attr->mode;
2531 }
2532
2533 static struct attribute *it87_attributes[] = {
2534         &dev_attr_alarms.attr,
2535         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2536         &dev_attr_vrm.attr,                             /* 2 */
2537         &dev_attr_cpu0_vid.attr,                        /* 3 */
2538         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2539         &sensor_dev_attr_in7_label.dev_attr.attr,
2540         &sensor_dev_attr_in8_label.dev_attr.attr,
2541         &sensor_dev_attr_in9_label.dev_attr.attr,
2542         NULL
2543 };
2544
2545 static const struct attribute_group it87_group = {
2546         .attrs = it87_attributes,
2547         .is_visible = it87_is_visible,
2548 };
2549
2550 static umode_t it87_fan_is_visible(struct kobject *kobj,
2551                                    struct attribute *attr, int index)
2552 {
2553         struct device *dev = container_of(kobj, struct device, kobj);
2554         struct it87_data *data = dev_get_drvdata(dev);
2555         int i = index / 5;      /* fan index */
2556         int a = index % 5;      /* attribute index */
2557
2558         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2559                 i = (index - 15) / 4 + 3;
2560                 a = (index - 15) % 4;
2561         }
2562
2563         if (!(data->has_fan & BIT(i)))
2564                 return 0;
2565
2566         if (a == 3) {                           /* beep */
2567                 if (!data->has_beep)
2568                         return 0;
2569                 /* first fan beep attribute is writable */
2570                 if (i == __ffs(data->has_fan))
2571                         return attr->mode | S_IWUSR;
2572         }
2573
2574         if (a == 4 && has_16bit_fans(data))     /* divisor */
2575                 return 0;
2576
2577         return attr->mode;
2578 }
2579
2580 static struct attribute *it87_attributes_fan[] = {
2581         &sensor_dev_attr_fan1_input.dev_attr.attr,
2582         &sensor_dev_attr_fan1_min.dev_attr.attr,
2583         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2584         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2585         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2586
2587         &sensor_dev_attr_fan2_input.dev_attr.attr,
2588         &sensor_dev_attr_fan2_min.dev_attr.attr,
2589         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2590         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2591         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2592
2593         &sensor_dev_attr_fan3_input.dev_attr.attr,
2594         &sensor_dev_attr_fan3_min.dev_attr.attr,
2595         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2596         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2597         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2598
2599         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2600         &sensor_dev_attr_fan4_min.dev_attr.attr,
2601         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2602         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2603
2604         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2605         &sensor_dev_attr_fan5_min.dev_attr.attr,
2606         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2607         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2608
2609         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2610         &sensor_dev_attr_fan6_min.dev_attr.attr,
2611         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2612         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2613         NULL
2614 };
2615
2616 static const struct attribute_group it87_group_fan = {
2617         .attrs = it87_attributes_fan,
2618         .is_visible = it87_fan_is_visible,
2619 };
2620
2621 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2622                                    struct attribute *attr, int index)
2623 {
2624         struct device *dev = container_of(kobj, struct device, kobj);
2625         struct it87_data *data = dev_get_drvdata(dev);
2626         int i = index / 4;      /* pwm index */
2627         int a = index % 4;      /* attribute index */
2628
2629         if (!(data->has_pwm & BIT(i)))
2630                 return 0;
2631
2632         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2633         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2634                 return attr->mode | S_IWUSR;
2635
2636         /* pwm2_freq is writable if there are two pwm frequency selects */
2637         if (has_pwm_freq2(data) && i == 1 && a == 2)
2638                 return attr->mode | S_IWUSR;
2639
2640         return attr->mode;
2641 }
2642
2643 static struct attribute *it87_attributes_pwm[] = {
2644         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2645         &sensor_dev_attr_pwm1.dev_attr.attr,
2646         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2647         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2648
2649         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2650         &sensor_dev_attr_pwm2.dev_attr.attr,
2651         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2652         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2653
2654         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2655         &sensor_dev_attr_pwm3.dev_attr.attr,
2656         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2657         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2658
2659         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2660         &sensor_dev_attr_pwm4.dev_attr.attr,
2661         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2662         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2663
2664         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2665         &sensor_dev_attr_pwm5.dev_attr.attr,
2666         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2667         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2668
2669         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2670         &sensor_dev_attr_pwm6.dev_attr.attr,
2671         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2672         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2673
2674         NULL
2675 };
2676
2677 static const struct attribute_group it87_group_pwm = {
2678         .attrs = it87_attributes_pwm,
2679         .is_visible = it87_pwm_is_visible,
2680 };
2681
2682 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2683                                         struct attribute *attr, int index)
2684 {
2685         struct device *dev = container_of(kobj, struct device, kobj);
2686         struct it87_data *data = dev_get_drvdata(dev);
2687         int i = index / 11;     /* pwm index */
2688         int a = index % 11;     /* attribute index */
2689
2690         if (index >= 33) {      /* pwm 4..6 */
2691                 i = (index - 33) / 6 + 3;
2692                 a = (index - 33) % 6 + 4;
2693         }
2694
2695         if (!(data->has_pwm & BIT(i)))
2696                 return 0;
2697
2698         if (has_newer_autopwm(data)) {
2699                 if (a < 4)      /* no auto point pwm */
2700                         return 0;
2701                 if (a == 8)     /* no auto_point4 */
2702                         return 0;
2703         }
2704         if (has_old_autopwm(data)) {
2705                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2706                         return 0;
2707         }
2708
2709         return attr->mode;
2710 }
2711
2712 static struct attribute *it87_attributes_auto_pwm[] = {
2713         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2714         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2715         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2716         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2717         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2718         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2719         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2720         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2721         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2722         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2723         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2724
2725         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2726         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2727         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2728         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2729         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2730         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2731         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2732         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2733         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2734         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2735         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2736
2737         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2738         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2739         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2740         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2741         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2742         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2743         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2744         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2745         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2746         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2747         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2748
2749         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2750         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2751         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2752         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2753         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2754         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2755
2756         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2757         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2758         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2759         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2760         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2761         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2762
2763         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2764         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2765         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2766         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2767         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2768         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2769
2770         NULL,
2771 };
2772
2773 static const struct attribute_group it87_group_auto_pwm = {
2774         .attrs = it87_attributes_auto_pwm,
2775         .is_visible = it87_auto_pwm_is_visible,
2776 };
2777
2778 /* SuperIO detection - will change isa_address if a chip is found */
2779 static int __init it87_find(int sioaddr, unsigned short *address,
2780                             struct it87_sio_data *sio_data)
2781 {
2782         const struct it87_devices *config;
2783         bool doexit = true;
2784         u16 chip_type;
2785         int err;
2786
2787         err = superio_enter(sioaddr);
2788         if (err)
2789                 return err;
2790
2791         err = -ENODEV;
2792         chip_type = superio_inw(sioaddr, DEVID);
2793         if (chip_type == 0xffff)
2794                 goto exit;
2795
2796         if (force_id)
2797                 chip_type = force_id;
2798
2799         switch (chip_type) {
2800         case IT8705F_DEVID:
2801                 sio_data->type = it87;
2802                 break;
2803         case IT8712F_DEVID:
2804                 sio_data->type = it8712;
2805                 break;
2806         case IT8716F_DEVID:
2807         case IT8726F_DEVID:
2808                 sio_data->type = it8716;
2809                 break;
2810         case IT8718F_DEVID:
2811                 sio_data->type = it8718;
2812                 break;
2813         case IT8720F_DEVID:
2814                 sio_data->type = it8720;
2815                 break;
2816         case IT8721F_DEVID:
2817                 sio_data->type = it8721;
2818                 break;
2819         case IT8728F_DEVID:
2820                 sio_data->type = it8728;
2821                 break;
2822         case IT8732F_DEVID:
2823                 sio_data->type = it8732;
2824                 break;
2825         case IT8792E_DEVID:
2826                 sio_data->type = it8792;
2827                 /*
2828                  * Disabling configuration mode on IT8792E can result in system
2829                  * hang-ups and access failures to the Super-IO chip at the
2830                  * second SIO address. Never exit configuration mode on this
2831                  * chip to avoid the problem.
2832                  */
2833                 doexit = false;
2834                 break;
2835         case IT8771E_DEVID:
2836                 sio_data->type = it8771;
2837                 break;
2838         case IT8772E_DEVID:
2839                 sio_data->type = it8772;
2840                 break;
2841         case IT8781F_DEVID:
2842                 sio_data->type = it8781;
2843                 break;
2844         case IT8782F_DEVID:
2845                 sio_data->type = it8782;
2846                 break;
2847         case IT8783E_DEVID:
2848                 sio_data->type = it8783;
2849                 break;
2850         case IT8786E_DEVID:
2851                 sio_data->type = it8786;
2852                 break;
2853         case IT8790E_DEVID:
2854                 sio_data->type = it8790;
2855                 doexit = false;         /* See IT8792E comment above */
2856                 break;
2857         case IT8603E_DEVID:
2858         case IT8623E_DEVID:
2859                 sio_data->type = it8603;
2860                 break;
2861         case IT8607E_DEVID:
2862                 sio_data->type = it8607;
2863                 break;
2864         case IT8613E_DEVID:
2865                 sio_data->type = it8613;
2866                 break;
2867         case IT8620E_DEVID:
2868                 sio_data->type = it8620;
2869                 break;
2870         case IT8622E_DEVID:
2871                 sio_data->type = it8622;
2872                 break;
2873         case IT8625E_DEVID:
2874                 sio_data->type = it8625;
2875                 break;
2876         case IT8628E_DEVID:
2877                 sio_data->type = it8628;
2878                 break;
2879         case IT8655E_DEVID:
2880                 sio_data->type = it8655;
2881                 break;
2882         case IT8665E_DEVID:
2883                 sio_data->type = it8665;
2884                 break;
2885         case IT8686E_DEVID:
2886                 sio_data->type = it8686;
2887                 break;
2888         case 0xffff:    /* No device at all */
2889                 goto exit;
2890         default:
2891                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2892                 goto exit;
2893         }
2894
2895         superio_select(sioaddr, PME);
2896         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2897                 pr_info("Device not activated, skipping\n");
2898                 goto exit;
2899         }
2900
2901         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2902         if (*address == 0) {
2903                 pr_info("Base address not set, skipping\n");
2904                 goto exit;
2905         }
2906
2907         err = 0;
2908         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2909         pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2910                 it87_devices[sio_data->type].suffix,
2911                 *address, sio_data->revision);
2912
2913         config = &it87_devices[sio_data->type];
2914
2915         /* in7 (VSB or VCCH5V) is always internal on some chips */
2916         if (has_in7_internal(config))
2917                 sio_data->internal |= BIT(1);
2918
2919         /* in8 (Vbat) is always internal */
2920         sio_data->internal |= BIT(2);
2921
2922         /* in9 (AVCC3), always internal if supported */
2923         if (has_avcc3(config))
2924                 sio_data->internal |= BIT(3); /* in9 is AVCC */
2925         else
2926                 sio_data->skip_in |= BIT(9);
2927
2928         if (!has_four_pwm(config))
2929                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2930         else if (!has_five_pwm(config))
2931                 sio_data->skip_pwm |= BIT(4) | BIT(5);
2932         else if (!has_six_pwm(config))
2933                 sio_data->skip_pwm |= BIT(5);
2934
2935         if (!has_vid(config))
2936                 sio_data->skip_vid = 1;
2937
2938         /* Read GPIO config and VID value from LDN 7 (GPIO) */
2939         if (sio_data->type == it87) {
2940                 /* The IT8705F has a different LD number for GPIO */
2941                 superio_select(sioaddr, 5);
2942                 sio_data->beep_pin = superio_inb(sioaddr,
2943                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
2944         } else if (sio_data->type == it8783) {
2945                 int reg25, reg27, reg2a, reg2c, regef;
2946
2947                 superio_select(sioaddr, GPIO);
2948
2949                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2950                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2951                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2952                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2953                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2954
2955                 /* Check if fan3 is there or not */
2956                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2957                         sio_data->skip_fan |= BIT(2);
2958                 if ((reg25 & BIT(4)) ||
2959                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
2960                         sio_data->skip_pwm |= BIT(2);
2961
2962                 /* Check if fan2 is there or not */
2963                 if (reg27 & BIT(7))
2964                         sio_data->skip_fan |= BIT(1);
2965                 if (reg27 & BIT(3))
2966                         sio_data->skip_pwm |= BIT(1);
2967
2968                 /* VIN5 */
2969                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2970                         sio_data->skip_in |= BIT(5); /* No VIN5 */
2971
2972                 /* VIN6 */
2973                 if (reg27 & BIT(1))
2974                         sio_data->skip_in |= BIT(6); /* No VIN6 */
2975
2976                 /*
2977                  * VIN7
2978                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2979                  */
2980                 if (reg27 & BIT(2)) {
2981                         /*
2982                          * The data sheet is a bit unclear regarding the
2983                          * internal voltage divider for VCCH5V. It says
2984                          * "This bit enables and switches VIN7 (pin 91) to the
2985                          * internal voltage divider for VCCH5V".
2986                          * This is different to other chips, where the internal
2987                          * voltage divider would connect VIN7 to an internal
2988                          * voltage source. Maybe that is the case here as well.
2989                          *
2990                          * Since we don't know for sure, re-route it if that is
2991                          * not the case, and ask the user to report if the
2992                          * resulting voltage is sane.
2993                          */
2994                         if (!(reg2c & BIT(1))) {
2995                                 reg2c |= BIT(1);
2996                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2997                                              reg2c);
2998                                 pr_notice("Routing internal VCCH5V to in7.\n");
2999                         }
3000                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3001                         pr_notice("Please report if it displays a reasonable voltage.\n");
3002                 }
3003
3004                 if (reg2c & BIT(0))
3005                         sio_data->internal |= BIT(0);
3006                 if (reg2c & BIT(1))
3007                         sio_data->internal |= BIT(1);
3008
3009                 sio_data->beep_pin = superio_inb(sioaddr,
3010                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3011         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3012                 int reg27, reg29;
3013
3014                 superio_select(sioaddr, GPIO);
3015
3016                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3017
3018                 /* Check if fan3 is there or not */
3019                 if (reg27 & BIT(6))
3020                         sio_data->skip_pwm |= BIT(2);
3021                 if (reg27 & BIT(7))
3022                         sio_data->skip_fan |= BIT(2);
3023
3024                 /* Check if fan2 is there or not */
3025                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3026                 if (reg29 & BIT(1))
3027                         sio_data->skip_pwm |= BIT(1);
3028                 if (reg29 & BIT(2))
3029                         sio_data->skip_fan |= BIT(1);
3030
3031                 switch (sio_data->type) {
3032                 case it8603:
3033                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3034                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3035                         break;
3036                 case it8607:
3037                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3038                         sio_data->skip_fan |= BIT(0);
3039                 default:
3040                         break;
3041                 }
3042
3043                 sio_data->beep_pin = superio_inb(sioaddr,
3044                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3045         } else if (sio_data->type == it8613) {
3046                 int reg27, reg29, reg2a;
3047
3048                 superio_select(sioaddr, GPIO);
3049
3050                 /* Check for pwm3, fan3, pwm5, fan5 */
3051                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3052                 if (reg27 & BIT(1))
3053                         sio_data->skip_fan |= BIT(4);
3054                 if (reg27 & BIT(3))
3055                         sio_data->skip_pwm |= BIT(4);
3056                 if (reg27 & BIT(6))
3057                         sio_data->skip_pwm |= BIT(2);
3058                 if (reg27 & BIT(7))
3059                         sio_data->skip_fan |= BIT(2);
3060
3061                 /* Check for pwm2, fan2 */
3062                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3063                 if (reg29 & BIT(1))
3064                         sio_data->skip_pwm |= BIT(1);
3065                 if (reg29 & BIT(2))
3066                         sio_data->skip_fan |= BIT(1);
3067
3068                 /* Check for pwm4, fan4 */
3069                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3070                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3071                         sio_data->skip_fan |= BIT(3);
3072                         sio_data->skip_pwm |= BIT(3);
3073                 }
3074
3075                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3076                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3077                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3078                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3079
3080                 sio_data->beep_pin = superio_inb(sioaddr,
3081                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3082         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3083                    sio_data->type == it8686) {
3084                 int reg;
3085
3086                 superio_select(sioaddr, GPIO);
3087
3088                 /* Check for pwm5 */
3089                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3090                 if (reg & BIT(6))
3091                         sio_data->skip_pwm |= BIT(4);
3092
3093                 /* Check for fan4, fan5 */
3094                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3095                 if (!(reg & BIT(5)))
3096                         sio_data->skip_fan |= BIT(3);
3097                 if (!(reg & BIT(4)))
3098                         sio_data->skip_fan |= BIT(4);
3099
3100                 /* Check for pwm3, fan3 */
3101                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3102                 if (reg & BIT(6))
3103                         sio_data->skip_pwm |= BIT(2);
3104                 if (reg & BIT(7))
3105                         sio_data->skip_fan |= BIT(2);
3106
3107                 /* Check for pwm4 */
3108                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3109                 if (reg & BIT(2))
3110                         sio_data->skip_pwm |= BIT(3);
3111
3112                 /* Check for pwm2, fan2 */
3113                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3114                 if (reg & BIT(1))
3115                         sio_data->skip_pwm |= BIT(1);
3116                 if (reg & BIT(2))
3117                         sio_data->skip_fan |= BIT(1);
3118                 /* Check for pwm6, fan6 */
3119                 if (!(reg & BIT(7))) {
3120                         sio_data->skip_pwm |= BIT(5);
3121                         sio_data->skip_fan |= BIT(5);
3122                 }
3123
3124                 /* Check if AVCC is on VIN3 */
3125                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3126                 if (reg & BIT(0)) {
3127                         /* For it8686, the bit just enables AVCC3 */
3128                         if (sio_data->type != it8686)
3129                                 sio_data->internal |= BIT(0);
3130                 } else {
3131                         sio_data->internal &= ~BIT(3);
3132                         sio_data->skip_in |= BIT(9);
3133                 }
3134
3135                 sio_data->beep_pin = superio_inb(sioaddr,
3136                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3137         } else if (sio_data->type == it8622) {
3138                 int reg;
3139
3140                 superio_select(sioaddr, GPIO);
3141
3142                 /* Check for pwm4, fan4 */
3143                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3144                 if (reg & BIT(6))
3145                         sio_data->skip_fan |= BIT(3);
3146                 if (reg & BIT(5))
3147                         sio_data->skip_pwm |= BIT(3);
3148
3149                 /* Check for pwm3, fan3, pwm5, fan5 */
3150                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3151                 if (reg & BIT(6))
3152                         sio_data->skip_pwm |= BIT(2);
3153                 if (reg & BIT(7))
3154                         sio_data->skip_fan |= BIT(2);
3155                 if (reg & BIT(3))
3156                         sio_data->skip_pwm |= BIT(4);
3157                 if (reg & BIT(1))
3158                         sio_data->skip_fan |= BIT(4);
3159
3160                 /* Check for pwm2, fan2 */
3161                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3162                 if (reg & BIT(1))
3163                         sio_data->skip_pwm |= BIT(1);
3164                 if (reg & BIT(2))
3165                         sio_data->skip_fan |= BIT(1);
3166
3167                 /* Check for AVCC */
3168                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3169                 if (!(reg & BIT(0)))
3170                         sio_data->skip_in |= BIT(9);
3171
3172                 sio_data->beep_pin = superio_inb(sioaddr,
3173                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3174         } else if (sio_data->type == it8732) {
3175                 int reg;
3176
3177                 superio_select(sioaddr, GPIO);
3178
3179                 /* Check for pwm2, fan2 */
3180                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3181                 if (reg & BIT(1))
3182                         sio_data->skip_pwm |= BIT(1);
3183                 if (reg & BIT(2))
3184                         sio_data->skip_fan |= BIT(1);
3185
3186                 /* Check for pwm3, fan3, fan4 */
3187                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3188                 if (reg & BIT(6))
3189                         sio_data->skip_pwm |= BIT(2);
3190                 if (reg & BIT(7))
3191                         sio_data->skip_fan |= BIT(2);
3192                 if (reg & BIT(5))
3193                         sio_data->skip_fan |= BIT(3);
3194
3195                 /* Check if AVCC is on VIN3 */
3196                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3197                 if (reg & BIT(0))
3198                         sio_data->internal |= BIT(0);
3199
3200                 sio_data->beep_pin = superio_inb(sioaddr,
3201                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3202         } else if (sio_data->type == it8655) {
3203                 int reg;
3204
3205                 superio_select(sioaddr, GPIO);
3206
3207                 /* Check for pwm2 */
3208                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3209                 if (reg & BIT(1))
3210                         sio_data->skip_pwm |= BIT(1);
3211
3212                 /* Check for fan2 */
3213                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3214                 if (reg & BIT(4))
3215                         sio_data->skip_fan |= BIT(1);
3216
3217                 /* Check for pwm3, fan3 */
3218                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3219                 if (reg & BIT(6))
3220                         sio_data->skip_pwm |= BIT(2);
3221                 if (reg & BIT(7))
3222                         sio_data->skip_fan |= BIT(2);
3223
3224                 sio_data->beep_pin = superio_inb(sioaddr,
3225                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3226         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3227                 int reg27, reg29, reg2d, regd3;
3228
3229                 superio_select(sioaddr, GPIO);
3230
3231                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3232                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3233                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3234                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3235
3236                 /* Check for pwm2, fan2 */
3237                 if (reg29 & BIT(1))
3238                         sio_data->skip_pwm |= BIT(1);
3239                 if (reg2d & BIT(4))
3240                         sio_data->skip_fan |= BIT(1);
3241
3242                 /* Check for pwm3, fan3 */
3243                 if (reg27 & BIT(6))
3244                         sio_data->skip_pwm |= BIT(2);
3245                 if (reg27 & BIT(7))
3246                         sio_data->skip_fan |= BIT(2);
3247
3248                 /* Check for pwm4, fan4, pwm5, fan5 */
3249                 if (sio_data->type == it8625) {
3250                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3251
3252                         if (reg25 & BIT(6))
3253                                 sio_data->skip_fan |= BIT(3);
3254                         if (reg25 & BIT(5))
3255                                 sio_data->skip_pwm |= BIT(3);
3256                         if (reg27 & BIT(3))
3257                                 sio_data->skip_pwm |= BIT(4);
3258                         if (reg27 & BIT(1))
3259                                 sio_data->skip_fan |= BIT(4);
3260                 } else {
3261                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3262
3263                         if (regd3 & BIT(2))
3264                                 sio_data->skip_pwm |= BIT(3);
3265                         if (regd3 & BIT(3))
3266                                 sio_data->skip_fan |= BIT(3);
3267                         if (reg26 & BIT(5))
3268                                 sio_data->skip_pwm |= BIT(4);
3269                         if (!(reg26 & BIT(4)))
3270                                 sio_data->skip_fan |= BIT(4);
3271                 }
3272
3273                 /* Check for pwm6, fan6 */
3274                 if (regd3 & BIT(0))
3275                         sio_data->skip_pwm |= BIT(5);
3276                 if (regd3 & BIT(1))
3277                         sio_data->skip_fan |= BIT(5);
3278
3279                 sio_data->beep_pin = superio_inb(sioaddr,
3280                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3281         } else {
3282                 int reg;
3283                 bool uart6;
3284
3285                 superio_select(sioaddr, GPIO);
3286
3287                 /* Check for fan4, fan5 */
3288                 if (has_five_fans(config)) {
3289                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3290                         switch (sio_data->type) {
3291                         case it8718:
3292                                 if (reg & BIT(5))
3293                                         sio_data->skip_fan |= BIT(3);
3294                                 if (reg & BIT(4))
3295                                         sio_data->skip_fan |= BIT(4);
3296                                 break;
3297                         case it8720:
3298                         case it8721:
3299                         case it8728:
3300                                 if (!(reg & BIT(5)))
3301                                         sio_data->skip_fan |= BIT(3);
3302                                 if (!(reg & BIT(4)))
3303                                         sio_data->skip_fan |= BIT(4);
3304                                 break;
3305                         default:
3306                                 break;
3307                         }
3308                 }
3309
3310                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3311                 if (!sio_data->skip_vid) {
3312                         /* We need at least 4 VID pins */
3313                         if (reg & 0x0f) {
3314                                 pr_info("VID is disabled (pins used for GPIO)\n");
3315                                 sio_data->skip_vid = 1;
3316                         }
3317                 }
3318
3319                 /* Check if fan3 is there or not */
3320                 if (reg & BIT(6))
3321                         sio_data->skip_pwm |= BIT(2);
3322                 if (reg & BIT(7))
3323                         sio_data->skip_fan |= BIT(2);
3324
3325                 /* Check if fan2 is there or not */
3326                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3327                 if (reg & BIT(1))
3328                         sio_data->skip_pwm |= BIT(1);
3329                 if (reg & BIT(2))
3330                         sio_data->skip_fan |= BIT(1);
3331
3332                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3333                     !(sio_data->skip_vid))
3334                         sio_data->vid_value = superio_inb(sioaddr,
3335                                                           IT87_SIO_VID_REG);
3336
3337                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3338
3339                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3340
3341                 /*
3342                  * The IT8720F has no VIN7 pin, so VCCH should always be
3343                  * routed internally to VIN7 with an internal divider.
3344                  * Curiously, there still is a configuration bit to control
3345                  * this, which means it can be set incorrectly. And even
3346                  * more curiously, many boards out there are improperly
3347                  * configured, even though the IT8720F datasheet claims
3348                  * that the internal routing of VCCH to VIN7 is the default
3349                  * setting. So we force the internal routing in this case.
3350                  *
3351                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3352                  * If UART6 is enabled, re-route VIN7 to the internal divider
3353                  * if that is not already the case.
3354                  */
3355                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3356                         reg |= BIT(1);
3357                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3358                         pr_notice("Routing internal VCCH to in7\n");
3359                 }
3360                 if (reg & BIT(0))
3361                         sio_data->internal |= BIT(0);
3362                 if (reg & BIT(1))
3363                         sio_data->internal |= BIT(1);
3364
3365                 /*
3366                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3367                  * While VIN7 can be routed to the internal voltage divider,
3368                  * VIN5 and VIN6 are not available if UART6 is enabled.
3369                  *
3370                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3371                  * is the temperature source. Since we can not read the
3372                  * temperature source here, skip_temp is preliminary.
3373                  */
3374                 if (uart6) {
3375                         sio_data->skip_in |= BIT(5) | BIT(6);
3376                         sio_data->skip_temp |= BIT(2);
3377                 }
3378
3379                 sio_data->beep_pin = superio_inb(sioaddr,
3380                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3381         }
3382         if (sio_data->beep_pin)
3383                 pr_info("Beeping is supported\n");
3384
3385 exit:
3386         superio_exit(sioaddr, doexit);
3387         return err;
3388 }
3389
3390 static void it87_init_regs(struct platform_device *pdev)
3391 {
3392         struct it87_data *data = platform_get_drvdata(pdev);
3393
3394         /* Initialize chip specific register pointers */
3395         switch (data->type) {
3396         case it8628:
3397         case it8686:
3398                 data->REG_FAN = IT87_REG_FAN;
3399                 data->REG_FANX = IT87_REG_FANX;
3400                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3401                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3402                 data->REG_PWM = IT87_REG_PWM;
3403                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3404                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3405                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3406                 break;
3407         case it8625:
3408         case it8655:
3409         case it8665:
3410                 data->REG_FAN = IT87_REG_FAN_8665;
3411                 data->REG_FANX = IT87_REG_FANX_8665;
3412                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3413                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3414                 data->REG_PWM = IT87_REG_PWM_8665;
3415                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3416                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3417                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3418                 break;
3419         case it8622:
3420                 data->REG_FAN = IT87_REG_FAN;
3421                 data->REG_FANX = IT87_REG_FANX;
3422                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3423                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3424                 data->REG_PWM = IT87_REG_PWM_8665;
3425                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3426                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3427                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3428                 break;
3429         case it8613:
3430                 data->REG_FAN = IT87_REG_FAN;
3431                 data->REG_FANX = IT87_REG_FANX;
3432                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3433                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3434                 data->REG_PWM = IT87_REG_PWM_8665;
3435                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3436                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3437                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3438                 break;
3439         default:
3440                 data->REG_FAN = IT87_REG_FAN;
3441                 data->REG_FANX = IT87_REG_FANX;
3442                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3443                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3444                 data->REG_PWM = IT87_REG_PWM;
3445                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3446                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3447                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3448                 break;
3449         }
3450 }
3451
3452 /* Called when we have found a new IT87. */
3453 static void it87_init_device(struct platform_device *pdev)
3454 {
3455         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3456         struct it87_data *data = platform_get_drvdata(pdev);
3457         int tmp, i;
3458         u8 mask;
3459
3460         if (has_new_tempmap(data)) {
3461                 data->pwm_temp_map_shift = 3;
3462                 data->pwm_temp_map_mask = 0x07;
3463         } else {
3464                 data->pwm_temp_map_shift = 0;
3465                 data->pwm_temp_map_mask = 0x03;
3466         }
3467
3468         /*
3469          * For each PWM channel:
3470          * - If it is in automatic mode, setting to manual mode should set
3471          *   the fan to full speed by default.
3472          * - If it is in manual mode, we need a mapping to temperature
3473          *   channels to use when later setting to automatic mode later.
3474          *   Map to the first sensor by default (we are clueless.)
3475          * In both cases, the value can (and should) be changed by the user
3476          * prior to switching to a different mode.
3477          * Note that this is no longer needed for the IT8721F and later, as
3478          * these have separate registers for the temperature mapping and the
3479          * manual duty cycle.
3480          */
3481         for (i = 0; i < NUM_AUTO_PWM; i++) {
3482                 data->pwm_temp_map[i] = 0;
3483                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3484                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3485         }
3486
3487         /*
3488          * Some chips seem to have default value 0xff for all limit
3489          * registers. For low voltage limits it makes no sense and triggers
3490          * alarms, so change to 0 instead. For high temperature limits, it
3491          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3492          * but is still confusing, so change to 127 degrees C.
3493          */
3494         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3495                 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3496                 if (tmp == 0xff)
3497                         it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3498         }
3499         for (i = 0; i < data->num_temp_limit; i++) {
3500                 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3501                 if (tmp == 0xff)
3502                         it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3503         }
3504
3505         /*
3506          * Temperature channels are not forcibly enabled, as they can be
3507          * set to two different sensor types and we can't guess which one
3508          * is correct for a given system. These channels can be enabled at
3509          * run-time through the temp{1-3}_type sysfs accessors if needed.
3510          */
3511
3512         /* Check if voltage monitors are reset manually or by some reason */
3513         tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3514         if ((tmp & 0xff) == 0) {
3515                 /* Enable all voltage monitors */
3516                 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3517         }
3518
3519         /* Check if tachometers are reset manually or by some reason */
3520         mask = 0x70 & ~(sio_data->skip_fan << 4);
3521         data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3522         if ((data->fan_main_ctrl & mask) == 0) {
3523                 /* Enable all fan tachometers */
3524                 data->fan_main_ctrl |= mask;
3525                 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3526                                  data->fan_main_ctrl);
3527         }
3528         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3529
3530         tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3531
3532         /* Set tachometers to 16-bit mode if needed */
3533         if (has_fan16_config(data)) {
3534                 if (~tmp & 0x07 & data->has_fan) {
3535                         dev_dbg(&pdev->dev,
3536                                 "Setting fan1-3 to 16-bit mode\n");
3537                         it87_write_value(data, IT87_REG_FAN_16BIT,
3538                                          tmp | 0x07);
3539                 }
3540         }
3541
3542         /* Check for additional fans */
3543         if (has_four_fans(data) && (tmp & BIT(4)))
3544                 data->has_fan |= BIT(3); /* fan4 enabled */
3545         if (has_five_fans(data) && (tmp & BIT(5)))
3546                 data->has_fan |= BIT(4); /* fan5 enabled */
3547         if (has_six_fans(data)) {
3548                 switch (data->type) {
3549                 case it8620:
3550                 case it8628:
3551                 case it8686:
3552                         if (tmp & BIT(2))
3553                                 data->has_fan |= BIT(5); /* fan6 enabled */
3554                         break;
3555                 case it8625:
3556                 case it8665:
3557                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3558                         if (tmp & BIT(3))
3559                                 data->has_fan |= BIT(5); /* fan6 enabled */
3560                         break;
3561                 default:
3562                         break;
3563                 }
3564         }
3565
3566         /* Fan input pins may be used for alternative functions */
3567         data->has_fan &= ~sio_data->skip_fan;
3568
3569         /* Check if pwm6 is enabled */
3570         if (has_six_pwm(data)) {
3571                 switch (data->type) {
3572                 case it8620:
3573                 case it8686:
3574                         tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3575                         if (!(tmp & BIT(3)))
3576                                 sio_data->skip_pwm |= BIT(5);
3577                         break;
3578                 default:
3579                         break;
3580                 }
3581         }
3582
3583         /* Start monitoring */
3584         it87_write_value(data, IT87_REG_CONFIG,
3585                          (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3586                          | (update_vbat ? 0x41 : 0x01));
3587 }
3588
3589 /* Return 1 if and only if the PWM interface is safe to use */
3590 static int it87_check_pwm(struct device *dev)
3591 {
3592         struct it87_data *data = dev_get_drvdata(dev);
3593         /*
3594          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3595          * and polarity set to active low is sign that this is the case so we
3596          * disable pwm control to protect the user.
3597          */
3598         int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3599
3600         if ((tmp & 0x87) == 0) {
3601                 if (fix_pwm_polarity) {
3602                         /*
3603                          * The user asks us to attempt a chip reconfiguration.
3604                          * This means switching to active high polarity and
3605                          * inverting all fan speed values.
3606                          */
3607                         int i;
3608                         u8 pwm[3];
3609
3610                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3611                                 pwm[i] = it87_read_value(data,
3612                                                          data->REG_PWM[i]);
3613
3614                         /*
3615                          * If any fan is in automatic pwm mode, the polarity
3616                          * might be correct, as suspicious as it seems, so we
3617                          * better don't change anything (but still disable the
3618                          * PWM interface).
3619                          */
3620                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3621                                 dev_info(dev,
3622                                          "Reconfiguring PWM to active high polarity\n");
3623                                 it87_write_value(data, IT87_REG_FAN_CTL,
3624                                                  tmp | 0x87);
3625                                 for (i = 0; i < 3; i++)
3626                                         it87_write_value(data,
3627                                                          data->REG_PWM[i],
3628                                                          0x7f & ~pwm[i]);
3629                                 return 1;
3630                         }
3631
3632                         dev_info(dev,
3633                                  "PWM configuration is too broken to be fixed\n");
3634                 }
3635
3636                 dev_info(dev,
3637                          "Detected broken BIOS defaults, disabling PWM interface\n");
3638                 return 0;
3639         } else if (fix_pwm_polarity) {
3640                 dev_info(dev,
3641                          "PWM configuration looks sane, won't touch\n");
3642         }
3643
3644         return 1;
3645 }
3646
3647 static int it87_probe(struct platform_device *pdev)
3648 {
3649         struct it87_data *data;
3650         struct resource *res;
3651         struct device *dev = &pdev->dev;
3652         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3653         int enable_pwm_interface;
3654         struct device *hwmon_dev;
3655
3656         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3657         if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3658                                  DRVNAME)) {
3659                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3660                         (unsigned long)res->start,
3661                         (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3662                 return -EBUSY;
3663         }
3664
3665         data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3666         if (!data)
3667                 return -ENOMEM;
3668
3669         data->addr = res->start;
3670         data->type = sio_data->type;
3671         data->features = it87_devices[sio_data->type].features;
3672         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3673         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3674         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3675         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3676         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3677
3678         /*
3679          * IT8705F Datasheet 0.4.1, 3h == Version G.
3680          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3681          * These are the first revisions with 16-bit tachometer support.
3682          */
3683         switch (data->type) {
3684         case it87:
3685                 if (sio_data->revision >= 0x03) {
3686                         data->features &= ~FEAT_OLD_AUTOPWM;
3687                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3688                 }
3689                 break;
3690         case it8712:
3691                 if (sio_data->revision >= 0x08) {
3692                         data->features &= ~FEAT_OLD_AUTOPWM;
3693                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3694                                           FEAT_FIVE_FANS;
3695                 }
3696                 break;
3697         default:
3698                 break;
3699         }
3700
3701         /* Now, we do the remaining detection. */
3702         if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3703             it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3704                 return -ENODEV;
3705
3706         platform_set_drvdata(pdev, data);
3707
3708         mutex_init(&data->update_lock);
3709
3710         /* Initialize register pointers */
3711         it87_init_regs(pdev);
3712
3713         /* Check PWM configuration */
3714         enable_pwm_interface = it87_check_pwm(dev);
3715
3716         /* Starting with IT8721F, we handle scaling of internal voltages */
3717         if (has_scaling(data)) {
3718                 if (sio_data->internal & BIT(0))
3719                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3720                 if (sio_data->internal & BIT(1))
3721                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3722                 if (sio_data->internal & BIT(2))
3723                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3724                 if (sio_data->internal & BIT(3))
3725                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3726         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3727                    sio_data->type == it8783) {
3728                 if (sio_data->internal & BIT(0))
3729                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3730                 if (sio_data->internal & BIT(1))
3731                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3732         }
3733
3734         data->has_temp = 0x07;
3735         if (sio_data->skip_temp & BIT(2)) {
3736                 if (sio_data->type == it8782 &&
3737                     !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3738                         data->has_temp &= ~BIT(2);
3739         }
3740
3741         data->in_internal = sio_data->internal;
3742         data->has_in = 0x3ff & ~sio_data->skip_in;
3743
3744         if (has_six_temp(data)) {
3745                 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3746
3747                 /* Check for additional temperature sensors */
3748                 if ((reg & 0x03) >= 0x02)
3749                         data->has_temp |= BIT(3);
3750                 if (((reg >> 2) & 0x03) >= 0x02)
3751                         data->has_temp |= BIT(4);
3752                 if (((reg >> 4) & 0x03) >= 0x02)
3753                         data->has_temp |= BIT(5);
3754
3755                 /* Check for additional voltage sensors */
3756                 if ((reg & 0x03) == 0x01)
3757                         data->has_in |= BIT(10);
3758                 if (((reg >> 2) & 0x03) == 0x01)
3759                         data->has_in |= BIT(11);
3760                 if (((reg >> 4) & 0x03) == 0x01)
3761                         data->has_in |= BIT(12);
3762         }
3763
3764         data->has_beep = !!sio_data->beep_pin;
3765
3766         /* Initialize the IT87 chip */
3767         it87_init_device(pdev);
3768
3769         if (!sio_data->skip_vid) {
3770                 data->has_vid = true;
3771                 data->vrm = vid_which_vrm();
3772                 /* VID reading from Super-I/O config space if available */
3773                 data->vid = sio_data->vid_value;
3774         }
3775
3776         /* Prepare for sysfs hooks */
3777         data->groups[0] = &it87_group;
3778         data->groups[1] = &it87_group_in;
3779         data->groups[2] = &it87_group_temp;
3780         data->groups[3] = &it87_group_fan;
3781
3782         if (enable_pwm_interface) {
3783                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3784                 data->has_pwm &= ~sio_data->skip_pwm;
3785
3786                 data->groups[4] = &it87_group_pwm;
3787                 if (has_old_autopwm(data) || has_newer_autopwm(data))
3788                         data->groups[5] = &it87_group_auto_pwm;
3789         }
3790
3791         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3792                                         it87_devices[sio_data->type].name,
3793                                         data, data->groups);
3794         return PTR_ERR_OR_ZERO(hwmon_dev);
3795 }
3796
3797 static struct platform_driver it87_driver = {
3798         .driver = {
3799                 .name   = DRVNAME,
3800         },
3801         .probe  = it87_probe,
3802 };
3803
3804 static int __init it87_device_add(int index, unsigned short address,
3805                                   const struct it87_sio_data *sio_data)
3806 {
3807         struct platform_device *pdev;
3808         struct resource res = {
3809                 .start  = address + IT87_EC_OFFSET,
3810                 .end    = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3811                 .name   = DRVNAME,
3812                 .flags  = IORESOURCE_IO,
3813         };
3814         int err;
3815
3816         err = acpi_check_resource_conflict(&res);
3817         if (err) {
3818                 if (!ignore_resource_conflict)
3819                         return err;
3820         }
3821
3822         pdev = platform_device_alloc(DRVNAME, address);
3823         if (!pdev)
3824                 return -ENOMEM;
3825
3826         err = platform_device_add_resources(pdev, &res, 1);
3827         if (err) {
3828                 pr_err("Device resource addition failed (%d)\n", err);
3829                 goto exit_device_put;
3830         }
3831
3832         err = platform_device_add_data(pdev, sio_data,
3833                                        sizeof(struct it87_sio_data));
3834         if (err) {
3835                 pr_err("Platform data allocation failed\n");
3836                 goto exit_device_put;
3837         }
3838
3839         err = platform_device_add(pdev);
3840         if (err) {
3841                 pr_err("Device addition failed (%d)\n", err);
3842                 goto exit_device_put;
3843         }
3844
3845         it87_pdev[index] = pdev;
3846         return 0;
3847
3848 exit_device_put:
3849         platform_device_put(pdev);
3850         return err;
3851 }
3852
3853 struct it87_dmi_data {
3854         bool sio2_force_config; /* force sio2 into configuration mode   */
3855         u8 skip_pwm;            /* pwm channels to skip for this board  */
3856 };
3857
3858 /*
3859  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
3860  * (IT8792E) needs to be in configuration mode before accessing the first
3861  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
3862  * This needs to be done before accessing the first Super-IO chip since
3863  * the second chip may have been accessed prior to loading this driver.
3864  *
3865  * The problem is also reported to affect IT8795E, which is used on X299 boards
3866  * and has the same chip ID as IT8792E (0x8733). It also appears to affect
3867  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
3868  * Z87X-OC.
3869  * DMI entries for those systems will be added as they become available and
3870  * as the problem is confirmed to affect those boards.
3871  */
3872 static struct it87_dmi_data gigabyte_sio2_force = {
3873         .sio2_force_config = true,
3874 };
3875
3876 /*
3877  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3878  * connected to a fan, but to something else. One user
3879  * has reported instant system power-off when changing
3880  * the PWM2 duty cycle, so we disable it.
3881  * I use the board name string as the trigger in case
3882  * the same board is ever used in other systems.
3883  */
3884 static struct it87_dmi_data nvidia_fn68pt = {
3885         .skip_pwm = BIT(1),
3886 };
3887
3888 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3889         {
3890                 .matches = {
3891                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3892                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
3893                 },
3894                 .driver_data = &gigabyte_sio2_force,
3895         },
3896         {
3897                 .matches = {
3898                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3899                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
3900                 },
3901                 .driver_data = &gigabyte_sio2_force,
3902         },
3903         {
3904                 .matches = {
3905                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3906                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
3907                 },
3908                 .driver_data = &gigabyte_sio2_force,
3909         },
3910         {
3911                 .matches = {
3912                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3913                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3914                 },
3915                 .driver_data = &nvidia_fn68pt,
3916         },
3917         { }
3918 };
3919
3920 static int __init sm_it87_init(void)
3921 {
3922         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3923         struct it87_dmi_data *dmi_data = NULL;
3924         int sioaddr[2] = { REG_2E, REG_4E };
3925         struct it87_sio_data sio_data;
3926         unsigned short isa_address;
3927         bool found = false;
3928         int i, err;
3929
3930         if (dmi)
3931                 dmi_data = dmi->driver_data;
3932
3933         err = platform_driver_register(&it87_driver);
3934         if (err)
3935                 return err;
3936
3937         if (dmi_data && dmi_data->sio2_force_config)
3938                 __superio_enter(REG_4E);
3939
3940         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3941                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3942                 isa_address = 0;
3943                 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3944                 if (err || isa_address == 0)
3945                         continue;
3946
3947                 if (dmi_data)
3948                         sio_data.skip_pwm |= dmi_data->skip_pwm;
3949                 err = it87_device_add(i, isa_address, &sio_data);
3950                 if (err)
3951                         goto exit_dev_unregister;
3952                 found = true;
3953         }
3954
3955         if (!found) {
3956                 err = -ENODEV;
3957                 goto exit_unregister;
3958         }
3959         return 0;
3960
3961 exit_dev_unregister:
3962         /* NULL check handled by platform_device_unregister */
3963         platform_device_unregister(it87_pdev[0]);
3964 exit_unregister:
3965         platform_driver_unregister(&it87_driver);
3966         return err;
3967 }
3968
3969 static void __exit sm_it87_exit(void)
3970 {
3971         /* NULL check handled by platform_device_unregister */
3972         platform_device_unregister(it87_pdev[1]);
3973         platform_device_unregister(it87_pdev[0]);
3974         platform_driver_unregister(&it87_driver);
3975 }
3976
3977 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3978 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3979 module_param(update_vbat, bool, 0);
3980 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3981 module_param(fix_pwm_polarity, bool, 0);
3982 MODULE_PARM_DESC(fix_pwm_polarity,
3983                  "Force PWM polarity to active high (DANGEROUS)");
3984 MODULE_LICENSE("GPL");
3985
3986 module_init(sm_it87_init);
3987 module_exit(sm_it87_exit);