git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8607E  Super I/O chip w/LPC interface
  15  *            IT8613E  Super I/O chip w/LPC interface
  16  *            IT8620E  Super I/O chip w/LPC interface
  17  *            IT8622E  Super I/O chip w/LPC interface
  18  *            IT8623E  Super I/O chip w/LPC interface
  19  *            IT8625E  Super I/O chip w/LPC interface
  20  *            IT8628E  Super I/O chip w/LPC interface
  21  *            IT8655E  Super I/O chip w/LPC interface
  22  *            IT8665E  Super I/O chip w/LPC interface
  23  *            IT8686E  Super I/O chip w/LPC interface
  24  *            IT8705F  Super I/O chip w/LPC interface
  25  *            IT8712F  Super I/O chip w/LPC interface
  26  *            IT8716F  Super I/O chip w/LPC interface
  27  *            IT8718F  Super I/O chip w/LPC interface
  28  *            IT8720F  Super I/O chip w/LPC interface
  29  *            IT8721F  Super I/O chip w/LPC interface
  30  *            IT8726F  Super I/O chip w/LPC interface
  31  *            IT8728F  Super I/O chip w/LPC interface
  32  *            IT8732F  Super I/O chip w/LPC interface
  33  *            IT8758E  Super I/O chip w/LPC interface
  34  *            IT8771E  Super I/O chip w/LPC interface
  35  *            IT8772E  Super I/O chip w/LPC interface
  36  *            IT8781F  Super I/O chip w/LPC interface
  37  *            IT8782F  Super I/O chip w/LPC interface
  38  *            IT8783E/F Super I/O chip w/LPC interface
  39  *            IT8786E  Super I/O chip w/LPC interface
  40  *            IT8790E  Super I/O chip w/LPC interface
  41  *            IT8792E  Super I/O chip w/LPC interface
  42  *            Sis950   A clone of the IT8705F
  43  *
  44  *  Copyright (C) 2001 Chris Gauthron
  45  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  46  *
  47  *  This program is free software; you can redistribute it and/or modify
  48  *  it under the terms of the GNU General Public License as published by
  49  *  the Free Software Foundation; either version 2 of the License, or
  50  *  (at your option) any later version.
  51  *
  52  *  This program is distributed in the hope that it will be useful,
  53  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  54  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  55  *  GNU General Public License for more details.
  56  */
  57
  58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  59
  60 #include <linux/bitops.h>
  61 #include <linux/module.h>
  62 #include <linux/init.h>
  63 #include <linux/slab.h>
  64 #include <linux/jiffies.h>
  65 #include <linux/platform_device.h>
  66 #include <linux/hwmon.h>
  67 #include <linux/hwmon-sysfs.h>
  68 #include <linux/hwmon-vid.h>
  69 #include <linux/err.h>
  70 #include <linux/mutex.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/string.h>
  73 #include <linux/dmi.h>
  74 #include <linux/acpi.h>
  75 #include <linux/io.h>
  76 #include "compat.h"
  77 #include "version.h"
  78
  79 #define DRVNAME "it87"
  80
  81 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  82              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  83              it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
  84              it8655, it8665, it8686 };
  85
  86 static unsigned short force_id;
  87 module_param(force_id, ushort, 0);
  88 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  89
  90 static bool ignore_resource_conflict;
  91 module_param(ignore_resource_conflict, bool, 0);
  92 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
  93
  94 static bool mmio;
  95 module_param(mmio, bool, 0);
  96 MODULE_PARM_DESC(mmio, "Use MMIO if available");
  97
  98 static struct platform_device *it87_pdev[2];
  99
 100 #define REG_2E  0x2e    /* The register to read/write */
 101 #define REG_4E  0x4e    /* Secondary register to read/write */
 102
 103 #define DEV     0x07    /* Register: Logical device select */
 104 #define PME     0x04    /* The device with the fan registers in it */
 105
 106 /* The device with the IT8718F/IT8720F VID value in it */
 107 #define GPIO    0x07
 108
 109 #define DEVID   0x20    /* Register: Device ID */
 110 #define DEVREV  0x22    /* Register: Device Revision */
 111
 112 static inline void __superio_enter(int ioreg)
 113 {
 114         outb(0x87, ioreg);
 115         outb(0x01, ioreg);
 116         outb(0x55, ioreg);
 117         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 118 }
 119
 120 static inline int superio_inb(int ioreg, int reg)
 121 {
 122         int val;
 123
 124         outb(reg, ioreg);
 125         val = inb(ioreg + 1);
 126
 127         return val;
 128 }
 129
 130 static inline void superio_outb(int ioreg, int reg, int val)
 131 {
 132         outb(reg, ioreg);
 133         outb(val, ioreg + 1);
 134 }
 135
 136 static int superio_inw(int ioreg, int reg)
 137 {
 138         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 139 }
 140
 141 static inline void superio_select(int ioreg, int ldn)
 142 {
 143         outb(DEV, ioreg);
 144         outb(ldn, ioreg + 1);
 145 }
 146
 147 static inline int superio_enter(int ioreg)
 148 {
 149         /*
 150          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 151          */
 152         if (!request_muxed_region(ioreg, 2, DRVNAME))
 153                 return -EBUSY;
 154
 155         __superio_enter(ioreg);
 156         return 0;
 157 }
 158
 159 static inline void superio_exit(int ioreg, bool doexit)
 160 {
 161         if (doexit) {
 162                 outb(0x02, ioreg);
 163                 outb(0x02, ioreg + 1);
 164         }
 165         release_region(ioreg, 2);
 166 }
 167
 168 /* Logical device 4 registers */
 169 #define IT8712F_DEVID 0x8712
 170 #define IT8705F_DEVID 0x8705
 171 #define IT8716F_DEVID 0x8716
 172 #define IT8718F_DEVID 0x8718
 173 #define IT8720F_DEVID 0x8720
 174 #define IT8721F_DEVID 0x8721
 175 #define IT8726F_DEVID 0x8726
 176 #define IT8728F_DEVID 0x8728
 177 #define IT8732F_DEVID 0x8732
 178 #define IT8792E_DEVID 0x8733
 179 #define IT8771E_DEVID 0x8771
 180 #define IT8772E_DEVID 0x8772
 181 #define IT8781F_DEVID 0x8781
 182 #define IT8782F_DEVID 0x8782
 183 #define IT8783E_DEVID 0x8783
 184 #define IT8786E_DEVID 0x8786
 185 #define IT8790E_DEVID 0x8790
 186 #define IT8603E_DEVID 0x8603
 187 #define IT8607E_DEVID 0x8607
 188 #define IT8613E_DEVID 0x8613
 189 #define IT8620E_DEVID 0x8620
 190 #define IT8622E_DEVID 0x8622
 191 #define IT8623E_DEVID 0x8623
 192 #define IT8625E_DEVID 0x8625
 193 #define IT8628E_DEVID 0x8628
 194 #define IT8655E_DEVID 0x8655
 195 #define IT8665E_DEVID 0x8665
 196 #define IT8686E_DEVID 0x8686
 197
 198 /* Logical device 4 (Environmental Monitor) registers */
 199 #define IT87_ACT_REG            0x30
 200 #define IT87_BASE_REG           0x60
 201 #define IT87_SPECIAL_CFG_REG    0xf3    /* special configuration register */
 202
 203 /* Global configuration registers (IT8712F and later) */
 204 #define IT87_EC_HWM_MIO_REG     0x24    /* MMIO configuration register */
 205 #define IT87_SIO_GPIO1_REG      0x25
 206 #define IT87_SIO_GPIO2_REG      0x26
 207 #define IT87_SIO_GPIO3_REG      0x27
 208 #define IT87_SIO_GPIO4_REG      0x28
 209 #define IT87_SIO_GPIO5_REG      0x29
 210 #define IT87_SIO_GPIO9_REG      0xd3
 211 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 212 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 213 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 214
 215 /* Logical device 7 (GPIO) registers (IT8712F and later) */
 216 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 217 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 218 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 219
 220 /* Update battery voltage after every reading if true */
 221 static bool update_vbat;
 222
 223 /* Not all BIOSes properly configure the PWM registers */
 224 static bool fix_pwm_polarity;
 225
 226 /* Many IT87 constants specified below */
 227
 228 /* Length of ISA address segment */
 229 #define IT87_EXTENT 8
 230
 231 /* Length of ISA address segment for Environmental Controller */
 232 #define IT87_EC_EXTENT 2
 233
 234 /* Offset of EC registers from ISA base address */
 235 #define IT87_EC_OFFSET 5
 236
 237 /* Where are the ISA address/data registers relative to the EC base address */
 238 #define IT87_ADDR_REG_OFFSET 0
 239 #define IT87_DATA_REG_OFFSET 1
 240
 241 /*----- The IT87 registers -----*/
 242
 243 #define IT87_REG_CONFIG        0x00
 244
 245 #define IT87_REG_ALARM1        0x01
 246 #define IT87_REG_ALARM2        0x02
 247 #define IT87_REG_ALARM3        0x03
 248
 249 #define IT87_REG_BANK           0x06
 250
 251 /*
 252  * The IT8718F and IT8720F have the VID value in a different register, in
 253  * Super-I/O configuration space.
 254  */
 255 #define IT87_REG_VID           0x0a
 256 /*
 257  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 258  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 259  * mode.
 260  */
 261 #define IT87_REG_FAN_DIV       0x0b
 262 #define IT87_REG_FAN_16BIT     0x0c
 263
 264 /*
 265  * Monitors:
 266  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 267  * - up to 6 temp (1 to 6)
 268  * - up to 6 fan (1 to 6)
 269  */
 270
 271 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 272 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 273 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 274 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 275
 276 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 277 static const u8 IT87_REG_FAN_MIN_8665[] =
 278                                         { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 279 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 280 static const u8 IT87_REG_FANX_MIN_8665[] =
 281                                         { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 282
 283 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 284
 285 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 286
 287 #define IT87_REG_FAN_MAIN_CTRL 0x13
 288 #define IT87_REG_FAN_CTL       0x14
 289
 290 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 291 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 292
 293 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 294
 295 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 296                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 297
 298 #define IT87_REG_TEMP(nr)      (0x29 + (nr))
 299
 300 #define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 301 #define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 302
 303 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 304 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 305
 306 static const u8 IT87_REG_TEMP_HIGH_8686[] =
 307                                         { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 308 static const u8 IT87_REG_TEMP_LOW_8686[] =
 309                                         { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 310
 311 #define IT87_REG_VIN_ENABLE    0x50
 312 #define IT87_REG_TEMP_ENABLE   0x51
 313 #define IT87_REG_TEMP_EXTRA    0x55
 314 #define IT87_REG_BEEP_ENABLE   0x5c
 315
 316 #define IT87_REG_CHIPID        0x58
 317
 318 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 319
 320 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 321 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 322
 323 #define IT87_REG_TEMP456_ENABLE 0x77
 324
 325 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 326 #define IT87_REG_TEMP_SRC2      0x23d
 327
 328 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 329 #define NUM_VIN_LIMIT           8
 330 #define NUM_TEMP                6
 331 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 332 #define NUM_FAN_DIV             3
 333 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 334 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 335
 336 struct it87_devices {
 337         const char *name;
 338         const char * const suffix;
 339         u32 features;
 340         u8 num_temp_limit;
 341         u8 num_temp_offset;
 342         u8 num_temp_map;        /* Number of temperature sources for pwm */
 343         u8 peci_mask;
 344         u8 old_peci_mask;
 345         u8 smbus_bitmap;        /* SMBus enable bits in extra config register */
 346         u8 ec_special_config;
 347 };
 348
 349 #define FEAT_12MV_ADC           BIT(0)
 350 #define FEAT_NEWER_AUTOPWM      BIT(1)
 351 #define FEAT_OLD_AUTOPWM        BIT(2)
 352 #define FEAT_16BIT_FANS         BIT(3)
 353 #define FEAT_TEMP_PECI          BIT(5)
 354 #define FEAT_TEMP_OLD_PECI      BIT(6)
 355 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 356 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 357 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 358 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 359 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 360 #define FEAT_10_9MV_ADC         BIT(12)
 361 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 362 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 363 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 364 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 365 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 366 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 367 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 368 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 369 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 370 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 371 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 372 #define FEAT_11MV_ADC           BIT(24)
 373 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 374 #define FEAT_MMIO               BIT(26) /* Chip supports MMIO */
 375 #define FEAT_FOUR_TEMP          BIT(27)
 376
 377 static const struct it87_devices it87_devices[] = {
 378         [it87] = {
 379                 .name = "it87",
 380                 .suffix = "F",
 381                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 382                                                 /* may need to overwrite */
 383                 .num_temp_limit = 3,
 384                 .num_temp_offset = 0,
 385                 .num_temp_map = 3,
 386         },
 387         [it8712] = {
 388                 .name = "it8712",
 389                 .suffix = "F",
 390                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 391                                                 /* may need to overwrite */
 392                 .num_temp_limit = 3,
 393                 .num_temp_offset = 0,
 394                 .num_temp_map = 3,
 395         },
 396         [it8716] = {
 397                 .name = "it8716",
 398                 .suffix = "F",
 399                 .features = FEAT_16BIT_FANS | FEAT_VID
 400                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 401                   | FEAT_FANCTL_ONOFF,
 402                 .num_temp_limit = 3,
 403                 .num_temp_offset = 3,
 404                 .num_temp_map = 3,
 405         },
 406         [it8718] = {
 407                 .name = "it8718",
 408                 .suffix = "F",
 409                 .features = FEAT_16BIT_FANS | FEAT_VID
 410                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 411                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 412                 .num_temp_limit = 3,
 413                 .num_temp_offset = 3,
 414                 .num_temp_map = 3,
 415                 .old_peci_mask = 0x4,
 416         },
 417         [it8720] = {
 418                 .name = "it8720",
 419                 .suffix = "F",
 420                 .features = FEAT_16BIT_FANS | FEAT_VID
 421                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 422                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 423                 .num_temp_limit = 3,
 424                 .num_temp_offset = 3,
 425                 .num_temp_map = 3,
 426                 .old_peci_mask = 0x4,
 427         },
 428         [it8721] = {
 429                 .name = "it8721",
 430                 .suffix = "F",
 431                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 432                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 433                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 434                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 435                 .num_temp_limit = 3,
 436                 .num_temp_offset = 3,
 437                 .num_temp_map = 3,
 438                 .peci_mask = 0x05,
 439                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 440         },
 441         [it8728] = {
 442                 .name = "it8728",
 443                 .suffix = "F",
 444                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 445                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 446                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 447                   | FEAT_FANCTL_ONOFF,
 448                 .num_temp_limit = 6,
 449                 .num_temp_offset = 3,
 450                 .num_temp_map = 3,
 451                 .peci_mask = 0x07,
 452         },
 453         [it8732] = {
 454                 .name = "it8732",
 455                 .suffix = "F",
 456                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 457                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 458                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 459                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
 460                 .num_temp_limit = 3,
 461                 .num_temp_offset = 3,
 462                 .num_temp_map = 3,
 463                 .peci_mask = 0x07,
 464                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 465         },
 466         [it8771] = {
 467                 .name = "it8771",
 468                 .suffix = "E",
 469                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 470                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 471                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 472                                 /* PECI: guesswork */
 473                                 /* 12mV ADC (OHM) */
 474                                 /* 16 bit fans (OHM) */
 475                                 /* three fans, always 16 bit (guesswork) */
 476                 .num_temp_limit = 3,
 477                 .num_temp_offset = 3,
 478                 .num_temp_map = 3,
 479                 .peci_mask = 0x07,
 480         },
 481         [it8772] = {
 482                 .name = "it8772",
 483                 .suffix = "E",
 484                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 485                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 486                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 487                                 /* PECI (coreboot) */
 488                                 /* 12mV ADC (HWSensors4, OHM) */
 489                                 /* 16 bit fans (HWSensors4, OHM) */
 490                                 /* three fans, always 16 bit (datasheet) */
 491                 .num_temp_limit = 3,
 492                 .num_temp_offset = 3,
 493                 .num_temp_map = 3,
 494                 .peci_mask = 0x07,
 495         },
 496         [it8781] = {
 497                 .name = "it8781",
 498                 .suffix = "F",
 499                 .features = FEAT_16BIT_FANS
 500                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 501                   | FEAT_FANCTL_ONOFF,
 502                 .num_temp_limit = 3,
 503                 .num_temp_offset = 3,
 504                 .num_temp_map = 3,
 505                 .old_peci_mask = 0x4,
 506         },
 507         [it8782] = {
 508                 .name = "it8782",
 509                 .suffix = "F",
 510                 .features = FEAT_16BIT_FANS
 511                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 512                   | FEAT_FANCTL_ONOFF,
 513                 .num_temp_limit = 3,
 514                 .num_temp_offset = 3,
 515                 .num_temp_map = 3,
 516                 .old_peci_mask = 0x4,
 517         },
 518         [it8783] = {
 519                 .name = "it8783",
 520                 .suffix = "E/F",
 521                 .features = FEAT_16BIT_FANS
 522                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 523                   | FEAT_FANCTL_ONOFF,
 524                 .num_temp_limit = 3,
 525                 .num_temp_offset = 3,
 526                 .num_temp_map = 3,
 527                 .old_peci_mask = 0x4,
 528         },
 529         [it8786] = {
 530                 .name = "it8786",
 531                 .suffix = "E",
 532                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 533                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 534                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 535                 .num_temp_limit = 3,
 536                 .num_temp_offset = 3,
 537                 .num_temp_map = 3,
 538                 .peci_mask = 0x07,
 539         },
 540         [it8790] = {
 541                 .name = "it8790",
 542                 .suffix = "E",
 543                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 544                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 545                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 546                 .num_temp_limit = 3,
 547                 .num_temp_offset = 3,
 548                 .num_temp_map = 3,
 549                 .peci_mask = 0x07,
 550         },
 551         [it8792] = {
 552                 .name = "it8792",
 553                 .suffix = "E",
 554                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 555                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 556                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 557                 .num_temp_limit = 3,
 558                 .num_temp_offset = 3,
 559                 .num_temp_map = 3,
 560                 .peci_mask = 0x07,
 561         },
 562         [it8603] = {
 563                 .name = "it8603",
 564                 .suffix = "E",
 565                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 566                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 567                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 568                 .num_temp_limit = 3,
 569                 .num_temp_offset = 3,
 570                 .num_temp_map = 4,
 571                 .peci_mask = 0x07,
 572         },
 573         [it8607] = {
 574                 .name = "it8607",
 575                 .suffix = "E",
 576                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 577                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 578                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 579                   | FEAT_FANCTL_ONOFF,
 580                 .num_temp_limit = 3,
 581                 .num_temp_offset = 3,
 582                 .num_temp_map = 6,
 583                 .peci_mask = 0x07,
 584         },
 585         [it8613] = {
 586                 .name = "it8613",
 587                 .suffix = "E",
 588                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 589                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 590                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 591                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 592                 .num_temp_limit = 6,
 593                 .num_temp_offset = 6,
 594                 .num_temp_map = 6,
 595                 .peci_mask = 0x07,
 596         },
 597         [it8620] = {
 598                 .name = "it8620",
 599                 .suffix = "E",
 600                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 601                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 602                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 603                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 604                   | FEAT_FANCTL_ONOFF,
 605                 .num_temp_limit = 3,
 606                 .num_temp_offset = 3,
 607                 .num_temp_map = 3,
 608                 .peci_mask = 0x07,
 609         },
 610         [it8622] = {
 611                 .name = "it8622",
 612                 .suffix = "E",
 613                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 614                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
 615                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 616                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 617                 .num_temp_limit = 3,
 618                 .num_temp_offset = 3,
 619                 .num_temp_map = 4,
 620                 .peci_mask = 0x0f,
 621                 .smbus_bitmap = BIT(1) | BIT(2),
 622         },
 623         [it8625] = {
 624                 .name = "it8625",
 625                 .suffix = "E",
 626                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 627                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 628                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 629                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 630                 .num_temp_limit = 6,
 631                 .num_temp_offset = 6,
 632                 .num_temp_map = 6,
 633                 .smbus_bitmap = BIT(1) | BIT(2),
 634         },
 635         [it8628] = {
 636                 .name = "it8628",
 637                 .suffix = "E",
 638                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 639                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 640                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 641                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 642                   | FEAT_FANCTL_ONOFF,
 643                 .num_temp_limit = 6,
 644                 .num_temp_offset = 3,
 645                 .num_temp_map = 3,
 646                 .peci_mask = 0x07,
 647         },
 648         [it8655] = {
 649                 .name = "it8655",
 650                 .suffix = "E",
 651                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 652                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 653                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
 654                   | FEAT_MMIO,
 655                 .num_temp_limit = 6,
 656                 .num_temp_offset = 6,
 657                 .num_temp_map = 6,
 658                 .smbus_bitmap = BIT(2),
 659         },
 660         [it8665] = {
 661                 .name = "it8665",
 662                 .suffix = "E",
 663                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 664                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 665                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 666                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO,
 667                 .num_temp_limit = 6,
 668                 .num_temp_offset = 6,
 669                 .num_temp_map = 6,
 670                 .smbus_bitmap = BIT(2),
 671         },
 672         [it8686] = {
 673                 .name = "it8686",
 674                 .suffix = "E",
 675                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 676                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 677                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 678                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 679                 .num_temp_limit = 6,
 680                 .num_temp_offset = 6,
 681                 .num_temp_map = 7,
 682                 .smbus_bitmap = BIT(1) | BIT(2),
 683         },
 684 };
 685
 686 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 687 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 688 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 689 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 690 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 691 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 692                                  ((data)->peci_mask & BIT(nr)))
 693 #define has_temp_old_peci(data, nr) \
 694                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 695                                  ((data)->old_peci_mask & BIT(nr)))
 696 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 697 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 698                                                      FEAT_SIX_FANS))
 699 #define has_vid(data)           ((data)->features & FEAT_VID)
 700 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 701 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 702 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 703 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 704                                                      | FEAT_SIX_PWM))
 705 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 706 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 707 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 708 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 709 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 710                                                      FEAT_FIVE_FANS | \
 711                                                      FEAT_SIX_FANS))
 712 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 713                                                      FEAT_FIVE_PWM \
 714                                                      | FEAT_SIX_PWM))
 715 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 716 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 717 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 718 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 719 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 720 #define has_mmio(data)          ((data)->features & FEAT_MMIO)
 721 #define has_four_temp(data)     ((data)->features & FEAT_FOUR_TEMP)
 722
 723 struct it87_sio_data {
 724         enum chips type;
 725         u8 sioaddr;
 726         u8 doexit;
 727         /* Values read from Super-I/O config space */
 728         u8 revision;
 729         u8 vid_value;
 730         u8 beep_pin;
 731         u8 internal;    /* Internal sensors can be labeled */
 732         /* Features skipped based on config or DMI */
 733         u16 skip_in;
 734         u8 skip_vid;
 735         u8 skip_fan;
 736         u8 skip_pwm;
 737         u8 skip_temp;
 738         u8 smbus_bitmap;
 739         u8 ec_special_config;
 740 };
 741
 742 /*
 743  * For each registered chip, we need to keep some data in memory.
 744  * The structure is dynamically allocated.
 745  */
 746 struct it87_data {
 747         const struct attribute_group *groups[7];
 748         enum chips type;
 749         u32 features;
 750         u8 peci_mask;
 751         u8 old_peci_mask;
 752
 753         u8 smbus_bitmap;        /* !=0 if SMBus needs to be disabled */
 754         u8 ec_special_config;   /* EC special config register restore value */
 755         u8 sioaddr;             /* SIO port address */
 756         bool doexit;            /* true if exit from sio config is ok */
 757
 758         void __iomem *mmio;     /* Remapped MMIO address if available */
 759         int (*read)(struct it87_data *, u16);
 760         void (*write)(struct it87_data *, u16, u8);
 761
 762         const u8 *REG_FAN;
 763         const u8 *REG_FANX;
 764         const u8 *REG_FAN_MIN;
 765         const u8 *REG_FANX_MIN;
 766
 767         const u8 *REG_PWM;
 768
 769         const u8 *REG_TEMP_OFFSET;
 770         const u8 *REG_TEMP_LOW;
 771         const u8 *REG_TEMP_HIGH;
 772
 773         unsigned short addr;
 774         const char *name;
 775         struct mutex update_lock;
 776         char valid;             /* !=0 if following fields are valid */
 777         unsigned long last_updated;     /* In jiffies */
 778
 779         u16 in_scaled;          /* Internal voltage sensors are scaled */
 780         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 781         u16 has_in;             /* Bitfield, voltage sensors enabled */
 782         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 783         u8 has_fan;             /* Bitfield, fans enabled */
 784         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 785         u8 has_temp;            /* Bitfield, temp sensors enabled */
 786         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 787         u8 num_temp_limit;      /* Number of temperature limit registers */
 788         u8 num_temp_offset;     /* Number of temperature offset registers */
 789         u8 temp_src[4];         /* Up to 4 temperature source registers */
 790         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 791         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 792         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 793         bool has_vid;           /* True if VID supported */
 794         u8 vid;                 /* Register encoding, combined */
 795         u8 vrm;
 796         u32 alarms;             /* Register encoding, combined */
 797         bool has_beep;          /* true if beep supported */
 798         u8 beeps;               /* Register encoding */
 799         u8 fan_main_ctrl;       /* Register value */
 800         u8 fan_ctl;             /* Register value */
 801
 802         /*
 803          * The following 3 arrays correspond to the same registers up to
 804          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 805          * 7, and we want to preserve settings on mode changes, so we have
 806          * to track all values separately.
 807          * Starting with the IT8721F, the manual PWM duty cycles are stored
 808          * in separate registers (8-bit values), so the separate tracking
 809          * is no longer needed, but it is still done to keep the driver
 810          * simple.
 811          */
 812         u8 has_pwm;             /* Bitfield, pwm control enabled */
 813         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 814         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 815         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 816         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 817         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 818         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 819
 820         /* Automatic fan speed control registers */
 821         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 822         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 823 };
 824
 825 static int adc_lsb(const struct it87_data *data, int nr)
 826 {
 827         int lsb;
 828
 829         if (has_12mv_adc(data))
 830                 lsb = 120;
 831         else if (has_10_9mv_adc(data))
 832                 lsb = 109;
 833         else if (has_11mv_adc(data))
 834                 lsb = 110;
 835         else
 836                 lsb = 160;
 837         if (data->in_scaled & BIT(nr))
 838                 lsb <<= 1;
 839         return lsb;
 840 }
 841
 842 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 843 {
 844         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 845         return clamp_val(val, 0, 255);
 846 }
 847
 848 static int in_from_reg(const struct it87_data *data, int nr, int val)
 849 {
 850         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 851 }
 852
 853 static inline u8 FAN_TO_REG(long rpm, int div)
 854 {
 855         if (rpm == 0)
 856                 return 255;
 857         rpm = clamp_val(rpm, 1, 1000000);
 858         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 859 }
 860
 861 static inline u16 FAN16_TO_REG(long rpm)
 862 {
 863         if (rpm == 0)
 864                 return 0xffff;
 865         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 866 }
 867
 868 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 869                                 1350000 / ((val) * (div)))
 870 /* The divider is fixed to 2 in 16-bit mode */
 871 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 872                              1350000 / ((val) * 2))
 873
 874 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 875                                     ((val) + 500) / 1000), -128, 127))
 876 #define TEMP_FROM_REG(val) ((val) * 1000)
 877
 878 static u8 pwm_to_reg(const struct it87_data *data, long val)
 879 {
 880         if (has_newer_autopwm(data))
 881                 return val;
 882         else
 883                 return val >> 1;
 884 }
 885
 886 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 887 {
 888         if (has_newer_autopwm(data))
 889                 return reg;
 890         else
 891                 return (reg & 0x7f) << 1;
 892 }
 893
 894 static int DIV_TO_REG(int val)
 895 {
 896         int answer = 0;
 897
 898         while (answer < 7 && (val >>= 1))
 899                 answer++;
 900         return answer;
 901 }
 902
 903 #define DIV_FROM_REG(val) BIT(val)
 904
 905 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 906 {
 907         u8 map;
 908
 909         map  = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 910         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 911                 map = 0;
 912
 913         return map;
 914 }
 915
 916 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 917 {
 918         u8 ctrl = data->pwm_ctrl[nr];
 919
 920         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 921                (map << data->pwm_temp_map_shift);
 922 }
 923
 924 /*
 925  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 926  * depending on the chip type, to calculate the actual PWM frequency.
 927  *
 928  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 929  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 930  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 931  * sometimes just one. It is unknown if this is a datasheet error or real,
 932  * so this is ignored for now.
 933  */
 934 static const unsigned int pwm_freq[8] = {
 935         48000000,
 936         24000000,
 937         12000000,
 938         8000000,
 939         6000000,
 940         3000000,
 941         1500000,
 942         750000,
 943 };
 944
 945 static int smbus_disable(struct it87_data *data)
 946 {
 947         int err;
 948
 949         if (data->smbus_bitmap) {
 950                 err = superio_enter(data->sioaddr);
 951                 if (err)
 952                         return err;
 953                 superio_select(data->sioaddr, PME);
 954                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 955                              data->ec_special_config & ~data->smbus_bitmap);
 956                 superio_exit(data->sioaddr, data->doexit);
 957         }
 958         return 0;
 959 }
 960
 961 static int smbus_enable(struct it87_data *data)
 962 {
 963         int err;
 964
 965         if (data->smbus_bitmap) {
 966                 err = superio_enter(data->sioaddr);
 967                 if (err)
 968                         return err;
 969
 970                 superio_select(data->sioaddr, PME);
 971                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
 972                              data->ec_special_config);
 973                 superio_exit(data->sioaddr, data->doexit);
 974         }
 975         return 0;
 976 }
 977
 978 static int _it87_io_read(struct it87_data *data, u16 reg)
 979 {
 980         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 981         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 982 }
 983
 984 static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
 985 {
 986         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 987         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 988 }
 989
 990 static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
 991 {
 992         u8 _bank = bank;
 993
 994         if (has_bank_sel(data)) {
 995                 u8 breg = _it87_io_read(data, IT87_REG_BANK);
 996
 997                 _bank = breg >> 5;
 998                 if (bank != _bank) {
 999                         breg &= 0x1f;
1000                         breg |= (bank << 5);
1001                         _it87_io_write(data, IT87_REG_BANK, breg);
1002                 }
1003         }
1004         return _bank;
1005 }
1006
1007 /*
1008  * Must be called with data->update_lock held, except during initialization.
1009  * Must be called with SMBus accesses disabled.
1010  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1011  * would slow down the IT87 access and should not be necessary.
1012  */
1013 static int it87_io_read(struct it87_data *data, u16 reg)
1014 {
1015         u8 bank;
1016         int val;
1017
1018         bank = it87_io_set_bank(data, reg >> 8);
1019         val = _it87_io_read(data, reg & 0xff);
1020         it87_io_set_bank(data, bank);
1021
1022         return val;
1023 }
1024
1025 /*
1026  * Must be called with data->update_lock held, except during initialization.
1027  * Must be called with SMBus accesses disabled
1028  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1029  * would slow down the IT87 access and should not be necessary.
1030  */
1031 static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1032 {
1033         u8 bank;
1034
1035         bank = it87_io_set_bank(data, reg >> 8);
1036         _it87_io_write(data, reg & 0xff, value);
1037         it87_io_set_bank(data, bank);
1038 }
1039
1040 static int it87_mmio_read(struct it87_data *data, u16 reg)
1041 {
1042         return readb(data->mmio + reg);
1043 }
1044
1045 static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1046 {
1047         writeb(value, data->mmio + reg);
1048 }
1049
1050 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1051 {
1052         u8 ctrl;
1053
1054         ctrl = data->read(data, data->REG_PWM[nr]);
1055         data->pwm_ctrl[nr] = ctrl;
1056         if (has_newer_autopwm(data)) {
1057                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1058                 data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1059         } else {
1060                 if (ctrl & 0x80)        /* Automatic mode */
1061                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1062                 else                            /* Manual mode */
1063                         data->pwm_duty[nr] = ctrl & 0x7f;
1064         }
1065
1066         if (has_old_autopwm(data)) {
1067                 int i;
1068
1069                 for (i = 0; i < 5 ; i++)
1070                         data->auto_temp[nr][i] = data->read(data,
1071                                                 IT87_REG_AUTO_TEMP(nr, i));
1072                 for (i = 0; i < 3 ; i++)
1073                         data->auto_pwm[nr][i] = data->read(data,
1074                                                 IT87_REG_AUTO_PWM(nr, i));
1075         } else if (has_newer_autopwm(data)) {
1076                 int i;
1077
1078                 /*
1079                  * 0: temperature hysteresis (base + 5)
1080                  * 1: fan off temperature (base + 0)
1081                  * 2: fan start temperature (base + 1)
1082                  * 3: fan max temperature (base + 2)
1083                  */
1084                 data->auto_temp[nr][0] =
1085                         data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1086
1087                 for (i = 0; i < 3 ; i++)
1088                         data->auto_temp[nr][i + 1] =
1089                                 data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1090                 /*
1091                  * 0: start pwm value (base + 3)
1092                  * 1: pwm slope (base + 4, 1/8th pwm)
1093                  */
1094                 data->auto_pwm[nr][0] =
1095                         data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1096                 data->auto_pwm[nr][1] =
1097                         data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1098         }
1099 }
1100
1101 static int it87_lock(struct it87_data *data)
1102 {
1103         int err;
1104
1105         mutex_lock(&data->update_lock);
1106         err = smbus_disable(data);
1107         if (err)
1108                 mutex_unlock(&data->update_lock);
1109         return err;
1110 }
1111
1112 static void it87_unlock(struct it87_data *data)
1113 {
1114         smbus_enable(data);
1115         mutex_unlock(&data->update_lock);
1116 }
1117
1118 static struct it87_data *it87_update_device(struct device *dev)
1119 {
1120         struct it87_data *data = dev_get_drvdata(dev);
1121         int err;
1122         int i;
1123
1124         err = it87_lock(data);
1125         if (err)
1126                 return ERR_PTR(err);
1127
1128         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1129             !data->valid) {
1130                 if (update_vbat) {
1131                         /*
1132                          * Cleared after each update, so reenable.  Value
1133                          * returned by this read will be previous value
1134                          */
1135                         data->write(data, IT87_REG_CONFIG,
1136                                     data->read(data, IT87_REG_CONFIG) | 0x40);
1137                 }
1138                 for (i = 0; i < NUM_VIN; i++) {
1139                         if (!(data->has_in & BIT(i)))
1140                                 continue;
1141
1142                         data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1143
1144                         /* VBAT and AVCC don't have limit registers */
1145                         if (i >= NUM_VIN_LIMIT)
1146                                 continue;
1147
1148                         data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1149                         data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1150                 }
1151
1152                 for (i = 0; i < NUM_FAN; i++) {
1153                         /* Skip disabled fans */
1154                         if (!(data->has_fan & BIT(i)))
1155                                 continue;
1156
1157                         data->fan[i][1] = data->read(data, data->REG_FAN_MIN[i]);
1158                         data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1159                         /* Add high byte if in 16-bit mode */
1160                         if (has_16bit_fans(data)) {
1161                                 data->fan[i][0] |= data->read(data,
1162                                                 data->REG_FANX[i]) << 8;
1163                                 data->fan[i][1] |= data->read(data,
1164                                                 data->REG_FANX_MIN[i]) << 8;
1165                         }
1166                 }
1167                 for (i = 0; i < NUM_TEMP; i++) {
1168                         if (!(data->has_temp & BIT(i)))
1169                                 continue;
1170                         data->temp[i][0] =
1171                                 data->read(data, IT87_REG_TEMP(i));
1172
1173                         if (i >= data->num_temp_limit)
1174                                 continue;
1175
1176                         if (i < data->num_temp_offset)
1177                                 data->temp[i][3] =
1178                                   data->read(data, data->REG_TEMP_OFFSET[i]);
1179
1180                         data->temp[i][1] =
1181                                 data->read(data, data->REG_TEMP_LOW[i]);
1182                         data->temp[i][2] =
1183                                 data->read(data, data->REG_TEMP_HIGH[i]);
1184                 }
1185
1186                 /* Newer chips don't have clock dividers */
1187                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1188                         i = data->read(data, IT87_REG_FAN_DIV);
1189                         data->fan_div[0] = i & 0x07;
1190                         data->fan_div[1] = (i >> 3) & 0x07;
1191                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1192                 }
1193
1194                 data->alarms =
1195                         data->read(data, IT87_REG_ALARM1) |
1196                         (data->read(data, IT87_REG_ALARM2) << 8) |
1197                         (data->read(data, IT87_REG_ALARM3) << 16);
1198                 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1199
1200                 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1201                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1202                 for (i = 0; i < NUM_PWM; i++) {
1203                         if (!(data->has_pwm & BIT(i)))
1204                                 continue;
1205                         it87_update_pwm_ctrl(data, i);
1206                 }
1207
1208                 data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1209                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1210                 /*
1211                  * The IT8705F does not have VID capability.
1212                  * The IT8718F and later don't use IT87_REG_VID for the
1213                  * same purpose.
1214                  */
1215                 if (data->type == it8712 || data->type == it8716) {
1216                         data->vid = data->read(data, IT87_REG_VID);
1217                         /*
1218                          * The older IT8712F revisions had only 5 VID pins,
1219                          * but we assume it is always safe to read 6 bits.
1220                          */
1221                         data->vid &= 0x3f;
1222                 }
1223                 data->last_updated = jiffies;
1224                 data->valid = 1;
1225         }
1226         it87_unlock(data);
1227         return data;
1228 }
1229
1230 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1231                        char *buf)
1232 {
1233         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1234         struct it87_data *data = it87_update_device(dev);
1235         int index = sattr->index;
1236         int nr = sattr->nr;
1237
1238         if (IS_ERR(data))
1239                 return PTR_ERR(data);
1240
1241         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1242 }
1243
1244 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1245                       const char *buf, size_t count)
1246 {
1247         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1248         struct it87_data *data = dev_get_drvdata(dev);
1249         int index = sattr->index;
1250         int nr = sattr->nr;
1251         unsigned long val;
1252         int err;
1253
1254         if (kstrtoul(buf, 10, &val) < 0)
1255                 return -EINVAL;
1256
1257         err = it87_lock(data);
1258         if (err)
1259                 return err;
1260
1261         data->in[nr][index] = in_to_reg(data, nr, val);
1262         data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1263                                      : IT87_REG_VIN_MAX(nr),
1264                     data->in[nr][index]);
1265         it87_unlock(data);
1266         return count;
1267 }
1268
1269 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1270 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1271                             0, 1);
1272 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1273                             0, 2);
1274
1275 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1276 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1277                             1, 1);
1278 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1279                             1, 2);
1280
1281 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1282 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1283                             2, 1);
1284 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1285                             2, 2);
1286
1287 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1288 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1289                             3, 1);
1290 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1291                             3, 2);
1292
1293 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1294 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1295                             4, 1);
1296 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1297                             4, 2);
1298
1299 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1300 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1301                             5, 1);
1302 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1303                             5, 2);
1304
1305 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1306 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1307                             6, 1);
1308 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1309                             6, 2);
1310
1311 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1312 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1313                             7, 1);
1314 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1315                             7, 2);
1316
1317 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1318 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1319 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1320 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1321 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1322
1323 /* Up to 6 temperatures */
1324 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1325                          char *buf)
1326 {
1327         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1328         int nr = sattr->nr;
1329         int index = sattr->index;
1330         struct it87_data *data = it87_update_device(dev);
1331
1332         if (IS_ERR(data))
1333                 return PTR_ERR(data);
1334
1335         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1336 }
1337
1338 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1339                         const char *buf, size_t count)
1340 {
1341         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1342         int nr = sattr->nr;
1343         int index = sattr->index;
1344         struct it87_data *data = dev_get_drvdata(dev);
1345         long val;
1346         u8 reg, regval;
1347         int err;
1348
1349         if (kstrtol(buf, 10, &val) < 0)
1350                 return -EINVAL;
1351
1352         err = it87_lock(data);
1353         if (err)
1354                 return err;
1355
1356         switch (index) {
1357         default:
1358         case 1:
1359                 reg = data->REG_TEMP_LOW[nr];
1360                 break;
1361         case 2:
1362                 reg = data->REG_TEMP_HIGH[nr];
1363                 break;
1364         case 3:
1365                 regval = data->read(data, IT87_REG_BEEP_ENABLE);
1366                 if (!(regval & 0x80)) {
1367                         regval |= 0x80;
1368                         data->write(data, IT87_REG_BEEP_ENABLE, regval);
1369                 }
1370                 data->valid = 0;
1371                 reg = data->REG_TEMP_OFFSET[nr];
1372                 break;
1373         }
1374
1375         data->temp[nr][index] = TEMP_TO_REG(val);
1376         data->write(data, reg, data->temp[nr][index]);
1377         it87_unlock(data);
1378         return count;
1379 }
1380
1381 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1382 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1383                             0, 1);
1384 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1385                             0, 2);
1386 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1387                             set_temp, 0, 3);
1388 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1389 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1390                             1, 1);
1391 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1392                             1, 2);
1393 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1394                             set_temp, 1, 3);
1395 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1396 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1397                             2, 1);
1398 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1399                             2, 2);
1400 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1401                             set_temp, 2, 3);
1402 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1403 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1404                             3, 1);
1405 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1406                             3, 2);
1407 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1408                             set_temp, 3, 3);
1409 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1410 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1411                             4, 1);
1412 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1413                             4, 2);
1414 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1415                             set_temp, 4, 3);
1416 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1417 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1418                             5, 1);
1419 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1420                             5, 2);
1421 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1422                             set_temp, 5, 3);
1423
1424 static const u8 temp_types_8686[NUM_TEMP][9] = {
1425         { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1426         { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1427         { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1428         { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1429         { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1430         { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1431 };
1432
1433 static int get_temp_type(struct it87_data *data, int index)
1434 {
1435         u8 reg, extra;
1436         int ttype, type = 0;
1437
1438         if (has_bank_sel(data)) {
1439                 u8 src1, src2;
1440
1441                 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1442
1443                 switch (data->type) {
1444                 case it8686:
1445                         if (src1 < 9)
1446                                 type = temp_types_8686[index][src1];
1447                         break;
1448                 case it8625:
1449                         if (index < 3)
1450                                 break;
1451                 case it8655:
1452                 case it8665:
1453                         if (src1 < 3) {
1454                                 index = src1;
1455                                 break;
1456                         }
1457                         src2 = data->temp_src[3];
1458                         switch(src1) {
1459                         case 3:
1460                                 type = (src2 & BIT(index)) ? 6 : 5;
1461                                 break;
1462                         case 4 ... 8:
1463                                 type = (src2 & BIT(index)) ? 4 : 6;
1464                                 break;
1465                         case 9:
1466                                 type = (src2 & BIT(index)) ? 5 : 0;
1467                                 break;
1468                         default:
1469                                 break;
1470                         }
1471                         return type;
1472                 default:
1473                         return 0;
1474                 }
1475         }
1476         if (type)
1477                 return type;
1478
1479         /* Dectect PECI vs. AMDTSI if possible */
1480         ttype = 6;
1481         if ((has_temp_peci(data, index)) && data->type != it8721) {
1482                 extra = data->read(data, 0x98); /* PCH/AMDTSI host status */
1483                 if (extra & BIT(6))
1484                         ttype = 5;
1485         }
1486
1487         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1488
1489         /* Per chip special detection */
1490         switch (data->type) {
1491         case it8622:
1492                 if (!(reg & 0xc0) && index == 3)
1493                         type = ttype;
1494                 break;
1495         default:
1496                 break;
1497         }
1498
1499         if (type || index >= 3)
1500                 return type;
1501
1502         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1503
1504         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1505             (has_temp_old_peci(data, index) && (extra & 0x80)))
1506                 type = ttype;           /* Intel PECI or AMDTSI */
1507         if (reg & BIT(index))
1508                 type = 3;               /* thermal diode */
1509         else if (reg & BIT(index + 3))
1510                 type = 4;               /* thermistor */
1511
1512         return type;
1513 }
1514
1515 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1516                               char *buf)
1517 {
1518         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1519         struct it87_data *data = it87_update_device(dev);
1520         int type;
1521
1522         if (IS_ERR(data))
1523                 return PTR_ERR(data);
1524
1525         type = get_temp_type(data, sensor_attr->index);
1526         return sprintf(buf, "%d\n", type);
1527 }
1528
1529 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1530                              const char *buf, size_t count)
1531 {
1532         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1533         int nr = sensor_attr->index;
1534
1535         struct it87_data *data = dev_get_drvdata(dev);
1536         long val;
1537         u8 reg, extra;
1538         int err;
1539
1540         if (kstrtol(buf, 10, &val) < 0)
1541                 return -EINVAL;
1542
1543         err = it87_lock(data);
1544         if (err)
1545                 return err;
1546
1547         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1548         reg &= ~(1 << nr);
1549         reg &= ~(8 << nr);
1550         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1551                 reg &= 0x3f;
1552         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1553         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1554                 extra &= 0x7f;
1555         if (val == 2) { /* backwards compatibility */
1556                 dev_warn(dev,
1557                          "Sensor type 2 is deprecated, please use 4 instead\n");
1558                 val = 4;
1559         }
1560         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1561         if (val == 3)
1562                 reg |= 1 << nr;
1563         else if (val == 4)
1564                 reg |= 8 << nr;
1565         else if (has_temp_peci(data, nr) && val == 6)
1566                 reg |= (nr + 1) << 6;
1567         else if (has_temp_old_peci(data, nr) && val == 6)
1568                 extra |= 0x80;
1569         else if (val != 0) {
1570                 count = -EINVAL;
1571                 goto unlock;
1572         }
1573
1574         data->sensor = reg;
1575         data->extra = extra;
1576         data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1577         if (has_temp_old_peci(data, nr))
1578                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1579         data->valid = 0;        /* Force cache refresh */
1580 unlock:
1581         it87_unlock(data);
1582         return count;
1583 }
1584
1585 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1586                           set_temp_type, 0);
1587 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1588                           set_temp_type, 1);
1589 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1590                           set_temp_type, 2);
1591 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1592                           set_temp_type, 3);
1593 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1594                           set_temp_type, 4);
1595 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1596                           set_temp_type, 5);
1597
1598 /* 6 Fans */
1599
1600 static int pwm_mode(const struct it87_data *data, int nr)
1601 {
1602         if (has_fanctl_onoff(data) && nr < 3 &&
1603             !(data->fan_main_ctrl & BIT(nr)))
1604                 return 0;                               /* Full speed */
1605         if (data->pwm_ctrl[nr] & 0x80)
1606                 return 2;                               /* Automatic mode */
1607         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1608             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1609                 return 0;                       /* Full speed */
1610
1611         return 1;                               /* Manual mode */
1612 }
1613
1614 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1615                         char *buf)
1616 {
1617         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1618         int nr = sattr->nr;
1619         int index = sattr->index;
1620         int speed;
1621         struct it87_data *data = it87_update_device(dev);
1622
1623         if (IS_ERR(data))
1624                 return PTR_ERR(data);
1625
1626         speed = has_16bit_fans(data) ?
1627                 FAN16_FROM_REG(data->fan[nr][index]) :
1628                 FAN_FROM_REG(data->fan[nr][index],
1629                              DIV_FROM_REG(data->fan_div[nr]));
1630         return sprintf(buf, "%d\n", speed);
1631 }
1632
1633 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1634                             char *buf)
1635 {
1636         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1637         struct it87_data *data = it87_update_device(dev);
1638         int nr = sensor_attr->index;
1639
1640         if (IS_ERR(data))
1641                 return PTR_ERR(data);
1642
1643         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1644 }
1645
1646 static ssize_t show_pwm_enable(struct device *dev,
1647                                struct device_attribute *attr, char *buf)
1648 {
1649         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1650         struct it87_data *data = it87_update_device(dev);
1651         int nr = sensor_attr->index;
1652
1653         if (IS_ERR(data))
1654                 return PTR_ERR(data);
1655
1656         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1657 }
1658
1659 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1660                         char *buf)
1661 {
1662         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1663         struct it87_data *data = it87_update_device(dev);
1664         int nr = sensor_attr->index;
1665
1666         if (IS_ERR(data))
1667                 return PTR_ERR(data);
1668
1669         return sprintf(buf, "%d\n",
1670                        pwm_from_reg(data, data->pwm_duty[nr]));
1671 }
1672
1673 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1674                              char *buf)
1675 {
1676         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1677         struct it87_data *data = it87_update_device(dev);
1678         int nr = sensor_attr->index;
1679         unsigned int freq;
1680         int index;
1681
1682         if (IS_ERR(data))
1683                 return PTR_ERR(data);
1684
1685         if (has_pwm_freq2(data) && nr == 1)
1686                 index = (data->extra >> 4) & 0x07;
1687         else
1688                 index = (data->fan_ctl >> 4) & 0x07;
1689
1690         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1691
1692         return sprintf(buf, "%u\n", freq);
1693 }
1694
1695 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1696                        const char *buf, size_t count)
1697 {
1698         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1699         int nr = sattr->nr;
1700         int index = sattr->index;
1701
1702         struct it87_data *data = dev_get_drvdata(dev);
1703         long val;
1704         int err;
1705         u8 reg;
1706
1707         if (kstrtol(buf, 10, &val) < 0)
1708                 return -EINVAL;
1709
1710         err = it87_lock(data);
1711         if (err)
1712                 return err;
1713
1714         if (has_16bit_fans(data)) {
1715                 data->fan[nr][index] = FAN16_TO_REG(val);
1716                 data->write(data, data->REG_FAN_MIN[nr],
1717                             data->fan[nr][index] & 0xff);
1718                 data->write(data, data->REG_FANX_MIN[nr],
1719                             data->fan[nr][index] >> 8);
1720         } else {
1721                 reg = data->read(data, IT87_REG_FAN_DIV);
1722                 switch (nr) {
1723                 case 0:
1724                         data->fan_div[nr] = reg & 0x07;
1725                         break;
1726                 case 1:
1727                         data->fan_div[nr] = (reg >> 3) & 0x07;
1728                         break;
1729                 case 2:
1730                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1731                         break;
1732                 }
1733                 data->fan[nr][index] =
1734                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1735                 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1736         }
1737         it87_unlock(data);
1738         return count;
1739 }
1740
1741 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1742                            const char *buf, size_t count)
1743 {
1744         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1745         struct it87_data *data = dev_get_drvdata(dev);
1746         int nr = sensor_attr->index;
1747         unsigned long val;
1748         int min, err;
1749         u8 old;
1750
1751         if (kstrtoul(buf, 10, &val) < 0)
1752                 return -EINVAL;
1753
1754         err = it87_lock(data);
1755         if (err)
1756                 return err;
1757
1758         old = data->read(data, IT87_REG_FAN_DIV);
1759
1760         /* Save fan min limit */
1761         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1762
1763         switch (nr) {
1764         case 0:
1765         case 1:
1766                 data->fan_div[nr] = DIV_TO_REG(val);
1767                 break;
1768         case 2:
1769                 if (val < 8)
1770                         data->fan_div[nr] = 1;
1771                 else
1772                         data->fan_div[nr] = 3;
1773         }
1774         val = old & 0x80;
1775         val |= (data->fan_div[0] & 0x07);
1776         val |= (data->fan_div[1] & 0x07) << 3;
1777         if (data->fan_div[2] == 3)
1778                 val |= 0x1 << 6;
1779         data->write(data, IT87_REG_FAN_DIV, val);
1780
1781         /* Restore fan min limit */
1782         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1783         data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1784         it87_unlock(data);
1785         return count;
1786 }
1787
1788 /* Returns 0 if OK, -EINVAL otherwise */
1789 static int check_trip_points(struct device *dev, int nr)
1790 {
1791         const struct it87_data *data = dev_get_drvdata(dev);
1792         int i, err = 0;
1793
1794         if (has_old_autopwm(data)) {
1795                 for (i = 0; i < 3; i++) {
1796                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1797                                 err = -EINVAL;
1798                 }
1799                 for (i = 0; i < 2; i++) {
1800                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1801                                 err = -EINVAL;
1802                 }
1803         } else if (has_newer_autopwm(data)) {
1804                 for (i = 1; i < 3; i++) {
1805                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1806                                 err = -EINVAL;
1807                 }
1808         }
1809
1810         if (err) {
1811                 dev_err(dev,
1812                         "Inconsistent trip points, not switching to automatic mode\n");
1813                 dev_err(dev, "Adjust the trip points and try again\n");
1814         }
1815         return err;
1816 }
1817
1818 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1819                               const char *buf, size_t count)
1820 {
1821         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1822         struct it87_data *data = dev_get_drvdata(dev);
1823         int nr = sensor_attr->index;
1824         long val;
1825         int err;
1826
1827         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1828                 return -EINVAL;
1829
1830         /* Check trip points before switching to automatic mode */
1831         if (val == 2) {
1832                 if (check_trip_points(dev, nr) < 0)
1833                         return -EINVAL;
1834         }
1835
1836         err = it87_lock(data);
1837         if (err)
1838                 return err;;
1839
1840         it87_update_pwm_ctrl(data, nr);
1841
1842         if (val == 0) {
1843                 if (nr < 3 && has_fanctl_onoff(data)) {
1844                         int tmp;
1845                         /* make sure the fan is on when in on/off mode */
1846                         tmp = data->read(data, IT87_REG_FAN_CTL);
1847                         data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1848                         /* set on/off mode */
1849                         data->fan_main_ctrl &= ~BIT(nr);
1850                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1851                                     data->fan_main_ctrl);
1852                 } else {
1853                         u8 ctrl;
1854
1855                         /* No on/off mode, set maximum pwm value */
1856                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1857                         data->write(data, IT87_REG_PWM_DUTY[nr],
1858                                     data->pwm_duty[nr]);
1859                         /* and set manual mode */
1860                         if (has_newer_autopwm(data)) {
1861                                 ctrl = temp_map_to_reg(data, nr,
1862                                                        data->pwm_temp_map[nr]);
1863                                 ctrl &= 0x7f;
1864                         } else {
1865                                 ctrl = data->pwm_duty[nr];
1866                         }
1867                         data->pwm_ctrl[nr] = ctrl;
1868                         data->write(data, data->REG_PWM[nr], ctrl);
1869                 }
1870         } else {
1871                 u8 ctrl;
1872
1873                 if (has_newer_autopwm(data)) {
1874                         ctrl = temp_map_to_reg(data, nr,
1875                                                data->pwm_temp_map[nr]);
1876                         if (val == 1)
1877                                 ctrl &= 0x7f;
1878                         else
1879                                 ctrl |= 0x80;
1880                 } else {
1881                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1882                 }
1883                 data->pwm_ctrl[nr] = ctrl;
1884                 data->write(data, data->REG_PWM[nr], ctrl);
1885
1886                 if (has_fanctl_onoff(data) && nr < 3) {
1887                         /* set SmartGuardian mode */
1888                         data->fan_main_ctrl |= BIT(nr);
1889                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1890                                     data->fan_main_ctrl);
1891                 }
1892         }
1893         it87_unlock(data);
1894         return count;
1895 }
1896
1897 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1898                        const char *buf, size_t count)
1899 {
1900         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1901         struct it87_data *data = dev_get_drvdata(dev);
1902         int nr = sensor_attr->index;
1903         long val;
1904         int err;
1905
1906         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1907                 return -EINVAL;
1908
1909         err = it87_lock(data);
1910         if (err)
1911                 return err;
1912
1913         it87_update_pwm_ctrl(data, nr);
1914         if (has_newer_autopwm(data)) {
1915                 /*
1916                  * If we are in automatic mode, the PWM duty cycle register
1917                  * is read-only so we can't write the value.
1918                  */
1919                 if (data->pwm_ctrl[nr] & 0x80) {
1920                         count = -EBUSY;
1921                         goto unlock;
1922                 }
1923                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1924                 data->write(data, IT87_REG_PWM_DUTY[nr],
1925                             data->pwm_duty[nr]);
1926         } else {
1927                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1928                 /*
1929                  * If we are in manual mode, write the duty cycle immediately;
1930                  * otherwise, just store it for later use.
1931                  */
1932                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1933                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1934                         data->write(data, data->REG_PWM[nr],
1935                                     data->pwm_ctrl[nr]);
1936                 }
1937         }
1938 unlock:
1939         it87_unlock(data);
1940         return count;
1941 }
1942
1943 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1944                             const char *buf, size_t count)
1945 {
1946         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1947         struct it87_data *data = dev_get_drvdata(dev);
1948         int nr = sensor_attr->index;
1949         unsigned long val;
1950         int err;
1951         int i;
1952
1953         if (kstrtoul(buf, 10, &val) < 0)
1954                 return -EINVAL;
1955
1956         val = clamp_val(val, 0, 1000000);
1957         val *= has_newer_autopwm(data) ? 256 : 128;
1958
1959         /* Search for the nearest available frequency */
1960         for (i = 0; i < 7; i++) {
1961                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1962                         break;
1963         }
1964
1965         err = it87_lock(data);
1966         if (err)
1967                 return err;
1968
1969         if (nr == 0) {
1970                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1971                 data->fan_ctl |= i << 4;
1972                 data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
1973         } else {
1974                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1975                 data->extra |= i << 4;
1976                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1977         }
1978         it87_unlock(data);
1979         return count;
1980 }
1981
1982 static ssize_t show_pwm_temp_map(struct device *dev,
1983                                  struct device_attribute *attr, char *buf)
1984 {
1985         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1986         struct it87_data *data = it87_update_device(dev);
1987         int nr = sensor_attr->index;
1988
1989         if (IS_ERR(data))
1990                 return PTR_ERR(data);
1991
1992         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1993 }
1994
1995 static ssize_t set_pwm_temp_map(struct device *dev,
1996                                 struct device_attribute *attr, const char *buf,
1997                                 size_t count)
1998 {
1999         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2000         struct it87_data *data = dev_get_drvdata(dev);
2001         int nr = sensor_attr->index;
2002         unsigned long val;
2003         int err;
2004         u8 map;
2005
2006         if (kstrtoul(buf, 10, &val) < 0)
2007                 return -EINVAL;
2008
2009         if (!val || val > data->pwm_num_temp_map)
2010                 return -EINVAL;
2011
2012         map = val - 1;
2013
2014         err = it87_lock(data);
2015         if (err)
2016                 return err;
2017
2018         it87_update_pwm_ctrl(data, nr);
2019         data->pwm_temp_map[nr] = map;
2020         /*
2021          * If we are in automatic mode, write the temp mapping immediately;
2022          * otherwise, just store it for later use.
2023          */
2024         if (data->pwm_ctrl[nr] & 0x80) {
2025                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
2026                 data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
2027         }
2028         it87_unlock(data);
2029         return count;
2030 }
2031
2032 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
2033                              char *buf)
2034 {
2035         struct it87_data *data = it87_update_device(dev);
2036         struct sensor_device_attribute_2 *sensor_attr =
2037                         to_sensor_dev_attr_2(attr);
2038         int nr = sensor_attr->nr;
2039         int point = sensor_attr->index;
2040
2041         if (IS_ERR(data))
2042                 return PTR_ERR(data);
2043
2044         return sprintf(buf, "%d\n",
2045                        pwm_from_reg(data, data->auto_pwm[nr][point]));
2046 }
2047
2048 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2049                             const char *buf, size_t count)
2050 {
2051         struct it87_data *data = dev_get_drvdata(dev);
2052         struct sensor_device_attribute_2 *sensor_attr =
2053                         to_sensor_dev_attr_2(attr);
2054         int nr = sensor_attr->nr;
2055         int point = sensor_attr->index;
2056         int regaddr;
2057         long val;
2058         int err;
2059
2060         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2061                 return -EINVAL;
2062
2063         err = it87_lock(data);
2064         if (err)
2065                 return err;
2066
2067         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2068         if (has_newer_autopwm(data))
2069                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2070         else
2071                 regaddr = IT87_REG_AUTO_PWM(nr, point);
2072         data->write(data, regaddr, data->auto_pwm[nr][point]);
2073         it87_unlock(data);
2074         return count;
2075 }
2076
2077 static ssize_t show_auto_pwm_slope(struct device *dev,
2078                                    struct device_attribute *attr, char *buf)
2079 {
2080         struct it87_data *data = it87_update_device(dev);
2081         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2082         int nr = sensor_attr->index;
2083
2084         if (IS_ERR(data))
2085                 return PTR_ERR(data);
2086
2087         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2088 }
2089
2090 static ssize_t set_auto_pwm_slope(struct device *dev,
2091                                   struct device_attribute *attr,
2092                                   const char *buf, size_t count)
2093 {
2094         struct it87_data *data = dev_get_drvdata(dev);
2095         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2096         int nr = sensor_attr->index;
2097         unsigned long val;
2098         int err;
2099
2100         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2101                 return -EINVAL;
2102
2103         err = it87_lock(data);
2104         if (err)
2105                 return err;
2106
2107         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2108         data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2109         it87_unlock(data);
2110         return count;
2111 }
2112
2113 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2114                               char *buf)
2115 {
2116         struct it87_data *data = it87_update_device(dev);
2117         struct sensor_device_attribute_2 *sensor_attr =
2118                         to_sensor_dev_attr_2(attr);
2119         int nr = sensor_attr->nr;
2120         int point = sensor_attr->index;
2121         int reg;
2122
2123         if (IS_ERR(data))
2124                 return PTR_ERR(data);
2125
2126         if (has_old_autopwm(data) || point)
2127                 reg = data->auto_temp[nr][point];
2128         else
2129                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2130
2131         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2132 }
2133
2134 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2135                              const char *buf, size_t count)
2136 {
2137         struct it87_data *data = dev_get_drvdata(dev);
2138         struct sensor_device_attribute_2 *sensor_attr =
2139                         to_sensor_dev_attr_2(attr);
2140         int nr = sensor_attr->nr;
2141         int point = sensor_attr->index;
2142         long val;
2143         int reg;
2144         int err;
2145
2146         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2147                 return -EINVAL;
2148
2149         err = it87_lock(data);
2150         if (err)
2151                 return err;
2152
2153         if (has_newer_autopwm(data) && !point) {
2154                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2155                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2156                 data->auto_temp[nr][0] = reg;
2157                 data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2158         } else {
2159                 reg = TEMP_TO_REG(val);
2160                 data->auto_temp[nr][point] = reg;
2161                 if (has_newer_autopwm(data))
2162                         point--;
2163                 data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2164         }
2165         it87_unlock(data);
2166         return count;
2167 }
2168
2169 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
2170 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2171                             0, 1);
2172 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
2173                           set_fan_div, 0);
2174
2175 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
2176 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2177                             1, 1);
2178 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
2179                           set_fan_div, 1);
2180
2181 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
2182 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2183                             2, 1);
2184 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
2185                           set_fan_div, 2);
2186
2187 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2188 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2189                             3, 1);
2190
2191 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2192 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2193                             4, 1);
2194
2195 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2196 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2197                             5, 1);
2198
2199 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2200                           show_pwm_enable, set_pwm_enable, 0);
2201 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2202 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2203                           set_pwm_freq, 0);
2204 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2205                           show_pwm_temp_map, set_pwm_temp_map, 0);
2206 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2207                             show_auto_pwm, set_auto_pwm, 0, 0);
2208 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2209                             show_auto_pwm, set_auto_pwm, 0, 1);
2210 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2211                             show_auto_pwm, set_auto_pwm, 0, 2);
2212 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2213                             show_auto_pwm, NULL, 0, 3);
2214 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2215                             show_auto_temp, set_auto_temp, 0, 1);
2216 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2217                             show_auto_temp, set_auto_temp, 0, 0);
2218 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2219                             show_auto_temp, set_auto_temp, 0, 2);
2220 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2221                             show_auto_temp, set_auto_temp, 0, 3);
2222 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2223                             show_auto_temp, set_auto_temp, 0, 4);
2224 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2225                             show_auto_pwm, set_auto_pwm, 0, 0);
2226 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2227                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2228
2229 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2230                           show_pwm_enable, set_pwm_enable, 1);
2231 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2232 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2233 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2234                           show_pwm_temp_map, set_pwm_temp_map, 1);
2235 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2236                             show_auto_pwm, set_auto_pwm, 1, 0);
2237 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2238                             show_auto_pwm, set_auto_pwm, 1, 1);
2239 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2240                             show_auto_pwm, set_auto_pwm, 1, 2);
2241 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2242                             show_auto_pwm, NULL, 1, 3);
2243 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2244                             show_auto_temp, set_auto_temp, 1, 1);
2245 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2246                             show_auto_temp, set_auto_temp, 1, 0);
2247 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2248                             show_auto_temp, set_auto_temp, 1, 2);
2249 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2250                             show_auto_temp, set_auto_temp, 1, 3);
2251 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2252                             show_auto_temp, set_auto_temp, 1, 4);
2253 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2254                             show_auto_pwm, set_auto_pwm, 1, 0);
2255 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2256                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2257
2258 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2259                           show_pwm_enable, set_pwm_enable, 2);
2260 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2261 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2262 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2263                           show_pwm_temp_map, set_pwm_temp_map, 2);
2264 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2265                             show_auto_pwm, set_auto_pwm, 2, 0);
2266 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2267                             show_auto_pwm, set_auto_pwm, 2, 1);
2268 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2269                             show_auto_pwm, set_auto_pwm, 2, 2);
2270 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2271                             show_auto_pwm, NULL, 2, 3);
2272 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2273                             show_auto_temp, set_auto_temp, 2, 1);
2274 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2275                             show_auto_temp, set_auto_temp, 2, 0);
2276 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2277                             show_auto_temp, set_auto_temp, 2, 2);
2278 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2279                             show_auto_temp, set_auto_temp, 2, 3);
2280 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2281                             show_auto_temp, set_auto_temp, 2, 4);
2282 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2283                             show_auto_pwm, set_auto_pwm, 2, 0);
2284 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2285                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2286
2287 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2288                           show_pwm_enable, set_pwm_enable, 3);
2289 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2290 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2291 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2292                           show_pwm_temp_map, set_pwm_temp_map, 3);
2293 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2294                             show_auto_temp, set_auto_temp, 2, 1);
2295 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2296                             show_auto_temp, set_auto_temp, 2, 0);
2297 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2298                             show_auto_temp, set_auto_temp, 2, 2);
2299 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2300                             show_auto_temp, set_auto_temp, 2, 3);
2301 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2302                             show_auto_pwm, set_auto_pwm, 3, 0);
2303 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2304                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2305
2306 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2307                           show_pwm_enable, set_pwm_enable, 4);
2308 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2309 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2310 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2311                           show_pwm_temp_map, set_pwm_temp_map, 4);
2312 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2313                             show_auto_temp, set_auto_temp, 2, 1);
2314 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2315                             show_auto_temp, set_auto_temp, 2, 0);
2316 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2317                             show_auto_temp, set_auto_temp, 2, 2);
2318 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2319                             show_auto_temp, set_auto_temp, 2, 3);
2320 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2321                             show_auto_pwm, set_auto_pwm, 4, 0);
2322 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2323                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2324
2325 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2326                           show_pwm_enable, set_pwm_enable, 5);
2327 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2328 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2329 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2330                           show_pwm_temp_map, set_pwm_temp_map, 5);
2331 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2332                             show_auto_temp, set_auto_temp, 2, 1);
2333 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2334                             show_auto_temp, set_auto_temp, 2, 0);
2335 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2336                             show_auto_temp, set_auto_temp, 2, 2);
2337 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2338                             show_auto_temp, set_auto_temp, 2, 3);
2339 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2340                             show_auto_pwm, set_auto_pwm, 5, 0);
2341 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2342                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2343
2344 /* Alarms */
2345 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2346                            char *buf)
2347 {
2348         struct it87_data *data = it87_update_device(dev);
2349
2350         if (IS_ERR(data))
2351                 return PTR_ERR(data);
2352
2353         return sprintf(buf, "%u\n", data->alarms);
2354 }
2355 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2356
2357 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2358                           char *buf)
2359 {
2360         struct it87_data *data = it87_update_device(dev);
2361         int bitnr = to_sensor_dev_attr(attr)->index;
2362
2363         if (IS_ERR(data))
2364                 return PTR_ERR(data);
2365
2366         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2367 }
2368
2369 static ssize_t clear_intrusion(struct device *dev,
2370                                struct device_attribute *attr, const char *buf,
2371                                size_t count)
2372 {
2373         struct it87_data *data = dev_get_drvdata(dev);
2374         int err, config;
2375         long val;
2376
2377         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2378                 return -EINVAL;
2379
2380         err = it87_lock(data);
2381         if (err)
2382                 return err;
2383
2384         config = data->read(data, IT87_REG_CONFIG);
2385         config |= BIT(5);
2386         data->write(data, IT87_REG_CONFIG, config);
2387         /* Invalidate cache to force re-read */
2388         data->valid = 0;
2389         it87_unlock(data);
2390         return count;
2391 }
2392
2393 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2394 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2395 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2396 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2397 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2398 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2399 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2400 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2401 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2402 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2403 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2404 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2405 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2406 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2407 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2408 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2409 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2410 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2411 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2412 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2413 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2414                           show_alarm, clear_intrusion, 4);
2415
2416 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2417                          char *buf)
2418 {
2419         struct it87_data *data = it87_update_device(dev);
2420         int bitnr = to_sensor_dev_attr(attr)->index;
2421
2422         if (IS_ERR(data))
2423                 return PTR_ERR(data);
2424
2425         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2426 }
2427
2428 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2429                         const char *buf, size_t count)
2430 {
2431         int bitnr = to_sensor_dev_attr(attr)->index;
2432         struct it87_data *data = dev_get_drvdata(dev);
2433         long val;
2434         int err;
2435
2436         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2437                 return -EINVAL;
2438
2439         err = it87_lock(data);
2440         if (err)
2441                 return err;
2442
2443         data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2444         if (val)
2445                 data->beeps |= BIT(bitnr);
2446         else
2447                 data->beeps &= ~BIT(bitnr);
2448         data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2449         it87_unlock(data);
2450         return count;
2451 }
2452
2453 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2454                           show_beep, set_beep, 1);
2455 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2456 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2457 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2458 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2459 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2460 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2461 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2462 /* fanX_beep writability is set later */
2463 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2464 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2465 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2466 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2467 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2468 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2469 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2470                           show_beep, set_beep, 2);
2471 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2472 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2473 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2474 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2475 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2476
2477 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2478                             char *buf)
2479 {
2480         struct it87_data *data = dev_get_drvdata(dev);
2481
2482         return sprintf(buf, "%u\n", data->vrm);
2483 }
2484
2485 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2486                              const char *buf, size_t count)
2487 {
2488         struct it87_data *data = dev_get_drvdata(dev);
2489         unsigned long val;
2490
2491         if (kstrtoul(buf, 10, &val) < 0)
2492                 return -EINVAL;
2493
2494         data->vrm = val;
2495
2496         return count;
2497 }
2498 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2499
2500 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2501                             char *buf)
2502 {
2503         struct it87_data *data = it87_update_device(dev);
2504
2505         if (IS_ERR(data))
2506                 return PTR_ERR(data);
2507
2508         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2509 }
2510 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2511
2512 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2513                           char *buf)
2514 {
2515         static const char * const labels[] = {
2516                 "+5V",
2517                 "5VSB",
2518                 "Vbat",
2519                 "AVCC",
2520         };
2521         static const char * const labels_it8721[] = {
2522                 "+3.3V",
2523                 "3VSB",
2524                 "Vbat",
2525                 "+3.3V",
2526         };
2527         struct it87_data *data = dev_get_drvdata(dev);
2528         int nr = to_sensor_dev_attr(attr)->index;
2529         const char *label;
2530
2531         if (has_vin3_5v(data) && nr == 0)
2532                 label = labels[0];
2533         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2534                  has_11mv_adc(data))
2535                 label = labels_it8721[nr];
2536         else
2537                 label = labels[nr];
2538
2539         return sprintf(buf, "%s\n", label);
2540 }
2541 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2542 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2543 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2544 /* AVCC3 */
2545 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2546
2547 static umode_t it87_in_is_visible(struct kobject *kobj,
2548                                   struct attribute *attr, int index)
2549 {
2550         struct device *dev = container_of(kobj, struct device, kobj);
2551         struct it87_data *data = dev_get_drvdata(dev);
2552         int i = index / 5;      /* voltage index */
2553         int a = index % 5;      /* attribute index */
2554
2555         if (index >= 40) {      /* in8 and higher only have input attributes */
2556                 i = index - 40 + 8;
2557                 a = 0;
2558         }
2559
2560         if (!(data->has_in & BIT(i)))
2561                 return 0;
2562
2563         if (a == 4 && !data->has_beep)
2564                 return 0;
2565
2566         return attr->mode;
2567 }
2568
2569 static struct attribute *it87_attributes_in[] = {
2570         &sensor_dev_attr_in0_input.dev_attr.attr,
2571         &sensor_dev_attr_in0_min.dev_attr.attr,
2572         &sensor_dev_attr_in0_max.dev_attr.attr,
2573         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2574         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2575
2576         &sensor_dev_attr_in1_input.dev_attr.attr,
2577         &sensor_dev_attr_in1_min.dev_attr.attr,
2578         &sensor_dev_attr_in1_max.dev_attr.attr,
2579         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2580         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2581
2582         &sensor_dev_attr_in2_input.dev_attr.attr,
2583         &sensor_dev_attr_in2_min.dev_attr.attr,
2584         &sensor_dev_attr_in2_max.dev_attr.attr,
2585         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2586         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2587
2588         &sensor_dev_attr_in3_input.dev_attr.attr,
2589         &sensor_dev_attr_in3_min.dev_attr.attr,
2590         &sensor_dev_attr_in3_max.dev_attr.attr,
2591         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2592         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2593
2594         &sensor_dev_attr_in4_input.dev_attr.attr,
2595         &sensor_dev_attr_in4_min.dev_attr.attr,
2596         &sensor_dev_attr_in4_max.dev_attr.attr,
2597         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2598         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2599
2600         &sensor_dev_attr_in5_input.dev_attr.attr,
2601         &sensor_dev_attr_in5_min.dev_attr.attr,
2602         &sensor_dev_attr_in5_max.dev_attr.attr,
2603         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2604         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2605
2606         &sensor_dev_attr_in6_input.dev_attr.attr,
2607         &sensor_dev_attr_in6_min.dev_attr.attr,
2608         &sensor_dev_attr_in6_max.dev_attr.attr,
2609         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2610         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2611
2612         &sensor_dev_attr_in7_input.dev_attr.attr,
2613         &sensor_dev_attr_in7_min.dev_attr.attr,
2614         &sensor_dev_attr_in7_max.dev_attr.attr,
2615         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2616         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2617
2618         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2619         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2620         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2621         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2622         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2623         NULL
2624 };
2625
2626 static const struct attribute_group it87_group_in = {
2627         .attrs = it87_attributes_in,
2628         .is_visible = it87_in_is_visible,
2629 };
2630
2631 static umode_t it87_temp_is_visible(struct kobject *kobj,
2632                                     struct attribute *attr, int index)
2633 {
2634         struct device *dev = container_of(kobj, struct device, kobj);
2635         struct it87_data *data = dev_get_drvdata(dev);
2636         int i = index / 7;      /* temperature index */
2637         int a = index % 7;      /* attribute index */
2638
2639         if (!(data->has_temp & BIT(i)))
2640                 return 0;
2641
2642         if (a && i >= data->num_temp_limit)
2643                 return 0;
2644
2645         if (a == 3) {
2646                 int type = get_temp_type(data, i);
2647
2648                 if (type == 0)
2649                         return 0;
2650                 if (has_bank_sel(data))
2651                         return 0444;
2652                 return attr->mode;
2653         }
2654
2655         if (a == 5 && i >= data->num_temp_offset)
2656                 return 0;
2657
2658         if (a == 6 && !data->has_beep)
2659                 return 0;
2660
2661         return attr->mode;
2662 }
2663
2664 static struct attribute *it87_attributes_temp[] = {
2665         &sensor_dev_attr_temp1_input.dev_attr.attr,
2666         &sensor_dev_attr_temp1_max.dev_attr.attr,
2667         &sensor_dev_attr_temp1_min.dev_attr.attr,
2668         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2669         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2670         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2671         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2672
2673         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2674         &sensor_dev_attr_temp2_max.dev_attr.attr,
2675         &sensor_dev_attr_temp2_min.dev_attr.attr,
2676         &sensor_dev_attr_temp2_type.dev_attr.attr,
2677         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2678         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2679         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2680
2681         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2682         &sensor_dev_attr_temp3_max.dev_attr.attr,
2683         &sensor_dev_attr_temp3_min.dev_attr.attr,
2684         &sensor_dev_attr_temp3_type.dev_attr.attr,
2685         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2686         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2687         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2688
2689         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2690         &sensor_dev_attr_temp4_max.dev_attr.attr,
2691         &sensor_dev_attr_temp4_min.dev_attr.attr,
2692         &sensor_dev_attr_temp4_type.dev_attr.attr,
2693         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2694         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2695         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2696
2697         &sensor_dev_attr_temp5_input.dev_attr.attr,
2698         &sensor_dev_attr_temp5_max.dev_attr.attr,
2699         &sensor_dev_attr_temp5_min.dev_attr.attr,
2700         &sensor_dev_attr_temp5_type.dev_attr.attr,
2701         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2702         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2703         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2704
2705         &sensor_dev_attr_temp6_input.dev_attr.attr,
2706         &sensor_dev_attr_temp6_max.dev_attr.attr,
2707         &sensor_dev_attr_temp6_min.dev_attr.attr,
2708         &sensor_dev_attr_temp6_type.dev_attr.attr,
2709         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2710         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2711         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2712         NULL
2713 };
2714
2715 static const struct attribute_group it87_group_temp = {
2716         .attrs = it87_attributes_temp,
2717         .is_visible = it87_temp_is_visible,
2718 };
2719
2720 static umode_t it87_is_visible(struct kobject *kobj,
2721                                struct attribute *attr, int index)
2722 {
2723         struct device *dev = container_of(kobj, struct device, kobj);
2724         struct it87_data *data = dev_get_drvdata(dev);
2725
2726         if ((index == 2 || index == 3) && !data->has_vid)
2727                 return 0;
2728
2729         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2730                 return 0;
2731
2732         return attr->mode;
2733 }
2734
2735 static struct attribute *it87_attributes[] = {
2736         &dev_attr_alarms.attr,
2737         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2738         &dev_attr_vrm.attr,                             /* 2 */
2739         &dev_attr_cpu0_vid.attr,                        /* 3 */
2740         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2741         &sensor_dev_attr_in7_label.dev_attr.attr,
2742         &sensor_dev_attr_in8_label.dev_attr.attr,
2743         &sensor_dev_attr_in9_label.dev_attr.attr,
2744         NULL
2745 };
2746
2747 static const struct attribute_group it87_group = {
2748         .attrs = it87_attributes,
2749         .is_visible = it87_is_visible,
2750 };
2751
2752 static umode_t it87_fan_is_visible(struct kobject *kobj,
2753                                    struct attribute *attr, int index)
2754 {
2755         struct device *dev = container_of(kobj, struct device, kobj);
2756         struct it87_data *data = dev_get_drvdata(dev);
2757         int i = index / 5;      /* fan index */
2758         int a = index % 5;      /* attribute index */
2759
2760         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2761                 i = (index - 15) / 4 + 3;
2762                 a = (index - 15) % 4;
2763         }
2764
2765         if (!(data->has_fan & BIT(i)))
2766                 return 0;
2767
2768         if (a == 3) {                           /* beep */
2769                 if (!data->has_beep)
2770                         return 0;
2771                 /* first fan beep attribute is writable */
2772                 if (i == __ffs(data->has_fan))
2773                         return attr->mode | S_IWUSR;
2774         }
2775
2776         if (a == 4 && has_16bit_fans(data))     /* divisor */
2777                 return 0;
2778
2779         return attr->mode;
2780 }
2781
2782 static struct attribute *it87_attributes_fan[] = {
2783         &sensor_dev_attr_fan1_input.dev_attr.attr,
2784         &sensor_dev_attr_fan1_min.dev_attr.attr,
2785         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2786         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2787         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2788
2789         &sensor_dev_attr_fan2_input.dev_attr.attr,
2790         &sensor_dev_attr_fan2_min.dev_attr.attr,
2791         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2792         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2793         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2794
2795         &sensor_dev_attr_fan3_input.dev_attr.attr,
2796         &sensor_dev_attr_fan3_min.dev_attr.attr,
2797         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2798         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2799         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2800
2801         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2802         &sensor_dev_attr_fan4_min.dev_attr.attr,
2803         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2804         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2805
2806         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2807         &sensor_dev_attr_fan5_min.dev_attr.attr,
2808         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2809         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2810
2811         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2812         &sensor_dev_attr_fan6_min.dev_attr.attr,
2813         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2814         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2815         NULL
2816 };
2817
2818 static const struct attribute_group it87_group_fan = {
2819         .attrs = it87_attributes_fan,
2820         .is_visible = it87_fan_is_visible,
2821 };
2822
2823 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2824                                    struct attribute *attr, int index)
2825 {
2826         struct device *dev = container_of(kobj, struct device, kobj);
2827         struct it87_data *data = dev_get_drvdata(dev);
2828         int i = index / 4;      /* pwm index */
2829         int a = index % 4;      /* attribute index */
2830
2831         if (!(data->has_pwm & BIT(i)))
2832                 return 0;
2833
2834         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2835         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2836                 return attr->mode | S_IWUSR;
2837
2838         /* pwm2_freq is writable if there are two pwm frequency selects */
2839         if (has_pwm_freq2(data) && i == 1 && a == 2)
2840                 return attr->mode | S_IWUSR;
2841
2842         return attr->mode;
2843 }
2844
2845 static struct attribute *it87_attributes_pwm[] = {
2846         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2847         &sensor_dev_attr_pwm1.dev_attr.attr,
2848         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2849         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2850
2851         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2852         &sensor_dev_attr_pwm2.dev_attr.attr,
2853         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2854         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2855
2856         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2857         &sensor_dev_attr_pwm3.dev_attr.attr,
2858         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2859         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2860
2861         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2862         &sensor_dev_attr_pwm4.dev_attr.attr,
2863         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2864         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2865
2866         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2867         &sensor_dev_attr_pwm5.dev_attr.attr,
2868         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2869         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2870
2871         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2872         &sensor_dev_attr_pwm6.dev_attr.attr,
2873         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2874         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2875
2876         NULL
2877 };
2878
2879 static const struct attribute_group it87_group_pwm = {
2880         .attrs = it87_attributes_pwm,
2881         .is_visible = it87_pwm_is_visible,
2882 };
2883
2884 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2885                                         struct attribute *attr, int index)
2886 {
2887         struct device *dev = container_of(kobj, struct device, kobj);
2888         struct it87_data *data = dev_get_drvdata(dev);
2889         int i = index / 11;     /* pwm index */
2890         int a = index % 11;     /* attribute index */
2891
2892         if (index >= 33) {      /* pwm 4..6 */
2893                 i = (index - 33) / 6 + 3;
2894                 a = (index - 33) % 6 + 4;
2895         }
2896
2897         if (!(data->has_pwm & BIT(i)))
2898                 return 0;
2899
2900         if (has_newer_autopwm(data)) {
2901                 if (a < 4)      /* no auto point pwm */
2902                         return 0;
2903                 if (a == 8)     /* no auto_point4 */
2904                         return 0;
2905         }
2906         if (has_old_autopwm(data)) {
2907                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2908                         return 0;
2909         }
2910
2911         return attr->mode;
2912 }
2913
2914 static struct attribute *it87_attributes_auto_pwm[] = {
2915         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2916         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2917         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2918         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2919         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2920         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2921         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2922         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2923         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2924         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2925         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2926
2927         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2928         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2929         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2930         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2931         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2932         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2933         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2934         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2935         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2936         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2937         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2938
2939         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2940         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2941         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2942         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2943         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2944         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2945         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2946         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2947         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2948         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2949         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2950
2951         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2952         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2953         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2954         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2955         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2956         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2957
2958         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2959         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2960         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2961         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2962         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2963         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2964
2965         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2966         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2967         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2968         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2969         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2970         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2971
2972         NULL,
2973 };
2974
2975 static const struct attribute_group it87_group_auto_pwm = {
2976         .attrs = it87_attributes_auto_pwm,
2977         .is_visible = it87_auto_pwm_is_visible,
2978 };
2979
2980 /* SuperIO detection - will change isa_address if a chip is found */
2981 static int __init it87_find(int sioaddr, unsigned short *address,
2982                             phys_addr_t *mmio_address, struct it87_sio_data *sio_data)
2983 {
2984         const struct it87_devices *config;
2985         phys_addr_t base = 0;
2986         bool doexit = true;
2987         char mmio_str[32];
2988         u16 chip_type;
2989         int err;
2990
2991         err = superio_enter(sioaddr);
2992         if (err)
2993                 return err;
2994
2995         sio_data->sioaddr = sioaddr;
2996
2997         err = -ENODEV;
2998         chip_type = superio_inw(sioaddr, DEVID);
2999         if (chip_type == 0xffff)
3000                 goto exit;
3001
3002         if (force_id)
3003                 chip_type = force_id;
3004
3005         switch (chip_type) {
3006         case IT8705F_DEVID:
3007                 sio_data->type = it87;
3008                 break;
3009         case IT8712F_DEVID:
3010                 sio_data->type = it8712;
3011                 break;
3012         case IT8716F_DEVID:
3013         case IT8726F_DEVID:
3014                 sio_data->type = it8716;
3015                 break;
3016         case IT8718F_DEVID:
3017                 sio_data->type = it8718;
3018                 break;
3019         case IT8720F_DEVID:
3020                 sio_data->type = it8720;
3021                 break;
3022         case IT8721F_DEVID:
3023                 sio_data->type = it8721;
3024                 break;
3025         case IT8728F_DEVID:
3026                 sio_data->type = it8728;
3027                 break;
3028         case IT8732F_DEVID:
3029                 sio_data->type = it8732;
3030                 break;
3031         case IT8792E_DEVID:
3032                 sio_data->type = it8792;
3033                 /*
3034                  * Disabling configuration mode on IT8792E can result in system
3035                  * hang-ups and access failures to the Super-IO chip at the
3036                  * second SIO address. Never exit configuration mode on this
3037                  * chip to avoid the problem.
3038                  */
3039                 doexit = false;
3040                 break;
3041         case IT8771E_DEVID:
3042                 sio_data->type = it8771;
3043                 break;
3044         case IT8772E_DEVID:
3045                 sio_data->type = it8772;
3046                 break;
3047         case IT8781F_DEVID:
3048                 sio_data->type = it8781;
3049                 break;
3050         case IT8782F_DEVID:
3051                 sio_data->type = it8782;
3052                 break;
3053         case IT8783E_DEVID:
3054                 sio_data->type = it8783;
3055                 break;
3056         case IT8786E_DEVID:
3057                 sio_data->type = it8786;
3058                 break;
3059         case IT8790E_DEVID:
3060                 sio_data->type = it8790;
3061                 doexit = false;         /* See IT8792E comment above */
3062                 break;
3063         case IT8603E_DEVID:
3064         case IT8623E_DEVID:
3065                 sio_data->type = it8603;
3066                 break;
3067         case IT8607E_DEVID:
3068                 sio_data->type = it8607;
3069                 break;
3070         case IT8613E_DEVID:
3071                 sio_data->type = it8613;
3072                 break;
3073         case IT8620E_DEVID:
3074                 sio_data->type = it8620;
3075                 break;
3076         case IT8622E_DEVID:
3077                 sio_data->type = it8622;
3078                 break;
3079         case IT8625E_DEVID:
3080                 sio_data->type = it8625;
3081                 break;
3082         case IT8628E_DEVID:
3083                 sio_data->type = it8628;
3084                 break;
3085         case IT8655E_DEVID:
3086                 sio_data->type = it8655;
3087                 break;
3088         case IT8665E_DEVID:
3089                 sio_data->type = it8665;
3090                 break;
3091         case IT8686E_DEVID:
3092                 sio_data->type = it8686;
3093                 break;
3094         case 0xffff:    /* No device at all */
3095                 goto exit;
3096         default:
3097                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3098                 goto exit;
3099         }
3100
3101         superio_select(sioaddr, PME);
3102         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3103                 pr_info("Device not activated, skipping\n");
3104                 goto exit;
3105         }
3106
3107         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3108         if (*address == 0) {
3109                 pr_info("Base address not set, skipping\n");
3110                 goto exit;
3111         }
3112
3113         sio_data->doexit = doexit;
3114
3115         err = 0;
3116         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3117
3118         config = &it87_devices[sio_data->type];
3119
3120         if (has_mmio(config) && mmio) {
3121                 u8 reg;
3122
3123                 reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
3124                 if (reg & BIT(5)) {
3125                         base = 0xf0000000 + ((reg & 0x0f) << 24);
3126                         base += (reg & 0xc0) << 14;
3127                 }
3128         }
3129         *mmio_address = base;
3130
3131         mmio_str[0] = '\0';
3132         if (base)
3133                 snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
3134
3135         pr_info("Found IT%04x%s chip at 0x%x%s, revision %d\n", chip_type,
3136                 it87_devices[sio_data->type].suffix,
3137                 *address, mmio_str, sio_data->revision);
3138
3139         /* in7 (VSB or VCCH5V) is always internal on some chips */
3140         if (has_in7_internal(config))
3141                 sio_data->internal |= BIT(1);
3142
3143         /* in8 (Vbat) is always internal */
3144         sio_data->internal |= BIT(2);
3145
3146         /* in9 (AVCC3), always internal if supported */
3147         if (has_avcc3(config))
3148                 sio_data->internal |= BIT(3); /* in9 is AVCC */
3149         else
3150                 sio_data->skip_in |= BIT(9);
3151
3152         if (!has_four_pwm(config))
3153                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3154         else if (!has_five_pwm(config))
3155                 sio_data->skip_pwm |= BIT(4) | BIT(5);
3156         else if (!has_six_pwm(config))
3157                 sio_data->skip_pwm |= BIT(5);
3158
3159         if (!has_vid(config))
3160                 sio_data->skip_vid = 1;
3161
3162         /* Read GPIO config and VID value from LDN 7 (GPIO) */
3163         if (sio_data->type == it87) {
3164                 /* The IT8705F has a different LD number for GPIO */
3165                 superio_select(sioaddr, 5);
3166                 sio_data->beep_pin = superio_inb(sioaddr,
3167                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3168         } else if (sio_data->type == it8783) {
3169                 int reg25, reg27, reg2a, reg2c, regef;
3170
3171                 superio_select(sioaddr, GPIO);
3172
3173                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3174                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3175                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3176                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3177                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3178
3179                 /* Check if fan3 is there or not */
3180                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3181                         sio_data->skip_fan |= BIT(2);
3182                 if ((reg25 & BIT(4)) ||
3183                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
3184                         sio_data->skip_pwm |= BIT(2);
3185
3186                 /* Check if fan2 is there or not */
3187                 if (reg27 & BIT(7))
3188                         sio_data->skip_fan |= BIT(1);
3189                 if (reg27 & BIT(3))
3190                         sio_data->skip_pwm |= BIT(1);
3191
3192                 /* VIN5 */
3193                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3194                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3195
3196                 /* VIN6 */
3197                 if (reg27 & BIT(1))
3198                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3199
3200                 /*
3201                  * VIN7
3202                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3203                  */
3204                 if (reg27 & BIT(2)) {
3205                         /*
3206                          * The data sheet is a bit unclear regarding the
3207                          * internal voltage divider for VCCH5V. It says
3208                          * "This bit enables and switches VIN7 (pin 91) to the
3209                          * internal voltage divider for VCCH5V".
3210                          * This is different to other chips, where the internal
3211                          * voltage divider would connect VIN7 to an internal
3212                          * voltage source. Maybe that is the case here as well.
3213                          *
3214                          * Since we don't know for sure, re-route it if that is
3215                          * not the case, and ask the user to report if the
3216                          * resulting voltage is sane.
3217                          */
3218                         if (!(reg2c & BIT(1))) {
3219                                 reg2c |= BIT(1);
3220                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3221                                              reg2c);
3222                                 pr_notice("Routing internal VCCH5V to in7.\n");
3223                         }
3224                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3225                         pr_notice("Please report if it displays a reasonable voltage.\n");
3226                 }
3227
3228                 if (reg2c & BIT(0))
3229                         sio_data->internal |= BIT(0);
3230                 if (reg2c & BIT(1))
3231                         sio_data->internal |= BIT(1);
3232
3233                 sio_data->beep_pin = superio_inb(sioaddr,
3234                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3235         } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3236                 int reg27, reg29;
3237
3238                 superio_select(sioaddr, GPIO);
3239
3240                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3241
3242                 /* Check if fan3 is there or not */
3243                 if (reg27 & BIT(6))
3244                         sio_data->skip_pwm |= BIT(2);
3245                 if (reg27 & BIT(7))
3246                         sio_data->skip_fan |= BIT(2);
3247
3248                 /* Check if fan2 is there or not */
3249                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3250                 if (reg29 & BIT(1))
3251                         sio_data->skip_pwm |= BIT(1);
3252                 if (reg29 & BIT(2))
3253                         sio_data->skip_fan |= BIT(1);
3254
3255                 switch (sio_data->type) {
3256                 case it8603:
3257                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3258                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3259                         break;
3260                 case it8607:
3261                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3262                         sio_data->skip_fan |= BIT(0);
3263                 default:
3264                         break;
3265                 }
3266
3267                 sio_data->beep_pin = superio_inb(sioaddr,
3268                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3269         } else if (sio_data->type == it8613) {
3270                 int reg27, reg29, reg2a;
3271
3272                 superio_select(sioaddr, GPIO);
3273
3274                 /* Check for pwm3, fan3, pwm5, fan5 */
3275                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3276                 if (reg27 & BIT(1))
3277                         sio_data->skip_fan |= BIT(4);
3278                 if (reg27 & BIT(3))
3279                         sio_data->skip_pwm |= BIT(4);
3280                 if (reg27 & BIT(6))
3281                         sio_data->skip_pwm |= BIT(2);
3282                 if (reg27 & BIT(7))
3283                         sio_data->skip_fan |= BIT(2);
3284
3285                 /* Check for pwm2, fan2 */
3286                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3287                 if (reg29 & BIT(1))
3288                         sio_data->skip_pwm |= BIT(1);
3289                 if (reg29 & BIT(2))
3290                         sio_data->skip_fan |= BIT(1);
3291
3292                 /* Check for pwm4, fan4 */
3293                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3294                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3295                         sio_data->skip_fan |= BIT(3);
3296                         sio_data->skip_pwm |= BIT(3);
3297                 }
3298
3299                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3300                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3301                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3302                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3303
3304                 sio_data->beep_pin = superio_inb(sioaddr,
3305                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3306         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3307                    sio_data->type == it8686) {
3308                 int reg;
3309
3310                 superio_select(sioaddr, GPIO);
3311
3312                 /* Check for pwm5 */
3313                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3314                 if (reg & BIT(6))
3315                         sio_data->skip_pwm |= BIT(4);
3316
3317                 /* Check for fan4, fan5 */
3318                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3319                 if (!(reg & BIT(5)))
3320                         sio_data->skip_fan |= BIT(3);
3321                 if (!(reg & BIT(4)))
3322                         sio_data->skip_fan |= BIT(4);
3323
3324                 /* Check for pwm3, fan3 */
3325                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3326                 if (reg & BIT(6))
3327                         sio_data->skip_pwm |= BIT(2);
3328                 if (reg & BIT(7))
3329                         sio_data->skip_fan |= BIT(2);
3330
3331                 /* Check for pwm4 */
3332                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3333                 if (reg & BIT(2))
3334                         sio_data->skip_pwm |= BIT(3);
3335
3336                 /* Check for pwm2, fan2 */
3337                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3338                 if (reg & BIT(1))
3339                         sio_data->skip_pwm |= BIT(1);
3340                 if (reg & BIT(2))
3341                         sio_data->skip_fan |= BIT(1);
3342                 /* Check for pwm6, fan6 */
3343                 if (!(reg & BIT(7))) {
3344                         sio_data->skip_pwm |= BIT(5);
3345                         sio_data->skip_fan |= BIT(5);
3346                 }
3347
3348                 /* Check if AVCC is on VIN3 */
3349                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3350                 if (reg & BIT(0)) {
3351                         /* For it8686, the bit just enables AVCC3 */
3352                         if (sio_data->type != it8686)
3353                                 sio_data->internal |= BIT(0);
3354                 } else {
3355                         sio_data->internal &= ~BIT(3);
3356                         sio_data->skip_in |= BIT(9);
3357                 }
3358
3359                 sio_data->beep_pin = superio_inb(sioaddr,
3360                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3361         } else if (sio_data->type == it8622) {
3362                 int reg;
3363
3364                 superio_select(sioaddr, GPIO);
3365
3366                 /* Check for pwm4, fan4 */
3367                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3368                 if (reg & BIT(6))
3369                         sio_data->skip_fan |= BIT(3);
3370                 if (reg & BIT(5))
3371                         sio_data->skip_pwm |= BIT(3);
3372
3373                 /* Check for pwm3, fan3, pwm5, fan5 */
3374                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3375                 if (reg & BIT(6))
3376                         sio_data->skip_pwm |= BIT(2);
3377                 if (reg & BIT(7))
3378                         sio_data->skip_fan |= BIT(2);
3379                 if (reg & BIT(3))
3380                         sio_data->skip_pwm |= BIT(4);
3381                 if (reg & BIT(1))
3382                         sio_data->skip_fan |= BIT(4);
3383
3384                 /* Check for pwm2, fan2 */
3385                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3386                 if (reg & BIT(1))
3387                         sio_data->skip_pwm |= BIT(1);
3388                 if (reg & BIT(2))
3389                         sio_data->skip_fan |= BIT(1);
3390
3391                 /* Check for AVCC */
3392                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3393                 if (!(reg & BIT(0)))
3394                         sio_data->skip_in |= BIT(9);
3395
3396                 sio_data->beep_pin = superio_inb(sioaddr,
3397                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3398         } else if (sio_data->type == it8732) {
3399                 int reg;
3400
3401                 superio_select(sioaddr, GPIO);
3402
3403                 /* Check for pwm2, fan2 */
3404                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3405                 if (reg & BIT(1))
3406                         sio_data->skip_pwm |= BIT(1);
3407                 if (reg & BIT(2))
3408                         sio_data->skip_fan |= BIT(1);
3409
3410                 /* Check for pwm3, fan3, fan4 */
3411                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3412                 if (reg & BIT(6))
3413                         sio_data->skip_pwm |= BIT(2);
3414                 if (reg & BIT(7))
3415                         sio_data->skip_fan |= BIT(2);
3416                 if (reg & BIT(5))
3417                         sio_data->skip_fan |= BIT(3);
3418
3419                 /* Check if AVCC is on VIN3 */
3420                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3421                 if (reg & BIT(0))
3422                         sio_data->internal |= BIT(0);
3423
3424                 sio_data->beep_pin = superio_inb(sioaddr,
3425                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3426         } else if (sio_data->type == it8655) {
3427                 int reg;
3428
3429                 superio_select(sioaddr, GPIO);
3430
3431                 /* Check for pwm2 */
3432                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3433                 if (reg & BIT(1))
3434                         sio_data->skip_pwm |= BIT(1);
3435
3436                 /* Check for fan2 */
3437                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3438                 if (reg & BIT(4))
3439                         sio_data->skip_fan |= BIT(1);
3440
3441                 /* Check for pwm3, fan3 */
3442                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3443                 if (reg & BIT(6))
3444                         sio_data->skip_pwm |= BIT(2);
3445                 if (reg & BIT(7))
3446                         sio_data->skip_fan |= BIT(2);
3447
3448                 sio_data->beep_pin = superio_inb(sioaddr,
3449                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3450         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3451                 int reg27, reg29, reg2d, regd3;
3452
3453                 superio_select(sioaddr, GPIO);
3454
3455                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3456                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3457                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3458                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3459
3460                 /* Check for pwm2, fan2 */
3461                 if (reg29 & BIT(1))
3462                         sio_data->skip_pwm |= BIT(1);
3463                 /*
3464                  * Note: Table 6-1 in datasheet claims that FAN_TAC2
3465                  * would be enabled with 29h[2]=0.
3466                  */
3467                 if (reg2d & BIT(4))
3468                         sio_data->skip_fan |= BIT(1);
3469
3470                 /* Check for pwm3, fan3 */
3471                 if (reg27 & BIT(6))
3472                         sio_data->skip_pwm |= BIT(2);
3473                 if (reg27 & BIT(7))
3474                         sio_data->skip_fan |= BIT(2);
3475
3476                 /* Check for pwm4, fan4, pwm5, fan5 */
3477                 if (sio_data->type == it8625) {
3478                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3479
3480                         if (reg25 & BIT(6))
3481                                 sio_data->skip_fan |= BIT(3);
3482                         if (reg25 & BIT(5))
3483                                 sio_data->skip_pwm |= BIT(3);
3484                         if (reg27 & BIT(3))
3485                                 sio_data->skip_pwm |= BIT(4);
3486                         if (reg27 & BIT(1))
3487                                 sio_data->skip_fan |= BIT(4);
3488                 } else {
3489                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3490
3491                         if (regd3 & BIT(2))
3492                                 sio_data->skip_pwm |= BIT(3);
3493                         if (regd3 & BIT(3))
3494                                 sio_data->skip_fan |= BIT(3);
3495                         if (reg26 & BIT(5))
3496                                 sio_data->skip_pwm |= BIT(4);
3497                         if (reg26 & BIT(4))
3498                                 sio_data->skip_fan |= BIT(4);
3499                 }
3500
3501                 /* Check for pwm6, fan6 */
3502                 if (regd3 & BIT(0))
3503                         sio_data->skip_pwm |= BIT(5);
3504                 if (regd3 & BIT(1))
3505                         sio_data->skip_fan |= BIT(5);
3506
3507                 sio_data->beep_pin = superio_inb(sioaddr,
3508                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3509         } else {
3510                 int reg;
3511                 bool uart6;
3512
3513                 superio_select(sioaddr, GPIO);
3514
3515                 /* Check for fan4, fan5 */
3516                 if (has_five_fans(config)) {
3517                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3518                         switch (sio_data->type) {
3519                         case it8718:
3520                                 if (reg & BIT(5))
3521                                         sio_data->skip_fan |= BIT(3);
3522                                 if (reg & BIT(4))
3523                                         sio_data->skip_fan |= BIT(4);
3524                                 break;
3525                         case it8720:
3526                         case it8721:
3527                         case it8728:
3528                                 if (!(reg & BIT(5)))
3529                                         sio_data->skip_fan |= BIT(3);
3530                                 if (!(reg & BIT(4)))
3531                                         sio_data->skip_fan |= BIT(4);
3532                                 break;
3533                         default:
3534                                 break;
3535                         }
3536                 }
3537
3538                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3539                 if (!sio_data->skip_vid) {
3540                         /* We need at least 4 VID pins */
3541                         if (reg & 0x0f) {
3542                                 pr_info("VID is disabled (pins used for GPIO)\n");
3543                                 sio_data->skip_vid = 1;
3544                         }
3545                 }
3546
3547                 /* Check if fan3 is there or not */
3548                 if (reg & BIT(6))
3549                         sio_data->skip_pwm |= BIT(2);
3550                 if (reg & BIT(7))
3551                         sio_data->skip_fan |= BIT(2);
3552
3553                 /* Check if fan2 is there or not */
3554                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3555                 if (reg & BIT(1))
3556                         sio_data->skip_pwm |= BIT(1);
3557                 if (reg & BIT(2))
3558                         sio_data->skip_fan |= BIT(1);
3559
3560                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3561                     !(sio_data->skip_vid))
3562                         sio_data->vid_value = superio_inb(sioaddr,
3563                                                           IT87_SIO_VID_REG);
3564
3565                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3566
3567                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3568
3569                 /*
3570                  * The IT8720F has no VIN7 pin, so VCCH should always be
3571                  * routed internally to VIN7 with an internal divider.
3572                  * Curiously, there still is a configuration bit to control
3573                  * this, which means it can be set incorrectly. And even
3574                  * more curiously, many boards out there are improperly
3575                  * configured, even though the IT8720F datasheet claims
3576                  * that the internal routing of VCCH to VIN7 is the default
3577                  * setting. So we force the internal routing in this case.
3578                  *
3579                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3580                  * If UART6 is enabled, re-route VIN7 to the internal divider
3581                  * if that is not already the case.
3582                  */
3583                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3584                         reg |= BIT(1);
3585                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3586                         pr_notice("Routing internal VCCH to in7\n");
3587                 }
3588                 if (reg & BIT(0))
3589                         sio_data->internal |= BIT(0);
3590                 if (reg & BIT(1))
3591                         sio_data->internal |= BIT(1);
3592
3593                 /*
3594                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3595                  * While VIN7 can be routed to the internal voltage divider,
3596                  * VIN5 and VIN6 are not available if UART6 is enabled.
3597                  *
3598                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3599                  * is the temperature source. Since we can not read the
3600                  * temperature source here, skip_temp is preliminary.
3601                  */
3602                 if (uart6) {
3603                         sio_data->skip_in |= BIT(5) | BIT(6);
3604                         sio_data->skip_temp |= BIT(2);
3605                 }
3606
3607                 sio_data->beep_pin = superio_inb(sioaddr,
3608                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3609         }
3610         if (sio_data->beep_pin)
3611                 pr_info("Beeping is supported\n");
3612
3613         if (config->smbus_bitmap && !base) {
3614                 u8 reg;
3615
3616                 superio_select(sioaddr, PME);
3617                 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3618                 sio_data->ec_special_config = reg;
3619                 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3620         }
3621
3622 exit:
3623         superio_exit(sioaddr, doexit);
3624         return err;
3625 }
3626
3627 static void it87_init_regs(struct platform_device *pdev)
3628 {
3629         struct it87_data *data = platform_get_drvdata(pdev);
3630
3631         /* Initialize chip specific register pointers */
3632         switch (data->type) {
3633         case it8628:
3634         case it8686:
3635                 data->REG_FAN = IT87_REG_FAN;
3636                 data->REG_FANX = IT87_REG_FANX;
3637                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3638                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3639                 data->REG_PWM = IT87_REG_PWM;
3640                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3641                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3642                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3643                 break;
3644         case it8625:
3645         case it8655:
3646         case it8665:
3647                 data->REG_FAN = IT87_REG_FAN_8665;
3648                 data->REG_FANX = IT87_REG_FANX_8665;
3649                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3650                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3651                 data->REG_PWM = IT87_REG_PWM_8665;
3652                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3653                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3654                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3655                 break;
3656         case it8622:
3657                 data->REG_FAN = IT87_REG_FAN;
3658                 data->REG_FANX = IT87_REG_FANX;
3659                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3660                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3661                 data->REG_PWM = IT87_REG_PWM_8665;
3662                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3663                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3664                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3665                 break;
3666         case it8613:
3667                 data->REG_FAN = IT87_REG_FAN;
3668                 data->REG_FANX = IT87_REG_FANX;
3669                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3670                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3671                 data->REG_PWM = IT87_REG_PWM_8665;
3672                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3673                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3674                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3675                 break;
3676         default:
3677                 data->REG_FAN = IT87_REG_FAN;
3678                 data->REG_FANX = IT87_REG_FANX;
3679                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3680                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3681                 data->REG_PWM = IT87_REG_PWM;
3682                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3683                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3684                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3685                 break;
3686         }
3687
3688         if (data->mmio) {
3689                 data->read = it87_mmio_read;
3690                 data->write = it87_mmio_write;
3691         } else if (has_bank_sel(data)) {
3692                 data->read = it87_io_read;
3693                 data->write = it87_io_write;
3694         } else {
3695                 data->read = _it87_io_read;
3696                 data->write = _it87_io_write;
3697         }
3698 }
3699
3700 /* Called when we have found a new IT87. */
3701 static void it87_init_device(struct platform_device *pdev)
3702 {
3703         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3704         struct it87_data *data = platform_get_drvdata(pdev);
3705         int tmp, i;
3706         u8 mask;
3707
3708         if (has_new_tempmap(data)) {
3709                 data->pwm_temp_map_shift = 3;
3710                 data->pwm_temp_map_mask = 0x07;
3711         } else {
3712                 data->pwm_temp_map_shift = 0;
3713                 data->pwm_temp_map_mask = 0x03;
3714         }
3715
3716         /*
3717          * For each PWM channel:
3718          * - If it is in automatic mode, setting to manual mode should set
3719          *   the fan to full speed by default.
3720          * - If it is in manual mode, we need a mapping to temperature
3721          *   channels to use when later setting to automatic mode later.
3722          *   Map to the first sensor by default (we are clueless.)
3723          * In both cases, the value can (and should) be changed by the user
3724          * prior to switching to a different mode.
3725          * Note that this is no longer needed for the IT8721F and later, as
3726          * these have separate registers for the temperature mapping and the
3727          * manual duty cycle.
3728          */
3729         for (i = 0; i < NUM_AUTO_PWM; i++) {
3730                 data->pwm_temp_map[i] = 0;
3731                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3732                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3733         }
3734
3735         /*
3736          * Some chips seem to have default value 0xff for all limit
3737          * registers. For low voltage limits it makes no sense and triggers
3738          * alarms, so change to 0 instead. For high temperature limits, it
3739          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3740          * but is still confusing, so change to 127 degrees C.
3741          */
3742         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3743                 tmp = data->read(data, IT87_REG_VIN_MIN(i));
3744                 if (tmp == 0xff)
3745                         data->write(data, IT87_REG_VIN_MIN(i), 0);
3746         }
3747         for (i = 0; i < data->num_temp_limit; i++) {
3748                 tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3749                 if (tmp == 0xff)
3750                         data->write(data, data->REG_TEMP_HIGH[i], 127);
3751         }
3752
3753         /*
3754          * Temperature channels are not forcibly enabled, as they can be
3755          * set to two different sensor types and we can't guess which one
3756          * is correct for a given system. These channels can be enabled at
3757          * run-time through the temp{1-3}_type sysfs accessors if needed.
3758          */
3759
3760         /* Check if voltage monitors are reset manually or by some reason */
3761         tmp = data->read(data, IT87_REG_VIN_ENABLE);
3762         if ((tmp & 0xff) == 0) {
3763                 /* Enable all voltage monitors */
3764                 data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3765         }
3766
3767         /* Check if tachometers are reset manually or by some reason */
3768         mask = 0x70 & ~(sio_data->skip_fan << 4);
3769         data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3770         if ((data->fan_main_ctrl & mask) == 0) {
3771                 /* Enable all fan tachometers */
3772                 data->fan_main_ctrl |= mask;
3773                 data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3774         }
3775         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3776
3777         tmp = data->read(data, IT87_REG_FAN_16BIT);
3778
3779         /* Set tachometers to 16-bit mode if needed */
3780         if (has_fan16_config(data)) {
3781                 if (~tmp & 0x07 & data->has_fan) {
3782                         dev_dbg(&pdev->dev,
3783                                 "Setting fan1-3 to 16-bit mode\n");
3784                         data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3785                 }
3786         }
3787
3788         /* Check for additional fans */
3789         if (has_four_fans(data) && (tmp & BIT(4)))
3790                 data->has_fan |= BIT(3); /* fan4 enabled */
3791         if (has_five_fans(data) && (tmp & BIT(5)))
3792                 data->has_fan |= BIT(4); /* fan5 enabled */
3793         if (has_six_fans(data)) {
3794                 switch (data->type) {
3795                 case it8620:
3796                 case it8628:
3797                 case it8686:
3798                         if (tmp & BIT(2))
3799                                 data->has_fan |= BIT(5); /* fan6 enabled */
3800                         break;
3801                 case it8625:
3802                 case it8665:
3803                         tmp = data->read(data, IT87_REG_FAN_DIV);
3804                         if (tmp & BIT(3))
3805                                 data->has_fan |= BIT(5); /* fan6 enabled */
3806                         break;
3807                 default:
3808                         break;
3809                 }
3810         }
3811
3812         /* Fan input pins may be used for alternative functions */
3813         data->has_fan &= ~sio_data->skip_fan;
3814
3815         /* Check if pwm6 is enabled */
3816         if (has_six_pwm(data)) {
3817                 switch (data->type) {
3818                 case it8620:
3819                 case it8686:
3820                         tmp = data->read(data, IT87_REG_FAN_DIV);
3821                         if (!(tmp & BIT(3)))
3822                                 sio_data->skip_pwm |= BIT(5);
3823                         break;
3824                 default:
3825                         break;
3826                 }
3827         }
3828
3829         if (has_bank_sel(data)) {
3830                 for (i = 0; i < 3; i++)
3831                         data->temp_src[i] =
3832                                 data->read(data, IT87_REG_TEMP_SRC1[i]);
3833                 data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3834         }
3835
3836         /* Start monitoring */
3837         data->write(data, IT87_REG_CONFIG,
3838                     (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3839                                         (update_vbat ? 0x41 : 0x01));
3840 }
3841
3842 /* Return 1 if and only if the PWM interface is safe to use */
3843 static int it87_check_pwm(struct device *dev)
3844 {
3845         struct it87_data *data = dev_get_drvdata(dev);
3846         /*
3847          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3848          * and polarity set to active low is sign that this is the case so we
3849          * disable pwm control to protect the user.
3850          */
3851         int tmp = data->read(data, IT87_REG_FAN_CTL);
3852
3853         if ((tmp & 0x87) == 0) {
3854                 if (fix_pwm_polarity) {
3855                         /*
3856                          * The user asks us to attempt a chip reconfiguration.
3857                          * This means switching to active high polarity and
3858                          * inverting all fan speed values.
3859                          */
3860                         int i;
3861                         u8 pwm[3];
3862
3863                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3864                                 pwm[i] = data->read(data,
3865                                                          data->REG_PWM[i]);
3866
3867                         /*
3868                          * If any fan is in automatic pwm mode, the polarity
3869                          * might be correct, as suspicious as it seems, so we
3870                          * better don't change anything (but still disable the
3871                          * PWM interface).
3872                          */
3873                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3874                                 dev_info(dev,
3875                                          "Reconfiguring PWM to active high polarity\n");
3876                                 data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3877                                 for (i = 0; i < 3; i++)
3878                                         data->write(data, data->REG_PWM[i],
3879                                                     0x7f & ~pwm[i]);
3880                                 return 1;
3881                         }
3882
3883                         dev_info(dev,
3884                                  "PWM configuration is too broken to be fixed\n");
3885                 }
3886
3887                 dev_info(dev,
3888                          "Detected broken BIOS defaults, disabling PWM interface\n");
3889                 return 0;
3890         } else if (fix_pwm_polarity) {
3891                 dev_info(dev,
3892                          "PWM configuration looks sane, won't touch\n");
3893         }
3894
3895         return 1;
3896 }
3897
3898 static int it87_probe(struct platform_device *pdev)
3899 {
3900         struct it87_data *data;
3901         struct resource *res;
3902         struct device *dev = &pdev->dev;
3903         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3904         int enable_pwm_interface;
3905         struct device *hwmon_dev;
3906         int err;
3907
3908         data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3909         if (!data)
3910                 return -ENOMEM;
3911
3912         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3913         if (res) {
3914                 if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3915                                          DRVNAME)) {
3916                         dev_err(dev, "Failed to request region %pR\n", res);
3917                         return -EBUSY;
3918                 }
3919         } else {
3920                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3921                 data->mmio = devm_ioremap_resource(dev, res);
3922                 if (IS_ERR(data->mmio))
3923                         return PTR_ERR(data->mmio);
3924         }
3925
3926         data->addr = res->start;
3927         data->type = sio_data->type;
3928         data->sioaddr = sio_data->sioaddr;
3929         data->smbus_bitmap = sio_data->smbus_bitmap;
3930         data->ec_special_config = sio_data->ec_special_config;
3931         data->doexit = sio_data->doexit;
3932         data->features = it87_devices[sio_data->type].features;
3933         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3934         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3935         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3936         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3937         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3938
3939         /*
3940          * IT8705F Datasheet 0.4.1, 3h == Version G.
3941          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3942          * These are the first revisions with 16-bit tachometer support.
3943          */
3944         switch (data->type) {
3945         case it87:
3946                 if (sio_data->revision >= 0x03) {
3947                         data->features &= ~FEAT_OLD_AUTOPWM;
3948                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3949                 }
3950                 break;
3951         case it8712:
3952                 if (sio_data->revision >= 0x08) {
3953                         data->features &= ~FEAT_OLD_AUTOPWM;
3954                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3955                                           FEAT_FIVE_FANS;
3956                 }
3957                 break;
3958         default:
3959                 break;
3960         }
3961
3962         platform_set_drvdata(pdev, data);
3963
3964         mutex_init(&data->update_lock);
3965
3966         /* Initialize register pointers */
3967         it87_init_regs(pdev);
3968
3969         err = smbus_disable(data);
3970         if (err)
3971                 return err;
3972
3973         /* Now, we do the remaining detection. */
3974         if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
3975             data->read(data, IT87_REG_CHIPID) != 0x90) {
3976                 smbus_enable(data);
3977                 return -ENODEV;
3978         }
3979
3980         /* Check PWM configuration */
3981         enable_pwm_interface = it87_check_pwm(dev);
3982
3983         /* Starting with IT8721F, we handle scaling of internal voltages */
3984         if (has_scaling(data)) {
3985                 if (sio_data->internal & BIT(0))
3986                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
3987                 if (sio_data->internal & BIT(1))
3988                         data->in_scaled |= BIT(7);      /* in7 is VSB */
3989                 if (sio_data->internal & BIT(2))
3990                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
3991                 if (sio_data->internal & BIT(3))
3992                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
3993         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3994                    sio_data->type == it8783) {
3995                 if (sio_data->internal & BIT(0))
3996                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
3997                 if (sio_data->internal & BIT(1))
3998                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
3999         }
4000
4001         data->has_temp = 0x07;
4002         if (sio_data->skip_temp & BIT(2)) {
4003                 if (sio_data->type == it8782 &&
4004                     !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
4005                         data->has_temp &= ~BIT(2);
4006         }
4007
4008         data->in_internal = sio_data->internal;
4009         data->has_in = 0x3ff & ~sio_data->skip_in;
4010
4011         if (has_four_temp(data)) {
4012                 data->has_temp |= BIT(3);
4013         } else if (has_six_temp(data)) {
4014                 u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
4015
4016                 /* Check for additional temperature sensors */
4017                 if ((reg & 0x03) >= 0x02)
4018                         data->has_temp |= BIT(3);
4019                 if (((reg >> 2) & 0x03) >= 0x02)
4020                         data->has_temp |= BIT(4);
4021                 if (((reg >> 4) & 0x03) >= 0x02)
4022                         data->has_temp |= BIT(5);
4023
4024                 /* Check for additional voltage sensors */
4025                 if ((reg & 0x03) == 0x01)
4026                         data->has_in |= BIT(10);
4027                 if (((reg >> 2) & 0x03) == 0x01)
4028                         data->has_in |= BIT(11);
4029                 if (((reg >> 4) & 0x03) == 0x01)
4030                         data->has_in |= BIT(12);
4031         }
4032
4033         data->has_beep = !!sio_data->beep_pin;
4034
4035         /* Initialize the IT87 chip */
4036         it87_init_device(pdev);
4037
4038         smbus_enable(data);
4039
4040         if (!sio_data->skip_vid) {
4041                 data->has_vid = true;
4042                 data->vrm = vid_which_vrm();
4043                 /* VID reading from Super-I/O config space if available */
4044                 data->vid = sio_data->vid_value;
4045         }
4046
4047         /* Prepare for sysfs hooks */
4048         data->groups[0] = &it87_group;
4049         data->groups[1] = &it87_group_in;
4050         data->groups[2] = &it87_group_temp;
4051         data->groups[3] = &it87_group_fan;
4052
4053         if (enable_pwm_interface) {
4054                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
4055                 data->has_pwm &= ~sio_data->skip_pwm;
4056
4057                 data->groups[4] = &it87_group_pwm;
4058                 if (has_old_autopwm(data) || has_newer_autopwm(data))
4059                         data->groups[5] = &it87_group_auto_pwm;
4060         }
4061
4062         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
4063                                         it87_devices[sio_data->type].name,
4064                                         data, data->groups);
4065         return PTR_ERR_OR_ZERO(hwmon_dev);
4066 }
4067
4068 static struct platform_driver it87_driver = {
4069         .driver = {
4070                 .name   = DRVNAME,
4071         },
4072         .probe  = it87_probe,
4073 };
4074
4075 static int __init it87_device_add(int index, unsigned short sio_address,
4076                                   phys_addr_t mmio_address,
4077                                   const struct it87_sio_data *sio_data)
4078 {
4079         struct platform_device *pdev;
4080         struct resource res = {
4081                 .name   = DRVNAME,
4082         };
4083         int err;
4084
4085         if (mmio_address) {
4086                 res.start = mmio_address;
4087                 res.end = mmio_address + 0x400 - 1;
4088                 res.flags = IORESOURCE_MEM;
4089         } else {
4090                 res.start = sio_address + IT87_EC_OFFSET;
4091                 res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
4092                 res.flags = IORESOURCE_IO;
4093         }
4094
4095         err = acpi_check_resource_conflict(&res);
4096         if (err) {
4097                 if (!ignore_resource_conflict)
4098                         return err;
4099         }
4100
4101         pdev = platform_device_alloc(DRVNAME, sio_address);
4102         if (!pdev)
4103                 return -ENOMEM;
4104
4105         err = platform_device_add_resources(pdev, &res, 1);
4106         if (err) {
4107                 pr_err("Device resource addition failed (%d)\n", err);
4108                 goto exit_device_put;
4109         }
4110
4111         err = platform_device_add_data(pdev, sio_data,
4112                                        sizeof(struct it87_sio_data));
4113         if (err) {
4114                 pr_err("Platform data allocation failed\n");
4115                 goto exit_device_put;
4116         }
4117
4118         err = platform_device_add(pdev);
4119         if (err) {
4120                 pr_err("Device addition failed (%d)\n", err);
4121                 goto exit_device_put;
4122         }
4123
4124         it87_pdev[index] = pdev;
4125         return 0;
4126
4127 exit_device_put:
4128         platform_device_put(pdev);
4129         return err;
4130 }
4131
4132 struct it87_dmi_data {
4133         bool sio2_force_config; /* force sio2 into configuration mode   */
4134         u8 skip_pwm;            /* pwm channels to skip for this board  */
4135 };
4136
4137 /*
4138  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4139  * (IT8792E) needs to be in configuration mode before accessing the first
4140  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4141  * This needs to be done before accessing the first Super-IO chip since
4142  * the second chip may have been accessed prior to loading this driver.
4143  *
4144  * The problem is also reported to affect IT8795E, which is used on X299 boards
4145  * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4146  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4147  * Z87X-OC.
4148  * DMI entries for those systems will be added as they become available and
4149  * as the problem is confirmed to affect those boards.
4150  */
4151 static struct it87_dmi_data gigabyte_sio2_force = {
4152         .sio2_force_config = true,
4153 };
4154
4155 /*
4156  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4157  * connected to a fan, but to something else. One user
4158  * has reported instant system power-off when changing
4159  * the PWM2 duty cycle, so we disable it.
4160  * I use the board name string as the trigger in case
4161  * the same board is ever used in other systems.
4162  */
4163 static struct it87_dmi_data nvidia_fn68pt = {
4164         .skip_pwm = BIT(1),
4165 };
4166
4167 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4168         {
4169                 .matches = {
4170                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4171                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4172                 },
4173                 .driver_data = &gigabyte_sio2_force,
4174         },
4175         {
4176                 .matches = {
4177                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4178                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4179                 },
4180                 .driver_data = &gigabyte_sio2_force,
4181         },
4182         {
4183                 .matches = {
4184                         DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
4185                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4186                 },
4187                 .driver_data = &gigabyte_sio2_force,
4188         },
4189         {
4190                 .matches = {
4191                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4192                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4193                 },
4194                 .driver_data = &nvidia_fn68pt,
4195         },
4196         { }
4197 };
4198
4199 static int __init sm_it87_init(void)
4200 {
4201         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4202         struct it87_dmi_data *dmi_data = NULL;
4203         int sioaddr[2] = { REG_2E, REG_4E };
4204         struct it87_sio_data sio_data;
4205         unsigned short isa_address;
4206         phys_addr_t mmio_address;
4207         bool found = false;
4208         int i, err;
4209
4210         pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4211
4212         if (dmi)
4213                 dmi_data = dmi->driver_data;
4214
4215         err = platform_driver_register(&it87_driver);
4216         if (err)
4217                 return err;
4218
4219         if (dmi_data && dmi_data->sio2_force_config)
4220                 __superio_enter(REG_4E);
4221
4222         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4223                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4224                 isa_address = 0;
4225                 mmio_address = 0;
4226                 err = it87_find(sioaddr[i], &isa_address, &mmio_address,
4227                                 &sio_data);
4228                 if (err || isa_address == 0)
4229                         continue;
4230
4231                 if (dmi_data)
4232                         sio_data.skip_pwm |= dmi_data->skip_pwm;
4233                 err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4234                 if (err)
4235                         goto exit_dev_unregister;
4236                 found = true;
4237         }
4238
4239         if (!found) {
4240                 err = -ENODEV;
4241                 goto exit_unregister;
4242         }
4243         return 0;
4244
4245 exit_dev_unregister:
4246         /* NULL check handled by platform_device_unregister */
4247         platform_device_unregister(it87_pdev[0]);
4248 exit_unregister:
4249         platform_driver_unregister(&it87_driver);
4250         return err;
4251 }
4252
4253 static void __exit sm_it87_exit(void)
4254 {
4255         /* NULL check handled by platform_device_unregister */
4256         platform_device_unregister(it87_pdev[1]);
4257         platform_device_unregister(it87_pdev[0]);
4258         platform_driver_unregister(&it87_driver);
4259 }
4260
4261 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4262 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4263 module_param(update_vbat, bool, 0);
4264 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4265 module_param(fix_pwm_polarity, bool, 0);
4266 MODULE_PARM_DESC(fix_pwm_polarity,
4267                  "Force PWM polarity to active high (DANGEROUS)");
4268 MODULE_LICENSE("GPL");
4269
4270 module_init(sm_it87_init);
4271 module_exit(sm_it87_exit);