2 * nct6775 - Driver for the hardware monitoring functionality of
3 * Nuvoton NCT677x Super-I/O chips
5 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
7 * Derived from w83627ehf driver
8 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
9 * Copyright (C) 2006 Yuan Mu (Winbond),
10 * Rudolf Marek <r.marek@assembler.cz>
11 * David Hubbard <david.c.hubbard@gmail.com>
12 * Daniel J Blueman <daniel.blueman@gmail.com>
13 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
15 * Shamelessly ripped from the w83627hf driver
16 * Copyright (C) 2003 Mark Studebaker
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 * Supports the following chips:
35 * Chip #vin #fan #pwm #temp chip IDs man ID
36 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
37 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
38 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
39 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
40 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
41 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
42 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
43 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
44 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
46 * #temp lists the number of monitored temperature sources (first value) plus
47 * the number of directly connectable temperature sensors (second value).
50 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
52 #include <linux/module.h>
53 #include <linux/init.h>
54 #include <linux/slab.h>
55 #include <linux/jiffies.h>
56 #include <linux/platform_device.h>
57 #include <linux/hwmon.h>
58 #include <linux/hwmon-sysfs.h>
59 #include <linux/hwmon-vid.h>
60 #include <linux/err.h>
61 #include <linux/mutex.h>
62 #include <linux/acpi.h>
63 #include <linux/bitops.h>
64 #include <linux/dmi.h>
66 #include <linux/debugfs.h>
72 enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
75 /* used to set data->name = nct6775_device_names[data->sio_kind] */
76 static const char * const nct6775_device_names[] = {
88 static const char * const nct6775_sio_names[] __initconst = {
100 static unsigned short force_id;
101 module_param(force_id, ushort, 0);
102 MODULE_PARM_DESC(force_id, "Override the detected device ID");
104 static unsigned short fan_debounce;
105 module_param(fan_debounce, ushort, 0);
106 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
108 #define DRVNAME "nct6775"
111 * Super-I/O constants and functions
114 #define NCT6775_LD_ACPI 0x0a
115 #define NCT6775_LD_HWM 0x0b
116 #define NCT6775_LD_VID 0x0d
117 #define NCT6775_LD_12 0x12
119 #define SIO_REG_LDSEL 0x07 /* Logical device select */
120 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
121 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
122 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
124 #define SIO_NCT6106_ID 0xc450
125 #define SIO_NCT6775_ID 0xb470
126 #define SIO_NCT6776_ID 0xc330
127 #define SIO_NCT6779_ID 0xc560
128 #define SIO_NCT6791_ID 0xc800
129 #define SIO_NCT6792_ID 0xc910
130 #define SIO_NCT6793_ID 0xd120
131 #define SIO_NCT6795_ID 0xd350
132 #define SIO_NCT6796_ID 0xd420
133 #define SIO_ID_MASK 0xFFF0
135 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
138 superio_outb(int ioreg, int reg, int val)
141 outb(val, ioreg + 1);
145 superio_inb(int ioreg, int reg)
148 return inb(ioreg + 1);
152 superio_select(int ioreg, int ld)
154 outb(SIO_REG_LDSEL, ioreg);
159 superio_enter(int ioreg)
162 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
164 if (!request_muxed_region(ioreg, 2, DRVNAME))
174 superio_exit(int ioreg)
178 outb(0x02, ioreg + 1);
179 release_region(ioreg, 2);
186 #define IOREGION_ALIGNMENT (~7)
187 #define IOREGION_OFFSET 5
188 #define IOREGION_LENGTH 2
189 #define ADDR_REG_OFFSET 0
190 #define DATA_REG_OFFSET 1
192 #define NCT6775_REG_BANK 0x4E
193 #define NCT6775_REG_CONFIG 0x40
196 * Not currently used:
197 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
198 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
199 * REG_MAN_ID is at port 0x4f
200 * REG_CHIP_ID is at port 0x58
203 #define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
204 #define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
206 #define NUM_REG_ALARM 7 /* Max number of alarm registers */
207 #define NUM_REG_BEEP 5 /* Max number of beep registers */
211 #define TEMP_SOURCE_VIRTUAL 0x1f
213 /* Common and NCT6775 specific data */
215 /* Voltage min/max registers for nr=7..14 are in bank 5 */
217 static const u16 NCT6775_REG_IN_MAX[] = {
218 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
219 0x55c, 0x55e, 0x560, 0x562 };
220 static const u16 NCT6775_REG_IN_MIN[] = {
221 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
222 0x55d, 0x55f, 0x561, 0x563 };
223 static const u16 NCT6775_REG_IN[] = {
224 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
227 #define NCT6775_REG_VBAT 0x5D
228 #define NCT6775_REG_DIODE 0x5E
229 #define NCT6775_DIODE_MASK 0x02
231 #define NCT6775_REG_FANDIV1 0x506
232 #define NCT6775_REG_FANDIV2 0x507
234 #define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
236 static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
238 /* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
240 static const s8 NCT6775_ALARM_BITS[] = {
241 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
242 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
244 6, 7, 11, -1, -1, /* fan1..fan5 */
245 -1, -1, -1, /* unused */
246 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
247 12, -1 }; /* intrusion0, intrusion1 */
249 #define FAN_ALARM_BASE 16
250 #define TEMP_ALARM_BASE 24
251 #define INTRUSION_ALARM_BASE 30
253 static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
256 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
259 static const s8 NCT6775_BEEP_BITS[] = {
260 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */
261 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
262 21, /* global beep enable */
263 6, 7, 11, 28, -1, /* fan1..fan5 */
264 -1, -1, -1, /* unused */
265 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
266 12, -1 }; /* intrusion0, intrusion1 */
268 #define BEEP_ENABLE_BASE 15
270 static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
271 static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
273 /* DC or PWM output fan configuration */
274 static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
275 static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
277 /* Advanced Fan control, some values are common for all fans */
279 static const u16 NCT6775_REG_TARGET[] = {
280 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01, 0xb01 };
281 static const u16 NCT6775_REG_FAN_MODE[] = {
282 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02, 0xb02 };
283 static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
284 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03, 0xb03 };
285 static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
286 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04, 0xb04 };
287 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
288 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05, 0xb05 };
289 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
290 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06, 0xb06 };
291 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
292 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
294 static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
295 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07, 0xb07 };
296 static const u16 NCT6775_REG_PWM[] = {
297 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09, 0xb09 };
298 static const u16 NCT6775_REG_PWM_READ[] = {
299 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09, 0xb09 };
301 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
302 static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
303 static const u16 NCT6775_REG_FAN_PULSES[] = { 0x641, 0x642, 0x643, 0x644, 0 };
304 static const u16 NCT6775_FAN_PULSE_SHIFT[] = { 0, 0, 0, 0, 0, 0 };
306 static const u16 NCT6775_REG_TEMP[] = {
307 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
309 static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
311 static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
312 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
313 static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
314 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
315 static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
316 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
318 static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
319 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
321 static const u16 NCT6775_REG_TEMP_SEL[] = {
322 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00, 0xb00 };
324 static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
325 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
326 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
327 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
328 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
329 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
330 static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
331 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
332 static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
333 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
335 static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
337 static const u16 NCT6775_REG_AUTO_TEMP[] = {
338 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21, 0xb21 };
339 static const u16 NCT6775_REG_AUTO_PWM[] = {
340 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27, 0xb27 };
342 #define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
343 #define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
345 static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
347 static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
348 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35, 0xb35 };
349 static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
350 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38, 0xb38 };
352 static const char *const nct6775_temp_label[] = {
366 "PCH_CHIP_CPU_MAX_TEMP",
376 #define NCT6775_TEMP_MASK 0x001ffffe
378 static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
384 static const u16 NCT6775_REG_TEMP_CRIT[32] = {
395 /* NCT6776 specific data */
397 /* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
398 #define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
399 #define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
401 static const s8 NCT6776_ALARM_BITS[] = {
402 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
403 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
405 6, 7, 11, 10, 23, /* fan1..fan5 */
406 -1, -1, -1, /* unused */
407 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
408 12, 9 }; /* intrusion0, intrusion1 */
410 static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
412 static const s8 NCT6776_BEEP_BITS[] = {
413 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
414 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */
415 24, /* global beep enable */
416 25, 26, 27, 28, 29, /* fan1..fan5 */
417 -1, -1, -1, /* unused */
418 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
419 30, 31 }; /* intrusion0, intrusion1 */
421 static const u16 NCT6776_REG_TOLERANCE_H[] = {
422 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c, 0xb0c };
424 static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
425 static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
427 static const u16 NCT6776_REG_FAN_MIN[] = {
428 0x63a, 0x63c, 0x63e, 0x640, 0x642, 0x64a, 0x64c };
429 static const u16 NCT6776_REG_FAN_PULSES[] = {
430 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0 };
432 static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
433 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
435 static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
436 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
438 static const char *const nct6776_temp_label[] = {
453 "PCH_CHIP_CPU_MAX_TEMP",
464 #define NCT6776_TEMP_MASK 0x007ffffe
466 static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
472 static const u16 NCT6776_REG_TEMP_CRIT[32] = {
477 /* NCT6779 specific data */
479 static const u16 NCT6779_REG_IN[] = {
480 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
481 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
483 static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
484 0x459, 0x45A, 0x45B, 0x568 };
486 static const s8 NCT6779_ALARM_BITS[] = {
487 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
488 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
490 6, 7, 11, 10, 23, /* fan1..fan5 */
491 -1, -1, -1, /* unused */
492 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
493 12, 9 }; /* intrusion0, intrusion1 */
495 static const s8 NCT6779_BEEP_BITS[] = {
496 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
497 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */
498 24, /* global beep enable */
499 25, 26, 27, 28, 29, /* fan1..fan5 */
500 -1, -1, -1, /* unused */
501 16, 17, -1, -1, -1, -1, /* temp1..temp6 */
502 30, 31 }; /* intrusion0, intrusion1 */
504 static const u16 NCT6779_REG_FAN[] = {
505 0x4b0, 0x4b2, 0x4b4, 0x4b6, 0x4b8, 0x4ba, 0x660 };
506 static const u16 NCT6779_REG_FAN_PULSES[] = {
507 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0 };
509 static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
510 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
511 #define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
512 static const u16 NCT6779_REG_CRITICAL_PWM[] = {
513 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37, 0xb37 };
515 static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
516 static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
517 static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
519 static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
521 static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
524 static const u16 NCT6779_REG_TEMP_OFFSET[] = {
525 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
527 static const char *const nct6779_temp_label[] = {
546 "PCH_CHIP_CPU_MAX_TEMP",
562 #define NCT6779_TEMP_MASK 0x07ffff7e
563 #define NCT6791_TEMP_MASK 0x87ffff7e
565 static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
566 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
567 0, 0, 0, 0, 0, 0, 0, 0,
568 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
571 static const u16 NCT6779_REG_TEMP_CRIT[32] = {
576 /* NCT6791 specific data */
578 #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
580 static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[NUM_FAN] = { 0, 0x239 };
581 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[NUM_FAN] = { 0, 0x23a };
582 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[NUM_FAN] = { 0, 0x23b };
583 static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[NUM_FAN] = { 0, 0x23c };
584 static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[NUM_FAN] = { 0, 0x23d };
585 static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[NUM_FAN] = { 0, 0x23e };
587 static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
588 0x459, 0x45A, 0x45B, 0x568, 0x45D };
590 static const s8 NCT6791_ALARM_BITS[] = {
591 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
592 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
594 6, 7, 11, 10, 23, 33, /* fan1..fan6 */
596 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
597 12, 9 }; /* intrusion0, intrusion1 */
599 /* NCT6792/NCT6793 specific data */
601 static const u16 NCT6792_REG_TEMP_MON[] = {
602 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
603 static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
604 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
606 static const char *const nct6792_temp_label[] = {
625 "PCH_CHIP_CPU_MAX_TEMP",
634 "PECI Agent 0 Calibration",
635 "PECI Agent 1 Calibration",
641 #define NCT6792_TEMP_MASK 0x9fffff7e
643 static const char *const nct6793_temp_label[] = {
662 "PCH_CHIP_CPU_MAX_TEMP",
672 "PECI Agent 0 Calibration",
673 "PECI Agent 1 Calibration",
678 #define NCT6793_TEMP_MASK 0xbfff037e
680 static const char *const nct6795_temp_label[] = {
699 "PCH_CHIP_CPU_MAX_TEMP",
709 "PECI Agent 0 Calibration",
710 "PECI Agent 1 Calibration",
715 #define NCT6795_TEMP_MASK 0xbfffff7e
717 static const char *const nct6796_temp_label[] = {
736 "PCH_CHIP_CPU_MAX_TEMP",
746 "PECI Agent 0 Calibration",
747 "PECI Agent 1 Calibration",
752 #define NCT6796_TEMP_MASK 0xbfff03fe
754 /* NCT6102D/NCT6106D specific data */
756 #define NCT6106_REG_VBAT 0x318
757 #define NCT6106_REG_DIODE 0x319
758 #define NCT6106_DIODE_MASK 0x01
760 static const u16 NCT6106_REG_IN_MAX[] = {
761 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
762 static const u16 NCT6106_REG_IN_MIN[] = {
763 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
764 static const u16 NCT6106_REG_IN[] = {
765 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
767 static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
768 static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
769 static const u16 NCT6106_REG_TEMP_HYST[] = {
770 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
771 static const u16 NCT6106_REG_TEMP_OVER[] = {
772 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
773 static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
774 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
775 static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
776 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
777 static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
778 static const u16 NCT6106_REG_TEMP_CONFIG[] = {
779 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
781 static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
782 static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
783 static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6, 0, 0 };
784 static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4, 0, 0 };
786 static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
787 static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
788 static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
789 static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
790 static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
791 static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
792 static const u16 NCT6106_REG_TEMP_SOURCE[] = {
793 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
795 static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
796 static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
797 0x11b, 0x12b, 0x13b };
799 static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
800 #define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
801 static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
803 static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
804 static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
805 static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
806 static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
807 static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
808 static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
810 static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
812 static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
813 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
814 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
815 static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c };
816 static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
817 static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
819 static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
820 static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
822 static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
823 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
825 static const s8 NCT6106_ALARM_BITS[] = {
826 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
827 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */
829 32, 33, 34, -1, -1, /* fan1..fan5 */
830 -1, -1, -1, /* unused */
831 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
832 48, -1 /* intrusion0, intrusion1 */
835 static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
836 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
838 static const s8 NCT6106_BEEP_BITS[] = {
839 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
840 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */
841 32, /* global beep enable */
842 24, 25, 26, 27, 28, /* fan1..fan5 */
843 -1, -1, -1, /* unused */
844 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
845 34, -1 /* intrusion0, intrusion1 */
848 static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
854 static const u16 NCT6106_REG_TEMP_CRIT[32] = {
859 static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
861 if (mode == 0 && pwm == 255)
866 static int pwm_enable_to_reg(enum pwm_enable mode)
877 /* 1 is DC mode, output in ms */
878 static unsigned int step_time_from_reg(u8 reg, u8 mode)
880 return mode ? 400 * reg : 100 * reg;
883 static u8 step_time_to_reg(unsigned int msec, u8 mode)
885 return clamp_val((mode ? (msec + 200) / 400 :
886 (msec + 50) / 100), 1, 255);
889 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
891 if (reg == 0 || reg == 255)
893 return 1350000U / (reg << divreg);
896 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
898 if ((reg & 0xff1f) == 0xff1f)
901 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
906 return 1350000U / reg;
909 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
911 if (reg == 0 || reg == 0xffff)
915 * Even though the registers are 16 bit wide, the fan divisor
918 return 1350000U / (reg << divreg);
921 static u16 fan_to_reg(u32 fan, unsigned int divreg)
926 return (1350000U / fan) >> divreg;
929 static inline unsigned int
936 * Some of the voltage inputs have internal scaling, the tables below
937 * contain 8 (the ADC LSB in mV) * scaling factor * 100
939 static const u16 scale_in[15] = {
940 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
944 static inline long in_from_reg(u8 reg, u8 nr)
946 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
949 static inline u8 in_to_reg(u32 val, u8 nr)
951 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
955 * Data structures and manipulation thereof
958 struct nct6775_data {
959 int addr; /* IO base of hw monitor block */
960 int sioreg; /* SIO register address */
964 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)
965 struct device *hwmon_dev;
968 const struct attribute_group *groups[6];
970 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
971 * 3=temp_crit, 4=temp_lcrit
973 u8 temp_src[NUM_TEMP];
974 u16 reg_temp_config[NUM_TEMP];
975 const char * const *temp_label;
983 const s8 *ALARM_BITS;
987 const u16 *REG_IN_MINMAX[2];
989 const u16 *REG_TARGET;
991 const u16 *REG_FAN_MODE;
992 const u16 *REG_FAN_MIN;
993 const u16 *REG_FAN_PULSES;
994 const u16 *FAN_PULSE_SHIFT;
995 const u16 *REG_FAN_TIME[3];
997 const u16 *REG_TOLERANCE_H;
999 const u8 *REG_PWM_MODE;
1000 const u8 *PWM_MODE_MASK;
1002 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1003 * [3]=pwm_max, [4]=pwm_step,
1004 * [5]=weight_duty_step, [6]=weight_duty_base
1006 const u16 *REG_PWM_READ;
1008 const u16 *REG_CRITICAL_PWM_ENABLE;
1009 u8 CRITICAL_PWM_ENABLE_MASK;
1010 const u16 *REG_CRITICAL_PWM;
1012 const u16 *REG_AUTO_TEMP;
1013 const u16 *REG_AUTO_PWM;
1015 const u16 *REG_CRITICAL_TEMP;
1016 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
1018 const u16 *REG_TEMP_SOURCE; /* temp register sources */
1019 const u16 *REG_TEMP_SEL;
1020 const u16 *REG_WEIGHT_TEMP_SEL;
1021 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
1023 const u16 *REG_TEMP_OFFSET;
1025 const u16 *REG_ALARM;
1026 const u16 *REG_BEEP;
1028 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
1029 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
1031 struct mutex update_lock;
1032 bool valid; /* true if following fields are valid */
1033 unsigned long last_updated; /* In jiffies */
1035 /* Register values */
1036 u8 bank; /* current register bank */
1037 u8 in_num; /* number of in inputs we have */
1038 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
1039 unsigned int rpm[NUM_FAN];
1040 u16 fan_min[NUM_FAN];
1041 u8 fan_pulses[NUM_FAN];
1042 u8 fan_div[NUM_FAN];
1044 u8 has_fan; /* some fan inputs can be disabled */
1045 u8 has_fan_min; /* some fans don't have min register */
1048 u8 num_temp_alarms; /* 2, 3, or 6 */
1049 u8 num_temp_beeps; /* 2, 3, or 6 */
1050 u8 temp_fixed_num; /* 3 or 6 */
1051 u8 temp_type[NUM_TEMP_FIXED];
1052 s8 temp_offset[NUM_TEMP_FIXED];
1053 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1054 * 3=temp_crit, 4=temp_lcrit */
1058 u8 pwm_num; /* number of pwm */
1059 u8 pwm_mode[NUM_FAN]; /* 1->DC variable voltage,
1060 * 0->PWM variable duty cycle
1062 enum pwm_enable pwm_enable[NUM_FAN];
1065 * 2->thermal cruise mode (also called SmartFan I)
1066 * 3->fan speed cruise mode
1068 * 5->enhanced variable thermal cruise (SmartFan IV)
1070 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1071 * [3]=pwm_max, [4]=pwm_step,
1072 * [5]=weight_duty_step, [6]=weight_duty_base
1075 u8 target_temp[NUM_FAN];
1076 u8 target_temp_mask;
1077 u32 target_speed[NUM_FAN];
1078 u32 target_speed_tolerance[NUM_FAN];
1079 u8 speed_tolerance_limit;
1081 u8 temp_tolerance[2][NUM_FAN];
1084 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
1086 /* Automatic fan speed control registers */
1088 u8 auto_pwm[NUM_FAN][7];
1089 u8 auto_temp[NUM_FAN][7];
1090 u8 pwm_temp_sel[NUM_FAN];
1091 u8 pwm_weight_temp_sel[NUM_FAN];
1092 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
1102 u16 have_temp_fixed;
1105 /* Remember extra register values over suspend/resume */
1112 struct nct6775_sio_data {
1117 #ifdef CONFIG_DEBUG_FS
1119 static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg);
1120 static u16 nct6775_read_value(struct nct6775_data *data, u16 reg);
1122 static const char *temp_attr_names[5] = {
1130 static int nct6775_seq_show(struct seq_file *s, void *v)
1132 struct device *dev = (struct device *)s->private;
1133 struct nct6775_data *data = dev_get_drvdata(dev);
1136 seq_printf(s, "Temperatures:\n");
1137 for (i = 0; i < NUM_TEMP; i++) {
1138 if (!(data->have_temp & BIT(i)))
1140 seq_printf(s, " temp%d [source %d, %s]:\n", i + 1,
1142 data->temp_label[data->temp_src[i]]);
1143 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1144 if (data->reg_temp[j][i]) {
1145 seq_printf(s, " %s: reg=0x%x val=0x%x cached 0x%x\n",
1147 data->reg_temp[j][i],
1148 nct6775_read_temp(data, data->reg_temp[j][i]),
1149 (u16)data->temp[j][i]);
1153 seq_printf(s, "Temperature sources:\n");
1154 for (i = 0; i < data->num_temp_alarms; i++) {
1155 seq_printf(s, " index %d register 0x%x: val=0x%x\n",
1156 i, data->REG_TEMP_SOURCE[i],
1157 nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f);
1162 static int nct6775_debug_open(struct inode *inode, struct file *file)
1164 return single_open(file, nct6775_seq_show, inode->i_private);
1167 static const struct file_operations nct6775_debug_operations = {
1168 .open = nct6775_debug_open,
1169 .llseek = seq_lseek,
1171 .release = single_release,
1174 static void nct6775_debugfs_exit(void *data)
1176 debugfs_remove_recursive(data);
1179 static int nct6775_debugfs_init(struct device *dev)
1181 struct dentry *rootdir;
1183 rootdir = debugfs_create_dir(dev_name(dev), NULL);
1187 devm_add_action(dev, nct6775_debugfs_exit, rootdir);
1189 debugfs_create_file("registers", S_IFREG | 0444, rootdir,
1190 dev, &nct6775_debug_operations);
1196 static int nct6775_debugfs_init(struct device *dev) { return 0; }
1199 struct sensor_device_template {
1200 struct device_attribute dev_attr;
1208 bool s2; /* true if both index and nr are used */
1211 struct sensor_device_attr_u {
1213 struct sensor_device_attribute a1;
1214 struct sensor_device_attribute_2 a2;
1219 #define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1220 .attr = {.name = _template, .mode = _mode }, \
1225 #define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1226 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1227 .u.index = _index, \
1230 #define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1232 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1233 .u.s.index = _index, \
1237 #define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1238 static struct sensor_device_template sensor_dev_template_##_name \
1239 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1242 #define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1244 static struct sensor_device_template sensor_dev_template_##_name \
1245 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1248 struct sensor_template_group {
1249 struct sensor_device_template **templates;
1250 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1254 static struct attribute_group *
1255 nct6775_create_attr_group(struct device *dev,
1256 const struct sensor_template_group *tg,
1259 struct attribute_group *group;
1260 struct sensor_device_attr_u *su;
1261 struct sensor_device_attribute *a;
1262 struct sensor_device_attribute_2 *a2;
1263 struct attribute **attrs;
1264 struct sensor_device_template **t;
1268 return ERR_PTR(-EINVAL);
1271 for (count = 0; *t; t++, count++)
1275 return ERR_PTR(-EINVAL);
1277 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1279 return ERR_PTR(-ENOMEM);
1281 attrs = devm_kzalloc(dev, sizeof(*attrs) * (repeat * count + 1),
1284 return ERR_PTR(-ENOMEM);
1286 su = devm_kzalloc(dev, sizeof(*su) * repeat * count,
1289 return ERR_PTR(-ENOMEM);
1291 group->attrs = attrs;
1292 group->is_visible = tg->is_visible;
1294 for (i = 0; i < repeat; i++) {
1296 while (*t != NULL) {
1297 snprintf(su->name, sizeof(su->name),
1298 (*t)->dev_attr.attr.name, tg->base + i);
1301 sysfs_attr_init(&a2->dev_attr.attr);
1302 a2->dev_attr.attr.name = su->name;
1303 a2->nr = (*t)->u.s.nr + i;
1304 a2->index = (*t)->u.s.index;
1305 a2->dev_attr.attr.mode =
1306 (*t)->dev_attr.attr.mode;
1307 a2->dev_attr.show = (*t)->dev_attr.show;
1308 a2->dev_attr.store = (*t)->dev_attr.store;
1309 *attrs = &a2->dev_attr.attr;
1312 sysfs_attr_init(&a->dev_attr.attr);
1313 a->dev_attr.attr.name = su->name;
1314 a->index = (*t)->u.index + i;
1315 a->dev_attr.attr.mode =
1316 (*t)->dev_attr.attr.mode;
1317 a->dev_attr.show = (*t)->dev_attr.show;
1318 a->dev_attr.store = (*t)->dev_attr.store;
1319 *attrs = &a->dev_attr.attr;
1330 static bool is_word_sized(struct nct6775_data *data, u16 reg)
1332 switch (data->kind) {
1334 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1335 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1336 reg == 0x111 || reg == 0x121 || reg == 0x131;
1338 return (((reg & 0xff00) == 0x100 ||
1339 (reg & 0xff00) == 0x200) &&
1340 ((reg & 0x00ff) == 0x50 ||
1341 (reg & 0x00ff) == 0x53 ||
1342 (reg & 0x00ff) == 0x55)) ||
1343 (reg & 0xfff0) == 0x630 ||
1344 reg == 0x640 || reg == 0x642 ||
1346 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1347 reg == 0x73 || reg == 0x75 || reg == 0x77;
1349 return (((reg & 0xff00) == 0x100 ||
1350 (reg & 0xff00) == 0x200) &&
1351 ((reg & 0x00ff) == 0x50 ||
1352 (reg & 0x00ff) == 0x53 ||
1353 (reg & 0x00ff) == 0x55)) ||
1354 (reg & 0xfff0) == 0x630 ||
1356 reg == 0x640 || reg == 0x642 ||
1357 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1358 reg == 0x73 || reg == 0x75 || reg == 0x77;
1365 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1366 ((reg & 0xfff0) == 0x4b0 && (reg & 0x000f) < 0x0b) ||
1368 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1369 reg == 0x640 || reg == 0x642 || reg == 0x64a ||
1370 reg == 0x64c || reg == 0x660 ||
1371 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1372 reg == 0x7b || reg == 0x7d;
1378 * On older chips, only registers 0x50-0x5f are banked.
1379 * On more recent chips, all registers are banked.
1380 * Assume that is the case and set the bank number for each access.
1381 * Cache the bank number so it only needs to be set if it changes.
1383 static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1387 if (data->bank != bank) {
1388 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1389 outb_p(bank, data->addr + DATA_REG_OFFSET);
1394 static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1396 int res, word_sized = is_word_sized(data, reg);
1398 nct6775_set_bank(data, reg);
1399 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1400 res = inb_p(data->addr + DATA_REG_OFFSET);
1402 outb_p((reg & 0xff) + 1,
1403 data->addr + ADDR_REG_OFFSET);
1404 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1409 static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1411 int word_sized = is_word_sized(data, reg);
1413 nct6775_set_bank(data, reg);
1414 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1416 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1417 outb_p((reg & 0xff) + 1,
1418 data->addr + ADDR_REG_OFFSET);
1420 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1424 /* We left-align 8-bit temperature values to make the code simpler */
1425 static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1429 res = nct6775_read_value(data, reg);
1430 if (!is_word_sized(data, reg))
1436 static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1438 if (!is_word_sized(data, reg))
1440 return nct6775_write_value(data, reg, value);
1443 /* This function assumes that the caller holds data->update_lock */
1444 static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1450 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1451 | (data->fan_div[0] & 0x7);
1452 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1455 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1456 | ((data->fan_div[1] << 4) & 0x70);
1457 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1460 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1461 | (data->fan_div[2] & 0x7);
1462 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1465 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1466 | ((data->fan_div[3] << 4) & 0x70);
1467 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1472 static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1474 if (data->kind == nct6775)
1475 nct6775_write_fan_div(data, nr);
1478 static void nct6775_update_fan_div(struct nct6775_data *data)
1482 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1483 data->fan_div[0] = i & 0x7;
1484 data->fan_div[1] = (i & 0x70) >> 4;
1485 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1486 data->fan_div[2] = i & 0x7;
1487 if (data->has_fan & BIT(3))
1488 data->fan_div[3] = (i & 0x70) >> 4;
1491 static void nct6775_update_fan_div_common(struct nct6775_data *data)
1493 if (data->kind == nct6775)
1494 nct6775_update_fan_div(data);
1497 static void nct6775_init_fan_div(struct nct6775_data *data)
1501 nct6775_update_fan_div_common(data);
1503 * For all fans, start with highest divider value if the divider
1504 * register is not initialized. This ensures that we get a
1505 * reading from the fan count register, even if it is not optimal.
1506 * We'll compute a better divider later on.
1508 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1509 if (!(data->has_fan & BIT(i)))
1511 if (data->fan_div[i] == 0) {
1512 data->fan_div[i] = 7;
1513 nct6775_write_fan_div_common(data, i);
1518 static void nct6775_init_fan_common(struct device *dev,
1519 struct nct6775_data *data)
1524 if (data->has_fan_div)
1525 nct6775_init_fan_div(data);
1528 * If fan_min is not set (0), set it to 0xff to disable it. This
1529 * prevents the unnecessary warning when fanX_min is reported as 0.
1531 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1532 if (data->has_fan_min & BIT(i)) {
1533 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1535 nct6775_write_value(data, data->REG_FAN_MIN[i],
1536 data->has_fan_div ? 0xff
1542 static void nct6775_select_fan_div(struct device *dev,
1543 struct nct6775_data *data, int nr, u16 reg)
1545 u8 fan_div = data->fan_div[nr];
1548 if (!data->has_fan_div)
1552 * If we failed to measure the fan speed, or the reported value is not
1553 * in the optimal range, and the clock divider can be modified,
1554 * let's try that for next time.
1556 if (reg == 0x00 && fan_div < 0x07)
1558 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1561 if (fan_div != data->fan_div[nr]) {
1562 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1563 nr + 1, div_from_reg(data->fan_div[nr]),
1564 div_from_reg(fan_div));
1566 /* Preserve min limit if possible */
1567 if (data->has_fan_min & BIT(nr)) {
1568 fan_min = data->fan_min[nr];
1569 if (fan_div > data->fan_div[nr]) {
1570 if (fan_min != 255 && fan_min > 1)
1573 if (fan_min != 255) {
1579 if (fan_min != data->fan_min[nr]) {
1580 data->fan_min[nr] = fan_min;
1581 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1585 data->fan_div[nr] = fan_div;
1586 nct6775_write_fan_div_common(data, nr);
1590 static void nct6775_update_pwm(struct device *dev)
1592 struct nct6775_data *data = dev_get_drvdata(dev);
1594 int fanmodecfg, reg;
1597 for (i = 0; i < data->pwm_num; i++) {
1598 if (!(data->has_pwm & BIT(i)))
1601 duty_is_dc = data->REG_PWM_MODE[i] &&
1602 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1603 & data->PWM_MODE_MASK[i]);
1604 data->pwm_mode[i] = !duty_is_dc;
1606 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1607 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1608 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1610 = nct6775_read_value(data,
1611 data->REG_PWM[j][i]);
1615 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1616 (fanmodecfg >> 4) & 7);
1618 if (!data->temp_tolerance[0][i] ||
1619 data->pwm_enable[i] != speed_cruise)
1620 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1621 if (!data->target_speed_tolerance[i] ||
1622 data->pwm_enable[i] == speed_cruise) {
1623 u8 t = fanmodecfg & 0x0f;
1625 if (data->REG_TOLERANCE_H) {
1626 t |= (nct6775_read_value(data,
1627 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1629 data->target_speed_tolerance[i] = t;
1632 data->temp_tolerance[1][i] =
1633 nct6775_read_value(data,
1634 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1636 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1637 data->pwm_temp_sel[i] = reg & 0x1f;
1638 /* If fan can stop, report floor as 0 */
1640 data->pwm[2][i] = 0;
1642 if (!data->REG_WEIGHT_TEMP_SEL[i])
1645 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1646 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1647 /* If weight is disabled, report weight source as 0 */
1648 if (j == 1 && !(reg & 0x80))
1649 data->pwm_weight_temp_sel[i] = 0;
1651 /* Weight temp data */
1652 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1653 data->weight_temp[j][i]
1654 = nct6775_read_value(data,
1655 data->REG_WEIGHT_TEMP[j][i]);
1660 static void nct6775_update_pwm_limits(struct device *dev)
1662 struct nct6775_data *data = dev_get_drvdata(dev);
1667 for (i = 0; i < data->pwm_num; i++) {
1668 if (!(data->has_pwm & BIT(i)))
1671 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1672 data->fan_time[j][i] =
1673 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1676 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1677 /* Update only in matching mode or if never updated */
1678 if (!data->target_temp[i] ||
1679 data->pwm_enable[i] == thermal_cruise)
1680 data->target_temp[i] = reg_t & data->target_temp_mask;
1681 if (!data->target_speed[i] ||
1682 data->pwm_enable[i] == speed_cruise) {
1683 if (data->REG_TOLERANCE_H) {
1684 reg_t |= (nct6775_read_value(data,
1685 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1687 data->target_speed[i] = reg_t;
1690 for (j = 0; j < data->auto_pwm_num; j++) {
1691 data->auto_pwm[i][j] =
1692 nct6775_read_value(data,
1693 NCT6775_AUTO_PWM(data, i, j));
1694 data->auto_temp[i][j] =
1695 nct6775_read_value(data,
1696 NCT6775_AUTO_TEMP(data, i, j));
1699 /* critical auto_pwm temperature data */
1700 data->auto_temp[i][data->auto_pwm_num] =
1701 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1703 switch (data->kind) {
1705 reg = nct6775_read_value(data,
1706 NCT6775_REG_CRITICAL_ENAB[i]);
1707 data->auto_pwm[i][data->auto_pwm_num] =
1708 (reg & 0x02) ? 0xff : 0x00;
1711 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1720 reg = nct6775_read_value(data,
1721 data->REG_CRITICAL_PWM_ENABLE[i]);
1722 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1723 reg = nct6775_read_value(data,
1724 data->REG_CRITICAL_PWM[i]);
1727 data->auto_pwm[i][data->auto_pwm_num] = reg;
1733 static struct nct6775_data *nct6775_update_device(struct device *dev)
1735 struct nct6775_data *data = dev_get_drvdata(dev);
1738 mutex_lock(&data->update_lock);
1740 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1742 /* Fan clock dividers */
1743 nct6775_update_fan_div_common(data);
1745 /* Measured voltages and limits */
1746 for (i = 0; i < data->in_num; i++) {
1747 if (!(data->have_in & BIT(i)))
1750 data->in[i][0] = nct6775_read_value(data,
1752 data->in[i][1] = nct6775_read_value(data,
1753 data->REG_IN_MINMAX[0][i]);
1754 data->in[i][2] = nct6775_read_value(data,
1755 data->REG_IN_MINMAX[1][i]);
1758 /* Measured fan speeds and limits */
1759 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1762 if (!(data->has_fan & BIT(i)))
1765 reg = nct6775_read_value(data, data->REG_FAN[i]);
1766 data->rpm[i] = data->fan_from_reg(reg,
1769 if (data->has_fan_min & BIT(i))
1770 data->fan_min[i] = nct6775_read_value(data,
1771 data->REG_FAN_MIN[i]);
1772 data->fan_pulses[i] =
1773 (nct6775_read_value(data, data->REG_FAN_PULSES[i])
1774 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1776 nct6775_select_fan_div(dev, data, i, reg);
1779 nct6775_update_pwm(dev);
1780 nct6775_update_pwm_limits(dev);
1782 /* Measured temperatures and limits */
1783 for (i = 0; i < NUM_TEMP; i++) {
1784 if (!(data->have_temp & BIT(i)))
1786 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1787 if (data->reg_temp[j][i])
1789 = nct6775_read_temp(data,
1790 data->reg_temp[j][i]);
1792 if (i >= NUM_TEMP_FIXED ||
1793 !(data->have_temp_fixed & BIT(i)))
1795 data->temp_offset[i]
1796 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1800 for (i = 0; i < NUM_REG_ALARM; i++) {
1803 if (!data->REG_ALARM[i])
1805 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1806 data->alarms |= ((u64)alarm) << (i << 3);
1810 for (i = 0; i < NUM_REG_BEEP; i++) {
1813 if (!data->REG_BEEP[i])
1815 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1816 data->beeps |= ((u64)beep) << (i << 3);
1819 data->last_updated = jiffies;
1823 mutex_unlock(&data->update_lock);
1828 * Sysfs callback functions
1831 show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1833 struct nct6775_data *data = nct6775_update_device(dev);
1834 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1835 int index = sattr->index;
1838 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1842 store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1845 struct nct6775_data *data = dev_get_drvdata(dev);
1846 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1847 int index = sattr->index;
1852 err = kstrtoul(buf, 10, &val);
1855 mutex_lock(&data->update_lock);
1856 data->in[nr][index] = in_to_reg(val, nr);
1857 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1858 data->in[nr][index]);
1859 mutex_unlock(&data->update_lock);
1864 show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1866 struct nct6775_data *data = nct6775_update_device(dev);
1867 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1868 int nr = data->ALARM_BITS[sattr->index];
1870 return sprintf(buf, "%u\n",
1871 (unsigned int)((data->alarms >> nr) & 0x01));
1874 static int find_temp_source(struct nct6775_data *data, int index, int count)
1876 int source = data->temp_src[index];
1879 for (nr = 0; nr < count; nr++) {
1882 src = nct6775_read_value(data,
1883 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1891 show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1893 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1894 struct nct6775_data *data = nct6775_update_device(dev);
1895 unsigned int alarm = 0;
1899 * For temperatures, there is no fixed mapping from registers to alarm
1900 * bits. Alarm bits are determined by the temperature source mapping.
1902 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1904 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1906 alarm = (data->alarms >> bit) & 0x01;
1908 return sprintf(buf, "%u\n", alarm);
1912 show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1914 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1915 struct nct6775_data *data = nct6775_update_device(dev);
1916 int nr = data->BEEP_BITS[sattr->index];
1918 return sprintf(buf, "%u\n",
1919 (unsigned int)((data->beeps >> nr) & 0x01));
1923 store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1926 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1927 struct nct6775_data *data = dev_get_drvdata(dev);
1928 int nr = data->BEEP_BITS[sattr->index];
1929 int regindex = nr >> 3;
1933 err = kstrtoul(buf, 10, &val);
1939 mutex_lock(&data->update_lock);
1941 data->beeps |= (1ULL << nr);
1943 data->beeps &= ~(1ULL << nr);
1944 nct6775_write_value(data, data->REG_BEEP[regindex],
1945 (data->beeps >> (regindex << 3)) & 0xff);
1946 mutex_unlock(&data->update_lock);
1951 show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1953 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1954 struct nct6775_data *data = nct6775_update_device(dev);
1955 unsigned int beep = 0;
1959 * For temperatures, there is no fixed mapping from registers to beep
1960 * enable bits. Beep enable bits are determined by the temperature
1963 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1965 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1967 beep = (data->beeps >> bit) & 0x01;
1969 return sprintf(buf, "%u\n", beep);
1973 store_temp_beep(struct device *dev, struct device_attribute *attr,
1974 const char *buf, size_t count)
1976 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1977 struct nct6775_data *data = dev_get_drvdata(dev);
1978 int nr, bit, regindex;
1982 err = kstrtoul(buf, 10, &val);
1988 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1992 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1993 regindex = bit >> 3;
1995 mutex_lock(&data->update_lock);
1997 data->beeps |= (1ULL << bit);
1999 data->beeps &= ~(1ULL << bit);
2000 nct6775_write_value(data, data->REG_BEEP[regindex],
2001 (data->beeps >> (regindex << 3)) & 0xff);
2002 mutex_unlock(&data->update_lock);
2007 static umode_t nct6775_in_is_visible(struct kobject *kobj,
2008 struct attribute *attr, int index)
2010 struct device *dev = container_of(kobj, struct device, kobj);
2011 struct nct6775_data *data = dev_get_drvdata(dev);
2012 int in = index / 5; /* voltage index */
2014 if (!(data->have_in & BIT(in)))
2020 SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
2021 SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
2022 SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
2024 SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
2025 store_in_reg, 0, 1);
2026 SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
2027 store_in_reg, 0, 2);
2030 * nct6775_in_is_visible uses the index into the following array
2031 * to determine if attributes should be created or not.
2032 * Any change in order or content must be matched.
2034 static struct sensor_device_template *nct6775_attributes_in_template[] = {
2035 &sensor_dev_template_in_input,
2036 &sensor_dev_template_in_alarm,
2037 &sensor_dev_template_in_beep,
2038 &sensor_dev_template_in_min,
2039 &sensor_dev_template_in_max,
2043 static const struct sensor_template_group nct6775_in_template_group = {
2044 .templates = nct6775_attributes_in_template,
2045 .is_visible = nct6775_in_is_visible,
2049 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
2051 struct nct6775_data *data = nct6775_update_device(dev);
2052 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2053 int nr = sattr->index;
2055 return sprintf(buf, "%d\n", data->rpm[nr]);
2059 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
2061 struct nct6775_data *data = nct6775_update_device(dev);
2062 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2063 int nr = sattr->index;
2065 return sprintf(buf, "%d\n",
2066 data->fan_from_reg_min(data->fan_min[nr],
2067 data->fan_div[nr]));
2071 show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
2073 struct nct6775_data *data = nct6775_update_device(dev);
2074 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2075 int nr = sattr->index;
2077 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
2081 store_fan_min(struct device *dev, struct device_attribute *attr,
2082 const char *buf, size_t count)
2084 struct nct6775_data *data = dev_get_drvdata(dev);
2085 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2086 int nr = sattr->index;
2092 err = kstrtoul(buf, 10, &val);
2096 mutex_lock(&data->update_lock);
2097 if (!data->has_fan_div) {
2098 /* NCT6776F or NCT6779D; we know this is a 13 bit register */
2104 val = 1350000U / val;
2105 val = (val & 0x1f) | ((val << 3) & 0xff00);
2107 data->fan_min[nr] = val;
2108 goto write_min; /* Leave fan divider alone */
2111 /* No min limit, alarm disabled */
2112 data->fan_min[nr] = 255;
2113 new_div = data->fan_div[nr]; /* No change */
2114 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
2117 reg = 1350000U / val;
2118 if (reg >= 128 * 255) {
2120 * Speed below this value cannot possibly be represented,
2121 * even with the highest divider (128)
2123 data->fan_min[nr] = 254;
2124 new_div = 7; /* 128 == BIT(7) */
2126 "fan%u low limit %lu below minimum %u, set to minimum\n",
2127 nr + 1, val, data->fan_from_reg_min(254, 7));
2130 * Speed above this value cannot possibly be represented,
2131 * even with the lowest divider (1)
2133 data->fan_min[nr] = 1;
2134 new_div = 0; /* 1 == BIT(0) */
2136 "fan%u low limit %lu above maximum %u, set to maximum\n",
2137 nr + 1, val, data->fan_from_reg_min(1, 0));
2140 * Automatically pick the best divider, i.e. the one such
2141 * that the min limit will correspond to a register value
2142 * in the 96..192 range
2145 while (reg > 192 && new_div < 7) {
2149 data->fan_min[nr] = reg;
2154 * Write both the fan clock divider (if it changed) and the new
2155 * fan min (unconditionally)
2157 if (new_div != data->fan_div[nr]) {
2158 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2159 nr + 1, div_from_reg(data->fan_div[nr]),
2160 div_from_reg(new_div));
2161 data->fan_div[nr] = new_div;
2162 nct6775_write_fan_div_common(data, nr);
2163 /* Give the chip time to sample a new speed value */
2164 data->last_updated = jiffies;
2168 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2169 mutex_unlock(&data->update_lock);
2175 show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2177 struct nct6775_data *data = nct6775_update_device(dev);
2178 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2179 int p = data->fan_pulses[sattr->index];
2181 return sprintf(buf, "%d\n", p ? : 4);
2185 store_fan_pulses(struct device *dev, struct device_attribute *attr,
2186 const char *buf, size_t count)
2188 struct nct6775_data *data = dev_get_drvdata(dev);
2189 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2190 int nr = sattr->index;
2195 err = kstrtoul(buf, 10, &val);
2202 mutex_lock(&data->update_lock);
2203 data->fan_pulses[nr] = val & 3;
2204 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2205 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2206 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2207 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2208 mutex_unlock(&data->update_lock);
2213 static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2214 struct attribute *attr, int index)
2216 struct device *dev = container_of(kobj, struct device, kobj);
2217 struct nct6775_data *data = dev_get_drvdata(dev);
2218 int fan = index / 6; /* fan index */
2219 int nr = index % 6; /* attribute index */
2221 if (!(data->has_fan & BIT(fan)))
2224 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2226 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2228 if (nr == 3 && !data->REG_FAN_PULSES[fan])
2230 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2232 if (nr == 5 && data->kind != nct6775)
2238 SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2239 SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2241 SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2242 store_beep, FAN_ALARM_BASE);
2243 SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2244 store_fan_pulses, 0);
2245 SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2247 SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2250 * nct6775_fan_is_visible uses the index into the following array
2251 * to determine if attributes should be created or not.
2252 * Any change in order or content must be matched.
2254 static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2255 &sensor_dev_template_fan_input,
2256 &sensor_dev_template_fan_alarm, /* 1 */
2257 &sensor_dev_template_fan_beep, /* 2 */
2258 &sensor_dev_template_fan_pulses,
2259 &sensor_dev_template_fan_min, /* 4 */
2260 &sensor_dev_template_fan_div, /* 5 */
2264 static const struct sensor_template_group nct6775_fan_template_group = {
2265 .templates = nct6775_attributes_fan_template,
2266 .is_visible = nct6775_fan_is_visible,
2271 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2273 struct nct6775_data *data = nct6775_update_device(dev);
2274 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2275 int nr = sattr->index;
2277 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2281 show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2283 struct nct6775_data *data = nct6775_update_device(dev);
2284 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2286 int index = sattr->index;
2288 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2292 store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2295 struct nct6775_data *data = dev_get_drvdata(dev);
2296 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2298 int index = sattr->index;
2302 err = kstrtol(buf, 10, &val);
2306 mutex_lock(&data->update_lock);
2307 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2308 nct6775_write_temp(data, data->reg_temp[index][nr],
2309 data->temp[index][nr]);
2310 mutex_unlock(&data->update_lock);
2315 show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2317 struct nct6775_data *data = nct6775_update_device(dev);
2318 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2320 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2324 store_temp_offset(struct device *dev, struct device_attribute *attr,
2325 const char *buf, size_t count)
2327 struct nct6775_data *data = dev_get_drvdata(dev);
2328 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2329 int nr = sattr->index;
2333 err = kstrtol(buf, 10, &val);
2337 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2339 mutex_lock(&data->update_lock);
2340 data->temp_offset[nr] = val;
2341 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2342 mutex_unlock(&data->update_lock);
2348 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2350 struct nct6775_data *data = nct6775_update_device(dev);
2351 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2352 int nr = sattr->index;
2354 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2358 store_temp_type(struct device *dev, struct device_attribute *attr,
2359 const char *buf, size_t count)
2361 struct nct6775_data *data = nct6775_update_device(dev);
2362 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2363 int nr = sattr->index;
2366 u8 vbat, diode, vbit, dbit;
2368 err = kstrtoul(buf, 10, &val);
2372 if (val != 1 && val != 3 && val != 4)
2375 mutex_lock(&data->update_lock);
2377 data->temp_type[nr] = val;
2379 dbit = data->DIODE_MASK << nr;
2380 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2381 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2383 case 1: /* CPU diode (diode, current mode) */
2387 case 3: /* diode, voltage mode */
2390 case 4: /* thermistor */
2393 nct6775_write_value(data, data->REG_VBAT, vbat);
2394 nct6775_write_value(data, data->REG_DIODE, diode);
2396 mutex_unlock(&data->update_lock);
2400 static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2401 struct attribute *attr, int index)
2403 struct device *dev = container_of(kobj, struct device, kobj);
2404 struct nct6775_data *data = dev_get_drvdata(dev);
2405 int temp = index / 10; /* temp index */
2406 int nr = index % 10; /* attribute index */
2408 if (!(data->have_temp & BIT(temp)))
2411 if (nr == 1 && !data->temp_label)
2414 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2415 return 0; /* alarm */
2417 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2418 return 0; /* beep */
2420 if (nr == 4 && !data->reg_temp[1][temp]) /* max */
2423 if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */
2426 if (nr == 6 && !data->reg_temp[3][temp]) /* crit */
2429 if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */
2432 /* offset and type only apply to fixed sensors */
2433 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2439 SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2440 SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2441 SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2443 SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2444 show_temp, store_temp, 0, 2);
2445 SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2447 SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2449 SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2450 show_temp_offset, store_temp_offset, 0);
2451 SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2452 store_temp_type, 0);
2453 SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2454 SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2455 store_temp_beep, 0);
2458 * nct6775_temp_is_visible uses the index into the following array
2459 * to determine if attributes should be created or not.
2460 * Any change in order or content must be matched.
2462 static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2463 &sensor_dev_template_temp_input,
2464 &sensor_dev_template_temp_label,
2465 &sensor_dev_template_temp_alarm, /* 2 */
2466 &sensor_dev_template_temp_beep, /* 3 */
2467 &sensor_dev_template_temp_max, /* 4 */
2468 &sensor_dev_template_temp_max_hyst, /* 5 */
2469 &sensor_dev_template_temp_crit, /* 6 */
2470 &sensor_dev_template_temp_lcrit, /* 7 */
2471 &sensor_dev_template_temp_offset, /* 8 */
2472 &sensor_dev_template_temp_type, /* 9 */
2476 static const struct sensor_template_group nct6775_temp_template_group = {
2477 .templates = nct6775_attributes_temp_template,
2478 .is_visible = nct6775_temp_is_visible,
2483 show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2485 struct nct6775_data *data = nct6775_update_device(dev);
2486 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2488 return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
2492 store_pwm_mode(struct device *dev, struct device_attribute *attr,
2493 const char *buf, size_t count)
2495 struct nct6775_data *data = dev_get_drvdata(dev);
2496 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2497 int nr = sattr->index;
2502 err = kstrtoul(buf, 10, &val);
2509 /* Setting DC mode (0) is not supported for all chips/channels */
2510 if (data->REG_PWM_MODE[nr] == 0) {
2516 mutex_lock(&data->update_lock);
2517 data->pwm_mode[nr] = val;
2518 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2519 reg &= ~data->PWM_MODE_MASK[nr];
2521 reg |= data->PWM_MODE_MASK[nr];
2522 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2523 mutex_unlock(&data->update_lock);
2528 show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2530 struct nct6775_data *data = nct6775_update_device(dev);
2531 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2533 int index = sattr->index;
2537 * For automatic fan control modes, show current pwm readings.
2538 * Otherwise, show the configured value.
2540 if (index == 0 && data->pwm_enable[nr] > manual)
2541 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2543 pwm = data->pwm[index][nr];
2545 return sprintf(buf, "%d\n", pwm);
2549 store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2552 struct nct6775_data *data = dev_get_drvdata(dev);
2553 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2555 int index = sattr->index;
2557 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2559 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2563 err = kstrtoul(buf, 10, &val);
2566 val = clamp_val(val, minval[index], maxval[index]);
2568 mutex_lock(&data->update_lock);
2569 data->pwm[index][nr] = val;
2570 nct6775_write_value(data, data->REG_PWM[index][nr], val);
2571 if (index == 2) { /* floor: disable if val == 0 */
2572 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2576 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2578 mutex_unlock(&data->update_lock);
2582 /* Returns 0 if OK, -EINVAL otherwise */
2583 static int check_trip_points(struct nct6775_data *data, int nr)
2587 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2588 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2591 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2592 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2595 /* validate critical temperature and pwm if enabled (pwm > 0) */
2596 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2597 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2598 data->auto_temp[nr][data->auto_pwm_num] ||
2599 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2600 data->auto_pwm[nr][data->auto_pwm_num])
2606 static void pwm_update_registers(struct nct6775_data *data, int nr)
2610 switch (data->pwm_enable[nr]) {
2615 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2616 reg = (reg & ~data->tolerance_mask) |
2617 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2618 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2619 nct6775_write_value(data, data->REG_TARGET[nr],
2620 data->target_speed[nr] & 0xff);
2621 if (data->REG_TOLERANCE_H) {
2622 reg = (data->target_speed[nr] >> 8) & 0x0f;
2623 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2624 nct6775_write_value(data,
2625 data->REG_TOLERANCE_H[nr],
2629 case thermal_cruise:
2630 nct6775_write_value(data, data->REG_TARGET[nr],
2631 data->target_temp[nr]);
2634 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2635 reg = (reg & ~data->tolerance_mask) |
2636 data->temp_tolerance[0][nr];
2637 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2643 show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2645 struct nct6775_data *data = nct6775_update_device(dev);
2646 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2648 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2652 store_pwm_enable(struct device *dev, struct device_attribute *attr,
2653 const char *buf, size_t count)
2655 struct nct6775_data *data = dev_get_drvdata(dev);
2656 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2657 int nr = sattr->index;
2662 err = kstrtoul(buf, 10, &val);
2669 if (val == sf3 && data->kind != nct6775)
2672 if (val == sf4 && check_trip_points(data, nr)) {
2673 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2674 dev_err(dev, "Adjust trip points and try again\n");
2678 mutex_lock(&data->update_lock);
2679 data->pwm_enable[nr] = val;
2682 * turn off pwm control: select manual mode, set pwm to maximum
2684 data->pwm[0][nr] = 255;
2685 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2687 pwm_update_registers(data, nr);
2688 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2690 reg |= pwm_enable_to_reg(val) << 4;
2691 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2692 mutex_unlock(&data->update_lock);
2697 show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2701 for (i = 0; i < NUM_TEMP; i++) {
2702 if (!(data->have_temp & BIT(i)))
2704 if (src == data->temp_src[i]) {
2710 return sprintf(buf, "%d\n", sel);
2714 show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2716 struct nct6775_data *data = nct6775_update_device(dev);
2717 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2718 int index = sattr->index;
2720 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2724 store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2725 const char *buf, size_t count)
2727 struct nct6775_data *data = nct6775_update_device(dev);
2728 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2729 int nr = sattr->index;
2733 err = kstrtoul(buf, 10, &val);
2736 if (val == 0 || val > NUM_TEMP)
2738 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2741 mutex_lock(&data->update_lock);
2742 src = data->temp_src[val - 1];
2743 data->pwm_temp_sel[nr] = src;
2744 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2747 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2748 mutex_unlock(&data->update_lock);
2754 show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2757 struct nct6775_data *data = nct6775_update_device(dev);
2758 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2759 int index = sattr->index;
2761 return show_pwm_temp_sel_common(data, buf,
2762 data->pwm_weight_temp_sel[index]);
2766 store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2767 const char *buf, size_t count)
2769 struct nct6775_data *data = nct6775_update_device(dev);
2770 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2771 int nr = sattr->index;
2775 err = kstrtoul(buf, 10, &val);
2780 if (val && (!(data->have_temp & BIT(val - 1)) ||
2781 !data->temp_src[val - 1]))
2784 mutex_lock(&data->update_lock);
2786 src = data->temp_src[val - 1];
2787 data->pwm_weight_temp_sel[nr] = src;
2788 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2790 reg |= (src | 0x80);
2791 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2793 data->pwm_weight_temp_sel[nr] = 0;
2794 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2796 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2798 mutex_unlock(&data->update_lock);
2804 show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2806 struct nct6775_data *data = nct6775_update_device(dev);
2807 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2809 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2813 store_target_temp(struct device *dev, struct device_attribute *attr,
2814 const char *buf, size_t count)
2816 struct nct6775_data *data = dev_get_drvdata(dev);
2817 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2818 int nr = sattr->index;
2822 err = kstrtoul(buf, 10, &val);
2826 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2827 data->target_temp_mask);
2829 mutex_lock(&data->update_lock);
2830 data->target_temp[nr] = val;
2831 pwm_update_registers(data, nr);
2832 mutex_unlock(&data->update_lock);
2837 show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2839 struct nct6775_data *data = nct6775_update_device(dev);
2840 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2841 int nr = sattr->index;
2843 return sprintf(buf, "%d\n",
2844 fan_from_reg16(data->target_speed[nr],
2845 data->fan_div[nr]));
2849 store_target_speed(struct device *dev, struct device_attribute *attr,
2850 const char *buf, size_t count)
2852 struct nct6775_data *data = dev_get_drvdata(dev);
2853 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2854 int nr = sattr->index;
2859 err = kstrtoul(buf, 10, &val);
2863 val = clamp_val(val, 0, 1350000U);
2864 speed = fan_to_reg(val, data->fan_div[nr]);
2866 mutex_lock(&data->update_lock);
2867 data->target_speed[nr] = speed;
2868 pwm_update_registers(data, nr);
2869 mutex_unlock(&data->update_lock);
2874 show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2877 struct nct6775_data *data = nct6775_update_device(dev);
2878 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2880 int index = sattr->index;
2882 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2886 store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2887 const char *buf, size_t count)
2889 struct nct6775_data *data = dev_get_drvdata(dev);
2890 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2892 int index = sattr->index;
2896 err = kstrtoul(buf, 10, &val);
2900 /* Limit tolerance as needed */
2901 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2903 mutex_lock(&data->update_lock);
2904 data->temp_tolerance[index][nr] = val;
2906 pwm_update_registers(data, nr);
2908 nct6775_write_value(data,
2909 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2911 mutex_unlock(&data->update_lock);
2916 * Fan speed tolerance is a tricky beast, since the associated register is
2917 * a tick counter, but the value is reported and configured as rpm.
2918 * Compute resulting low and high rpm values and report the difference.
2921 show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2924 struct nct6775_data *data = nct6775_update_device(dev);
2925 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2926 int nr = sattr->index;
2927 int low = data->target_speed[nr] - data->target_speed_tolerance[nr];
2928 int high = data->target_speed[nr] + data->target_speed_tolerance[nr];
2938 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2939 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2941 return sprintf(buf, "%d\n", tolerance);
2945 store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2946 const char *buf, size_t count)
2948 struct nct6775_data *data = dev_get_drvdata(dev);
2949 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2950 int nr = sattr->index;
2955 err = kstrtoul(buf, 10, &val);
2959 high = fan_from_reg16(data->target_speed[nr],
2960 data->fan_div[nr]) + val;
2961 low = fan_from_reg16(data->target_speed[nr],
2962 data->fan_div[nr]) - val;
2968 val = (fan_to_reg(low, data->fan_div[nr]) -
2969 fan_to_reg(high, data->fan_div[nr])) / 2;
2971 /* Limit tolerance as needed */
2972 val = clamp_val(val, 0, data->speed_tolerance_limit);
2974 mutex_lock(&data->update_lock);
2975 data->target_speed_tolerance[nr] = val;
2976 pwm_update_registers(data, nr);
2977 mutex_unlock(&data->update_lock);
2981 SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2982 SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2984 SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2985 store_pwm_enable, 0);
2986 SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2987 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2988 SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2989 show_target_temp, store_target_temp, 0);
2990 SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2991 show_target_speed, store_target_speed, 0);
2992 SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2993 show_speed_tolerance, store_speed_tolerance, 0);
2995 /* Smart Fan registers */
2998 show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
3000 struct nct6775_data *data = nct6775_update_device(dev);
3001 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3003 int index = sattr->index;
3005 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
3009 store_weight_temp(struct device *dev, struct device_attribute *attr,
3010 const char *buf, size_t count)
3012 struct nct6775_data *data = dev_get_drvdata(dev);
3013 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3015 int index = sattr->index;
3019 err = kstrtoul(buf, 10, &val);
3023 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
3025 mutex_lock(&data->update_lock);
3026 data->weight_temp[index][nr] = val;
3027 nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
3028 mutex_unlock(&data->update_lock);
3032 SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
3033 show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
3034 SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
3035 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
3036 SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
3037 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
3038 SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
3039 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
3040 SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
3041 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
3042 SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
3043 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
3046 show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
3048 struct nct6775_data *data = nct6775_update_device(dev);
3049 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3051 int index = sattr->index;
3053 return sprintf(buf, "%d\n",
3054 step_time_from_reg(data->fan_time[index][nr],
3055 data->pwm_mode[nr]));
3059 store_fan_time(struct device *dev, struct device_attribute *attr,
3060 const char *buf, size_t count)
3062 struct nct6775_data *data = dev_get_drvdata(dev);
3063 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3065 int index = sattr->index;
3069 err = kstrtoul(buf, 10, &val);
3073 val = step_time_to_reg(val, data->pwm_mode[nr]);
3074 mutex_lock(&data->update_lock);
3075 data->fan_time[index][nr] = val;
3076 nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
3077 mutex_unlock(&data->update_lock);
3081 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)
3083 show_name(struct device *dev, struct device_attribute *attr, char *buf)
3085 struct nct6775_data *data = dev_get_drvdata(dev);
3087 return sprintf(buf, "%s\n", data->name);
3090 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
3094 show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
3096 struct nct6775_data *data = nct6775_update_device(dev);
3097 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3099 return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
3103 store_auto_pwm(struct device *dev, struct device_attribute *attr,
3104 const char *buf, size_t count)
3106 struct nct6775_data *data = dev_get_drvdata(dev);
3107 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3109 int point = sattr->index;
3114 err = kstrtoul(buf, 10, &val);
3120 if (point == data->auto_pwm_num) {
3121 if (data->kind != nct6775 && !val)
3123 if (data->kind != nct6779 && val)
3127 mutex_lock(&data->update_lock);
3128 data->auto_pwm[nr][point] = val;
3129 if (point < data->auto_pwm_num) {
3130 nct6775_write_value(data,
3131 NCT6775_AUTO_PWM(data, nr, point),
3132 data->auto_pwm[nr][point]);
3134 switch (data->kind) {
3136 /* disable if needed (pwm == 0) */
3137 reg = nct6775_read_value(data,
3138 NCT6775_REG_CRITICAL_ENAB[nr]);
3143 nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
3147 break; /* always enabled, nothing to do */
3155 nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
3157 reg = nct6775_read_value(data,
3158 data->REG_CRITICAL_PWM_ENABLE[nr]);
3160 reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
3162 reg |= data->CRITICAL_PWM_ENABLE_MASK;
3163 nct6775_write_value(data,
3164 data->REG_CRITICAL_PWM_ENABLE[nr],
3169 mutex_unlock(&data->update_lock);
3174 show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3176 struct nct6775_data *data = nct6775_update_device(dev);
3177 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3179 int point = sattr->index;
3182 * We don't know for sure if the temperature is signed or unsigned.
3183 * Assume it is unsigned.
3185 return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3189 store_auto_temp(struct device *dev, struct device_attribute *attr,
3190 const char *buf, size_t count)
3192 struct nct6775_data *data = dev_get_drvdata(dev);
3193 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3195 int point = sattr->index;
3199 err = kstrtoul(buf, 10, &val);
3205 mutex_lock(&data->update_lock);
3206 data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3207 if (point < data->auto_pwm_num) {
3208 nct6775_write_value(data,
3209 NCT6775_AUTO_TEMP(data, nr, point),
3210 data->auto_temp[nr][point]);
3212 nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3213 data->auto_temp[nr][point]);
3215 mutex_unlock(&data->update_lock);
3219 static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3220 struct attribute *attr, int index)
3222 struct device *dev = container_of(kobj, struct device, kobj);
3223 struct nct6775_data *data = dev_get_drvdata(dev);
3224 int pwm = index / 36; /* pwm index */
3225 int nr = index % 36; /* attribute index */
3227 if (!(data->has_pwm & BIT(pwm)))
3230 if ((nr >= 14 && nr <= 18) || nr == 21) /* weight */
3231 if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3233 if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */
3235 if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */
3237 if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */
3240 if (nr >= 22 && nr <= 35) { /* auto point */
3241 int api = (nr - 22) / 2; /* auto point index */
3243 if (api > data->auto_pwm_num)
3249 SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3250 show_fan_time, store_fan_time, 0, 0);
3251 SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3252 show_fan_time, store_fan_time, 0, 1);
3253 SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3254 show_fan_time, store_fan_time, 0, 2);
3255 SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3257 SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3259 SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3260 show_temp_tolerance, store_temp_tolerance, 0, 0);
3261 SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3262 S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3265 SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3268 SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3271 SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3272 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3273 SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3274 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3276 SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3277 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3278 SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3279 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3281 SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3282 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3283 SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3284 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3286 SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3287 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3288 SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3289 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3291 SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3292 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3293 SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3294 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3296 SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3297 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3298 SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3299 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3301 SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3302 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3303 SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3304 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3307 * nct6775_pwm_is_visible uses the index into the following array
3308 * to determine if attributes should be created or not.
3309 * Any change in order or content must be matched.
3311 static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3312 &sensor_dev_template_pwm,
3313 &sensor_dev_template_pwm_mode,
3314 &sensor_dev_template_pwm_enable,
3315 &sensor_dev_template_pwm_temp_sel,
3316 &sensor_dev_template_pwm_temp_tolerance,
3317 &sensor_dev_template_pwm_crit_temp_tolerance,
3318 &sensor_dev_template_pwm_target_temp,
3319 &sensor_dev_template_fan_target,
3320 &sensor_dev_template_fan_tolerance,
3321 &sensor_dev_template_pwm_stop_time,
3322 &sensor_dev_template_pwm_step_up_time,
3323 &sensor_dev_template_pwm_step_down_time,
3324 &sensor_dev_template_pwm_start,
3325 &sensor_dev_template_pwm_floor,
3326 &sensor_dev_template_pwm_weight_temp_sel, /* 14 */
3327 &sensor_dev_template_pwm_weight_temp_step,
3328 &sensor_dev_template_pwm_weight_temp_step_tol,
3329 &sensor_dev_template_pwm_weight_temp_step_base,
3330 &sensor_dev_template_pwm_weight_duty_step, /* 18 */
3331 &sensor_dev_template_pwm_max, /* 19 */
3332 &sensor_dev_template_pwm_step, /* 20 */
3333 &sensor_dev_template_pwm_weight_duty_base, /* 21 */
3334 &sensor_dev_template_pwm_auto_point1_pwm, /* 22 */
3335 &sensor_dev_template_pwm_auto_point1_temp,
3336 &sensor_dev_template_pwm_auto_point2_pwm,
3337 &sensor_dev_template_pwm_auto_point2_temp,
3338 &sensor_dev_template_pwm_auto_point3_pwm,
3339 &sensor_dev_template_pwm_auto_point3_temp,
3340 &sensor_dev_template_pwm_auto_point4_pwm,
3341 &sensor_dev_template_pwm_auto_point4_temp,
3342 &sensor_dev_template_pwm_auto_point5_pwm,
3343 &sensor_dev_template_pwm_auto_point5_temp,
3344 &sensor_dev_template_pwm_auto_point6_pwm,
3345 &sensor_dev_template_pwm_auto_point6_temp,
3346 &sensor_dev_template_pwm_auto_point7_pwm,
3347 &sensor_dev_template_pwm_auto_point7_temp, /* 35 */
3352 static const struct sensor_template_group nct6775_pwm_template_group = {
3353 .templates = nct6775_attributes_pwm_template,
3354 .is_visible = nct6775_pwm_is_visible,
3359 cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
3361 struct nct6775_data *data = dev_get_drvdata(dev);
3363 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3366 static DEVICE_ATTR_RO(cpu0_vid);
3368 /* Case open detection */
3371 clear_caseopen(struct device *dev, struct device_attribute *attr,
3372 const char *buf, size_t count)
3374 struct nct6775_data *data = dev_get_drvdata(dev);
3375 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3380 if (kstrtoul(buf, 10, &val) || val != 0)
3383 mutex_lock(&data->update_lock);
3386 * Use CR registers to clear caseopen status.
3387 * The CR registers are the same for all chips, and not all chips
3388 * support clearing the caseopen status through "regular" registers.
3390 ret = superio_enter(data->sioreg);
3396 superio_select(data->sioreg, NCT6775_LD_ACPI);
3397 reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
3398 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3399 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3400 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3401 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3402 superio_exit(data->sioreg);
3404 data->valid = false; /* Force cache refresh */
3406 mutex_unlock(&data->update_lock);
3410 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3411 clear_caseopen, INTRUSION_ALARM_BASE);
3412 static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3413 clear_caseopen, INTRUSION_ALARM_BASE + 1);
3414 static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3415 store_beep, INTRUSION_ALARM_BASE);
3416 static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3417 store_beep, INTRUSION_ALARM_BASE + 1);
3418 static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3419 store_beep, BEEP_ENABLE_BASE);
3421 static umode_t nct6775_other_is_visible(struct kobject *kobj,
3422 struct attribute *attr, int index)
3424 struct device *dev = container_of(kobj, struct device, kobj);
3425 struct nct6775_data *data = dev_get_drvdata(dev);
3427 if (index == 0 && !data->have_vid)
3430 if (index == 1 || index == 2) {
3431 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
3435 if (index == 3 || index == 4) {
3436 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
3444 * nct6775_other_is_visible uses the index into the following array
3445 * to determine if attributes should be created or not.
3446 * Any change in order or content must be matched.
3448 static struct attribute *nct6775_attributes_other[] = {
3449 &dev_attr_cpu0_vid.attr, /* 0 */
3450 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */
3451 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */
3452 &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */
3453 &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */
3454 &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */
3455 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)
3456 &dev_attr_name.attr,
3461 static const struct attribute_group nct6775_group_other = {
3462 .attrs = nct6775_attributes_other,
3463 .is_visible = nct6775_other_is_visible,
3466 static inline void nct6775_init_device(struct nct6775_data *data)
3471 /* Start monitoring if needed */
3472 if (data->REG_CONFIG) {
3473 tmp = nct6775_read_value(data, data->REG_CONFIG);
3475 nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3478 /* Enable temperature sensors if needed */
3479 for (i = 0; i < NUM_TEMP; i++) {
3480 if (!(data->have_temp & BIT(i)))
3482 if (!data->reg_temp_config[i])
3484 tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3486 nct6775_write_value(data, data->reg_temp_config[i],
3490 /* Enable VBAT monitoring if needed */
3491 tmp = nct6775_read_value(data, data->REG_VBAT);
3493 nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
3495 diode = nct6775_read_value(data, data->REG_DIODE);
3497 for (i = 0; i < data->temp_fixed_num; i++) {
3498 if (!(data->have_temp_fixed & BIT(i)))
3500 if ((tmp & (data->DIODE_MASK << i))) /* diode */
3502 = 3 - ((diode >> i) & data->DIODE_MASK);
3503 else /* thermistor */
3504 data->temp_type[i] = 4;
3509 nct6775_check_fan_inputs(struct nct6775_data *data)
3511 bool fan3pin = false, fan4pin = false, fan4min = false;
3512 bool fan5pin = false, fan6pin = false, fan7pin = false;
3513 bool pwm3pin = false, pwm4pin = false, pwm5pin = false;
3514 bool pwm6pin = false, pwm7pin = false;
3515 int sioreg = data->sioreg;
3518 /* Store SIO_REG_ENABLE for use during resume */
3519 superio_select(sioreg, NCT6775_LD_HWM);
3520 data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3522 /* fan4 and fan5 share some pins with the GPIO and serial flash */
3523 if (data->kind == nct6775) {
3524 regval = superio_inb(sioreg, 0x2c);
3526 fan3pin = regval & BIT(6);
3527 pwm3pin = regval & BIT(7);
3529 /* On NCT6775, fan4 shares pins with the fdc interface */
3530 fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
3531 } else if (data->kind == nct6776) {
3532 bool gpok = superio_inb(sioreg, 0x27) & 0x80;
3533 const char *board_vendor, *board_name;
3535 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3536 board_name = dmi_get_system_info(DMI_BOARD_NAME);
3538 if (board_name && board_vendor &&
3539 !strcmp(board_vendor, "ASRock")) {
3541 * Auxiliary fan monitoring is not enabled on ASRock
3542 * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode.
3543 * Observed with BIOS version 2.00.
3545 if (!strcmp(board_name, "Z77 Pro4-M")) {
3546 if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3547 data->sio_reg_enable |= 0xe0;
3548 superio_outb(sioreg, SIO_REG_ENABLE,
3549 data->sio_reg_enable);
3554 if (data->sio_reg_enable & 0x80)
3557 fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
3559 if (data->sio_reg_enable & 0x40)
3562 fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
3564 if (data->sio_reg_enable & 0x20)
3567 fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
3571 } else if (data->kind == nct6106) {
3572 regval = superio_inb(sioreg, 0x24);
3573 fan3pin = !(regval & 0x80);
3574 pwm3pin = regval & 0x08;
3576 /* NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D */
3577 int regval_1b, regval_2a, regval_2f;
3580 regval = superio_inb(sioreg, 0x1c);
3582 fan3pin = !(regval & BIT(5));
3583 fan4pin = !(regval & BIT(6));
3584 fan5pin = !(regval & BIT(7));
3586 pwm3pin = !(regval & BIT(0));
3587 pwm4pin = !(regval & BIT(1));
3588 pwm5pin = !(regval & BIT(2));
3590 regval = superio_inb(sioreg, 0x2d);
3591 switch (data->kind) {
3594 fan6pin = regval & BIT(1);
3595 pwm6pin = regval & BIT(0);
3600 regval_1b = superio_inb(sioreg, 0x1b);
3601 regval_2a = superio_inb(sioreg, 0x2a);
3602 regval_2f = superio_inb(sioreg, 0x2f);
3603 dsw_en = regval_2f & BIT(3);
3606 pwm5pin = regval & BIT(7);
3609 fan5pin = regval_1b & BIT(5);
3611 superio_select(sioreg, NCT6775_LD_12);
3612 if (data->kind != nct6796) {
3613 int regval_eb = superio_inb(sioreg, 0xeb);
3616 fan6pin = regval & BIT(1);
3617 pwm6pin = regval & BIT(0);
3621 fan5pin = regval_eb & BIT(5);
3623 pwm5pin = (regval_eb & BIT(4)) &&
3624 !(regval_2a & BIT(0));
3626 fan6pin = regval_eb & BIT(3);
3628 pwm6pin = regval_eb & BIT(2);
3631 if (data->kind == nct6795 || data->kind == nct6796) {
3632 int regval_ed = superio_inb(sioreg, 0xed);
3635 fan6pin = (regval_2a & BIT(4)) &&
3637 (dsw_en && (regval_ed & BIT(4))));
3639 pwm6pin = (regval_2a & BIT(3)) &&
3640 (regval_ed & BIT(2));
3643 if (data->kind == nct6796) {
3644 int regval_1d = superio_inb(sioreg, 0x1d);
3645 int regval_2b = superio_inb(sioreg, 0x2b);
3647 fan7pin = !(regval_2b & BIT(2));
3648 pwm7pin = !(regval_1d & (BIT(2) | BIT(3)));
3652 default: /* NCT6779D */
3659 /* fan 1 and 2 (0x03) are always present */
3660 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3661 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3662 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3663 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3664 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3665 (pwm5pin << 4) | (pwm6pin << 5) | (pwm7pin << 6);
3668 static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3669 int *available, int *mask)
3674 for (i = 0; i < data->pwm_num && *available; i++) {
3679 src = nct6775_read_value(data, regp[i]);
3681 if (!src || (*mask & BIT(src)))
3683 if (!(data->temp_mask & BIT(src)))
3686 index = __ffs(*available);
3687 nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
3688 *available &= ~BIT(index);
3693 static int nct6775_probe(struct platform_device *pdev)
3695 struct device *dev = &pdev->dev;
3696 struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
3697 struct nct6775_data *data;
3698 struct resource *res;
3700 int src, mask, available;
3701 const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
3702 const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
3703 const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
3704 int num_reg_temp, num_reg_temp_mon;
3706 struct attribute_group *group;
3707 struct device *hwmon_dev;
3708 int num_attr_groups = 0;
3710 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3711 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3715 data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3720 data->kind = sio_data->kind;
3721 data->sioreg = sio_data->sioreg;
3722 data->addr = res->start;
3723 mutex_init(&data->update_lock);
3724 data->name = nct6775_device_names[data->kind];
3725 data->bank = 0xff; /* Force initial bank selection */
3726 platform_set_drvdata(pdev, data);
3728 switch (data->kind) {
3732 data->auto_pwm_num = 4;
3733 data->temp_fixed_num = 3;
3734 data->num_temp_alarms = 6;
3735 data->num_temp_beeps = 6;
3737 data->fan_from_reg = fan_from_reg13;
3738 data->fan_from_reg_min = fan_from_reg13;
3740 data->temp_label = nct6776_temp_label;
3741 data->temp_mask = NCT6776_TEMP_MASK;
3743 data->REG_VBAT = NCT6106_REG_VBAT;
3744 data->REG_DIODE = NCT6106_REG_DIODE;
3745 data->DIODE_MASK = NCT6106_DIODE_MASK;
3746 data->REG_VIN = NCT6106_REG_IN;
3747 data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3748 data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3749 data->REG_TARGET = NCT6106_REG_TARGET;
3750 data->REG_FAN = NCT6106_REG_FAN;
3751 data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3752 data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3753 data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3754 data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3755 data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3756 data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3757 data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3758 data->REG_PWM[0] = NCT6106_REG_PWM;
3759 data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3760 data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3761 data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3762 data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3763 data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3764 data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3765 data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3766 data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3767 data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3768 data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3769 data->REG_CRITICAL_TEMP_TOLERANCE
3770 = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3771 data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3772 data->CRITICAL_PWM_ENABLE_MASK
3773 = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3774 data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3775 data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3776 data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3777 data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3778 data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3779 data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3780 data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3781 data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3782 data->REG_ALARM = NCT6106_REG_ALARM;
3783 data->ALARM_BITS = NCT6106_ALARM_BITS;
3784 data->REG_BEEP = NCT6106_REG_BEEP;
3785 data->BEEP_BITS = NCT6106_BEEP_BITS;
3787 reg_temp = NCT6106_REG_TEMP;
3788 reg_temp_mon = NCT6106_REG_TEMP_MON;
3789 num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
3790 num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
3791 reg_temp_over = NCT6106_REG_TEMP_OVER;
3792 reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3793 reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3794 reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3795 reg_temp_crit = NCT6106_REG_TEMP_CRIT;
3796 reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3797 reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
3803 data->auto_pwm_num = 6;
3804 data->has_fan_div = true;
3805 data->temp_fixed_num = 3;
3806 data->num_temp_alarms = 3;
3807 data->num_temp_beeps = 3;
3809 data->ALARM_BITS = NCT6775_ALARM_BITS;
3810 data->BEEP_BITS = NCT6775_BEEP_BITS;
3812 data->fan_from_reg = fan_from_reg16;
3813 data->fan_from_reg_min = fan_from_reg8;
3814 data->target_temp_mask = 0x7f;
3815 data->tolerance_mask = 0x0f;
3816 data->speed_tolerance_limit = 15;
3818 data->temp_label = nct6775_temp_label;
3819 data->temp_mask = NCT6775_TEMP_MASK;
3821 data->REG_CONFIG = NCT6775_REG_CONFIG;
3822 data->REG_VBAT = NCT6775_REG_VBAT;
3823 data->REG_DIODE = NCT6775_REG_DIODE;
3824 data->DIODE_MASK = NCT6775_DIODE_MASK;
3825 data->REG_VIN = NCT6775_REG_IN;
3826 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3827 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3828 data->REG_TARGET = NCT6775_REG_TARGET;
3829 data->REG_FAN = NCT6775_REG_FAN;
3830 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3831 data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
3832 data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
3833 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3834 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3835 data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3836 data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
3837 data->REG_PWM[0] = NCT6775_REG_PWM;
3838 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3839 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3840 data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3841 data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
3842 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3843 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3844 data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3845 data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
3846 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3847 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3848 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3849 data->REG_CRITICAL_TEMP_TOLERANCE
3850 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3851 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3852 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3853 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3854 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3855 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3856 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3857 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3858 data->REG_ALARM = NCT6775_REG_ALARM;
3859 data->REG_BEEP = NCT6775_REG_BEEP;
3861 reg_temp = NCT6775_REG_TEMP;
3862 reg_temp_mon = NCT6775_REG_TEMP_MON;
3863 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3864 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3865 reg_temp_over = NCT6775_REG_TEMP_OVER;
3866 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3867 reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3868 reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3869 reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3875 data->auto_pwm_num = 4;
3876 data->has_fan_div = false;
3877 data->temp_fixed_num = 3;
3878 data->num_temp_alarms = 3;
3879 data->num_temp_beeps = 6;
3881 data->ALARM_BITS = NCT6776_ALARM_BITS;
3882 data->BEEP_BITS = NCT6776_BEEP_BITS;
3884 data->fan_from_reg = fan_from_reg13;
3885 data->fan_from_reg_min = fan_from_reg13;
3886 data->target_temp_mask = 0xff;
3887 data->tolerance_mask = 0x07;
3888 data->speed_tolerance_limit = 63;
3890 data->temp_label = nct6776_temp_label;
3891 data->temp_mask = NCT6776_TEMP_MASK;
3893 data->REG_CONFIG = NCT6775_REG_CONFIG;
3894 data->REG_VBAT = NCT6775_REG_VBAT;
3895 data->REG_DIODE = NCT6775_REG_DIODE;
3896 data->DIODE_MASK = NCT6775_DIODE_MASK;
3897 data->REG_VIN = NCT6775_REG_IN;
3898 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3899 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3900 data->REG_TARGET = NCT6775_REG_TARGET;
3901 data->REG_FAN = NCT6775_REG_FAN;
3902 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3903 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3904 data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
3905 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3906 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3907 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3908 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3909 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3910 data->REG_PWM[0] = NCT6775_REG_PWM;
3911 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3912 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3913 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3914 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3915 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3916 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3917 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3918 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3919 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3920 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3921 data->REG_CRITICAL_TEMP_TOLERANCE
3922 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3923 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3924 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3925 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3926 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3927 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3928 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3929 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3930 data->REG_ALARM = NCT6775_REG_ALARM;
3931 data->REG_BEEP = NCT6776_REG_BEEP;
3933 reg_temp = NCT6775_REG_TEMP;
3934 reg_temp_mon = NCT6775_REG_TEMP_MON;
3935 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3936 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3937 reg_temp_over = NCT6775_REG_TEMP_OVER;
3938 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3939 reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3940 reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3941 reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3947 data->auto_pwm_num = 4;
3948 data->has_fan_div = false;
3949 data->temp_fixed_num = 6;
3950 data->num_temp_alarms = 2;
3951 data->num_temp_beeps = 2;
3953 data->ALARM_BITS = NCT6779_ALARM_BITS;
3954 data->BEEP_BITS = NCT6779_BEEP_BITS;
3956 data->fan_from_reg = fan_from_reg13;
3957 data->fan_from_reg_min = fan_from_reg13;
3958 data->target_temp_mask = 0xff;
3959 data->tolerance_mask = 0x07;
3960 data->speed_tolerance_limit = 63;
3962 data->temp_label = nct6779_temp_label;
3963 data->temp_mask = NCT6779_TEMP_MASK;
3965 data->REG_CONFIG = NCT6775_REG_CONFIG;
3966 data->REG_VBAT = NCT6775_REG_VBAT;
3967 data->REG_DIODE = NCT6775_REG_DIODE;
3968 data->DIODE_MASK = NCT6775_DIODE_MASK;
3969 data->REG_VIN = NCT6779_REG_IN;
3970 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3971 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3972 data->REG_TARGET = NCT6775_REG_TARGET;
3973 data->REG_FAN = NCT6779_REG_FAN;
3974 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3975 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3976 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3977 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3978 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3979 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3980 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3981 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3982 data->REG_PWM[0] = NCT6775_REG_PWM;
3983 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3984 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3985 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3986 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3987 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3988 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3989 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3990 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3991 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3992 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3993 data->REG_CRITICAL_TEMP_TOLERANCE
3994 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3995 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3996 data->CRITICAL_PWM_ENABLE_MASK
3997 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3998 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
3999 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4000 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4001 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4002 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
4003 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
4004 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
4005 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
4006 data->REG_ALARM = NCT6779_REG_ALARM;
4007 data->REG_BEEP = NCT6776_REG_BEEP;
4009 reg_temp = NCT6779_REG_TEMP;
4010 reg_temp_mon = NCT6779_REG_TEMP_MON;
4011 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4012 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4013 reg_temp_over = NCT6779_REG_TEMP_OVER;
4014 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4015 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4016 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4017 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4026 data->pwm_num = (data->kind == nct6796) ? 7 : 6;
4027 data->auto_pwm_num = 4;
4028 data->has_fan_div = false;
4029 data->temp_fixed_num = 6;
4030 data->num_temp_alarms = 2;
4031 data->num_temp_beeps = 2;
4033 data->ALARM_BITS = NCT6791_ALARM_BITS;
4034 data->BEEP_BITS = NCT6779_BEEP_BITS;
4036 data->fan_from_reg = fan_from_reg13;
4037 data->fan_from_reg_min = fan_from_reg13;
4038 data->target_temp_mask = 0xff;
4039 data->tolerance_mask = 0x07;
4040 data->speed_tolerance_limit = 63;
4042 switch (data->kind) {
4045 data->temp_label = nct6779_temp_label;
4046 data->temp_mask = NCT6791_TEMP_MASK;
4049 data->temp_label = nct6792_temp_label;
4050 data->temp_mask = NCT6792_TEMP_MASK;
4053 data->temp_label = nct6793_temp_label;
4054 data->temp_mask = NCT6793_TEMP_MASK;
4057 data->temp_label = nct6795_temp_label;
4058 data->temp_mask = NCT6795_TEMP_MASK;
4061 data->temp_label = nct6796_temp_label;
4062 data->temp_mask = NCT6796_TEMP_MASK;
4066 data->REG_CONFIG = NCT6775_REG_CONFIG;
4067 data->REG_VBAT = NCT6775_REG_VBAT;
4068 data->REG_DIODE = NCT6775_REG_DIODE;
4069 data->DIODE_MASK = NCT6775_DIODE_MASK;
4070 data->REG_VIN = NCT6779_REG_IN;
4071 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
4072 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
4073 data->REG_TARGET = NCT6775_REG_TARGET;
4074 data->REG_FAN = NCT6779_REG_FAN;
4075 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
4076 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
4077 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
4078 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
4079 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
4080 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
4081 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
4082 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
4083 data->REG_PWM[0] = NCT6775_REG_PWM;
4084 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
4085 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
4086 data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
4087 data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
4088 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
4089 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
4090 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
4091 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
4092 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
4093 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
4094 data->REG_CRITICAL_TEMP_TOLERANCE
4095 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
4096 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
4097 data->CRITICAL_PWM_ENABLE_MASK
4098 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
4099 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4100 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4101 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4102 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4103 data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
4104 data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
4105 data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
4106 data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
4107 data->REG_ALARM = NCT6791_REG_ALARM;
4108 if (data->kind == nct6791)
4109 data->REG_BEEP = NCT6776_REG_BEEP;
4111 data->REG_BEEP = NCT6792_REG_BEEP;
4113 reg_temp = NCT6779_REG_TEMP;
4114 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4115 if (data->kind == nct6791) {
4116 reg_temp_mon = NCT6779_REG_TEMP_MON;
4117 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4119 reg_temp_mon = NCT6792_REG_TEMP_MON;
4120 num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
4122 reg_temp_over = NCT6779_REG_TEMP_OVER;
4123 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4124 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4125 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4126 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4132 data->have_in = BIT(data->in_num) - 1;
4133 data->have_temp = 0;
4136 * On some boards, not all available temperature sources are monitored,
4137 * even though some of the monitoring registers are unused.
4138 * Get list of unused monitoring registers, then detect if any fan
4139 * controls are configured to use unmonitored temperature sources.
4140 * If so, assign the unmonitored temperature sources to available
4141 * monitoring registers.
4145 for (i = 0; i < num_reg_temp; i++) {
4146 if (reg_temp[i] == 0)
4149 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4150 if (!src || (mask & BIT(src)))
4151 available |= BIT(i);
4157 * Now find unmonitored temperature registers and enable monitoring
4158 * if additional monitoring registers are available.
4160 add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
4161 add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
4164 s = NUM_TEMP_FIXED; /* First dynamic temperature attribute */
4165 for (i = 0; i < num_reg_temp; i++) {
4166 if (reg_temp[i] == 0)
4169 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4170 if (!src || (mask & BIT(src)))
4173 if (!(data->temp_mask & BIT(src))) {
4175 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4176 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4182 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4183 if (src <= data->temp_fixed_num) {
4184 data->have_temp |= BIT(src - 1);
4185 data->have_temp_fixed |= BIT(src - 1);
4186 data->reg_temp[0][src - 1] = reg_temp[i];
4187 data->reg_temp[1][src - 1] = reg_temp_over[i];
4188 data->reg_temp[2][src - 1] = reg_temp_hyst[i];
4189 if (reg_temp_crit_h && reg_temp_crit_h[i])
4190 data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4191 else if (reg_temp_crit[src - 1])
4192 data->reg_temp[3][src - 1]
4193 = reg_temp_crit[src - 1];
4194 if (reg_temp_crit_l && reg_temp_crit_l[i])
4195 data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
4196 data->reg_temp_config[src - 1] = reg_temp_config[i];
4197 data->temp_src[src - 1] = src;
4204 /* Use dynamic index for other sources */
4205 data->have_temp |= BIT(s);
4206 data->reg_temp[0][s] = reg_temp[i];
4207 data->reg_temp[1][s] = reg_temp_over[i];
4208 data->reg_temp[2][s] = reg_temp_hyst[i];
4209 data->reg_temp_config[s] = reg_temp_config[i];
4210 if (reg_temp_crit_h && reg_temp_crit_h[i])
4211 data->reg_temp[3][s] = reg_temp_crit_h[i];
4212 else if (reg_temp_crit[src - 1])
4213 data->reg_temp[3][s] = reg_temp_crit[src - 1];
4214 if (reg_temp_crit_l && reg_temp_crit_l[i])
4215 data->reg_temp[4][s] = reg_temp_crit_l[i];
4217 data->temp_src[s] = src;
4222 * Repeat with temperatures used for fan control.
4223 * This set of registers does not support limits.
4225 for (i = 0; i < num_reg_temp_mon; i++) {
4226 if (reg_temp_mon[i] == 0)
4229 src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
4233 if (!(data->temp_mask & BIT(src))) {
4235 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4236 src, i, data->REG_TEMP_SEL[i],
4242 * For virtual temperature sources, the 'virtual' temperature
4243 * for each fan reflects a different temperature, and there
4244 * are no duplicates.
4246 if (src != TEMP_SOURCE_VIRTUAL) {
4247 if (mask & BIT(src))
4252 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4253 if (src <= data->temp_fixed_num) {
4254 if (data->have_temp & BIT(src - 1))
4256 data->have_temp |= BIT(src - 1);
4257 data->have_temp_fixed |= BIT(src - 1);
4258 data->reg_temp[0][src - 1] = reg_temp_mon[i];
4259 data->temp_src[src - 1] = src;
4266 /* Use dynamic index for other sources */
4267 data->have_temp |= BIT(s);
4268 data->reg_temp[0][s] = reg_temp_mon[i];
4269 data->temp_src[s] = src;
4273 #ifdef USE_ALTERNATE
4275 * Go through the list of alternate temp registers and enable
4277 * The temperature is already monitored if the respective bit in <mask>
4280 for (i = 0; i < 32; i++) {
4281 if (!(data->temp_mask & BIT(i + 1)))
4283 if (!reg_temp_alternate[i])
4285 if (mask & BIT(i + 1))
4287 if (i < data->temp_fixed_num) {
4288 if (data->have_temp & BIT(i))
4290 data->have_temp |= BIT(i);
4291 data->have_temp_fixed |= BIT(i);
4292 data->reg_temp[0][i] = reg_temp_alternate[i];
4293 if (i < num_reg_temp) {
4294 data->reg_temp[1][i] = reg_temp_over[i];
4295 data->reg_temp[2][i] = reg_temp_hyst[i];
4297 data->temp_src[i] = i + 1;
4301 if (s >= NUM_TEMP) /* Abort if no more space */
4304 data->have_temp |= BIT(s);
4305 data->reg_temp[0][s] = reg_temp_alternate[i];
4306 data->temp_src[s] = i + 1;
4309 #endif /* USE_ALTERNATE */
4311 /* Initialize the chip */
4312 nct6775_init_device(data);
4314 err = superio_enter(sio_data->sioreg);
4318 cr2a = superio_inb(sio_data->sioreg, 0x2a);
4319 switch (data->kind) {
4321 data->have_vid = (cr2a & 0x40);
4324 data->have_vid = (cr2a & 0x60) == 0x40;
4338 * We can get the VID input values directly at logical device D 0xe3.
4340 if (data->have_vid) {
4341 superio_select(sio_data->sioreg, NCT6775_LD_VID);
4342 data->vid = superio_inb(sio_data->sioreg, 0xe3);
4343 data->vrm = vid_which_vrm();
4349 superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4350 tmp = superio_inb(sio_data->sioreg,
4351 NCT6775_REG_CR_FAN_DEBOUNCE);
4352 switch (data->kind) {
4371 superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4373 dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4377 nct6775_check_fan_inputs(data);
4379 superio_exit(sio_data->sioreg);
4381 /* Read fan clock dividers immediately */
4382 nct6775_init_fan_common(dev, data);
4384 /* Register sysfs hooks */
4385 group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4388 return PTR_ERR(group);
4390 data->groups[num_attr_groups++] = group;
4392 group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4393 fls(data->have_in));
4395 return PTR_ERR(group);
4397 data->groups[num_attr_groups++] = group;
4399 group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4400 fls(data->has_fan));
4402 return PTR_ERR(group);
4404 data->groups[num_attr_groups++] = group;
4406 group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4407 fls(data->have_temp));
4409 return PTR_ERR(group);
4411 data->groups[num_attr_groups++] = group;
4412 data->groups[num_attr_groups++] = &nct6775_group_other;
4414 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)
4415 err = sysfs_create_groups(&dev->kobj, data->groups);
4418 hwmon_dev = hwmon_device_register(dev);
4419 if (IS_ERR(hwmon_dev)) {
4420 sysfs_remove_groups(&dev->kobj, data->groups);
4421 return PTR_ERR(hwmon_dev);
4423 data->hwmon_dev = hwmon_dev;
4425 hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4426 data, data->groups);
4427 if (!IS_ERR(hwmon_dev))
4428 nct6775_debugfs_init(hwmon_dev);
4430 return PTR_ERR_OR_ZERO(hwmon_dev);
4433 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)
4434 static int nct6775_remove(struct platform_device *pdev)
4436 struct nct6775_data *data = platform_get_drvdata(pdev);
4438 hwmon_device_unregister(data->hwmon_dev);
4439 sysfs_remove_groups(&pdev->dev.kobj, data->groups);
4444 static void nct6791_enable_io_mapping(int sioaddr)
4448 val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4450 pr_info("Enabling hardware monitor logical device mappings.\n");
4451 superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4456 static int __maybe_unused nct6775_suspend(struct device *dev)
4458 struct nct6775_data *data = nct6775_update_device(dev);
4460 mutex_lock(&data->update_lock);
4461 data->vbat = nct6775_read_value(data, data->REG_VBAT);
4462 if (data->kind == nct6775) {
4463 data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4464 data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4466 mutex_unlock(&data->update_lock);
4471 static int __maybe_unused nct6775_resume(struct device *dev)
4473 struct nct6775_data *data = dev_get_drvdata(dev);
4474 int sioreg = data->sioreg;
4478 mutex_lock(&data->update_lock);
4479 data->bank = 0xff; /* Force initial bank selection */
4481 err = superio_enter(sioreg);
4485 superio_select(sioreg, NCT6775_LD_HWM);
4486 reg = superio_inb(sioreg, SIO_REG_ENABLE);
4487 if (reg != data->sio_reg_enable)
4488 superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4490 if (data->kind == nct6791 || data->kind == nct6792 ||
4491 data->kind == nct6793 || data->kind == nct6795 ||
4492 data->kind == nct6796)
4493 nct6791_enable_io_mapping(sioreg);
4495 superio_exit(sioreg);
4497 /* Restore limits */
4498 for (i = 0; i < data->in_num; i++) {
4499 if (!(data->have_in & BIT(i)))
4502 nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4504 nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4508 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
4509 if (!(data->has_fan_min & BIT(i)))
4512 nct6775_write_value(data, data->REG_FAN_MIN[i],
4516 for (i = 0; i < NUM_TEMP; i++) {
4517 if (!(data->have_temp & BIT(i)))
4520 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
4521 if (data->reg_temp[j][i])
4522 nct6775_write_temp(data, data->reg_temp[j][i],
4526 /* Restore other settings */
4527 nct6775_write_value(data, data->REG_VBAT, data->vbat);
4528 if (data->kind == nct6775) {
4529 nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4530 nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4534 /* Force re-reading all values */
4535 data->valid = false;
4536 mutex_unlock(&data->update_lock);
4541 static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
4543 static struct platform_driver nct6775_driver = {
4545 .owner = THIS_MODULE,
4547 .pm = &nct6775_dev_pm_ops,
4549 .probe = nct6775_probe,
4550 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)
4551 .remove = nct6775_remove,
4555 /* nct6775_find() looks for a '627 in the Super-I/O config space */
4556 static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
4562 err = superio_enter(sioaddr);
4566 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4567 superio_inb(sioaddr, SIO_REG_DEVID + 1);
4568 if (force_id && val != 0xffff)
4571 switch (val & SIO_ID_MASK) {
4572 case SIO_NCT6106_ID:
4573 sio_data->kind = nct6106;
4575 case SIO_NCT6775_ID:
4576 sio_data->kind = nct6775;
4578 case SIO_NCT6776_ID:
4579 sio_data->kind = nct6776;
4581 case SIO_NCT6779_ID:
4582 sio_data->kind = nct6779;
4584 case SIO_NCT6791_ID:
4585 sio_data->kind = nct6791;
4587 case SIO_NCT6792_ID:
4588 sio_data->kind = nct6792;
4590 case SIO_NCT6793_ID:
4591 sio_data->kind = nct6793;
4593 case SIO_NCT6795_ID:
4594 sio_data->kind = nct6795;
4596 case SIO_NCT6796_ID:
4597 sio_data->kind = nct6796;
4601 pr_debug("unsupported chip ID: 0x%04x\n", val);
4602 superio_exit(sioaddr);
4606 /* We have a known chip, find the HWM I/O address */
4607 superio_select(sioaddr, NCT6775_LD_HWM);
4608 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4609 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
4610 addr = val & IOREGION_ALIGNMENT;
4612 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4613 superio_exit(sioaddr);
4617 /* Activate logical device if needed */
4618 val = superio_inb(sioaddr, SIO_REG_ENABLE);
4619 if (!(val & 0x01)) {
4620 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4621 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4624 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
4625 sio_data->kind == nct6793 || sio_data->kind == nct6795 ||
4626 sio_data->kind == nct6796)
4627 nct6791_enable_io_mapping(sioaddr);
4629 superio_exit(sioaddr);
4630 pr_info("Found %s or compatible chip at %#x:%#x\n",
4631 nct6775_sio_names[sio_data->kind], sioaddr, addr);
4632 sio_data->sioreg = sioaddr;
4638 * when Super-I/O functions move to a separate file, the Super-I/O
4639 * bus will manage the lifetime of the device and this module will only keep
4640 * track of the nct6775 driver. But since we use platform_device_alloc(), we
4641 * must keep track of the device
4643 static struct platform_device *pdev[2];
4645 static int __init sensors_nct6775_init(void)
4650 struct resource res;
4651 struct nct6775_sio_data sio_data;
4652 int sioaddr[2] = { 0x2e, 0x4e };
4654 err = platform_driver_register(&nct6775_driver);
4659 * initialize sio_data->kind and sio_data->sioreg.
4661 * when Super-I/O functions move to a separate file, the Super-I/O
4662 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
4663 * nct6775 hardware monitor, and call probe()
4665 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4666 address = nct6775_find(sioaddr[i], &sio_data);
4672 pdev[i] = platform_device_alloc(DRVNAME, address);
4675 goto exit_device_unregister;
4678 err = platform_device_add_data(pdev[i], &sio_data,
4679 sizeof(struct nct6775_sio_data));
4681 goto exit_device_put;
4683 memset(&res, 0, sizeof(res));
4685 res.start = address + IOREGION_OFFSET;
4686 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4687 res.flags = IORESOURCE_IO;
4689 err = acpi_check_resource_conflict(&res);
4691 platform_device_put(pdev[i]);
4696 err = platform_device_add_resources(pdev[i], &res, 1);
4698 goto exit_device_put;
4700 /* platform_device_add calls probe() */
4701 err = platform_device_add(pdev[i]);
4703 goto exit_device_put;
4707 goto exit_unregister;
4713 platform_device_put(pdev[i]);
4714 exit_device_unregister:
4717 platform_device_unregister(pdev[i]);
4720 platform_driver_unregister(&nct6775_driver);
4724 static void __exit sensors_nct6775_exit(void)
4728 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4730 platform_device_unregister(pdev[i]);
4732 platform_driver_unregister(&nct6775_driver);
4735 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4736 MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
4737 MODULE_LICENSE("GPL");
4739 module_init(sensors_nct6775_init);
4740 module_exit(sensors_nct6775_exit);