Fix MIPS cache coherency on Linux

MIPS chips require manual control of on-chip caches. The cacheflush
syscall being used here only exists on MIPS Linux, other OSs will
require revisiting.

diff --git a/libraries/liblmdb/mdb.c b/libraries/liblmdb/mdb.c
index 84477c428585303a5cd7edfdc63818f947ffd51f..e1d774887b65fe7796661a1bc6a762dc0fff5fbe 100644 (file)
--- a/libraries/liblmdb/mdb.c
+++ b/libraries/liblmdb/mdb.c
@@ -70,6 +70,15 @@
 #include <fcntl.h>
 #endif
 
+#if defined(__mips) && defined(__linux)
+/* MIPS has cache coherency issues, requires explicit cache control */
+#include <asm/cachectl.h>
+extern int cacheflush(char *addr, int nbytes, int cache);
+#define CACHEFLUSH(addr, bytes, cache) cacheflush(addr, bytes, cache)
+#else
+#define CACHEFLUSH(addr, bytes, cache)
+#endif
+
 #include <errno.h>
 #include <limits.h>
 #include <stddef.h>
@@ -3581,6 +3590,11 @@ done:
        if (env->me_txns)
                env->me_txns->mti_txnid = txn->mt_txnid;
 
+       /* MIPS has cache coherency issues, this is a no-op everywhere else */
+       if (!(env->me_flags & MDB_WRITEMAP)) {
+               CACHEFLUSH(env->me_map, txn->mt_next_pgno * env->me_psize, DCACHE);
+       }
+
        return MDB_SUCCESS;
 }