git.sur5r.net Git - openocd/blob - contrib/loaders/flash/stm32f1x.S

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   3  *   andreas.fritiofson@gmail.com                                          *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21         .text
  22         .syntax unified
  23         .cpu cortex-m3
  24         .thumb
  25         .thumb_func
  26         .global write
  27
  28         /* Params:
  29          * r0 - flash base (in), status (out)
  30          * r1 - count (halfword-16bit)
  31          * r2 - workarea start
  32          * r3 - workarea end
  33          * r4 - target address
  34          * Clobbered:
  35          * r5 - rp
  36          * r6 - wp, tmp
  37          */
  38
  39 #define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register from flash reg base */
  40 #define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
  41
  42 wait_fifo:
  43         ldr     r6, [r2, #0]    /* read wp */
  44         cmp     r6, #0                  /* abort if wp == 0 */
  45         beq     exit
  46         ldr     r5, [r2, #4]    /* read rp */
  47         cmp     r5, r6                  /* wait until rp != wp */
  48         beq     wait_fifo
  49         movs    r6, #1                  /* set PG flag to enable flash programming */
  50         str     r6, [r0, #STM32_FLASH_CR_OFFSET]
  51         ldrh    r6, [r5], #2    /* "*target_address++ = *rp++" */
  52         strh    r6, [r4], #2
  53 busy:
  54         ldr     r6, [r0, #STM32_FLASH_SR_OFFSET]        /* wait until BSY flag is reset */
  55         tst     r6, #1
  56         bne     busy
  57         tst     r6, #0x14               /* check the error bits */
  58         bne     error
  59         cmp     r5, r3                  /* wrap rp at end of buffer */
  60         it      cs
  61         addcs   r5, r2, #8
  62         str     r5, [r2, #4]    /* store rp */
  63         subs    r1, r1, #1              /* decrement halfword count */
  64         cbz     r1, exit                /* loop if not done */
  65         b               wait_fifo
  66 error:
  67         movs    r0, #0
  68         str     r0, [r2, #2]    /* set rp = 0 on error */
  69 exit:
  70         mov             r0, r6                  /* return status in r0 */
  71         bkpt    #0