git.sur5r.net Git - openocd/blob - src/flash/cfi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "replacements.h"
  27
  28 #include "cfi.h"
  29 #include "non_cfi.h"
  30
  31 #include "flash.h"
  32 #include "target.h"
  33 #include "log.h"
  34 #include "armv4_5.h"
  35 #include "algorithm.h"
  36 #include "binarybuffer.h"
  37 #include "types.h"
  38
  39 #include <stdlib.h>
  40 #include <string.h>
  41 #include <unistd.h>
  42
  43 static int cfi_register_commands(struct command_context_s *cmd_ctx);
  44 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  45 static int cfi_erase(struct flash_bank_s *bank, int first, int last);
  46 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
  47 static int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  48 static int cfi_probe(struct flash_bank_s *bank);
  49 static int cfi_auto_probe(struct flash_bank_s *bank);
  50 static int cfi_protect_check(struct flash_bank_s *bank);
  51 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
  52
  53 //static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54
  55 #define CFI_MAX_BUS_WIDTH       4
  56 #define CFI_MAX_CHIP_WIDTH      4
  57
  58 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  59 #define CFI_MAX_INTEL_CODESIZE 256
  60
  61 flash_driver_t cfi_flash =
  62 {
  63         .name = "cfi",
  64         .register_commands = cfi_register_commands,
  65         .flash_bank_command = cfi_flash_bank_command,
  66         .erase = cfi_erase,
  67         .protect = cfi_protect,
  68         .write = cfi_write,
  69         .probe = cfi_probe,
  70         .auto_probe = cfi_auto_probe,
  71         .erase_check = default_flash_blank_check,
  72         .protect_check = cfi_protect_check,
  73         .info = cfi_info
  74 };
  75
  76 static cfi_unlock_addresses_t cfi_unlock_addresses[] =
  77 {
  78         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  79         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  80 };
  81
  82 /* CFI fixups foward declarations */
  83 static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  84 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  85 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  86
  87 /* fixup after reading cmdset 0002 primary query table */
  88 static cfi_fixup_t cfi_0002_fixups[] = {
  89         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  90         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  91         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  92         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  93         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  94         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  95         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  96         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  97         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  98         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  99         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
 100         {0, 0, NULL, NULL}
 101 };
 102
 103 /* fixup after reading cmdset 0001 primary query table */
 104 static cfi_fixup_t cfi_0001_fixups[] = {
 105         {0, 0, NULL, NULL}
 106 };
 107
 108 static void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
 109 {
 110         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 111         cfi_fixup_t *f;
 112
 113         for (f = fixups; f->fixup; f++)
 114         {
 115                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
 116                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
 117                 {
 118                         f->fixup(bank, f->param);
 119                 }
 120         }
 121 }
 122
 123 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
 124 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
 125 {
 126         /* while the sector list isn't built, only accesses to sector 0 work */
 127         if (sector == 0)
 128                 return bank->base + offset * bank->bus_width;
 129         else
 130         {
 131                 if (!bank->sectors)
 132                 {
 133                         LOG_ERROR("BUG: sector list not yet built");
 134                         exit(-1);
 135                 }
 136                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 137         }
 138
 139 }
 140
 141 static void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
 142 {
 143         int i;
 144
 145         /* clear whole buffer, to ensure bits that exceed the bus_width
 146          * are set to zero
 147          */
 148         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 149                 cmd_buf[i] = 0;
 150
 151         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 152         {
 153                 for (i = bank->bus_width; i > 0; i--)
 154                 {
 155                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 156                 }
 157         }
 158         else
 159         {
 160                 for (i = 1; i <= bank->bus_width; i++)
 161                 {
 162                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 163                 }
 164         }
 165 }
 166
 167 /* read unsigned 8-bit value from the bank
 168  * flash banks are expected to be made of similar chips
 169  * the query result should be the same for all
 170  */
 171 static u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
 172 {
 173         target_t *target = bank->target;
 174         u8 data[CFI_MAX_BUS_WIDTH];
 175
 176         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 177
 178         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 179                 return data[0];
 180         else
 181                 return data[bank->bus_width - 1];
 182 }
 183
 184 /* read unsigned 8-bit value from the bank
 185  * in case of a bank made of multiple chips,
 186  * the individual values are ORed
 187  */
 188 static u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
 189 {
 190         target_t *target = bank->target;
 191         u8 data[CFI_MAX_BUS_WIDTH];
 192         int i;
 193
 194         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 195
 196         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 197         {
 198                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 199                         data[0] |= data[i];
 200
 201                 return data[0];
 202         }
 203         else
 204         {
 205                 u8 value = 0;
 206                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 207                         value |= data[bank->bus_width - 1 - i];
 208
 209                 return value;
 210         }
 211 }
 212
 213 static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
 214 {
 215         target_t *target = bank->target;
 216         u8 data[CFI_MAX_BUS_WIDTH * 2];
 217
 218         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 219
 220         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 221                 return data[0] | data[bank->bus_width] << 8;
 222         else
 223                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 224 }
 225
 226 static u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
 227 {
 228         target_t *target = bank->target;
 229         u8 data[CFI_MAX_BUS_WIDTH * 4];
 230
 231         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 232
 233         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 234                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 235         else
 236                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 237                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 238 }
 239
 240 static void cfi_intel_clear_status_register(flash_bank_t *bank)
 241 {
 242         target_t *target = bank->target;
 243         u8 command[8];
 244
 245         if (target->state != TARGET_HALTED)
 246         {
 247                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 248                 exit(-1);
 249         }
 250
 251         cfi_command(bank, 0x50, command);
 252         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 253 }
 254
 255 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 256 {
 257         u8 status;
 258
 259         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 260         {
 261                 LOG_DEBUG("status: 0x%x", status);
 262                 alive_sleep(1);
 263         }
 264
 265         /* mask out bit 0 (reserved) */
 266         status = status & 0xfe;
 267
 268         LOG_DEBUG("status: 0x%x", status);
 269
 270         if ((status & 0x80) != 0x80)
 271         {
 272                 LOG_ERROR("timeout while waiting for WSM to become ready");
 273         }
 274         else if (status != 0x80)
 275         {
 276                 LOG_ERROR("status register: 0x%x", status);
 277                 if (status & 0x2)
 278                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 279                 if (status & 0x4)
 280                         LOG_ERROR("Program suspended");
 281                 if (status & 0x8)
 282                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 283                 if (status & 0x10)
 284                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 285                 if (status & 0x20)
 286                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 287                 if (status & 0x40)
 288                         LOG_ERROR("Block Erase Suspended");
 289
 290                 cfi_intel_clear_status_register(bank);
 291         }
 292
 293         return status;
 294 }
 295
 296 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 297 {
 298         u8 status, oldstatus;
 299
 300         oldstatus = cfi_get_u8(bank, 0, 0x0);
 301
 302         do {
 303                 status = cfi_get_u8(bank, 0, 0x0);
 304                 if ((status ^ oldstatus) & 0x40) {
 305                         if (status & 0x20) {
 306                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 307                                 status = cfi_get_u8(bank, 0, 0x0);
 308                                 if ((status ^ oldstatus) & 0x40) {
 309                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 310                                         return(ERROR_FLASH_OPERATION_FAILED);
 311                                 } else {
 312                                         LOG_DEBUG("status: 0x%x", status);
 313                                         return(ERROR_OK);
 314                                 }
 315                         }
 316                 } else {
 317                         LOG_DEBUG("status: 0x%x", status);
 318                         return(ERROR_OK);
 319                 }
 320
 321                 oldstatus = status;
 322                 alive_sleep(1);
 323         } while (timeout-- > 0);
 324
 325         LOG_ERROR("timeout, status: 0x%x", status);
 326
 327         return(ERROR_FLASH_BUSY);
 328 }
 329
 330 static int cfi_read_intel_pri_ext(flash_bank_t *bank)
 331 {
 332         int retval;
 333         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 334         cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
 335         target_t *target = bank->target;
 336         u8 command[8];
 337
 338         cfi_info->pri_ext = pri_ext;
 339
 340         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 341         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 342         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 343
 344         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 345         {
 346                 cfi_command(bank, 0xf0, command);
 347                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 348                 {
 349                         return retval;
 350                 }
 351                 cfi_command(bank, 0xff, command);
 352                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 353                 {
 354                         return retval;
 355                 }
 356                 LOG_ERROR("Could not read bank flash bank information");
 357                 return ERROR_FLASH_BANK_INVALID;
 358         }
 359
 360         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 361         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 362
 363         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 364
 365         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 366         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 367         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 368
 369         LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 370
 371         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 372         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 373
 374         LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 375                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 376                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 377
 378         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 379         if (pri_ext->num_protection_fields != 1)
 380         {
 381                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 382         }
 383
 384         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 385         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 386         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 387
 388         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 389
 390         return ERROR_OK;
 391 }
 392
 393 static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 394 {
 395         int retval;
 396         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 397         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 398         target_t *target = bank->target;
 399         u8 command[8];
 400
 401         cfi_info->pri_ext = pri_ext;
 402
 403         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 404         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 405         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 406
 407         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 408         {
 409                 cfi_command(bank, 0xf0, command);
 410                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 411                 {
 412                         return retval;
 413                 }
 414                 LOG_ERROR("Could not read spansion bank information");
 415                 return ERROR_FLASH_BANK_INVALID;
 416         }
 417
 418         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 419         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 420
 421         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 422
 423         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 424         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 425         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 426         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 427         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 428         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 429         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 430         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 431         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 432         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 433         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 434
 435         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 436               pri_ext->EraseSuspend, pri_ext->BlkProt);
 437
 438         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 439               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 440
 441         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 442
 443
 444         LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 445                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 446                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 447
 448         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 449
 450         /* default values for implementation specific workarounds */
 451         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 452         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 453         pri_ext->_reversed_geometry = 0;
 454
 455         return ERROR_OK;
 456 }
 457
 458 static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 459 {
 460         int retval;
 461         cfi_atmel_pri_ext_t atmel_pri_ext;
 462         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 463         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 464         target_t *target = bank->target;
 465         u8 command[8];
 466
 467         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 468          * but a different primary extended query table.
 469          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 470          */
 471
 472         memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
 473
 474         cfi_info->pri_ext = pri_ext;
 475
 476         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 477         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 478         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 479
 480         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 481         {
 482                 cfi_command(bank, 0xf0, command);
 483                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 484                 {
 485                         return retval;
 486                 }
 487                 LOG_ERROR("Could not read atmel bank information");
 488                 return ERROR_FLASH_BANK_INVALID;
 489         }
 490
 491         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 492         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 493         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 494
 495         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 496         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 497
 498         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 499
 500         pri_ext->major_version = atmel_pri_ext.major_version;
 501         pri_ext->minor_version = atmel_pri_ext.minor_version;
 502
 503         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 504         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 505         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 506         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 507
 508         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 509                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 510
 511         if (atmel_pri_ext.features & 0x02)
 512                 pri_ext->EraseSuspend = 2;
 513
 514         if (atmel_pri_ext.bottom_boot)
 515                 pri_ext->TopBottom = 2;
 516         else
 517                 pri_ext->TopBottom = 3;
 518
 519         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 520         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 521
 522         return ERROR_OK;
 523 }
 524
 525 static int cfi_read_0002_pri_ext(flash_bank_t *bank)
 526 {
 527         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 528
 529         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 530         {
 531                 return cfi_read_atmel_pri_ext(bank);
 532         }
 533         else
 534         {
 535                 return cfi_read_spansion_pri_ext(bank);
 536         }
 537 }
 538
 539 static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 540 {
 541         int printed;
 542         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 543         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 544
 545         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 546         buf += printed;
 547         buf_size -= printed;
 548
 549         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 550                            pri_ext->pri[1], pri_ext->pri[2],
 551                            pri_ext->major_version, pri_ext->minor_version);
 552         buf += printed;
 553         buf_size -= printed;
 554
 555         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 556                            (pri_ext->SiliconRevision) >> 2,
 557                            (pri_ext->SiliconRevision) & 0x03);
 558         buf += printed;
 559         buf_size -= printed;
 560
 561         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 562                            pri_ext->EraseSuspend,
 563                            pri_ext->BlkProt);
 564         buf += printed;
 565         buf_size -= printed;
 566
 567         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 568                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 569                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 570
 571         return ERROR_OK;
 572 }
 573
 574 static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 575 {
 576         int printed;
 577         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 578         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 579
 580         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 581         buf += printed;
 582         buf_size -= printed;
 583
 584         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 585         buf += printed;
 586         buf_size -= printed;
 587
 588         printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 589         buf += printed;
 590         buf_size -= printed;
 591
 592         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 593                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 594                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 595         buf += printed;
 596         buf_size -= printed;
 597
 598         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 599
 600         return ERROR_OK;
 601 }
 602
 603 static int cfi_register_commands(struct command_context_s *cmd_ctx)
 604 {
 605         /*command_t *cfi_cmd = */
 606         register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
 607         /*
 608         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 609                                          "print part id of cfi flash bank <num>");
 610         */
 611         return ERROR_OK;
 612 }
 613
 614 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 615  */
 616 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 617 {
 618         cfi_flash_bank_t *cfi_info;
 619         int i;
 620         (void) cmd_ctx;
 621         (void) cmd;
 622
 623         if (argc < 6)
 624         {
 625                 LOG_WARNING("incomplete flash_bank cfi configuration");
 626                 return ERROR_FLASH_BANK_INVALID;
 627         }
 628
 629         if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
 630                 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
 631         {
 632                 LOG_ERROR("chip and bus width have to specified in bytes");
 633                 return ERROR_FLASH_BANK_INVALID;
 634         }
 635
 636         cfi_info = malloc(sizeof(cfi_flash_bank_t));
 637         cfi_info->probed = 0;
 638         bank->driver_priv = cfi_info;
 639
 640         cfi_info->write_algorithm = NULL;
 641
 642         cfi_info->x16_as_x8 = 0;
 643         cfi_info->jedec_probe = 0;
 644         cfi_info->not_cfi = 0;
 645
 646         for (i = 6; i < argc; i++)
 647         {
 648                 if (strcmp(args[i], "x16_as_x8") == 0)
 649                 {
 650                         cfi_info->x16_as_x8 = 1;
 651                 }
 652                 else if (strcmp(args[i], "jedec_probe") == 0)
 653                 {
 654                         cfi_info->jedec_probe = 1;
 655                 }
 656         }
 657
 658         cfi_info->write_algorithm = NULL;
 659
 660         /* bank wasn't probed yet */
 661         cfi_info->qry[0] = -1;
 662
 663         return ERROR_OK;
 664 }
 665
 666 static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 667 {
 668         int retval;
 669         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 670         target_t *target = bank->target;
 671         u8 command[8];
 672         int i;
 673
 674         cfi_intel_clear_status_register(bank);
 675
 676         for (i = first; i <= last; i++)
 677         {
 678                 cfi_command(bank, 0x20, command);
 679                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 680                 {
 681                         return retval;
 682                 }
 683
 684                 cfi_command(bank, 0xd0, command);
 685                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 686                 {
 687                         return retval;
 688                 }
 689
 690                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 691                         bank->sectors[i].is_erased = 1;
 692                 else
 693                 {
 694                         cfi_command(bank, 0xff, command);
 695                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 696                         {
 697                                 return retval;
 698                         }
 699
 700                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 701                         return ERROR_FLASH_OPERATION_FAILED;
 702                 }
 703         }
 704
 705         cfi_command(bank, 0xff, command);
 706         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 707
 708 }
 709
 710 static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 711 {
 712         int retval;
 713         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 714         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 715         target_t *target = bank->target;
 716         u8 command[8];
 717         int i;
 718
 719         for (i = first; i <= last; i++)
 720         {
 721                 cfi_command(bank, 0xaa, command);
 722                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 723                 {
 724                         return retval;
 725                 }
 726
 727                 cfi_command(bank, 0x55, command);
 728                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 729                 {
 730                         return retval;
 731                 }
 732
 733                 cfi_command(bank, 0x80, command);
 734                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 735                 {
 736                         return retval;
 737                 }
 738
 739                 cfi_command(bank, 0xaa, command);
 740                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 741                 {
 742                         return retval;
 743                 }
 744
 745                 cfi_command(bank, 0x55, command);
 746                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 747                 {
 748                         return retval;
 749                 }
 750
 751                 cfi_command(bank, 0x30, command);
 752                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 753                 {
 754                         return retval;
 755                 }
 756
 757                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 758                         bank->sectors[i].is_erased = 1;
 759                 else
 760                 {
 761                         cfi_command(bank, 0xf0, command);
 762                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 763                         {
 764                                 return retval;
 765                         }
 766
 767                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 768                         return ERROR_FLASH_OPERATION_FAILED;
 769                 }
 770         }
 771
 772         cfi_command(bank, 0xf0, command);
 773         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 774 }
 775
 776 static int cfi_erase(struct flash_bank_s *bank, int first, int last)
 777 {
 778         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 779
 780         if (bank->target->state != TARGET_HALTED)
 781         {
 782                 LOG_ERROR("Target not halted");
 783                 return ERROR_TARGET_NOT_HALTED;
 784         }
 785
 786         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 787         {
 788                 return ERROR_FLASH_SECTOR_INVALID;
 789         }
 790
 791         if (cfi_info->qry[0] != 'Q')
 792                 return ERROR_FLASH_BANK_NOT_PROBED;
 793
 794         switch(cfi_info->pri_id)
 795         {
 796                 case 1:
 797                 case 3:
 798                         return cfi_intel_erase(bank, first, last);
 799                         break;
 800                 case 2:
 801                         return cfi_spansion_erase(bank, first, last);
 802                         break;
 803                 default:
 804                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 805                         break;
 806         }
 807
 808         return ERROR_OK;
 809 }
 810
 811 static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 812 {
 813         int retval;
 814         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 815         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 816         target_t *target = bank->target;
 817         u8 command[8];
 818         int retry = 0;
 819         int i;
 820
 821         /* if the device supports neither legacy lock/unlock (bit 3) nor
 822          * instant individual block locking (bit 5).
 823          */
 824         if (!(pri_ext->feature_support & 0x28))
 825                 return ERROR_FLASH_OPERATION_FAILED;
 826
 827         cfi_intel_clear_status_register(bank);
 828
 829         for (i = first; i <= last; i++)
 830         {
 831                 cfi_command(bank, 0x60, command);
 832                 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 833                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 834                 {
 835                         return retval;
 836                 }
 837                 if (set)
 838                 {
 839                         cfi_command(bank, 0x01, command);
 840                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 841                         if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 842                         {
 843                                 return retval;
 844                         }
 845                         bank->sectors[i].is_protected = 1;
 846                 }
 847                 else
 848                 {
 849                         cfi_command(bank, 0xd0, command);
 850                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 851                         if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 852                         {
 853                                 return retval;
 854                         }
 855                         bank->sectors[i].is_protected = 0;
 856                 }
 857
 858                 /* instant individual block locking doesn't require reading of the status register */
 859                 if (!(pri_ext->feature_support & 0x20))
 860                 {
 861                         /* Clear lock bits operation may take up to 1.4s */
 862                         cfi_intel_wait_status_busy(bank, 1400);
 863                 }
 864                 else
 865                 {
 866                         u8 block_status;
 867                         /* read block lock bit, to verify status */
 868                         cfi_command(bank, 0x90, command);
 869                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 870                         {
 871                                 return retval;
 872                         }
 873                         block_status = cfi_get_u8(bank, i, 0x2);
 874
 875                         if ((block_status & 0x1) != set)
 876                         {
 877                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 878                                 cfi_command(bank, 0x70, command);
 879                                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 880                                 {
 881                                         return retval;
 882                                 }
 883                                 cfi_intel_wait_status_busy(bank, 10);
 884
 885                                 if (retry > 10)
 886                                         return ERROR_FLASH_OPERATION_FAILED;
 887                                 else
 888                                 {
 889                                         i--;
 890                                         retry++;
 891                                 }
 892                         }
 893                 }
 894         }
 895
 896         /* if the device doesn't support individual block lock bits set/clear,
 897          * all blocks have been unlocked in parallel, so we set those that should be protected
 898          */
 899         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 900         {
 901                 for (i = 0; i < bank->num_sectors; i++)
 902                 {
 903                         if (bank->sectors[i].is_protected == 1)
 904                         {
 905                                 cfi_intel_clear_status_register(bank);
 906
 907                                 cfi_command(bank, 0x60, command);
 908                                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 909                                 {
 910                                         return retval;
 911                                 }
 912
 913                                 cfi_command(bank, 0x01, command);
 914                                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 915                                 {
 916                                         return retval;
 917                                 }
 918
 919                                 cfi_intel_wait_status_busy(bank, 100);
 920                         }
 921                 }
 922         }
 923
 924         cfi_command(bank, 0xff, command);
 925         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 926 }
 927
 928 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 929 {
 930         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 931
 932         if (bank->target->state != TARGET_HALTED)
 933         {
 934                 LOG_ERROR("Target not halted");
 935                 return ERROR_TARGET_NOT_HALTED;
 936         }
 937
 938         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 939         {
 940                 return ERROR_FLASH_SECTOR_INVALID;
 941         }
 942
 943         if (cfi_info->qry[0] != 'Q')
 944                 return ERROR_FLASH_BANK_NOT_PROBED;
 945
 946         switch(cfi_info->pri_id)
 947         {
 948                 case 1:
 949                 case 3:
 950                         cfi_intel_protect(bank, set, first, last);
 951                         break;
 952                 default:
 953                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
 954                         break;
 955         }
 956
 957         return ERROR_OK;
 958 }
 959
 960 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 961 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
 962 {
 963         /* target_t *target = bank->target; */
 964
 965         int i;
 966
 967         /* NOTE:
 968          * The data to flash must not be changed in endian! We write a bytestrem in
 969          * target byte order already. Only the control and status byte lane of the flash
 970          * WSM is interpreted by the CPU in different ways, when read a u16 or u32
 971          * word (data seems to be in the upper or lower byte lane for u16 accesses).
 972          */
 973
 974 #if 0
 975         if (target->endianness == TARGET_LITTLE_ENDIAN)
 976         {
 977 #endif
 978                 /* shift bytes */
 979                 for (i = 0; i < bank->bus_width - 1; i++)
 980                         word[i] = word[i + 1];
 981                 word[bank->bus_width - 1] = byte;
 982 #if 0
 983         }
 984         else
 985         {
 986                 /* shift bytes */
 987                 for (i = bank->bus_width - 1; i > 0; i--)
 988                         word[i] = word[i - 1];
 989                 word[0] = byte;
 990         }
 991 #endif
 992 }
 993
 994 /* Convert code image to target endian */
 995 /* FIXME create general block conversion fcts in target.c?) */
 996 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
 997 {
 998         u32 i;
 999         for (i=0; i< count; i++)
1000         {
1001                 target_buffer_set_u32(target, dest, *src);
1002                 dest+=4;
1003                 src++;
1004         }
1005 }
1006
1007 static u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
1008 {
1009         target_t *target = bank->target;
1010
1011         u8 buf[CFI_MAX_BUS_WIDTH];
1012         cfi_command(bank, cmd, buf);
1013         switch (bank->bus_width)
1014         {
1015         case 1 :
1016                 return buf[0];
1017                 break;
1018         case 2 :
1019                 return target_buffer_get_u16(target, buf);
1020                 break;
1021         case 4 :
1022                 return target_buffer_get_u32(target, buf);
1023                 break;
1024         default :
1025                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1026                 return 0;
1027         }
1028 }
1029
1030 static int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1031 {
1032         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1033         target_t *target = bank->target;
1034         reg_param_t reg_params[7];
1035         armv4_5_algorithm_t armv4_5_info;
1036         working_area_t *source;
1037         u32 buffer_size = 32768;
1038         u32 write_command_val, busy_pattern_val, error_pattern_val;
1039
1040         /* algorithm register usage:
1041          * r0: source address (in RAM)
1042          * r1: target address (in Flash)
1043          * r2: count
1044          * r3: flash write command
1045          * r4: status byte (returned to host)
1046          * r5: busy test pattern
1047          * r6: error test pattern
1048          */
1049
1050         static const u32 word_32_code[] = {
1051                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1052                 0xe5813000,   /*                str r3, [r1] */
1053                 0xe5814000,   /*                str r4, [r1] */
1054                 0xe5914000,   /* busy:  ldr r4, [r1] */
1055                 0xe0047005,   /*                and r7, r4, r5 */
1056                 0xe1570005,   /*                cmp r7, r5 */
1057                 0x1afffffb,   /*                bne busy */
1058                 0xe1140006,   /*                tst r4, r6 */
1059                 0x1a000003,   /*                bne done */
1060                 0xe2522001,   /*                subs r2, r2, #1 */
1061                 0x0a000001,   /*                beq done */
1062                 0xe2811004,   /*                add r1, r1 #4 */
1063                 0xeafffff2,   /*                b loop */
1064                 0xeafffffe    /* done:  b -2 */
1065         };
1066
1067         static const u32 word_16_code[] = {
1068                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1069                 0xe1c130b0,   /*                strh r3, [r1] */
1070                 0xe1c140b0,   /*                strh r4, [r1] */
1071                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1072                 0xe0047005,   /*                and r7, r4, r5 */
1073                 0xe1570005,   /*                cmp r7, r5 */
1074                 0x1afffffb,   /*                bne busy */
1075                 0xe1140006,   /*                tst r4, r6 */
1076                 0x1a000003,   /*                bne done */
1077                 0xe2522001,   /*                subs r2, r2, #1 */
1078                 0x0a000001,   /*                beq done */
1079                 0xe2811002,   /*                add r1, r1 #2 */
1080                 0xeafffff2,   /*                b loop */
1081                 0xeafffffe    /* done:  b -2 */
1082         };
1083
1084         static const u32 word_8_code[] = {
1085                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1086                 0xe5c13000,   /*                strb r3, [r1] */
1087                 0xe5c14000,   /*                strb r4, [r1] */
1088                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1089                 0xe0047005,   /*                and r7, r4, r5 */
1090                 0xe1570005,   /*                cmp r7, r5 */
1091                 0x1afffffb,   /*                bne busy */
1092                 0xe1140006,   /*                tst r4, r6 */
1093                 0x1a000003,   /*                bne done */
1094                 0xe2522001,   /*                subs r2, r2, #1 */
1095                 0x0a000001,   /*                beq done */
1096                 0xe2811001,   /*                add r1, r1 #1 */
1097                 0xeafffff2,   /*                b loop */
1098                 0xeafffffe    /* done:  b -2 */
1099         };
1100         u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1101         const u32 *target_code_src;
1102         u32 target_code_size;
1103         int retval = ERROR_OK;
1104
1105
1106         cfi_intel_clear_status_register(bank);
1107
1108         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1109         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1110         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1111
1112         /* If we are setting up the write_algorith, we need target_code_src */
1113         /* if not we only need target_code_size.                                                                                                                */
1114         /*                                                                                                                                                                                                                                                                      */
1115         /* However, we don't want to create multiple code paths, so we                  */
1116         /* do the unecessary evaluation of target_code_src, which the                   */
1117         /* compiler will probably nicely optimize away if not needed                            */
1118
1119         /* prepare algorithm code for target endian */
1120         switch (bank->bus_width)
1121         {
1122         case 1 :
1123                 target_code_src = word_8_code;
1124                 target_code_size = sizeof(word_8_code);
1125                 break;
1126         case 2 :
1127                 target_code_src = word_16_code;
1128                 target_code_size = sizeof(word_16_code);
1129                 break;
1130         case 4 :
1131                 target_code_src = word_32_code;
1132                 target_code_size = sizeof(word_32_code);
1133                 break;
1134         default:
1135                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1136                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1137         }
1138
1139         /* flash write code */
1140         if (!cfi_info->write_algorithm)
1141         {
1142                 if ( target_code_size > sizeof(target_code) )
1143                 {
1144                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1145                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1146                 }
1147                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1148
1149                 /* Get memory for block write handler */
1150                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1151                 if (retval != ERROR_OK)
1152                 {
1153                         LOG_WARNING("No working area available, can't do block memory writes");
1154                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1155                 };
1156
1157                 /* write algorithm code to working area */
1158                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1159                 if (retval != ERROR_OK)
1160                 {
1161                         LOG_ERROR("Unable to write block write code to target");
1162                         goto cleanup;
1163                 }
1164         }
1165
1166         /* Get a workspace buffer for the data to flash starting with 32k size.
1167            Half size until buffer would be smaller 256 Bytem then fail back */
1168         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1169         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1170         {
1171                 buffer_size /= 2;
1172                 if (buffer_size <= 256)
1173                 {
1174                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1175                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1176                         goto cleanup;
1177                 }
1178         };
1179
1180         /* setup algo registers */
1181         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1182         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1183         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1184         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1185         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1186         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1187         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1188
1189         /* prepare command and status register patterns */
1190         write_command_val = cfi_command_val(bank, 0x40);
1191         busy_pattern_val  = cfi_command_val(bank, 0x80);
1192         error_pattern_val = cfi_command_val(bank, 0x7e);
1193
1194         LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1195
1196         /* Programming main loop */
1197         while (count > 0)
1198         {
1199                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1200                 u32 wsm_error;
1201
1202                 if((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1203                 {
1204                         goto cleanup;
1205                 }
1206
1207                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1208                 buf_set_u32(reg_params[1].value, 0, 32, address);
1209                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1210
1211                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1212                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1213                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1214
1215                 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1216
1217                 /* Execute algorithm, assume breakpoint for last instruction */
1218                 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1219                         cfi_info->write_algorithm->address,
1220                         cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1221                         10000, /* 10s should be enough for max. 32k of data */
1222                         &armv4_5_info);
1223
1224                 /* On failure try a fall back to direct word writes */
1225                 if (retval != ERROR_OK)
1226                 {
1227                         cfi_intel_clear_status_register(bank);
1228                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1229                         retval = ERROR_FLASH_OPERATION_FAILED;
1230                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1231                         /* FIXME To allow fall back or recovery, we must save the actual status
1232                            somewhere, so that a higher level code can start recovery. */
1233                         goto cleanup;
1234                 }
1235
1236                 /* Check return value from algo code */
1237                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1238                 if (wsm_error)
1239                 {
1240                         /* read status register (outputs debug inforation) */
1241                         cfi_intel_wait_status_busy(bank, 100);
1242                         cfi_intel_clear_status_register(bank);
1243                         retval = ERROR_FLASH_OPERATION_FAILED;
1244                         goto cleanup;
1245                 }
1246
1247                 buffer += thisrun_count;
1248                 address += thisrun_count;
1249                 count -= thisrun_count;
1250         }
1251
1252         /* free up resources */
1253 cleanup:
1254         if (source)
1255                 target_free_working_area(target, source);
1256
1257         if (cfi_info->write_algorithm)
1258         {
1259                 target_free_working_area(target, cfi_info->write_algorithm);
1260                 cfi_info->write_algorithm = NULL;
1261         }
1262
1263         destroy_reg_param(&reg_params[0]);
1264         destroy_reg_param(&reg_params[1]);
1265         destroy_reg_param(&reg_params[2]);
1266         destroy_reg_param(&reg_params[3]);
1267         destroy_reg_param(&reg_params[4]);
1268         destroy_reg_param(&reg_params[5]);
1269         destroy_reg_param(&reg_params[6]);
1270
1271         return retval;
1272 }
1273
1274 static int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1275 {
1276         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1277         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1278         target_t *target = bank->target;
1279         reg_param_t reg_params[10];
1280         armv4_5_algorithm_t armv4_5_info;
1281         working_area_t *source;
1282         u32 buffer_size = 32768;
1283         u32 status;
1284         int retval, retvaltemp;
1285         int exit_code = ERROR_OK;
1286
1287         /* input parameters - */
1288         /*      R0 = source address */
1289         /*      R1 = destination address */
1290         /*      R2 = number of writes */
1291         /*      R3 = flash write command */
1292         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1293         /* output parameters - */
1294         /*      R5 = 0x80 ok 0x00 bad */
1295         /* temp registers - */
1296         /*      R6 = value read from flash to test status */
1297         /*      R7 = holding register */
1298         /* unlock registers - */
1299         /*  R8 = unlock1_addr */
1300         /*  R9 = unlock1_cmd */
1301         /*  R10 = unlock2_addr */
1302         /*  R11 = unlock2_cmd */
1303
1304         static const u32 word_32_code[] = {
1305                                                 /* 00008100 <sp_32_code>:               */
1306                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1307                 0xe5889000,     /* str  r9, [r8]                                */
1308                 0xe58ab000,     /* str  r11, [r10]                              */
1309                 0xe5883000,     /* str  r3, [r8]                                */
1310                 0xe5815000,     /* str  r5, [r1]                                */
1311                 0xe1a00000,     /* nop                                                  */
1312                                                 /*                                                              */
1313                                                 /* 00008110 <sp_32_busy>:               */
1314                 0xe5916000,     /* ldr  r6, [r1]                                */
1315                 0xe0257006,     /* eor  r7, r5, r6                              */
1316                 0xe0147007,     /* ands r7, r4, r7                              */
1317                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1318                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1319                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1320                 0xe5916000,     /* ldr  r6, [r1]                                */
1321                 0xe0257006,     /* eor  r7, r5, r6                              */
1322                 0xe0147007,     /* ands r7, r4, r7                              */
1323                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1324                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1325                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1326                                                 /*                                                              */
1327                                 /* 00008140 <sp_32_cont>:                               */
1328                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1329                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1330                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1331                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1332                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1333                                                 /*                                                              */
1334                                                 /* 00008154 <sp_32_done>:               */
1335                 0xeafffffe              /* b    8154 <sp_32_done>               */
1336                 };
1337
1338                 static const u32 word_16_code[] = {
1339                                 /* 00008158 <sp_16_code>:              */
1340                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1341                 0xe1c890b0,     /* strh r9, [r8]                                */
1342                 0xe1cab0b0,     /* strh r11, [r10]                              */
1343                 0xe1c830b0,     /* strh r3, [r8]                                */
1344                 0xe1c150b0,     /* strh r5, [r1]                       */
1345                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1346                                 /*                                     */
1347                                 /* 00008168 <sp_16_busy>:              */
1348                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1349                 0xe0257006,     /* eor  r7, r5, r6                     */
1350                 0xe0147007,     /* ands r7, r4, r7                     */
1351                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1352                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1353                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1354                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1355                 0xe0257006,     /* eor  r7, r5, r6                     */
1356                 0xe0147007,     /* ands r7, r4, r7                     */
1357                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1358                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1359                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1360                                 /*                                     */
1361                                 /* 00008198 <sp_16_cont>:              */
1362                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1363                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1364                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1365                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1366                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1367                                 /*                                     */
1368                                 /* 000081ac <sp_16_done>:              */
1369                 0xeafffffe      /* b    81ac <sp_16_done>              */
1370                 };
1371
1372                 static const u32 word_8_code[] = {
1373                                 /* 000081b0 <sp_16_code_end>:          */
1374                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1375                 0xe5c89000,     /* strb r9, [r8]                                */
1376                 0xe5cab000,     /* strb r11, [r10]                              */
1377                 0xe5c83000,     /* strb r3, [r8]                                */
1378                 0xe5c15000,     /* strb r5, [r1]                       */
1379                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1380                                 /*                                     */
1381                                 /* 000081c0 <sp_8_busy>:               */
1382                 0xe5d16000,     /* ldrb r6, [r1]                       */
1383                 0xe0257006,     /* eor  r7, r5, r6                     */
1384                 0xe0147007,     /* ands r7, r4, r7                     */
1385                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1386                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1387                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1388                 0xe5d16000,     /* ldrb r6, [r1]                       */
1389                 0xe0257006,     /* eor  r7, r5, r6                     */
1390                 0xe0147007,     /* ands r7, r4, r7                     */
1391                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1392                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1393                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1394                                 /*                                     */
1395                                 /* 000081f0 <sp_8_cont>:               */
1396                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1397                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1398                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1399                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1400                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1401                                 /*                                     */
1402                                 /* 00008204 <sp_8_done>:               */
1403                 0xeafffffe      /* b    8204 <sp_8_done>               */
1404         };
1405
1406         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1407         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1408         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1409
1410         /* flash write code */
1411         if (!cfi_info->write_algorithm)
1412         {
1413                 u8 *target_code;
1414                 int target_code_size;
1415                 const u32 *src;
1416
1417                 /* convert bus-width dependent algorithm code to correct endiannes */
1418                 switch (bank->bus_width)
1419                 {
1420                 case 1:
1421                         src = word_8_code;
1422                         target_code_size = sizeof(word_8_code);
1423                         break;
1424                 case 2:
1425                         src = word_16_code;
1426                         target_code_size = sizeof(word_16_code);
1427                         break;
1428                 case 4:
1429                         src = word_32_code;
1430                         target_code_size = sizeof(word_32_code);
1431                         break;
1432                 default:
1433                         LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1434                         return ERROR_FLASH_OPERATION_FAILED;
1435                 }
1436                 target_code = malloc(target_code_size);
1437                 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1438
1439                 /* allocate working area */
1440                 retval=target_alloc_working_area(target, target_code_size,
1441                                 &cfi_info->write_algorithm);
1442                 if (retval != ERROR_OK)
1443                 {
1444                         free(target_code);
1445                         return retval;
1446                 }
1447
1448                 /* write algorithm code to working area */
1449                 if((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1450                                     target_code_size, target_code)) != ERROR_OK)
1451                 {
1452                         free(target_code);
1453                         return retval;
1454                 }
1455
1456                 free(target_code);
1457         }
1458         /* the following code still assumes target code is fixed 24*4 bytes */
1459
1460         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1461         {
1462                 buffer_size /= 2;
1463                 if (buffer_size <= 256)
1464                 {
1465                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1466                         if (cfi_info->write_algorithm)
1467                                 target_free_working_area(target, cfi_info->write_algorithm);
1468
1469                         LOG_WARNING("not enough working area available, can't do block memory writes");
1470                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1471                 }
1472         };
1473
1474         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1475         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1476         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1477         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1478         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1479         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1480         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1481         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1482         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1483         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1484
1485         while (count > 0)
1486         {
1487                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1488
1489                 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1490
1491                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1492                 buf_set_u32(reg_params[1].value, 0, 32, address);
1493                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1494                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1495                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1496                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1497                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1498                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1499                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1500
1501                 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1502                                                      cfi_info->write_algorithm->address,
1503                                                      cfi_info->write_algorithm->address + ((24 * 4) - 4),
1504                                                      10000, &armv4_5_info);
1505
1506                 status = buf_get_u32(reg_params[5].value, 0, 32);
1507
1508                 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1509                 {
1510                         LOG_DEBUG("status: 0x%x", status);
1511                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1512                         break;
1513                 }
1514
1515                 buffer += thisrun_count;
1516                 address += thisrun_count;
1517                 count -= thisrun_count;
1518         }
1519
1520         target_free_working_area(target, source);
1521
1522         destroy_reg_param(&reg_params[0]);
1523         destroy_reg_param(&reg_params[1]);
1524         destroy_reg_param(&reg_params[2]);
1525         destroy_reg_param(&reg_params[3]);
1526         destroy_reg_param(&reg_params[4]);
1527         destroy_reg_param(&reg_params[5]);
1528         destroy_reg_param(&reg_params[6]);
1529         destroy_reg_param(&reg_params[7]);
1530         destroy_reg_param(&reg_params[8]);
1531         destroy_reg_param(&reg_params[9]);
1532
1533         return exit_code;
1534 }
1535
1536 static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1537 {
1538         int retval;
1539         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1540         target_t *target = bank->target;
1541         u8 command[8];
1542
1543         cfi_intel_clear_status_register(bank);
1544         cfi_command(bank, 0x40, command);
1545         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1546         {
1547                 return retval;
1548         }
1549
1550         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1551         {
1552                 return retval;
1553         }
1554
1555         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1556         {
1557                 cfi_command(bank, 0xff, command);
1558                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1559                 {
1560                         return retval;
1561                 }
1562
1563                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1564                 return ERROR_FLASH_OPERATION_FAILED;
1565         }
1566
1567         return ERROR_OK;
1568 }
1569
1570 static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1571 {
1572         int retval;
1573         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1574         target_t *target = bank->target;
1575         u8 command[8];
1576
1577         /* Calculate buffer size and boundary mask */
1578         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1579         u32 buffermask = buffersize-1;
1580         u32 bufferwsize;
1581
1582         /* Check for valid range */
1583         if (address & buffermask)
1584         {
1585                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1586                 return ERROR_FLASH_OPERATION_FAILED;
1587         }
1588         switch(bank->chip_width)
1589         {
1590         case 4 : bufferwsize = buffersize / 4; break;
1591         case 2 : bufferwsize = buffersize / 2; break;
1592         case 1 : bufferwsize = buffersize; break;
1593         default:
1594                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1595                 return ERROR_FLASH_OPERATION_FAILED;
1596         }
1597
1598         bufferwsize/=(bank->bus_width / bank->chip_width);
1599
1600
1601         /* Check for valid size */
1602         if (wordcount > bufferwsize)
1603         {
1604                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1605                 return ERROR_FLASH_OPERATION_FAILED;
1606         }
1607
1608         /* Write to flash buffer */
1609         cfi_intel_clear_status_register(bank);
1610
1611         /* Initiate buffer operation _*/
1612         cfi_command(bank, 0xE8, command);
1613         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1614         {
1615                 return retval;
1616         }
1617         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1618         {
1619                 cfi_command(bank, 0xff, command);
1620                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1621                 {
1622                         return retval;
1623                 }
1624
1625                 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1626                 return ERROR_FLASH_OPERATION_FAILED;
1627         }
1628
1629         /* Write buffer wordcount-1 and data words */
1630         cfi_command(bank, bufferwsize-1, command);
1631         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1632         {
1633                 return retval;
1634         }
1635
1636         if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1637         {
1638                 return retval;
1639         }
1640
1641         /* Commit write operation */
1642         cfi_command(bank, 0xd0, command);
1643         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1644         {
1645                 return retval;
1646         }
1647         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1648         {
1649                 cfi_command(bank, 0xff, command);
1650                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1651                 {
1652                         return retval;
1653                 }
1654
1655                 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1656                 return ERROR_FLASH_OPERATION_FAILED;
1657         }
1658
1659         return ERROR_OK;
1660 }
1661
1662 static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1663 {
1664         int retval;
1665         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1666         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1667         target_t *target = bank->target;
1668         u8 command[8];
1669
1670         cfi_command(bank, 0xaa, command);
1671         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1672         {
1673                 return retval;
1674         }
1675
1676         cfi_command(bank, 0x55, command);
1677         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1678         {
1679                 return retval;
1680         }
1681
1682         cfi_command(bank, 0xa0, command);
1683         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1684         {
1685                 return retval;
1686         }
1687
1688         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1689         {
1690                 return retval;
1691         }
1692
1693         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1694         {
1695                 cfi_command(bank, 0xf0, command);
1696                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1697                 {
1698                         return retval;
1699                 }
1700
1701                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1702                 return ERROR_FLASH_OPERATION_FAILED;
1703         }
1704
1705         return ERROR_OK;
1706 }
1707
1708 static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1709 {
1710         int retval;
1711         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1712         target_t *target = bank->target;
1713         u8 command[8];
1714         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1715
1716         /* Calculate buffer size and boundary mask */
1717         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1718         u32 buffermask = buffersize-1;
1719         u32 bufferwsize;
1720
1721         /* Check for valid range */
1722         if (address & buffermask)
1723         {
1724                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1725                 return ERROR_FLASH_OPERATION_FAILED;
1726         }
1727         switch(bank->chip_width)
1728         {
1729         case 4 : bufferwsize = buffersize / 4; break;
1730         case 2 : bufferwsize = buffersize / 2; break;
1731         case 1 : bufferwsize = buffersize; break;
1732         default:
1733                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1734                 return ERROR_FLASH_OPERATION_FAILED;
1735         }
1736
1737         bufferwsize/=(bank->bus_width / bank->chip_width);
1738
1739         /* Check for valid size */
1740         if (wordcount > bufferwsize)
1741         {
1742                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1743                 return ERROR_FLASH_OPERATION_FAILED;
1744         }
1745
1746         // Unlock
1747         cfi_command(bank, 0xaa, command);
1748         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1749         {
1750                 return retval;
1751         }
1752
1753         cfi_command(bank, 0x55, command);
1754         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1755         {
1756                 return retval;
1757         }
1758
1759         // Buffer load command
1760         cfi_command(bank, 0x25, command);
1761         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1762         {
1763                 return retval;
1764         }
1765
1766         /* Write buffer wordcount-1 and data words */
1767         cfi_command(bank, bufferwsize-1, command);
1768         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1769         {
1770                 return retval;
1771         }
1772
1773         if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1774         {
1775                 return retval;
1776         }
1777
1778         /* Commit write operation */
1779         cfi_command(bank, 0x29, command);
1780         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1781         {
1782                 return retval;
1783         }
1784
1785         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1786         {
1787                 cfi_command(bank, 0xf0, command);
1788                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1789                 {
1790                         return retval;
1791                 }
1792
1793                 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
1794                 return ERROR_FLASH_OPERATION_FAILED;
1795         }
1796
1797         return ERROR_OK;
1798 }
1799
1800 static int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1801 {
1802         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1803
1804         switch(cfi_info->pri_id)
1805         {
1806                 case 1:
1807                 case 3:
1808                         return cfi_intel_write_word(bank, word, address);
1809                         break;
1810                 case 2:
1811                         return cfi_spansion_write_word(bank, word, address);
1812                         break;
1813                 default:
1814                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1815                         break;
1816         }
1817
1818         return ERROR_FLASH_OPERATION_FAILED;
1819 }
1820
1821 static int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1822 {
1823         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1824
1825         switch(cfi_info->pri_id)
1826         {
1827                 case 1:
1828                 case 3:
1829                         return cfi_intel_write_words(bank, word, wordcount, address);
1830                         break;
1831                 case 2:
1832                         return cfi_spansion_write_words(bank, word, wordcount, address);
1833                         break;
1834                 default:
1835                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1836                         break;
1837         }
1838
1839         return ERROR_FLASH_OPERATION_FAILED;
1840 }
1841
1842 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1843 {
1844         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1845         target_t *target = bank->target;
1846         u32 address = bank->base + offset;      /* address of first byte to be programmed */
1847         u32 write_p, copy_p;
1848         int align;      /* number of unaligned bytes */
1849         int blk_count; /* number of bus_width bytes for block copy */
1850         u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1851         int i;
1852         int retval;
1853
1854         if (bank->target->state != TARGET_HALTED)
1855         {
1856                 LOG_ERROR("Target not halted");
1857                 return ERROR_TARGET_NOT_HALTED;
1858         }
1859
1860         if (offset + count > bank->size)
1861                 return ERROR_FLASH_DST_OUT_OF_BANK;
1862
1863         if (cfi_info->qry[0] != 'Q')
1864                 return ERROR_FLASH_BANK_NOT_PROBED;
1865
1866         /* start at the first byte of the first word (bus_width size) */
1867         write_p = address & ~(bank->bus_width - 1);
1868         if ((align = address - write_p) != 0)
1869         {
1870                 LOG_INFO("Fixup %d unaligned head bytes", align );
1871
1872                 for (i = 0; i < bank->bus_width; i++)
1873                         current_word[i] = 0;
1874                 copy_p = write_p;
1875
1876                 /* copy bytes before the first write address */
1877                 for (i = 0; i < align; ++i, ++copy_p)
1878                 {
1879                         u8 byte;
1880                         if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1881                         {
1882                                 return retval;
1883                         }
1884                         cfi_add_byte(bank, current_word, byte);
1885                 }
1886
1887                 /* add bytes from the buffer */
1888                 for (; (i < bank->bus_width) && (count > 0); i++)
1889                 {
1890                         cfi_add_byte(bank, current_word, *buffer++);
1891                         count--;
1892                         copy_p++;
1893                 }
1894
1895                 /* if the buffer is already finished, copy bytes after the last write address */
1896                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1897                 {
1898                         u8 byte;
1899                         if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1900                         {
1901                                 return retval;
1902                         }
1903                         cfi_add_byte(bank, current_word, byte);
1904                 }
1905
1906                 retval = cfi_write_word(bank, current_word, write_p);
1907                 if (retval != ERROR_OK)
1908                         return retval;
1909                 write_p = copy_p;
1910         }
1911
1912         /* handle blocks of bus_size aligned bytes */
1913         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1914         switch(cfi_info->pri_id)
1915         {
1916                 /* try block writes (fails without working area) */
1917                 case 1:
1918                 case 3:
1919                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1920                         break;
1921                 case 2:
1922                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1923                         break;
1924                 default:
1925                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1926                         retval = ERROR_FLASH_OPERATION_FAILED;
1927                         break;
1928         }
1929         if (retval == ERROR_OK)
1930         {
1931                 /* Increment pointers and decrease count on succesful block write */
1932                 buffer += blk_count;
1933                 write_p += blk_count;
1934                 count -= blk_count;
1935         }
1936         else
1937         {
1938                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1939                 {
1940                         //adjust buffersize for chip width
1941                         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1942                         u32 buffermask = buffersize-1;
1943                         u32 bufferwsize;
1944
1945                         switch(bank->chip_width)
1946                         {
1947                         case 4 : bufferwsize = buffersize / 4; break;
1948                         case 2 : bufferwsize = buffersize / 2; break;
1949                         case 1 : bufferwsize = buffersize; break;
1950                         default:
1951                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1952                                 return ERROR_FLASH_OPERATION_FAILED;
1953                         }
1954
1955                         bufferwsize/=(bank->bus_width / bank->chip_width);
1956
1957                         /* fall back to memory writes */
1958                         while (count >= (u32)bank->bus_width)
1959                         {
1960                                 int fallback;
1961                                 if ((write_p & 0xff) == 0)
1962                                 {
1963                                         LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1964                                 }
1965                                 fallback = 1;
1966                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1967                                 {
1968                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1969                                         if (retval == ERROR_OK)
1970                                         {
1971                                                 buffer += buffersize;
1972                                                 write_p += buffersize;
1973                                                 count -= buffersize;
1974                                                 fallback=0;
1975                                         }
1976                                 }
1977                                 /* try the slow way? */
1978                                 if (fallback)
1979                                 {
1980                                         for (i = 0; i < bank->bus_width; i++)
1981                                                 current_word[i] = 0;
1982
1983                                         for (i = 0; i < bank->bus_width; i++)
1984                                         {
1985                                                 cfi_add_byte(bank, current_word, *buffer++);
1986                                         }
1987
1988                                         retval = cfi_write_word(bank, current_word, write_p);
1989                                         if (retval != ERROR_OK)
1990                                                 return retval;
1991
1992                                         write_p += bank->bus_width;
1993                                         count -= bank->bus_width;
1994                                 }
1995                         }
1996                 }
1997                 else
1998                         return retval;
1999         }
2000
2001         /* return to read array mode, so we can read from flash again for padding */
2002         cfi_command(bank, 0xf0, current_word);
2003         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2004         {
2005                 return retval;
2006         }
2007         cfi_command(bank, 0xff, current_word);
2008         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2009         {
2010                 return retval;
2011         }
2012
2013         /* handle unaligned tail bytes */
2014         if (count > 0)
2015         {
2016                 LOG_INFO("Fixup %d unaligned tail bytes", count );
2017
2018                 copy_p = write_p;
2019                 for (i = 0; i < bank->bus_width; i++)
2020                         current_word[i] = 0;
2021
2022                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2023                 {
2024                         cfi_add_byte(bank, current_word, *buffer++);
2025                         count--;
2026                 }
2027                 for (; i < bank->bus_width; ++i, ++copy_p)
2028                 {
2029                         u8 byte;
2030                         if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2031                         {
2032                                 return retval;
2033                         }
2034                         cfi_add_byte(bank, current_word, byte);
2035                 }
2036                 retval = cfi_write_word(bank, current_word, write_p);
2037                 if (retval != ERROR_OK)
2038                         return retval;
2039         }
2040
2041         /* return to read array mode */
2042         cfi_command(bank, 0xf0, current_word);
2043         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2044         {
2045                 return retval;
2046         }
2047         cfi_command(bank, 0xff, current_word);
2048         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2049 }
2050
2051 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2052 {
2053         (void) param;
2054         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2055         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2056
2057         pri_ext->_reversed_geometry = 1;
2058 }
2059
2060 static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2061 {
2062         int i;
2063         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2064         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2065         (void) param;
2066
2067         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2068         {
2069                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2070
2071                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2072                 {
2073                         int j = (cfi_info->num_erase_regions - 1) - i;
2074                         u32 swap;
2075
2076                         swap = cfi_info->erase_region_info[i];
2077                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2078                         cfi_info->erase_region_info[j] = swap;
2079                 }
2080         }
2081 }
2082
2083 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2084 {
2085         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2086         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2087         cfi_unlock_addresses_t *unlock_addresses = param;
2088
2089         pri_ext->_unlock1 = unlock_addresses->unlock1;
2090         pri_ext->_unlock2 = unlock_addresses->unlock2;
2091 }
2092
2093 static int cfi_probe(struct flash_bank_s *bank)
2094 {
2095         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2096         target_t *target = bank->target;
2097         u8 command[8];
2098         int num_sectors = 0;
2099         int i;
2100         int sector = 0;
2101         u32 unlock1 = 0x555;
2102         u32 unlock2 = 0x2aa;
2103         int retval;
2104
2105         if (bank->target->state != TARGET_HALTED)
2106         {
2107                 LOG_ERROR("Target not halted");
2108                 return ERROR_TARGET_NOT_HALTED;
2109         }
2110
2111         cfi_info->probed = 0;
2112
2113         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2114          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2115          */
2116         if (cfi_info->jedec_probe)
2117         {
2118                 unlock1 = 0x5555;
2119                 unlock2 = 0x2aaa;
2120         }
2121
2122         /* switch to read identifier codes mode ("AUTOSELECT") */
2123         cfi_command(bank, 0xaa, command);
2124         if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2125         {
2126                 return retval;
2127         }
2128         cfi_command(bank, 0x55, command);
2129         if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2130         {
2131                 return retval;
2132         }
2133         cfi_command(bank, 0x90, command);
2134         if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2135         {
2136                 return retval;
2137         }
2138
2139         if (bank->chip_width == 1)
2140         {
2141                 u8 manufacturer, device_id;
2142                 if((retval = target_read_u8(target, bank->base + 0x0, &manufacturer)) != ERROR_OK)
2143                 {
2144                         return retval;
2145                 }
2146                 if((retval = target_read_u8(target, bank->base + 0x1, &device_id)) != ERROR_OK)
2147                 {
2148                         return retval;
2149                 }
2150                 cfi_info->manufacturer = manufacturer;
2151                 cfi_info->device_id = device_id;
2152         }
2153         else if (bank->chip_width == 2)
2154         {
2155                 if((retval = target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer)) != ERROR_OK)
2156                 {
2157                         return retval;
2158                 }
2159                 if((retval = target_read_u16(target, bank->base + 0x2, &cfi_info->device_id)) != ERROR_OK)
2160                 {
2161                         return retval;
2162                 }
2163         }
2164
2165         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2166         /* switch back to read array mode */
2167         cfi_command(bank, 0xf0, command);
2168         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2169         {
2170                 return retval;
2171         }
2172         cfi_command(bank, 0xff, command);
2173         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2174         {
2175                 return retval;
2176         }
2177
2178         /* check device/manufacturer ID for known non-CFI flashes. */
2179         cfi_fixup_non_cfi(bank);
2180
2181         /* query only if this is a CFI compatible flash,
2182          * otherwise the relevant info has already been filled in
2183          */
2184         if (cfi_info->not_cfi == 0)
2185         {
2186                 /* enter CFI query mode
2187                  * according to JEDEC Standard No. 68.01,
2188                  * a single bus sequence with address = 0x55, data = 0x98 should put
2189                  * the device into CFI query mode.
2190                  *
2191                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2192                  */
2193                 cfi_command(bank, 0x98, command);
2194                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2195                 {
2196                         return retval;
2197                 }
2198
2199                 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2200                 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2201                 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2202
2203                 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2204
2205                 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2206                 {
2207                         cfi_command(bank, 0xf0, command);
2208                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2209                         {
2210                                 return retval;
2211                         }
2212                         cfi_command(bank, 0xff, command);
2213                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2214                         {
2215                                 return retval;
2216                         }
2217                         LOG_ERROR("Could not probe bank: no QRY");
2218                         return ERROR_FLASH_BANK_INVALID;
2219                 }
2220
2221                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2222                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2223                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2224                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2225
2226                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2227
2228                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2229                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2230                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2231                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2232                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2233                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2234                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2235                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2236                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2237                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2238                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2239                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2240
2241                 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2242                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2243                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2244                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2245                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2246                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2247                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2248                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2249                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2250                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2251                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2252
2253                 cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
2254                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2255                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2256                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2257
2258                 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2259
2260                 if (cfi_info->num_erase_regions)
2261                 {
2262                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2263                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2264                         {
2265                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2266                                 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2267                         }
2268                 }
2269                 else
2270                 {
2271                         cfi_info->erase_region_info = NULL;
2272                 }
2273
2274                 /* We need to read the primary algorithm extended query table before calculating
2275                  * the sector layout to be able to apply fixups
2276                  */
2277                 switch(cfi_info->pri_id)
2278                 {
2279                         /* Intel command set (standard and extended) */
2280                         case 0x0001:
2281                         case 0x0003:
2282                                 cfi_read_intel_pri_ext(bank);
2283                                 break;
2284                         /* AMD/Spansion, Atmel, ... command set */
2285                         case 0x0002:
2286                                 cfi_read_0002_pri_ext(bank);
2287                                 break;
2288                         default:
2289                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2290                                 break;
2291                 }
2292
2293                 /* return to read array mode
2294                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2295                  */
2296                 cfi_command(bank, 0xf0, command);
2297                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2298                 {
2299                         return retval;
2300                 }
2301                 cfi_command(bank, 0xff, command);
2302                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2303                 {
2304                         return retval;
2305                 }
2306         }
2307
2308         /* apply fixups depending on the primary command set */
2309         switch(cfi_info->pri_id)
2310         {
2311                 /* Intel command set (standard and extended) */
2312                 case 0x0001:
2313                 case 0x0003:
2314                         cfi_fixup(bank, cfi_0001_fixups);
2315                         break;
2316                 /* AMD/Spansion, Atmel, ... command set */
2317                 case 0x0002:
2318                         cfi_fixup(bank, cfi_0002_fixups);
2319                         break;
2320                 default:
2321                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2322                         break;
2323         }
2324
2325         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2326         {
2327                 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, cfi_info->dev_size);
2328         }
2329
2330         if (cfi_info->num_erase_regions == 0)
2331         {
2332                 /* a device might have only one erase block, spanning the whole device */
2333                 bank->num_sectors = 1;
2334                 bank->sectors = malloc(sizeof(flash_sector_t));
2335
2336                 bank->sectors[sector].offset = 0x0;
2337                 bank->sectors[sector].size = bank->size;
2338                 bank->sectors[sector].is_erased = -1;
2339                 bank->sectors[sector].is_protected = -1;
2340         }
2341         else
2342         {
2343                 u32 offset = 0;
2344
2345                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2346                 {
2347                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2348                 }
2349
2350                 bank->num_sectors = num_sectors;
2351                 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2352
2353                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2354                 {
2355                         u32 j;
2356                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2357                         {
2358                                 bank->sectors[sector].offset = offset;
2359                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2360                                 offset += bank->sectors[sector].size;
2361                                 bank->sectors[sector].is_erased = -1;
2362                                 bank->sectors[sector].is_protected = -1;
2363                                 sector++;
2364                         }
2365                 }
2366                 if (offset != cfi_info->dev_size)
2367                 {
2368                         LOG_WARNING("CFI size is 0x%x, but total sector size is 0x%x", cfi_info->dev_size, offset);
2369                 }
2370         }
2371
2372         cfi_info->probed = 1;
2373
2374         return ERROR_OK;
2375 }
2376
2377 static int cfi_auto_probe(struct flash_bank_s *bank)
2378 {
2379         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2380         if (cfi_info->probed)
2381                 return ERROR_OK;
2382         return cfi_probe(bank);
2383 }
2384
2385
2386 static int cfi_intel_protect_check(struct flash_bank_s *bank)
2387 {
2388         int retval;
2389         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2390         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2391         target_t *target = bank->target;
2392         u8 command[CFI_MAX_BUS_WIDTH];
2393         int i;
2394
2395         /* check if block lock bits are supported on this device */
2396         if (!(pri_ext->blk_status_reg_mask & 0x1))
2397                 return ERROR_FLASH_OPERATION_FAILED;
2398
2399         cfi_command(bank, 0x90, command);
2400         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2401         {
2402                 return retval;
2403         }
2404
2405         for (i = 0; i < bank->num_sectors; i++)
2406         {
2407                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2408
2409                 if (block_status & 1)
2410                         bank->sectors[i].is_protected = 1;
2411                 else
2412                         bank->sectors[i].is_protected = 0;
2413         }
2414
2415         cfi_command(bank, 0xff, command);
2416         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2417 }
2418
2419 static int cfi_spansion_protect_check(struct flash_bank_s *bank)
2420 {
2421         int retval;
2422         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2423         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2424         target_t *target = bank->target;
2425         u8 command[8];
2426         int i;
2427
2428         cfi_command(bank, 0xaa, command);
2429         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2430         {
2431                 return retval;
2432         }
2433
2434         cfi_command(bank, 0x55, command);
2435         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2436         {
2437                 return retval;
2438         }
2439
2440         cfi_command(bank, 0x90, command);
2441         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2442         {
2443                 return retval;
2444         }
2445
2446         for (i = 0; i < bank->num_sectors; i++)
2447         {
2448                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2449
2450                 if (block_status & 1)
2451                         bank->sectors[i].is_protected = 1;
2452                 else
2453                         bank->sectors[i].is_protected = 0;
2454         }
2455
2456         cfi_command(bank, 0xf0, command);
2457         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2458 }
2459
2460 static int cfi_protect_check(struct flash_bank_s *bank)
2461 {
2462         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2463
2464         if (bank->target->state != TARGET_HALTED)
2465         {
2466                 LOG_ERROR("Target not halted");
2467                 return ERROR_TARGET_NOT_HALTED;
2468         }
2469
2470         if (cfi_info->qry[0] != 'Q')
2471                 return ERROR_FLASH_BANK_NOT_PROBED;
2472
2473         switch(cfi_info->pri_id)
2474         {
2475                 case 1:
2476                 case 3:
2477                         return cfi_intel_protect_check(bank);
2478                         break;
2479                 case 2:
2480                         return cfi_spansion_protect_check(bank);
2481                         break;
2482                 default:
2483                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2484                         break;
2485         }
2486
2487         return ERROR_OK;
2488 }
2489
2490 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2491 {
2492         int printed;
2493         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2494
2495         if (cfi_info->qry[0] == (char)-1)
2496         {
2497                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2498                 return ERROR_OK;
2499         }
2500
2501         if (cfi_info->not_cfi == 0)
2502                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2503         else
2504                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2505         buf += printed;
2506         buf_size -= printed;
2507
2508         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2509                 cfi_info->manufacturer, cfi_info->device_id);
2510         buf += printed;
2511         buf_size -= printed;
2512
2513         if (cfi_info->not_cfi == 0)
2514         {
2515         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2516         buf += printed;
2517         buf_size -= printed;
2518
2519                 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2520                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2521         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2522         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2523         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2524         buf += printed;
2525         buf_size -= printed;
2526
2527                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2528                                    1 << cfi_info->word_write_timeout_typ,
2529                                    1 << cfi_info->buf_write_timeout_typ,
2530                                    1 << cfi_info->block_erase_timeout_typ,
2531                                    1 << cfi_info->chip_erase_timeout_typ);
2532         buf += printed;
2533         buf_size -= printed;
2534
2535                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2536                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2537                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2538                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2539                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2540         buf += printed;
2541         buf_size -= printed;
2542
2543                 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2544                                    cfi_info->dev_size,
2545                                    cfi_info->interface_desc,
2546                                    1 << cfi_info->max_buf_write_size);
2547         buf += printed;
2548         buf_size -= printed;
2549
2550         switch(cfi_info->pri_id)
2551         {
2552                 case 1:
2553                 case 3:
2554                         cfi_intel_info(bank, buf, buf_size);
2555                         break;
2556                 case 2:
2557                         cfi_spansion_info(bank, buf, buf_size);
2558                         break;
2559                 default:
2560                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2561                         break;
2562         }
2563         }
2564
2565         return ERROR_OK;
2566 }