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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   partially based on                                                    *
   6  *       linux/include/linux/mtd/nand.h                                        *
   7  *                                                                         *
   8  *   Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>                   *
   9  *                      Steven J. Hill <sjhill@realitydiluted.com>         *
  10  *                      Thomas Gleixner <tglx@linutronix.de>               *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program; if not, write to the                         *
  24  *   Free Software Foundation, Inc.,                                       *
  25  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  26  ***************************************************************************/
  27 #ifndef NAND_H
  28 #define NAND_H
  29
  30 #include "flash.h"
  31
  32 struct nand_device_s;
  33
  34 typedef struct nand_flash_controller_s
  35 {
  36         char *name;
  37         int (*nand_device_command)(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
  38         int (*register_commands)(struct command_context_s *cmd_ctx);
  39         int (*init)(struct nand_device_s *device);
  40         int (*reset)(struct nand_device_s *device);
  41         int (*command)(struct nand_device_s *device, u8 command);
  42         int (*address)(struct nand_device_s *device, u8 address);
  43         int (*write_data)(struct nand_device_s *device, u16 data);
  44         int (*read_data)(struct nand_device_s *device, void *data);
  45         int (*write_block_data)(struct nand_device_s *device, u8 *data, int size);
  46         int (*read_block_data)(struct nand_device_s *device, u8 *data, int size);
  47         int (*write_page)(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  48         int (*read_page)(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  49         int (*controller_ready)(struct nand_device_s *device, int timeout);
  50         int (*nand_ready)(struct nand_device_s *device, int timeout);
  51 } nand_flash_controller_t;
  52
  53 typedef struct nand_block_s
  54 {
  55         u32 offset;
  56         u32 size;
  57         int is_erased;
  58         int is_bad;
  59 } nand_block_t;
  60
  61 typedef struct nand_device_s
  62 {
  63         nand_flash_controller_t *controller;
  64         void *controller_priv;
  65         struct nand_manufacturer_s *manufacturer;
  66         struct nand_info_s *device;
  67         int bus_width;
  68         int address_cycles;
  69         int page_size;
  70         int erase_size;
  71         int use_raw;
  72         int num_blocks;
  73         nand_block_t *blocks;
  74         struct nand_device_s *next;
  75 } nand_device_t;
  76
  77 /* NAND Flash Manufacturer ID Codes
  78  */
  79 enum
  80 {
  81         NAND_MFR_TOSHIBA = 0x98,
  82         NAND_MFR_SAMSUNG = 0xec,
  83         NAND_MFR_FUJITSU = 0x04,
  84         NAND_MFR_NATIONAL = 0x8f,
  85         NAND_MFR_RENESAS = 0x07,
  86         NAND_MFR_STMICRO = 0x20,
  87         NAND_MFR_HYNIX = 0xad,
  88 };
  89
  90 typedef struct nand_manufacturer_s
  91 {
  92     int id;
  93         char *name;
  94 } nand_manufacturer_t;
  95
  96 typedef struct nand_info_s
  97 {
  98         char *name;
  99         int id;
 100         int page_size;
 101         int chip_size;
 102         int erase_size;
 103         int options;
 104 } nand_info_t;
 105
 106 /* Option constants for bizarre disfunctionality and real features
 107  */
 108 enum {
 109         /* Chip can not auto increment pages */
 110         NAND_NO_AUTOINCR = 0x00000001,
 111
 112         /* Buswitdh is 16 bit */
 113         NAND_BUSWIDTH_16 = 0x00000002,
 114
 115         /* Device supports partial programming without padding */
 116         NAND_NO_PADDING = 0x00000004,
 117
 118         /* Chip has cache program function */
 119         NAND_CACHEPRG = 0x00000008,
 120
 121         /* Chip has copy back function */
 122         NAND_COPYBACK = 0x00000010,
 123
 124         /* AND Chip which has 4 banks and a confusing page / block
 125          * assignment. See Renesas datasheet for further information */
 126         NAND_IS_AND = 0x00000020,
 127
 128         /* Chip has a array of 4 pages which can be read without
 129          * additional ready /busy waits */
 130         NAND_4PAGE_ARRAY = 0x00000040,
 131
 132         /* Chip requires that BBT is periodically rewritten to prevent
 133          * bits from adjacent blocks from 'leaking' in altering data.
 134          * This happens with the Renesas AG-AND chips, possibly others.  */
 135         BBT_AUTO_REFRESH = 0x00000080,
 136
 137         /* Chip does not require ready check on read. True
 138          * for all large page devices, as they do not support
 139          * autoincrement.*/
 140         NAND_NO_READRDY = 0x00000100,
 141
 142         /* Options valid for Samsung large page devices */
 143         NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
 144
 145         /* Options for new chips with large page size. The pagesize and the
 146          * erasesize is determined from the extended id bytes
 147          */
 148         LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
 149         LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
 150 };
 151
 152 enum
 153 {
 154         /* Standard NAND flash commands */
 155         NAND_CMD_READ0 = 0x0,
 156         NAND_CMD_READ1 = 0x1,
 157         NAND_CMD_RNDOUT = 0x5,
 158         NAND_CMD_PAGEPROG = 0x10,
 159         NAND_CMD_READOOB = 0x50,
 160         NAND_CMD_ERASE1 = 0x60,
 161         NAND_CMD_STATUS = 0x70,
 162         NAND_CMD_STATUS_MULTI = 0x71,
 163         NAND_CMD_SEQIN = 0x80,
 164         NAND_CMD_RNDIN = 0x85,
 165         NAND_CMD_READID = 0x90,
 166         NAND_CMD_ERASE2 = 0xd0,
 167         NAND_CMD_RESET = 0xff,
 168
 169         /* Extended commands for large page devices */
 170         NAND_CMD_READSTART = 0x30,
 171         NAND_CMD_RNDOUTSTART = 0xE0,
 172         NAND_CMD_CACHEDPROG = 0x15,
 173 };
 174
 175 /* Status bits */
 176 enum
 177 {
 178         NAND_STATUS_FAIL = 0x01,
 179         NAND_STATUS_FAIL_N1 = 0x02,
 180         NAND_STATUS_TRUE_READY = 0x20,
 181         NAND_STATUS_READY = 0x40,
 182         NAND_STATUS_WP = 0x80,
 183 };
 184
 185 /* OOB (spare) data formats */
 186 enum oob_formats
 187 {
 188         NAND_OOB_NONE = 0x0,    /* no OOB data at all */
 189         NAND_OOB_RAW = 0x1,             /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
 190         NAND_OOB_ONLY = 0x2,    /* only OOB data */
 191         NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
 192         NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
 193         NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
 194         NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
 195 };
 196
 197 /* Function prototypes */
 198 extern nand_device_t *get_nand_device_by_num(int num);
 199 extern int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
 200 extern int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
 201 extern int nand_read_status(struct nand_device_s *device, u8 *status);
 202
 203 extern int nand_register_commands(struct command_context_s *cmd_ctx);
 204 extern int nand_init(struct command_context_s *cmd_ctx);
 205
 206 #define         ERROR_NAND_DEVICE_INVALID               (-1100)
 207 #define         ERROR_NAND_OPERATION_FAILED             (-1101)
 208 #define         ERROR_NAND_OPERATION_TIMEOUT    (-1102)
 209 #define         ERROR_NAND_OPERATION_NOT_SUPPORTED      (-1103)
 210 #define         ERROR_NAND_DEVICE_NOT_PROBED    (-1104)
 211 #define         ERROR_NAND_ERROR_CORRECTION_FAILED      (-1105)
 212
 213 #endif /* NAND_H */