git.sur5r.net Git - openocd/blob - src/flash/nor/efm32.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *                                                                         *
  11  *   Copyright (C) 2013 by Roman Dmitrienko                                *
  12  *   me@iamroman.org                                                       *
  13  *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  28  ***************************************************************************/
  29
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "imp.h"
  35 #include <helper/binarybuffer.h>
  36 #include <target/algorithm.h>
  37 #include <target/armv7m.h>
  38 #include <target/cortex_m.h>
  39
  40 /* keep family IDs in decimal */
  41 #define EFM_FAMILY_ID_GECKO             71
  42 #define EFM_FAMILY_ID_GIANT_GECKO       72
  43 #define EFM_FAMILY_ID_TINY_GECKO        73
  44 #define EFM_FAMILY_ID_LEOPARD_GECKO     74
  45 #define EFM_FAMILY_ID_WONDER_GECKO      75
  46
  47 #define EFM32_FLASH_ERASE_TMO           100
  48 #define EFM32_FLASH_WDATAREADY_TMO      100
  49 #define EFM32_FLASH_WRITE_TMO           100
  50
  51 /* size in bytes, not words; must fit all Gecko devices */
  52 #define LOCKBITS_PAGE_SZ                512
  53
  54 #define EFM32_MSC_INFO_BASE             0x0fe00000
  55
  56 #define EFM32_MSC_USER_DATA             EFM32_MSC_INFO_BASE
  57 #define EFM32_MSC_LOCK_BITS             (EFM32_MSC_INFO_BASE+0x4000)
  58 #define EFM32_MSC_DEV_INFO              (EFM32_MSC_INFO_BASE+0x8000)
  59
  60 /* PAGE_SIZE is only present in Leopard and Giant Gecko MCUs */
  61 #define EFM32_MSC_DI_PAGE_SIZE          (EFM32_MSC_DEV_INFO+0x1e7)
  62 #define EFM32_MSC_DI_FLASH_SZ           (EFM32_MSC_DEV_INFO+0x1f8)
  63 #define EFM32_MSC_DI_RAM_SZ             (EFM32_MSC_DEV_INFO+0x1fa)
  64 #define EFM32_MSC_DI_PART_NUM           (EFM32_MSC_DEV_INFO+0x1fc)
  65 #define EFM32_MSC_DI_PART_FAMILY        (EFM32_MSC_DEV_INFO+0x1fe)
  66 #define EFM32_MSC_DI_PROD_REV           (EFM32_MSC_DEV_INFO+0x1ff)
  67
  68 #define EFM32_MSC_REGBASE               0x400c0000
  69 #define EFM32_MSC_WRITECTRL             (EFM32_MSC_REGBASE+0x008)
  70 #define EFM32_MSC_WRITECTRL_WREN_MASK   0x1
  71 #define EFM32_MSC_WRITECMD              (EFM32_MSC_REGBASE+0x00c)
  72 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
  73 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
  74 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
  75 #define EFM32_MSC_ADDRB                 (EFM32_MSC_REGBASE+0x010)
  76 #define EFM32_MSC_WDATA                 (EFM32_MSC_REGBASE+0x018)
  77 #define EFM32_MSC_STATUS                (EFM32_MSC_REGBASE+0x01c)
  78 #define EFM32_MSC_STATUS_BUSY_MASK      0x1
  79 #define EFM32_MSC_STATUS_LOCKED_MASK    0x2
  80 #define EFM32_MSC_STATUS_INVADDR_MASK   0x4
  81 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
  82 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
  83 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
  84 #define EFM32_MSC_LOCK                  (EFM32_MSC_REGBASE+0x03c)
  85 #define EFM32_MSC_LOCK_LOCKKEY          0x1b71
  86
  87 struct efm32x_flash_bank {
  88         int probed;
  89         uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
  90 };
  91
  92 struct efm32_info {
  93         uint16_t flash_sz_kib;
  94         uint16_t ram_sz_kib;
  95         uint16_t part_num;
  96         uint8_t part_family;
  97         uint8_t prod_rev;
  98         uint16_t page_size;
  99 };
 100
 101 static int efm32x_write(struct flash_bank *bank, uint8_t *buffer,
 102         uint32_t offset, uint32_t count);
 103
 104 static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
 105 {
 106         return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
 107 }
 108
 109 static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
 110 {
 111         return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
 112 }
 113
 114 static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
 115 {
 116         return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
 117 }
 118
 119 static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
 120 {
 121         return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
 122 }
 123
 124 static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
 125 {
 126         return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
 127 }
 128
 129 static int efm32x_read_info(struct flash_bank *bank,
 130         struct efm32_info *efm32_info)
 131 {
 132         int ret;
 133         uint32_t cpuid = 0;
 134
 135         memset(efm32_info, 0, sizeof(struct efm32_info));
 136
 137         ret = target_read_u32(bank->target, CPUID, &cpuid);
 138         if (ERROR_OK != ret)
 139                 return ret;
 140
 141         if (((cpuid >> 4) & 0xfff) == 0xc23) {
 142                 /* Cortex M3 device */
 143         } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
 144                 /* Cortex M4 device */
 145         } else {
 146                 LOG_ERROR("Target is not CortexM3 or M4");
 147                 return ERROR_FAIL;
 148         }
 149
 150         ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
 151         if (ERROR_OK != ret)
 152                 return ret;
 153
 154         ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
 155         if (ERROR_OK != ret)
 156                 return ret;
 157
 158         ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
 159         if (ERROR_OK != ret)
 160                 return ret;
 161
 162         ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
 163         if (ERROR_OK != ret)
 164                 return ret;
 165
 166         ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
 167         if (ERROR_OK != ret)
 168                 return ret;
 169
 170         if (EFM_FAMILY_ID_GECKO == efm32_info->part_family ||
 171                         EFM_FAMILY_ID_TINY_GECKO == efm32_info->part_family)
 172                 efm32_info->page_size = 512;
 173         else if (EFM_FAMILY_ID_GIANT_GECKO == efm32_info->part_family ||
 174                         EFM_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family) {
 175                 if (efm32_info->prod_rev >= 18) {
 176                         uint8_t pg_size = 0;
 177                         ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
 178                                 &pg_size);
 179                         if (ERROR_OK != ret)
 180                                 return ret;
 181
 182                         efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
 183                 } else {
 184                         /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
 185                            for MCUs with PROD_REV < 18 */
 186                         if (efm32_info->flash_sz_kib < 512)
 187                                 efm32_info->page_size = 2048;
 188                         else
 189                                 efm32_info->page_size = 4096;
 190                 }
 191
 192                 if ((2048 != efm32_info->page_size) &&
 193                                 (4096 != efm32_info->page_size)) {
 194                         LOG_ERROR("Invalid page size %u", efm32_info->page_size);
 195                         return ERROR_FAIL;
 196                 }
 197         } else if (EFM_FAMILY_ID_WONDER_GECKO == efm32_info->part_family) {
 198                 uint8_t pg_size = 0;
 199                 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
 200                         &pg_size);
 201                 if (ERROR_OK != ret)
 202                         return ret;
 203
 204                 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
 205                 if (2048 != efm32_info->page_size) {
 206                         LOG_ERROR("Invalid page size %u", efm32_info->page_size);
 207                         return ERROR_FAIL;
 208                 }
 209         } else {
 210                 LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
 211                 return ERROR_FAIL;
 212         }
 213
 214         return ERROR_OK;
 215 }
 216
 217 /* flash bank efm32 <base> <size> 0 0 <target#>
 218  */
 219 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
 220 {
 221         struct efm32x_flash_bank *efm32x_info;
 222
 223         if (CMD_ARGC < 6)
 224                 return ERROR_COMMAND_SYNTAX_ERROR;
 225
 226         efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
 227
 228         bank->driver_priv = efm32x_info;
 229         efm32x_info->probed = 0;
 230         memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
 231
 232         return ERROR_OK;
 233 }
 234
 235 /* set or reset given bits in a register */
 236 static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
 237         uint32_t bitmask, int set)
 238 {
 239         int ret = 0;
 240         uint32_t reg_val = 0;
 241
 242         ret = target_read_u32(bank->target, reg, &reg_val);
 243         if (ERROR_OK != ret)
 244                 return ret;
 245
 246         if (set)
 247                 reg_val |= bitmask;
 248         else
 249                 reg_val &= ~bitmask;
 250
 251         return target_write_u32(bank->target, reg, reg_val);
 252 }
 253
 254 static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
 255 {
 256         return efm32x_set_reg_bits(bank, EFM32_MSC_WRITECTRL,
 257                 EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
 258 }
 259
 260 static int efm32x_msc_lock(struct flash_bank *bank, int lock)
 261 {
 262         return target_write_u32(bank->target, EFM32_MSC_LOCK,
 263                 (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
 264 }
 265
 266 static int efm32x_wait_status(struct flash_bank *bank, int timeout,
 267         uint32_t wait_mask, int wait_for_set)
 268 {
 269         int ret = 0;
 270         uint32_t status = 0;
 271
 272         while (1) {
 273                 ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
 274                 if (ERROR_OK != ret)
 275                         break;
 276
 277                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 278
 279                 if (((status & wait_mask) == 0) && (0 == wait_for_set))
 280                         break;
 281                 else if (((status & wait_mask) != 0) && wait_for_set)
 282                         break;
 283
 284                 if (timeout-- <= 0) {
 285                         LOG_ERROR("timed out waiting for MSC status");
 286                         return ERROR_FAIL;
 287                 }
 288
 289                 alive_sleep(1);
 290         }
 291
 292         if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
 293                 LOG_WARNING("page erase was aborted");
 294
 295         return ret;
 296 }
 297
 298 static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
 299 {
 300         /* this function DOES NOT set WREN; must be set already */
 301         /* 1. write address to ADDRB
 302            2. write LADDRIM
 303            3. check status (INVADDR, LOCKED)
 304            4. write ERASEPAGE
 305            5. wait until !STATUS_BUSY
 306          */
 307         int ret = 0;
 308         uint32_t status = 0;
 309
 310         LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
 311
 312         ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr);
 313         if (ERROR_OK != ret)
 314                 return ret;
 315
 316         ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
 317                 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 318         if (ERROR_OK != ret)
 319                 return ret;
 320
 321         ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
 322         if (ERROR_OK != ret)
 323                 return ret;
 324
 325         LOG_DEBUG("status 0x%" PRIx32, status);
 326
 327         if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
 328                 LOG_ERROR("Page is locked");
 329                 return ERROR_FAIL;
 330         } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
 331                 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
 332                 return ERROR_FAIL;
 333         }
 334
 335         ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
 336                 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
 337         if (ERROR_OK != ret)
 338                 return ret;
 339
 340         return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
 341                 EFM32_MSC_STATUS_BUSY_MASK, 0);
 342 }
 343
 344 static int efm32x_erase(struct flash_bank *bank, int first, int last)
 345 {
 346         struct target *target = bank->target;
 347         int i = 0;
 348         int ret = 0;
 349
 350         if (TARGET_HALTED != target->state) {
 351                 LOG_ERROR("Target not halted");
 352                 return ERROR_TARGET_NOT_HALTED;
 353         }
 354
 355         efm32x_msc_lock(bank, 0);
 356         ret = efm32x_set_wren(bank, 1);
 357         if (ERROR_OK != ret) {
 358                 LOG_ERROR("Failed to enable MSC write");
 359                 return ret;
 360         }
 361
 362         for (i = first; i <= last; i++) {
 363                 ret = efm32x_erase_page(bank, bank->sectors[i].offset);
 364                 if (ERROR_OK != ret)
 365                         LOG_ERROR("Failed to erase page %d", i);
 366         }
 367
 368         ret = efm32x_set_wren(bank, 0);
 369         efm32x_msc_lock(bank, 1);
 370
 371         return ret;
 372 }
 373
 374 static int efm32x_read_lock_data(struct flash_bank *bank)
 375 {
 376         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 377         struct target *target = bank->target;
 378         int i = 0;
 379         int data_size = 0;
 380         uint32_t *ptr = NULL;
 381         int ret = 0;
 382
 383         assert(!(bank->num_sectors & 0x1f));
 384
 385         data_size = bank->num_sectors / 8; /* number of data bytes */
 386         data_size /= 4; /* ...and data dwords */
 387
 388         ptr = efm32x_info->lb_page;
 389
 390         for (i = 0; i < data_size; i++, ptr++) {
 391                 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
 392                 if (ERROR_OK != ret) {
 393                         LOG_ERROR("Failed to read PLW %d", i);
 394                         return ret;
 395                 }
 396         }
 397
 398         /* also, read ULW, DLW and MLW */
 399
 400         /* ULW, word 126 */
 401         ptr = efm32x_info->lb_page + 126;
 402         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
 403         if (ERROR_OK != ret) {
 404                 LOG_ERROR("Failed to read ULW");
 405                 return ret;
 406         }
 407
 408         /* DLW, word 127 */
 409         ptr = efm32x_info->lb_page + 127;
 410         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
 411         if (ERROR_OK != ret) {
 412                 LOG_ERROR("Failed to read DLW");
 413                 return ret;
 414         }
 415
 416         /* MLW, word 125, present in GG and LG */
 417         ptr = efm32x_info->lb_page + 125;
 418         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
 419         if (ERROR_OK != ret) {
 420                 LOG_ERROR("Failed to read MLW");
 421                 return ret;
 422         }
 423
 424         return ERROR_OK;
 425 }
 426
 427 static int efm32x_write_lock_data(struct flash_bank *bank)
 428 {
 429         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 430         int ret = 0;
 431
 432         ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
 433         if (ERROR_OK != ret) {
 434                 LOG_ERROR("Failed to erase LB page");
 435                 return ret;
 436         }
 437
 438         return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
 439                 LOCKBITS_PAGE_SZ);
 440 }
 441
 442 static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
 443 {
 444         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 445         uint32_t dw = efm32x_info->lb_page[page >> 5];
 446         uint32_t mask = 0;
 447
 448         mask = 1 << (page & 0x1f);
 449
 450         return (dw & mask) ? 0 : 1;
 451 }
 452
 453 static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
 454 {
 455         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 456         uint32_t *dw = &efm32x_info->lb_page[page >> 5];
 457         uint32_t mask = 0;
 458
 459         mask = 1 << (page & 0x1f);
 460
 461         if (!set)
 462                 *dw |= mask;
 463         else
 464                 *dw &= ~mask;
 465
 466         return ERROR_OK;
 467 }
 468
 469 static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
 470 {
 471         struct target *target = bank->target;
 472         int i = 0;
 473         int ret = 0;
 474
 475         if (!set) {
 476                 LOG_ERROR("Erase device data to reset page locks");
 477                 return ERROR_FAIL;
 478         }
 479
 480         if (target->state != TARGET_HALTED) {
 481                 LOG_ERROR("Target not halted");
 482                 return ERROR_TARGET_NOT_HALTED;
 483         }
 484
 485         for (i = first; i <= last; i++) {
 486                 ret = efm32x_set_page_lock(bank, i, set);
 487                 if (ERROR_OK != ret) {
 488                         LOG_ERROR("Failed to set lock on page %d", i);
 489                         return ret;
 490                 }
 491         }
 492
 493         ret = efm32x_write_lock_data(bank);
 494         if (ERROR_OK != ret) {
 495                 LOG_ERROR("Failed to write LB page");
 496                 return ret;
 497         }
 498
 499         return ERROR_OK;
 500 }
 501
 502 static int efm32x_write_block(struct flash_bank *bank, uint8_t *buf,
 503         uint32_t offset, uint32_t count)
 504 {
 505         struct target *target = bank->target;
 506         uint32_t buffer_size = 16384;
 507         struct working_area *write_algorithm;
 508         struct working_area *source;
 509         uint32_t address = bank->base + offset;
 510         struct reg_param reg_params[5];
 511         struct armv7m_algorithm armv7m_info;
 512         int ret = ERROR_OK;
 513
 514         /* see contrib/loaders/flash/efm32.S for src */
 515         static const uint8_t efm32x_flash_write_code[] = {
 516                 /* #define EFM32_MSC_WRITECTRL_OFFSET      0x008 */
 517                 /* #define EFM32_MSC_WRITECMD_OFFSET       0x00c */
 518                 /* #define EFM32_MSC_ADDRB_OFFSET          0x010 */
 519                 /* #define EFM32_MSC_WDATA_OFFSET          0x018 */
 520                 /* #define EFM32_MSC_STATUS_OFFSET         0x01c */
 521                 /* #define EFM32_MSC_LOCK_OFFSET           0x03c */
 522
 523                         0x15, 0x4e,    /* ldr     r6, =#0x1b71 */
 524                         0xc6, 0x63,    /* str     r6, [r0, #EFM32_MSC_LOCK_OFFSET] */
 525                         0x01, 0x26,    /* movs    r6, #1 */
 526                         0x86, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
 527
 528                 /* wait_fifo: */
 529                         0x16, 0x68,    /* ldr     r6, [r2, #0] */
 530                         0x00, 0x2e,    /* cmp     r6, #0 */
 531                         0x22, 0xd0,    /* beq     exit */
 532                         0x55, 0x68,    /* ldr     r5, [r2, #4] */
 533                         0xb5, 0x42,    /* cmp     r5, r6 */
 534                         0xf9, 0xd0,    /* beq     wait_fifo */
 535
 536                         0x04, 0x61,    /* str     r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
 537                         0x01, 0x26,    /* movs    r6, #1 */
 538                         0xc6, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
 539                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 540                         0x06, 0x27,    /* movs    r7, #6 */
 541                         0x3e, 0x42,    /* tst     r6, r7 */
 542                         0x16, 0xd1,    /* bne     error */
 543
 544                 /* wait_wdataready: */
 545                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 546                         0x08, 0x27,    /* movs    r7, #8 */
 547                         0x3e, 0x42,    /* tst     r6, r7 */
 548                         0xfb, 0xd0,    /* beq     wait_wdataready */
 549
 550                         0x2e, 0x68,    /* ldr     r6, [r5] */
 551                         0x86, 0x61,    /* str     r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
 552                         0x08, 0x26,    /* movs    r6, #8 */
 553                         0xc6, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
 554
 555                         0x04, 0x35,    /* adds    r5, #4 */
 556                         0x04, 0x34,    /* adds    r4, #4 */
 557
 558                 /* busy: */
 559                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 560                         0x01, 0x27,    /* movs    r7, #1 */
 561                         0x3e, 0x42,    /* tst     r6, r7 */
 562                         0xfb, 0xd1,    /* bne     busy */
 563
 564                         0x9d, 0x42,    /* cmp     r5, r3 */
 565                         0x01, 0xd3,    /* bcc     no_wrap */
 566                         0x15, 0x46,    /* mov     r5, r2 */
 567                         0x08, 0x35,    /* adds    r5, #8 */
 568
 569                 /* no_wrap: */
 570                         0x55, 0x60,    /* str     r5, [r2, #4] */
 571                         0x01, 0x39,    /* subs    r1, r1, #1 */
 572                         0x00, 0x29,    /* cmp     r1, #0 */
 573                         0x02, 0xd0,    /* beq     exit */
 574                         0xdb, 0xe7,    /* b       wait_fifo */
 575
 576                 /* error: */
 577                         0x00, 0x20,    /* movs    r0, #0 */
 578                         0x50, 0x60,    /* str     r0, [r2, #4] */
 579
 580                 /* exit: */
 581                         0x30, 0x46,    /* mov     r0, r6 */
 582                         0x00, 0xbe,    /* bkpt    #0 */
 583
 584                 /* LOCKKEY */
 585                         0x71, 0x1b, 0x00, 0x00
 586         };
 587
 588         /* flash write code */
 589         if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
 590                         &write_algorithm) != ERROR_OK) {
 591                 LOG_WARNING("no working area available, can't do block memory writes");
 592                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 593         };
 594
 595         ret = target_write_buffer(target, write_algorithm->address,
 596                         sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
 597         if (ret != ERROR_OK)
 598                 return ret;
 599
 600         /* memory buffer */
 601         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 602                 buffer_size /= 2;
 603                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 604                 if (buffer_size <= 256) {
 605                         /* we already allocated the writing code, but failed to get a
 606                          * buffer, free the algorithm */
 607                         target_free_working_area(target, write_algorithm);
 608
 609                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 610                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 611                 }
 612         };
 613
 614         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 615         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (word-32bit) */
 616         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 617         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 618         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 619
 620         buf_set_u32(reg_params[0].value, 0, 32, EFM32_MSC_REGBASE);
 621         buf_set_u32(reg_params[1].value, 0, 32, count);
 622         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 623         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 624         buf_set_u32(reg_params[4].value, 0, 32, address);
 625
 626         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 627         armv7m_info.core_mode = ARM_MODE_THREAD;
 628
 629         ret = target_run_flash_async_algorithm(target, buf, count, 4,
 630                         0, NULL,
 631                         5, reg_params,
 632                         source->address, source->size,
 633                         write_algorithm->address, 0,
 634                         &armv7m_info);
 635
 636         if (ret == ERROR_FLASH_OPERATION_FAILED) {
 637                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 638                                 buf_get_u32(reg_params[4].value, 0, 32));
 639
 640                 if (buf_get_u32(reg_params[0].value, 0, 32) &
 641                                 EFM32_MSC_STATUS_LOCKED_MASK) {
 642                         LOG_ERROR("flash memory write protected");
 643                 }
 644
 645                 if (buf_get_u32(reg_params[0].value, 0, 32) &
 646                                 EFM32_MSC_STATUS_INVADDR_MASK) {
 647                         LOG_ERROR("invalid flash memory write address");
 648                 }
 649         }
 650
 651         target_free_working_area(target, source);
 652         target_free_working_area(target, write_algorithm);
 653
 654         destroy_reg_param(&reg_params[0]);
 655         destroy_reg_param(&reg_params[1]);
 656         destroy_reg_param(&reg_params[2]);
 657         destroy_reg_param(&reg_params[3]);
 658         destroy_reg_param(&reg_params[4]);
 659
 660         return ret;
 661 }
 662
 663 static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 664         uint32_t val)
 665 {
 666         /* this function DOES NOT set WREN; must be set already */
 667         /* 1. write address to ADDRB
 668            2. write LADDRIM
 669            3. check status (INVADDR, LOCKED)
 670            4. wait for WDATAREADY
 671            5. write data to WDATA
 672            6. write WRITECMD_WRITEONCE to WRITECMD
 673            7. wait until !STATUS_BUSY
 674          */
 675
 676         /* FIXME: EFM32G ref states (7.3.2) that writes should be
 677          * performed twice per dword */
 678
 679         int ret = 0;
 680         uint32_t status = 0;
 681
 682         /* if not called, GDB errors will be reported during large writes */
 683         keep_alive();
 684
 685         ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr);
 686         if (ERROR_OK != ret)
 687                 return ret;
 688
 689         ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
 690                 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 691         if (ERROR_OK != ret)
 692                 return ret;
 693
 694         ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
 695         if (ERROR_OK != ret)
 696                 return ret;
 697
 698         LOG_DEBUG("status 0x%" PRIx32, status);
 699
 700         if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
 701                 LOG_ERROR("Page is locked");
 702                 return ERROR_FAIL;
 703         } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
 704                 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
 705                 return ERROR_FAIL;
 706         }
 707
 708         ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
 709                 EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
 710         if (ERROR_OK != ret) {
 711                 LOG_ERROR("Wait for WDATAREADY failed");
 712                 return ret;
 713         }
 714
 715         ret = target_write_u32(bank->target, EFM32_MSC_WDATA, val);
 716         if (ERROR_OK != ret) {
 717                 LOG_ERROR("WDATA write failed");
 718                 return ret;
 719         }
 720
 721         ret = target_write_u32(bank->target, EFM32_MSC_WRITECMD,
 722                 EFM32_MSC_WRITECMD_WRITEONCE_MASK);
 723         if (ERROR_OK != ret) {
 724                 LOG_ERROR("WRITECMD write failed");
 725                 return ret;
 726         }
 727
 728         ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
 729                 EFM32_MSC_STATUS_BUSY_MASK, 0);
 730         if (ERROR_OK != ret) {
 731                 LOG_ERROR("Wait for BUSY failed");
 732                 return ret;
 733         }
 734
 735         return ERROR_OK;
 736 }
 737
 738 static int efm32x_write(struct flash_bank *bank, uint8_t *buffer,
 739                 uint32_t offset, uint32_t count)
 740 {
 741         struct target *target = bank->target;
 742         uint8_t *new_buffer = NULL;
 743
 744         if (target->state != TARGET_HALTED) {
 745                 LOG_ERROR("Target not halted");
 746                 return ERROR_TARGET_NOT_HALTED;
 747         }
 748
 749         if (offset & 0x3) {
 750                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
 751                         "alignment", offset);
 752                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 753         }
 754
 755         if (count & 0x3) {
 756                 uint32_t old_count = count;
 757                 count = (old_count | 3) + 1;
 758                 new_buffer = malloc(count);
 759                 if (new_buffer == NULL) {
 760                         LOG_ERROR("odd number of bytes to write and no memory "
 761                                 "for padding buffer");
 762                         return ERROR_FAIL;
 763                 }
 764                 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
 765                         "and padding with 0xff", old_count, count);
 766                 memset(new_buffer, 0xff, count);
 767                 buffer = memcpy(new_buffer, buffer, old_count);
 768         }
 769
 770         uint32_t words_remaining = count / 4;
 771         int retval, retval2;
 772
 773         /* unlock flash registers */
 774         efm32x_msc_lock(bank, 0);
 775         retval = efm32x_set_wren(bank, 1);
 776         if (retval != ERROR_OK)
 777                 goto cleanup;
 778
 779         /* try using a block write */
 780         retval = efm32x_write_block(bank, buffer, offset, words_remaining);
 781
 782         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 783                 /* if block write failed (no sufficient working area),
 784                  * we use normal (slow) single word accesses */
 785                 LOG_WARNING("couldn't use block writes, falling back to single "
 786                         "memory accesses");
 787
 788                 while (words_remaining > 0) {
 789                         uint32_t value;
 790                         memcpy(&value, buffer, sizeof(uint32_t));
 791
 792                         retval = efm32x_write_word(bank, offset, value);
 793                         if (retval != ERROR_OK)
 794                                 goto reset_pg_and_lock;
 795
 796                         words_remaining--;
 797                         buffer += 4;
 798                         offset += 4;
 799                 }
 800         }
 801
 802 reset_pg_and_lock:
 803         retval2 = efm32x_set_wren(bank, 0);
 804         efm32x_msc_lock(bank, 1);
 805         if (retval == ERROR_OK)
 806                 retval = retval2;
 807
 808 cleanup:
 809         if (new_buffer)
 810                 free(new_buffer);
 811
 812         return retval;
 813 }
 814
 815 static int efm32x_probe(struct flash_bank *bank)
 816 {
 817         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 818         struct efm32_info efm32_mcu_info;
 819         int ret;
 820         int i;
 821         uint32_t base_address = 0x00000000;
 822
 823         efm32x_info->probed = 0;
 824         memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
 825
 826         ret = efm32x_read_info(bank, &efm32_mcu_info);
 827         if (ERROR_OK != ret)
 828                 return ret;
 829
 830         switch (efm32_mcu_info.part_family) {
 831                 case EFM_FAMILY_ID_GECKO:
 832                         LOG_INFO("Gecko MCU detected");
 833                         break;
 834                 case EFM_FAMILY_ID_GIANT_GECKO:
 835                         LOG_INFO("Giant Gecko MCU detected");
 836                         break;
 837                 case EFM_FAMILY_ID_TINY_GECKO:
 838                         LOG_INFO("Tiny Gecko MCU detected");
 839                         break;
 840                 case EFM_FAMILY_ID_LEOPARD_GECKO:
 841                         LOG_INFO("Leopard Gecko MCU detected");
 842                         break;
 843                 case EFM_FAMILY_ID_WONDER_GECKO:
 844                         LOG_INFO("Wonder Gecko MCU detected");
 845                         break;
 846                 default:
 847                         LOG_ERROR("Unsupported MCU family %d",
 848                                 efm32_mcu_info.part_family);
 849                         return ERROR_FAIL;
 850         }
 851
 852         LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
 853         LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
 854
 855         assert(0 != efm32_mcu_info.page_size);
 856
 857         int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
 858                 efm32_mcu_info.page_size;
 859
 860         assert(num_pages > 0);
 861
 862         if (bank->sectors) {
 863                 free(bank->sectors);
 864                 bank->sectors = NULL;
 865         }
 866
 867         bank->base = base_address;
 868         bank->size = (num_pages * efm32_mcu_info.page_size);
 869         bank->num_sectors = num_pages;
 870
 871         ret = efm32x_read_lock_data(bank);
 872         if (ERROR_OK != ret) {
 873                 LOG_ERROR("Failed to read LB data");
 874                 return ret;
 875         }
 876
 877         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 878
 879         for (i = 0; i < num_pages; i++) {
 880                 bank->sectors[i].offset = i * efm32_mcu_info.page_size;
 881                 bank->sectors[i].size = efm32_mcu_info.page_size;
 882                 bank->sectors[i].is_erased = -1;
 883                 bank->sectors[i].is_protected = 1;
 884         }
 885
 886         efm32x_info->probed = 1;
 887
 888         return ERROR_OK;
 889 }
 890
 891 static int efm32x_auto_probe(struct flash_bank *bank)
 892 {
 893         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 894         if (efm32x_info->probed)
 895                 return ERROR_OK;
 896         return efm32x_probe(bank);
 897 }
 898
 899 static int efm32x_protect_check(struct flash_bank *bank)
 900 {
 901         struct target *target = bank->target;
 902         int ret = 0;
 903         int i = 0;
 904
 905         if (target->state != TARGET_HALTED) {
 906                 LOG_ERROR("Target not halted");
 907                 return ERROR_TARGET_NOT_HALTED;
 908         }
 909
 910         ret = efm32x_read_lock_data(bank);
 911         if (ERROR_OK != ret) {
 912                 LOG_ERROR("Failed to read LB data");
 913                 return ret;
 914         }
 915
 916         assert(NULL != bank->sectors);
 917
 918         for (i = 0; i < bank->num_sectors; i++)
 919                 bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
 920
 921         return ERROR_OK;
 922 }
 923
 924 static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
 925 {
 926         struct efm32_info info;
 927         int ret = 0;
 928         int printed = 0;
 929
 930         ret = efm32x_read_info(bank, &info);
 931         if (ERROR_OK != ret) {
 932                 LOG_ERROR("Failed to read EFM32 info");
 933                 return ret;
 934         }
 935
 936         printed = snprintf(buf, buf_size, "EFM32 ");
 937         buf += printed;
 938         buf_size -= printed;
 939
 940         if (0 >= buf_size)
 941                 return ERROR_BUF_TOO_SMALL;
 942
 943         switch (info.part_family) {
 944                 case EFM_FAMILY_ID_GECKO:
 945                         printed = snprintf(buf, buf_size, "Gecko");
 946                         break;
 947                 case EFM_FAMILY_ID_GIANT_GECKO:
 948                         printed = snprintf(buf, buf_size, "Giant Gecko");
 949                         break;
 950                 case EFM_FAMILY_ID_TINY_GECKO:
 951                         printed = snprintf(buf, buf_size, "Tiny Gecko");
 952                         break;
 953                 case EFM_FAMILY_ID_LEOPARD_GECKO:
 954                         printed = snprintf(buf, buf_size, "Leopard Gecko");
 955                         break;
 956                 case EFM_FAMILY_ID_WONDER_GECKO:
 957                         printed = snprintf(buf, buf_size, "Wonder Gecko");
 958                         break;
 959         }
 960
 961         buf += printed;
 962         buf_size -= printed;
 963
 964         if (0 >= buf_size)
 965                 return ERROR_BUF_TOO_SMALL;
 966
 967         printed = snprintf(buf, buf_size, " - Rev: %d", info.prod_rev);
 968         buf += printed;
 969         buf_size -= printed;
 970
 971         if (0 >= buf_size)
 972                 return ERROR_BUF_TOO_SMALL;
 973
 974         return ERROR_OK;
 975 }
 976
 977 static const struct command_registration efm32x_exec_command_handlers[] = {
 978         COMMAND_REGISTRATION_DONE
 979 };
 980
 981 static const struct command_registration efm32x_command_handlers[] = {
 982         {
 983                 .name = "efm32",
 984                 .mode = COMMAND_ANY,
 985                 .help = "efm32 flash command group",
 986                 .usage = "",
 987                 .chain = efm32x_exec_command_handlers,
 988         },
 989         COMMAND_REGISTRATION_DONE
 990 };
 991
 992 struct flash_driver efm32_flash = {
 993         .name = "efm32",
 994         .commands = efm32x_command_handlers,
 995         .flash_bank_command = efm32x_flash_bank_command,
 996         .erase = efm32x_erase,
 997         .protect = efm32x_protect,
 998         .write = efm32x_write,
 999         .read = default_flash_read,
1000         .probe = efm32x_probe,
1001         .auto_probe = efm32x_auto_probe,
1002         .erase_check = default_flash_blank_check,
1003         .protect_check = efm32x_protect_check,
1004         .info = get_efm32x_info,
1005 };