git.sur5r.net Git - openocd/blob - src/flash/nor/nrf51.c

   1 /***************************************************************************
   2  *   Copyright (C) 2013 Synapse Product Development                        *
   3  *   Andrey Smirnov <andrew.smironv@gmail.com>                             *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "imp.h"
  26
  27 enum {
  28         NRF51_FLASH_BASE = 0x00000000,
  29 };
  30
  31 enum nrf51_ficr_registers {
  32         NRF51_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
  33
  34 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
  35
  36         NRF51_FICR_CODEPAGESIZE         = NRF51_FICR_REG(0x010),
  37         NRF51_FICR_CODESIZE             = NRF51_FICR_REG(0x014),
  38         NRF51_FICR_CLENR0               = NRF51_FICR_REG(0x028),
  39         NRF51_FICR_PPFC                 = NRF51_FICR_REG(0x02C),
  40         NRF51_FICR_NUMRAMBLOCK          = NRF51_FICR_REG(0x034),
  41         NRF51_FICR_SIZERAMBLOCK0        = NRF51_FICR_REG(0x038),
  42         NRF51_FICR_SIZERAMBLOCK1        = NRF51_FICR_REG(0x03C),
  43         NRF51_FICR_SIZERAMBLOCK2        = NRF51_FICR_REG(0x040),
  44         NRF51_FICR_SIZERAMBLOCK3        = NRF51_FICR_REG(0x044),
  45         NRF51_FICR_CONFIGID             = NRF51_FICR_REG(0x05C),
  46         NRF51_FICR_DEVICEID0            = NRF51_FICR_REG(0x060),
  47         NRF51_FICR_DEVICEID1            = NRF51_FICR_REG(0x064),
  48         NRF51_FICR_ER0                  = NRF51_FICR_REG(0x080),
  49         NRF51_FICR_ER1                  = NRF51_FICR_REG(0x084),
  50         NRF51_FICR_ER2                  = NRF51_FICR_REG(0x088),
  51         NRF51_FICR_ER3                  = NRF51_FICR_REG(0x08C),
  52         NRF51_FICR_IR0                  = NRF51_FICR_REG(0x090),
  53         NRF51_FICR_IR1                  = NRF51_FICR_REG(0x094),
  54         NRF51_FICR_IR2                  = NRF51_FICR_REG(0x098),
  55         NRF51_FICR_IR3                  = NRF51_FICR_REG(0x09C),
  56         NRF51_FICR_DEVICEADDRTYPE       = NRF51_FICR_REG(0x0A0),
  57         NRF51_FICR_DEVICEADDR0          = NRF51_FICR_REG(0x0A4),
  58         NRF51_FICR_DEVICEADDR1          = NRF51_FICR_REG(0x0A8),
  59         NRF51_FICR_OVERRIDEN            = NRF51_FICR_REG(0x0AC),
  60         NRF51_FICR_NRF_1MBIT0           = NRF51_FICR_REG(0x0B0),
  61         NRF51_FICR_NRF_1MBIT1           = NRF51_FICR_REG(0x0B4),
  62         NRF51_FICR_NRF_1MBIT2           = NRF51_FICR_REG(0x0B8),
  63         NRF51_FICR_NRF_1MBIT3           = NRF51_FICR_REG(0x0BC),
  64         NRF51_FICR_NRF_1MBIT4           = NRF51_FICR_REG(0x0C0),
  65         NRF51_FICR_BLE_1MBIT0           = NRF51_FICR_REG(0x0EC),
  66         NRF51_FICR_BLE_1MBIT1           = NRF51_FICR_REG(0x0F0),
  67         NRF51_FICR_BLE_1MBIT2           = NRF51_FICR_REG(0x0F4),
  68         NRF51_FICR_BLE_1MBIT3           = NRF51_FICR_REG(0x0F8),
  69         NRF51_FICR_BLE_1MBIT4           = NRF51_FICR_REG(0x0FC),
  70 };
  71
  72 enum nrf51_uicr_registers {
  73         NRF51_UICR_BASE = 0x10001000, /* User Information
  74                                        * Configuration Regsters */
  75
  76 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
  77
  78         NRF51_UICR_CLENR0       = NRF51_UICR_REG(0x000),
  79         NRF51_UICR_RBPCONF      = NRF51_UICR_REG(0x004),
  80         NRF51_UICR_XTALFREQ     = NRF51_UICR_REG(0x008),
  81         NRF51_UICR_FWID         = NRF51_UICR_REG(0x010),
  82 };
  83
  84 enum nrf51_nvmc_registers {
  85         NRF51_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
  86                                        * Controller Regsters */
  87
  88 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
  89
  90         NRF51_NVMC_READY        = NRF51_NVMC_REG(0x400),
  91         NRF51_NVMC_CONFIG       = NRF51_NVMC_REG(0x504),
  92         NRF51_NVMC_ERASEPAGE    = NRF51_NVMC_REG(0x508),
  93         NRF51_NVMC_ERASEALL     = NRF51_NVMC_REG(0x50C),
  94         NRF51_NVMC_ERASEUICR    = NRF51_NVMC_REG(0x514),
  95 };
  96
  97 enum nrf51_nvmc_config_bits {
  98         NRF51_NVMC_CONFIG_REN = 0x00,
  99         NRF51_NVMC_CONFIG_WEN = 0x01,
 100         NRF51_NVMC_CONFIG_EEN = 0x02,
 101
 102 };
 103
 104 struct nrf51_info {
 105         uint32_t code_page_size;
 106         uint32_t code_memory_size;
 107
 108         bool probed;
 109         struct target *target;
 110 };
 111
 112 static int nrf51_probe(struct flash_bank *bank);
 113
 114 static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip)
 115 {
 116         if (bank->target->state != TARGET_HALTED) {
 117                 LOG_ERROR("Target not halted");
 118                 return ERROR_TARGET_NOT_HALTED;
 119         }
 120
 121         *chip = (struct nrf51_info *)bank->driver_priv;
 122
 123         if (!(*chip)->probed)
 124                 return nrf51_probe(bank);
 125
 126         return ERROR_OK;
 127 }
 128
 129 static int nrf51_wait_for_nvmc(struct nrf51_info *chip)
 130 {
 131         uint32_t ready;
 132         int res;
 133         int timeout = 100;
 134
 135         do {
 136                 res = target_read_u32(chip->target, NRF51_NVMC_READY, &ready);
 137                 if (res != ERROR_OK) {
 138                         LOG_ERROR("Couldn't read NVMC_READY register");
 139                         return res;
 140                 }
 141
 142                 if (ready == 0x00000001)
 143                         return ERROR_OK;
 144
 145                 alive_sleep(1);
 146         } while (timeout--);
 147
 148         return ERROR_FLASH_BUSY;
 149 }
 150
 151 static int nrf51_nvmc_erase_enable(struct nrf51_info *chip)
 152 {
 153         int res;
 154         res = target_write_u32(chip->target,
 155                                NRF51_NVMC_CONFIG,
 156                                NRF51_NVMC_CONFIG_EEN);
 157
 158         if (res != ERROR_OK) {
 159                 LOG_ERROR("Failed to enable erase operation");
 160                 return res;
 161         }
 162
 163         /*
 164           According to NVMC examples in Nordic SDK busy status must be
 165           checked after writing to NVMC_CONFIG
 166          */
 167         res = nrf51_wait_for_nvmc(chip);
 168         if (res != ERROR_OK)
 169                 LOG_ERROR("Erase enable did not complete");
 170
 171         return res;
 172 }
 173
 174 static int nrf51_nvmc_write_enable(struct nrf51_info *chip)
 175 {
 176         int res;
 177         res = target_write_u32(chip->target,
 178                                NRF51_NVMC_CONFIG,
 179                                NRF51_NVMC_CONFIG_WEN);
 180
 181         if (res != ERROR_OK) {
 182                 LOG_ERROR("Failed to enable write operation");
 183                 return res;
 184         }
 185
 186         /*
 187           According to NVMC examples in Nordic SDK busy status must be
 188           checked after writing to NVMC_CONFIG
 189          */
 190         res = nrf51_wait_for_nvmc(chip);
 191         if (res != ERROR_OK)
 192                 LOG_ERROR("Write enable did not complete");
 193
 194         return res;
 195 }
 196
 197 static int nrf51_nvmc_read_only(struct nrf51_info *chip)
 198 {
 199         int res;
 200         res = target_write_u32(chip->target,
 201                                NRF51_NVMC_CONFIG,
 202                                NRF51_NVMC_CONFIG_REN);
 203
 204         if (res != ERROR_OK) {
 205                 LOG_ERROR("Failed to enable read-only operation");
 206                 return res;
 207         }
 208         /*
 209           According to NVMC examples in Nordic SDK busy status must be
 210           checked after writing to NVMC_CONFIG
 211          */
 212         res = nrf51_wait_for_nvmc(chip);
 213         if (res != ERROR_OK)
 214                 LOG_ERROR("Read only enable did not complete");
 215
 216         return res;
 217 }
 218
 219 static int nrf51_nvmc_generic_erase(struct nrf51_info *chip,
 220                                uint32_t erase_register, uint32_t erase_value)
 221 {
 222         int res;
 223
 224         res = nrf51_nvmc_erase_enable(chip);
 225         if (res != ERROR_OK)
 226                 goto error;
 227
 228         res = target_write_u32(chip->target,
 229                                erase_register,
 230                                erase_value);
 231         if (res != ERROR_OK)
 232                 goto set_read_only;
 233
 234         res = nrf51_wait_for_nvmc(chip);
 235         if (res != ERROR_OK)
 236                 goto set_read_only;
 237
 238         return nrf51_nvmc_read_only(chip);
 239
 240 set_read_only:
 241         nrf51_nvmc_read_only(chip);
 242 error:
 243         LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
 244                   erase_register, erase_value);
 245         return ERROR_FAIL;
 246 }
 247
 248 static int nrf51_protect_check(struct flash_bank *bank)
 249 {
 250         int res;
 251         uint32_t clenr0;
 252
 253         struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
 254
 255         assert(chip != NULL);
 256
 257         res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
 258                               &clenr0);
 259         if (res != ERROR_OK) {
 260                 LOG_ERROR("Couldn't read code region 0 size[FICR]");
 261                 return res;
 262         }
 263
 264         if (clenr0 == 0xFFFFFFFF) {
 265                 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 266                                       &clenr0);
 267                 if (res != ERROR_OK) {
 268                         LOG_ERROR("Couldn't read code region 0 size[UICR]");
 269                         return res;
 270                 }
 271         }
 272
 273         for (int i = 0; i < bank->num_sectors; i++)
 274                 bank->sectors[i].is_protected =
 275                         clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
 276
 277         return ERROR_OK;
 278 }
 279
 280 static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
 281 {
 282         int res;
 283         uint32_t clenr0, ppfc;
 284         struct nrf51_info *chip;
 285
 286         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 287         if (res != ERROR_OK)
 288                 return res;
 289
 290         if (first != 0) {
 291                 LOG_ERROR("Code region 0 must start at the begining of the bank");
 292                 return ERROR_FAIL;
 293         }
 294
 295         res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 296                               &ppfc);
 297         if (res != ERROR_OK) {
 298                 LOG_ERROR("Couldn't read PPFC register");
 299                 return res;
 300         }
 301
 302         if ((ppfc & 0xFF) == 0x00) {
 303                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
 304                 return ERROR_FAIL;
 305         };
 306
 307         res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 308                               &clenr0);
 309         if (res != ERROR_OK) {
 310                 LOG_ERROR("Couldn't read code region 0 size[UICR]");
 311                 return res;
 312         }
 313
 314         if (clenr0 == 0xFFFFFFFF) {
 315                 res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
 316                                        clenr0);
 317                 if (res != ERROR_OK) {
 318                         LOG_ERROR("Couldn't write code region 0 size[UICR]");
 319                         return res;
 320                 }
 321
 322         } else {
 323                 LOG_ERROR("You need to perform chip erase before changing the protection settings");
 324         }
 325
 326         nrf51_protect_check(bank);
 327
 328         return ERROR_OK;
 329 }
 330
 331 static int nrf51_probe(struct flash_bank *bank)
 332 {
 333         uint32_t id;
 334         int res;
 335         struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
 336
 337         res = target_read_u32(chip->target, NRF51_FICR_DEVICEID0, &id);
 338         if (res != ERROR_OK) {
 339                 LOG_ERROR("Couldn't read Device ID 0 register");
 340                 return res;
 341         }
 342
 343         res = target_read_u32(chip->target, NRF51_FICR_DEVICEID1, &id);
 344         if (res != ERROR_OK) {
 345                 LOG_ERROR("Couldn't read Device ID 1 register");
 346                 return res;
 347         }
 348
 349         res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
 350                               &chip->code_page_size);
 351         if (res != ERROR_OK) {
 352                 LOG_ERROR("Couldn't read code page size");
 353                 return res;
 354         }
 355
 356         res = target_read_u32(chip->target, NRF51_FICR_CODESIZE,
 357                               &chip->code_memory_size);
 358         if (res != ERROR_OK) {
 359                 LOG_ERROR("Couldn't read code memory size");
 360                 return res;
 361         }
 362
 363         bank->size = chip->code_memory_size * 1024;
 364         bank->num_sectors = bank->size / chip->code_page_size;
 365         bank->sectors = calloc(bank->num_sectors,
 366                                sizeof((bank->sectors)[0]));
 367         if (!bank->sectors)
 368                 return ERROR_FLASH_BANK_NOT_PROBED;
 369
 370         /* Fill out the sector information: all NRF51 sectors are the same size and
 371          * there is always a fixed number of them. */
 372         for (int i = 0; i < bank->num_sectors; i++) {
 373                 bank->sectors[i].size = chip->code_page_size;
 374                 bank->sectors[i].offset = i * chip->code_page_size;
 375
 376                 /* mark as unknown */
 377                 bank->sectors[i].is_erased = -1;
 378                 bank->sectors[i].is_protected = -1;
 379         }
 380
 381         nrf51_protect_check(bank);
 382
 383         chip->probed = true;
 384
 385         return ERROR_OK;
 386 }
 387
 388 static int nrf51_auto_probe(struct flash_bank *bank)
 389 {
 390         struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
 391
 392         if (chip->probed)
 393                 return ERROR_OK;
 394
 395         return nrf51_probe(bank);
 396 }
 397
 398 static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address)
 399 {
 400         struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
 401
 402         for (int i = 0; i < bank->num_sectors; i++)
 403                 if (bank->sectors[i].offset <= address &&
 404                     address < (bank->sectors[i].offset + chip->code_page_size))
 405                         return &bank->sectors[i];
 406         return NULL;
 407 }
 408
 409 static int nrf51_erase_all(struct nrf51_info *chip)
 410 {
 411         return nrf51_nvmc_generic_erase(chip,
 412                                         NRF51_NVMC_ERASEALL,
 413                                         0x00000001);
 414 }
 415
 416 static int nrf51_erase_page(struct nrf51_info *chip, struct flash_sector *sector)
 417 {
 418         int res;
 419
 420         if (sector->is_protected)
 421                 return ERROR_FAIL;
 422
 423         res = nrf51_nvmc_generic_erase(chip,
 424                                        NRF51_NVMC_ERASEPAGE,
 425                                        sector->offset);
 426         if (res == ERROR_OK)
 427                 sector->is_erased = 1;
 428
 429         return res;
 430 }
 431
 432 static int nrf51_write_page(struct flash_bank *bank, uint32_t offset, const uint8_t *buffer)
 433 {
 434         assert(offset % 4 == 0);
 435
 436         int res = ERROR_FAIL;
 437         struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
 438         struct flash_sector *sector = nrf51_find_sector_by_address(bank, offset);
 439
 440         if (!sector)
 441                 goto error;
 442
 443         if (sector->is_protected)
 444                 goto error;
 445
 446         if (!sector->is_erased) {
 447                 res = nrf51_erase_page(chip, sector);
 448                 if (res != ERROR_OK)
 449                         goto error;
 450         }
 451
 452         res = nrf51_nvmc_write_enable(chip);
 453         if (res != ERROR_OK)
 454                 goto error;
 455
 456         sector->is_erased = 0;
 457         res = target_write_memory(bank->target, offset, 4,
 458                                   chip->code_page_size / 4, buffer);
 459         if (res != ERROR_OK)
 460                 goto set_read_only;
 461
 462         return nrf51_nvmc_read_only(chip);
 463
 464 set_read_only:
 465         nrf51_nvmc_read_only(chip);
 466 error:
 467         LOG_ERROR("Failed to write sector @ 0x%08"PRIx32, sector->offset);
 468         return res;
 469 }
 470
 471 static int nrf51_erase(struct flash_bank *bank, int first, int last)
 472 {
 473         int res;
 474         struct nrf51_info *chip;
 475
 476         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 477         if (res != ERROR_OK)
 478                 return res;
 479
 480         /* For each sector to be erased */
 481         for (int s = first; s <= last && res == ERROR_OK; s++)
 482                 res = nrf51_erase_page(chip, &bank->sectors[s]);
 483
 484         return res;
 485 }
 486
 487 static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
 488                        uint32_t offset, uint32_t count)
 489 {
 490         int res;
 491         struct {
 492                 uint32_t start, end;
 493         } region;
 494         struct nrf51_info *chip;
 495
 496         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 497         if (res != ERROR_OK)
 498                 return res;
 499
 500         region.start = offset;
 501         region.end   = offset + count;
 502
 503         struct {
 504                 size_t   length;
 505                 const uint8_t *buffer;
 506         }  start_extra, end_extra;
 507
 508         start_extra.length      = region.start % chip->code_page_size;
 509         start_extra.buffer      = buffer;
 510         end_extra.length        = region.end  % chip->code_page_size;
 511         end_extra.buffer        = buffer + count - end_extra.length;
 512
 513         if (start_extra.length) {
 514                 uint8_t page[chip->code_page_size];
 515
 516                 res = target_read_memory(bank->target,
 517                                          region.start - start_extra.length,
 518                                          1, start_extra.length, page);
 519                 if (res != ERROR_OK)
 520                         return res;
 521
 522                 memcpy(page + start_extra.length,
 523                        start_extra.buffer,
 524                        chip->code_page_size - start_extra.length);
 525
 526                 res = nrf51_write_page(bank,
 527                                        region.start - start_extra.length,
 528                                        page);
 529                 if (res != ERROR_OK)
 530                         return res;
 531         }
 532
 533         if (end_extra.length) {
 534                 uint8_t page[chip->code_page_size];
 535
 536                 /* Retrieve the full row contents from Flash */
 537                 res = target_read_memory(bank->target,
 538                                          region.end,
 539                                          1,
 540                                          (chip->code_page_size - end_extra.length),
 541                                          page + end_extra.length);
 542                 if (res != ERROR_OK)
 543                         return res;
 544
 545                 memcpy(page, end_extra.buffer, end_extra.length);
 546
 547                 res = nrf51_write_page(bank,
 548                                        region.end - end_extra.length,
 549                                        page);
 550                 if (res != ERROR_OK)
 551                         return res;
 552         }
 553
 554
 555         region.start += start_extra.length;
 556         region.end   -= end_extra.length;
 557
 558         for (uint32_t address = region.start; address < region.end;
 559              address += chip->code_page_size) {
 560                 res = nrf51_write_page(bank, address, &buffer[address - region.start]);
 561
 562                 if (res != ERROR_OK)
 563                         return res;
 564
 565         }
 566
 567         return ERROR_OK;
 568 }
 569
 570 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command)
 571 {
 572         struct nrf51_info *chip;
 573
 574         /* Create a new chip */
 575         chip = calloc(1, sizeof(*chip));
 576         if (!chip)
 577                 return ERROR_FAIL;
 578
 579         chip->target = bank->target;
 580         chip->probed = false;
 581
 582         bank->driver_priv = chip;
 583
 584         if (bank->base != NRF51_FLASH_BASE) {
 585                 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
 586                                 "[nrf51 series] )",
 587                                 bank->base, NRF51_FLASH_BASE);
 588                 return ERROR_FAIL;
 589         }
 590
 591         return ERROR_OK;
 592 }
 593
 594 COMMAND_HANDLER(nrf51_handle_mass_erase_command)
 595 {
 596         int res;
 597         struct flash_bank *bank;
 598
 599         res = get_flash_bank_by_num(0, &bank);
 600         if (res != ERROR_OK)
 601                 return res;
 602
 603         struct nrf51_info *chip;
 604
 605         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 606         if (res != ERROR_OK)
 607                 return res;
 608
 609         uint32_t ppfc;
 610
 611         res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 612                               &ppfc);
 613         if (res != ERROR_OK) {
 614                 LOG_ERROR("Couldn't read PPFC register");
 615                 return res;
 616         }
 617
 618         if ((ppfc & 0xFF) == 0x00) {
 619                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
 620                           "mass erase command won't work.");
 621                 return ERROR_FAIL;
 622         };
 623
 624         res = nrf51_erase_all(chip);
 625         if (res != ERROR_OK) {
 626                 LOG_ERROR("Failed to erase the chip");
 627                 nrf51_protect_check(bank);
 628                 return res;
 629         }
 630
 631         for (int i = 0; i < bank->num_sectors; i++)
 632                 bank->sectors[i].is_erased = 1;
 633
 634         return nrf51_protect_check(bank);
 635 }
 636
 637 static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
 638 {
 639         int res;
 640
 641         struct nrf51_info *chip;
 642
 643         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 644         if (res != ERROR_OK)
 645                 return res;
 646
 647         struct {
 648                 uint32_t address, value;
 649         } ficr[] = {
 650                 { .address = NRF51_FICR_CODEPAGESIZE    },
 651                 { .address = NRF51_FICR_CODESIZE        },
 652                 { .address = NRF51_FICR_CLENR0          },
 653                 { .address = NRF51_FICR_PPFC            },
 654                 { .address = NRF51_FICR_NUMRAMBLOCK     },
 655                 { .address = NRF51_FICR_SIZERAMBLOCK0   },
 656                 { .address = NRF51_FICR_SIZERAMBLOCK1   },
 657                 { .address = NRF51_FICR_SIZERAMBLOCK2   },
 658                 { .address = NRF51_FICR_SIZERAMBLOCK3   },
 659                 { .address = NRF51_FICR_CONFIGID        },
 660                 { .address = NRF51_FICR_DEVICEID0       },
 661                 { .address = NRF51_FICR_DEVICEID1       },
 662                 { .address = NRF51_FICR_ER0             },
 663                 { .address = NRF51_FICR_ER1             },
 664                 { .address = NRF51_FICR_ER2             },
 665                 { .address = NRF51_FICR_ER3             },
 666                 { .address = NRF51_FICR_IR0             },
 667                 { .address = NRF51_FICR_IR1             },
 668                 { .address = NRF51_FICR_IR2             },
 669                 { .address = NRF51_FICR_IR3             },
 670                 { .address = NRF51_FICR_DEVICEADDRTYPE  },
 671                 { .address = NRF51_FICR_DEVICEADDR0     },
 672                 { .address = NRF51_FICR_DEVICEADDR1     },
 673                 { .address = NRF51_FICR_OVERRIDEN       },
 674                 { .address = NRF51_FICR_NRF_1MBIT0      },
 675                 { .address = NRF51_FICR_NRF_1MBIT1      },
 676                 { .address = NRF51_FICR_NRF_1MBIT2      },
 677                 { .address = NRF51_FICR_NRF_1MBIT3      },
 678                 { .address = NRF51_FICR_NRF_1MBIT4      },
 679                 { .address = NRF51_FICR_BLE_1MBIT0      },
 680                 { .address = NRF51_FICR_BLE_1MBIT1      },
 681                 { .address = NRF51_FICR_BLE_1MBIT2      },
 682                 { .address = NRF51_FICR_BLE_1MBIT3      },
 683                 { .address = NRF51_FICR_BLE_1MBIT4      },
 684         }, uicr[] = {
 685                 { .address = NRF51_UICR_CLENR0,         },
 686                 { .address = NRF51_UICR_RBPCONF         },
 687                 { .address = NRF51_UICR_XTALFREQ        },
 688                 { .address = NRF51_UICR_FWID            },
 689         };
 690
 691         for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
 692                 res = target_read_u32(chip->target, ficr[i].address,
 693                                       &ficr[i].value);
 694                 if (res != ERROR_OK) {
 695                         LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
 696                         return res;
 697                 }
 698         }
 699
 700         for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
 701                 res = target_read_u32(chip->target, uicr[i].address,
 702                                       &uicr[i].value);
 703                 if (res != ERROR_OK) {
 704                         LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
 705                         return res;
 706                 }
 707         }
 708
 709         snprintf(buf, buf_size,
 710                  "\n[factory information control block]\n\n"
 711                  "code page size: %"PRIu32"B\n"
 712                  "code memory size: %"PRIu32"kB\n"
 713                  "code region 0 size: %"PRIu32"kB\n"
 714                  "pre-programmed code: %s\n"
 715                  "number of ram blocks: %"PRIu32"\n"
 716                  "ram block 0 size: %"PRIu32"B\n"
 717                  "ram block 1 size: %"PRIu32"B\n"
 718                  "ram block 2 size: %"PRIu32"B\n"
 719                  "ram block 3 size: %"PRIu32 "B\n"
 720                  "config id: %" PRIx32 "\n"
 721                  "device id: 0x%"PRIx32"%08"PRIx32"\n"
 722                  "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
 723                  "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
 724                  "device address type: 0x%"PRIx32"\n"
 725                  "device address: 0x%"PRIx32"%08"PRIx32"\n"
 726                  "override enable: %"PRIx32"\n"
 727                  "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
 728                  "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
 729                  "\n[user information control block]\n\n"
 730                  "code region 0 size: %"PRIu32"kB\n"
 731                  "read back protection configuration: %"PRIx32"\n"
 732                  "reset value for XTALFREQ: %"PRIx32"\n"
 733                  "firmware id: 0x%04"PRIx32,
 734                  ficr[0].value,
 735                  ficr[1].value,
 736                  (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
 737                  ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
 738                  ficr[4].value,
 739                  ficr[5].value,
 740                  (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
 741                  (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
 742                  (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
 743                  ficr[9].value,
 744                  ficr[10].value, ficr[11].value,
 745                  ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
 746                  ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
 747                  ficr[20].value,
 748                  ficr[21].value, ficr[22].value,
 749                  ficr[23].value,
 750                  ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
 751                  ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
 752                  (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
 753                  uicr[1].value & 0xFFFF,
 754                  uicr[2].value & 0xFF,
 755                  uicr[3].value & 0xFFFF);
 756
 757         return ERROR_OK;
 758 }
 759
 760 static const struct command_registration nrf51_exec_command_handlers[] = {
 761         {
 762                 .name           = "mass_erase",
 763                 .handler        = nrf51_handle_mass_erase_command,
 764                 .mode           = COMMAND_EXEC,
 765                 .help           = "Erase all flash contents of the chip.",
 766         },
 767         COMMAND_REGISTRATION_DONE
 768 };
 769
 770 static const struct command_registration nrf51_command_handlers[] = {
 771         {
 772                 .name   = "nrf51",
 773                 .mode   = COMMAND_ANY,
 774                 .help   = "nrf51 flash command group",
 775                 .usage  = "",
 776                 .chain  = nrf51_exec_command_handlers,
 777         },
 778         COMMAND_REGISTRATION_DONE
 779 };
 780
 781 struct flash_driver nrf51_flash = {
 782         .name                   = "nrf51",
 783         .commands               = nrf51_command_handlers,
 784         .flash_bank_command     = nrf51_flash_bank_command,
 785         .info                   = nrf51_info,
 786         .erase                  = nrf51_erase,
 787         .protect                = nrf51_protect,
 788         .write                  = nrf51_write,
 789         .read                   = default_flash_read,
 790         .probe                  = nrf51_probe,
 791         .auto_probe             = nrf51_auto_probe,
 792         .erase_check            = default_flash_blank_check,
 793         .protect_check          = nrf51_protect_check,
 794 };