git.sur5r.net Git - openocd/blob - src/flash/nor/spearsmi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 /* SPEAr Serial Memory Interface (SMI) controller is a SPI bus controller
  21  * specifically designed for SPI memories.
  22  * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
  23  * Two working modes are available:
  24  * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
  25  *   on the bus.
  26  * - HW mode: the SPI but is under SMI control. Memory content is directly
  27  *   accessible in CPU memory space. CPU can read, write and execute memory
  28  *   content. */
  29
  30 /* ATTENTION:
  31  * To have flash memory mapped in CPU memory space, the SMI controller
  32  * have to be in "HW mode". This requires following constraints:
  33  * 1) The command "reset init" have to initialize SMI controller and put
  34  *    it in HW mode;
  35  * 2) every command in this file have to return to prompt in HW mode. */
  36
  37 #ifdef HAVE_CONFIG_H
  38 #include "config.h"
  39 #endif
  40
  41 #include "imp.h"
  42 #include <jtag/jtag.h>
  43 #include <helper/time_support.h>
  44
  45 #define SMI_READ_REG(a) (_SMI_READ_REG(a))
  46 #define _SMI_READ_REG(a)                \
  47 {                                       \
  48         int __a;                        \
  49         uint32_t __v;                   \
  50                                         \
  51         __a = target_read_u32(target, io_base + (a), &__v); \
  52         if (__a != ERROR_OK)            \
  53             return __a;                 \
  54         __v;                            \
  55 }
  56
  57 #define SMI_WRITE_REG(a,v)              \
  58 {                                       \
  59         int __r;                        \
  60                                         \
  61         __r = target_write_u32(target, io_base + (a), (v)); \
  62         if (__r != ERROR_OK)            \
  63             return __r;                 \
  64 }
  65
  66 #define SMI_POLL_TFF(timeout)           \
  67 {                                       \
  68         int __r;                        \
  69                                         \
  70         __r = poll_tff(target, io_base, timeout); \
  71         if (__r != ERROR_OK)            \
  72             return __r;                 \
  73 }
  74
  75 #define SMI_SET_SW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  76         SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
  77 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
  78         (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
  79 #define SMI_SET_HW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  80         SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
  81 #define SMI_CLEAR_TFF()         SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
  82
  83 #define SMI_BANK_SIZE      (0x01000000)
  84
  85 #define SMI_CR1 (0x00) /* Control register 1 */
  86 #define SMI_CR2 (0x04) /* Control register 2 */
  87 #define SMI_SR  (0x08) /* Status register */
  88 #define SMI_TR  (0x0c) /* TX */
  89 #define SMI_RR  (0x10) /* RX */
  90
  91 /* fields in SMI_CR1 */
  92 #define SMI_SW_MODE       0x10000000 /* set to enable SW Mode */
  93 #define SMI_WB_MODE       0x20000000 /* Write Burst Mode */
  94
  95 /* fields in SMI_CR2 */
  96 #define SMI_TX_LEN_1      0x00000001 /* data length = 1 byte */
  97 #define SMI_TX_LEN_4      0x00000004 /* data length = 4 byte */
  98 #define SMI_RX_LEN_3      0x00000030 /* data length = 3 byte */
  99 #define SMI_SEND          0x00000080 /* Send data */
 100 #define SMI_RSR           0x00000400 /* reads status reg */
 101 #define SMI_WE            0x00000800 /* Write Enable */
 102 #define SMI_SEL_BANK0     0x00000000 /* Select Bank0 */
 103 #define SMI_SEL_BANK1     0x00001000 /* Select Bank1 */
 104 #define SMI_SEL_BANK2     0x00002000 /* Select Bank2 */
 105 #define SMI_SEL_BANK3     0x00003000 /* Select Bank3 */
 106
 107 /* fields in SMI_SR */
 108 #define SMI_WIP_BIT       0x00000001 /* WIP Bit of SPI SR on SMI SR */
 109 #define SMI_WEL_BIT       0x00000002 /* WEL Bit of SPI SR on SMI SR */
 110 #define SMI_TFF           0x00000100 /* Transfer Finished Flag */
 111
 112 /* Commands */
 113 #define SMI_READ_ID       0x0000009F /* Read Flash Identification */
 114
 115 /* Timeout in ms */
 116 #define SMI_CMD_TIMEOUT   (100)
 117 #define SMI_PROBE_TIMEOUT (100)
 118 #define SMI_MAX_TIMEOUT  (3000)
 119
 120 struct spearsmi_flash_bank
 121 {
 122         int probed;
 123         uint32_t io_base;
 124         uint32_t bank_num;
 125         struct flash_device *dev;
 126 };
 127
 128 /* data structure to maintain flash ids from different vendors */
 129 struct flash_device {
 130         char *name;
 131         uint8_t erase_cmd;
 132         uint32_t device_id;
 133         uint32_t pagesize;
 134         unsigned long sectorsize;
 135         unsigned long size_in_bytes;
 136 };
 137
 138 #define FLASH_ID(n, es, id, psize, ssize, size) \
 139 {                               \
 140         .name = n,              \
 141         .erase_cmd = es,        \
 142         .device_id = id,        \
 143         .pagesize = psize,      \
 144         .sectorsize = ssize,    \
 145         .size_in_bytes = size   \
 146 }
 147
 148 /* List below is taken from Linux driver. It is not exhaustive of all the
 149  * possible SPI memories, nor exclusive for SMI. Could be shared with
 150  * other SPI drivers. */
 151 static struct flash_device flash_devices[] = {
 152         /* name, erase_cmd, device_id, pagesize, sectorsize, size_in_bytes */
 153         FLASH_ID("st m25p05",      0xd8, 0x00102020, 0x80,  0x8000,  0x10000),
 154         FLASH_ID("st m25p10",      0xd8, 0x00112020, 0x80,  0x8000,  0x20000),
 155         FLASH_ID("st m25p20",      0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
 156         FLASH_ID("st m25p40",      0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
 157         FLASH_ID("st m25p80",      0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
 158         FLASH_ID("st m25p16",      0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
 159         FLASH_ID("st m25p32",      0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
 160         FLASH_ID("st m25p64",      0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
 161         FLASH_ID("st m25p128",     0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
 162         FLASH_ID("st m45pe10",     0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
 163         FLASH_ID("st m45pe20",     0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
 164         FLASH_ID("st m45pe40",     0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
 165         FLASH_ID("st m45pe80",     0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
 166         FLASH_ID("sp s25fl004",    0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
 167         FLASH_ID("sp s25fl008",    0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
 168         FLASH_ID("sp s25fl016",    0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
 169         FLASH_ID("sp s25fl032",    0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
 170         FLASH_ID("sp s25fl064",    0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
 171         FLASH_ID("atmel 25f512",   0x52, 0x0065001f, 0x80,  0x8000,  0x10000),
 172         FLASH_ID("atmel 25f1024",  0x52, 0x0060001f, 0x100, 0x8000,  0x20000),
 173         FLASH_ID("atmel 25f2048",  0x52, 0x0063001f, 0x100, 0x10000, 0x40000),
 174         FLASH_ID("atmel 25f4096",  0x52, 0x0064001f, 0x100, 0x10000, 0x80000),
 175         FLASH_ID("atmel 25fs040",  0xd7, 0x0004661f, 0x100, 0x10000, 0x80000),
 176         FLASH_ID("mac 25l512",     0xd8, 0x001020c2, 0x010, 0x10000, 0x10000),
 177         FLASH_ID("mac 25l1005",    0xd8, 0x001120c2, 0x010, 0x10000, 0x20000),
 178         FLASH_ID("mac 25l2005",    0xd8, 0x001220c2, 0x010, 0x10000, 0x40000),
 179         FLASH_ID("mac 25l4005",    0xd8, 0x001320c2, 0x010, 0x10000, 0x80000),
 180         FLASH_ID("mac 25l8005",    0xd8, 0x001420c2, 0x010, 0x10000, 0x100000),
 181         FLASH_ID("mac 25l1605",    0xd8, 0x001520c2, 0x100, 0x10000, 0x200000),
 182         FLASH_ID("mac 25l3205",    0xd8, 0x001620c2, 0x100, 0x10000, 0x400000),
 183         FLASH_ID("mac 25l6405",    0xd8, 0x001720c2, 0x100, 0x10000, 0x800000),
 184         FLASH_ID(NULL,             0,    0,          0,     0,       0)
 185 };
 186
 187 struct spearsmi_target {
 188         char *name;
 189         uint32_t tap_idcode;
 190         uint32_t smi_base;
 191         uint32_t io_base;
 192 };
 193
 194 static struct spearsmi_target target_devices[] = {
 195         /* name,          tap_idcode, smi_base,   io_base */
 196         { "SPEAr3xx/6xx", 0x07926041, 0xf8000000, 0xfc000000 },
 197         { "STR75x",       0x4f1f0041, 0x80000000, 0x90000000 },
 198         { NULL,           0,          0,          0 }
 199 };
 200
 201 FLASH_BANK_COMMAND_HANDLER(spearsmi_flash_bank_command)
 202 {
 203         struct spearsmi_flash_bank *spearsmi_info;
 204
 205         LOG_DEBUG(__FUNCTION__);
 206
 207         if (CMD_ARGC < 6)
 208         {
 209                 LOG_WARNING("incomplete flash_bank spearsmi configuration");
 210                 return ERROR_FLASH_BANK_INVALID;
 211         }
 212
 213         spearsmi_info = malloc(sizeof(struct spearsmi_flash_bank));
 214         if (spearsmi_info == NULL)
 215         {
 216                 LOG_ERROR("not enough memory");
 217                 return ERROR_FAIL;
 218         }
 219
 220         bank->driver_priv = spearsmi_info;
 221         spearsmi_info->probed = 0;
 222
 223         return ERROR_OK;
 224 }
 225
 226 /* Poll transmit finished flag */
 227 /* timeout in ms */
 228 static int poll_tff(struct target *target, uint32_t io_base, int timeout)
 229 {
 230         long long endtime;
 231
 232         if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 233                 return ERROR_OK;
 234
 235         endtime = timeval_ms() + timeout;
 236         do {
 237                 alive_sleep(1);
 238                 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 239                         return ERROR_OK;
 240         } while (timeval_ms() < endtime);
 241
 242         LOG_ERROR("Timeout while polling TFF");
 243         return ERROR_FLASH_OPERATION_FAILED;
 244 }
 245
 246 /* Read the status register of the external SPI flash chip.
 247  * The operation is triggered by setting SMI_RSR bit.
 248  * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
 249 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
 250 {
 251         struct target *target = bank->target;
 252         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 253         uint32_t io_base = spearsmi_info->io_base;
 254
 255         /* clear transmit finished flag */
 256         SMI_CLEAR_TFF();
 257
 258         /* Read status */
 259         SMI_WRITE_REG(SMI_CR2, spearsmi_info->bank_num | SMI_RSR);
 260
 261         /* Poll transmit finished flag */
 262         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 263
 264         /* clear transmit finished flag */
 265         SMI_CLEAR_TFF();
 266
 267         *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
 268
 269         /* clean-up SMI_CR2 */
 270         SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
 271
 272         return ERROR_OK;
 273 }
 274
 275 /* check for WIP (write in progress) bit in status register */
 276 /* timeout in ms */
 277 static int wait_till_ready(struct flash_bank *bank, int timeout)
 278 {
 279         uint32_t status;
 280         int retval;
 281         long long endtime;
 282
 283     endtime = timeval_ms() + timeout;
 284     do {
 285         /* read flash status register */
 286         retval = read_status_reg(bank, &status);
 287         if (retval != ERROR_OK)
 288             return retval;
 289
 290                 if ((status & SMI_WIP_BIT) == 0)
 291                         return ERROR_OK;
 292                 alive_sleep(1);
 293     } while (timeval_ms() < endtime);
 294
 295         LOG_ERROR("timeout");
 296         return ERROR_FAIL;
 297 }
 298
 299 /* Send "write enable" command to SPI flash chip.
 300  * The operation is triggered by setting SMI_WE bit, and SMI sends
 301  * the proper SPI command (0x06) */
 302 static int smi_write_enable(struct flash_bank *bank)
 303 {
 304         struct target *target = bank->target;
 305         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 306         uint32_t io_base = spearsmi_info->io_base;
 307         uint32_t status;
 308         int retval;
 309
 310         /* Enter in HW mode */
 311         SMI_SET_HW_MODE(); /* AB: is this correct ?*/
 312
 313         /* clear transmit finished flag */
 314         SMI_CLEAR_TFF();
 315
 316         /* Send write enable command */
 317         SMI_WRITE_REG(SMI_CR2, spearsmi_info->bank_num | SMI_WE);
 318
 319         /* Poll transmit finished flag */
 320         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 321
 322         /* read flash status register */
 323         retval = read_status_reg(bank, &status);
 324         if (retval != ERROR_OK)
 325                 return retval;
 326
 327         /* Check write enabled */
 328         if ((status & SMI_WEL_BIT) == 0)
 329         {
 330                 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
 331                 return ERROR_FAIL;
 332         }
 333
 334         return ERROR_OK;
 335 }
 336
 337 static uint32_t erase_command(struct spearsmi_flash_bank *spearsmi_info,
 338         uint32_t offset)
 339 {
 340         union {
 341                 uint32_t command;
 342                 uint8_t x[4];
 343         } cmd;
 344
 345         cmd.x[0] = spearsmi_info->dev->erase_cmd;
 346         cmd.x[1] = offset >> 16;
 347         cmd.x[2] = offset >> 8;
 348         cmd.x[3] = offset;
 349
 350         return cmd.command;
 351 }
 352
 353 static int smi_erase_sector(struct flash_bank *bank, int sector)
 354 {
 355         struct target *target = bank->target;
 356         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 357         uint32_t io_base = spearsmi_info->io_base;
 358         uint32_t cmd;
 359         int retval;
 360
 361         retval = smi_write_enable(bank);
 362         if (retval != ERROR_OK)
 363                 return retval;
 364
 365         /* Switch to SW mode to send sector erase command */
 366         SMI_SET_SW_MODE();
 367
 368         /* clear transmit finished flag */
 369         SMI_CLEAR_TFF();
 370
 371         /* send SPI command "block erase" */
 372         cmd = erase_command(spearsmi_info, bank->sectors[sector].offset);
 373         SMI_WRITE_REG(SMI_TR, cmd);
 374         SMI_WRITE_REG(SMI_CR2, spearsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
 375
 376         /* Poll transmit finished flag */
 377         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 378
 379         /* poll WIP for end of self timed Sector Erase cycle */
 380         retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
 381         if (retval != ERROR_OK)
 382                 return retval;
 383
 384         return ERROR_OK;
 385 }
 386
 387 static int spearsmi_erase(struct flash_bank *bank, int first, int last)
 388 {
 389         struct target *target = bank->target;
 390         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 391         uint32_t io_base = spearsmi_info->io_base;
 392         int retval = ERROR_OK;
 393         int sector;
 394
 395         LOG_DEBUG("%s: from sector %d to sector %d", __FUNCTION__, first, last);
 396
 397         if (target->state != TARGET_HALTED)
 398         {
 399                 LOG_ERROR("Target not halted");
 400                 return ERROR_TARGET_NOT_HALTED;
 401         }
 402
 403         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 404         {
 405                 LOG_ERROR("Flash sector invalid");
 406                 return ERROR_FLASH_SECTOR_INVALID;
 407         }
 408
 409         if (!(spearsmi_info->probed))
 410         {
 411                 LOG_ERROR("Flash bank not probed");
 412                 return ERROR_FLASH_BANK_NOT_PROBED;
 413         }
 414
 415         for (sector = first; sector <= last; sector++)
 416         {
 417                 if (bank->sectors[sector].is_protected)
 418                 {
 419                         LOG_ERROR("Flash sector %d protected", sector);
 420                         return ERROR_FAIL;
 421                 }
 422         }
 423
 424         for (sector = first; sector <= last; sector++)
 425         {
 426                 retval = smi_erase_sector(bank, sector);
 427                 if (retval != ERROR_OK)
 428                         break;
 429                 keep_alive();
 430         }
 431
 432         /* Switch to HW mode before return to prompt */
 433         SMI_SET_HW_MODE();
 434         return retval;
 435 }
 436
 437 static int spearsmi_protect(struct flash_bank *bank, int set,
 438         int first, int last)
 439 {
 440         int sector;
 441
 442         for (sector = first; sector <= last; sector++)
 443                 bank->sectors[sector].is_protected = set;
 444         return ERROR_OK;
 445 }
 446
 447 static int smi_write_buffer(struct flash_bank *bank, uint8_t *buffer,
 448         uint32_t address, uint32_t len)
 449 {
 450         struct target *target = bank->target;
 451         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 452         uint32_t io_base = spearsmi_info->io_base;
 453         int retval;
 454
 455         LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
 456                 __FUNCTION__, address, len);
 457
 458         retval = smi_write_enable(bank);
 459         if (retval != ERROR_OK)
 460                 return retval;
 461
 462         /* HW mode, write burst mode */
 463         SMI_SET_HWWB_MODE();
 464
 465         retval = target_write_buffer(target, address, len, buffer);
 466         if (retval != ERROR_OK)
 467                 return retval;
 468
 469         return ERROR_OK;
 470 }
 471
 472 static int spearsmi_write(struct flash_bank *bank, uint8_t *buffer,
 473         uint32_t offset, uint32_t count)
 474 {
 475         struct target *target = bank->target;
 476         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 477         uint32_t io_base = spearsmi_info->io_base;
 478         uint32_t cur_count, page_size, page_offset;
 479         int sector;
 480         int retval = ERROR_OK;
 481
 482         LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
 483                 __FUNCTION__, offset, count);
 484
 485         if (target->state != TARGET_HALTED)
 486         {
 487                 LOG_ERROR("Target not halted");
 488                 return ERROR_TARGET_NOT_HALTED;
 489         }
 490
 491         if (offset + count > spearsmi_info->dev->size_in_bytes)
 492         {
 493                 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
 494                 count = spearsmi_info->dev->size_in_bytes - offset;
 495         }
 496
 497         /* Check sector protection */
 498         for (sector = 0; sector < bank->num_sectors; sector++)
 499         {
 500                 /* Start offset in or before this sector? */
 501                 /* End offset in or behind this sector? */
 502                 if ( (offset <
 503                                 (bank->sectors[sector].offset + bank->sectors[sector].size))
 504                         && ((offset + count - 1) >= bank->sectors[sector].offset)
 505                         && bank->sectors[sector].is_protected )
 506                 {
 507                         LOG_ERROR("Flash sector %d protected", sector);
 508                         return ERROR_FAIL;
 509                 }
 510         }
 511
 512         page_size = spearsmi_info->dev->pagesize;
 513
 514         /* unaligned buffer head */
 515         if (count > 0 && (offset & 3) != 0)
 516         {
 517                 cur_count = 4 - (offset & 3);
 518                 if (cur_count > count)
 519                         cur_count = count;
 520                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 521                         cur_count);
 522                 if (retval != ERROR_OK)
 523                         goto err;
 524                 offset += cur_count;
 525                 buffer += cur_count;
 526                 count -= cur_count;
 527         }
 528
 529         page_offset = offset % page_size;
 530         /* central part, aligned words */
 531         while (count >= 4)
 532         {
 533                 /* clip block at page boundary */
 534                 if (page_offset + count > page_size)
 535                         cur_count = page_size - page_offset;
 536                 else
 537                         cur_count = count & ~3;
 538
 539                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 540                         cur_count);
 541                 if (retval != ERROR_OK)
 542                         goto err;
 543
 544                 page_offset = 0;
 545                 buffer += cur_count;
 546                 offset += cur_count;
 547                 count -= cur_count;
 548
 549                 keep_alive();
 550         }
 551
 552         /* buffer tail */
 553         if (count > 0)
 554                 retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
 555
 556 err:
 557         /* Switch to HW mode before return to prompt */
 558         SMI_SET_HW_MODE();
 559         return retval;
 560 }
 561
 562 /* Return ID of flash device */
 563 /* On exit, SW mode is kept */
 564 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
 565 {
 566         struct target *target = bank->target;
 567         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 568         uint32_t io_base = spearsmi_info->io_base;
 569         int retval;
 570
 571         if (target->state != TARGET_HALTED)
 572         {
 573                 LOG_ERROR("Target not halted");
 574                 return ERROR_TARGET_NOT_HALTED;
 575         }
 576
 577         /* poll WIP */
 578         retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
 579         if (retval != ERROR_OK)
 580                 return retval;
 581
 582         /* enter in SW mode */
 583         SMI_SET_SW_MODE();
 584
 585         /* clear transmit finished flag */
 586         SMI_CLEAR_TFF();
 587
 588         /* Send SPI command "read ID" */
 589         SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
 590         SMI_WRITE_REG(SMI_CR2,
 591                 spearsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
 592
 593         /* Poll transmit finished flag */
 594         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 595
 596         /* clear transmit finished flag */
 597         SMI_CLEAR_TFF();
 598
 599         /* read ID from Receive Register */
 600         *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
 601         return ERROR_OK;
 602 }
 603
 604 static int spearsmi_probe(struct flash_bank *bank)
 605 {
 606         struct target *target = bank->target;
 607         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 608         uint32_t io_base;
 609         struct flash_sector *sectors;
 610         uint32_t id = 0; /* silence uninitialized warning */
 611         struct spearsmi_target *target_device;
 612         int retval;
 613
 614         if (spearsmi_info->probed)
 615                 free(bank->sectors);
 616         spearsmi_info->probed = 0;
 617
 618         for (target_device=target_devices ; target_device->name ; ++target_device)
 619                 if (target_device->tap_idcode == target->tap->idcode)
 620                         break;
 621         if (!target_device->name)
 622         {
 623                 LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SMI capable",
 624                                 target->tap->idcode);
 625                 return ERROR_FAIL;
 626         }
 627
 628         switch (bank->base - target_device->smi_base)
 629         {
 630                 case 0:
 631                         spearsmi_info->bank_num = SMI_SEL_BANK0;
 632                         break;
 633                 case SMI_BANK_SIZE:
 634                         spearsmi_info->bank_num = SMI_SEL_BANK1;
 635                         break;
 636                 case 2*SMI_BANK_SIZE:
 637                         spearsmi_info->bank_num = SMI_SEL_BANK2;
 638                         break;
 639                 case 3*SMI_BANK_SIZE:
 640                         spearsmi_info->bank_num = SMI_SEL_BANK3;
 641                         break;
 642                 default:
 643                         LOG_ERROR("Invalid SMI base address 0x%" PRIx32, bank->base);
 644                         return ERROR_FAIL;
 645         }
 646         io_base = target_device->io_base;
 647         spearsmi_info->io_base = io_base;
 648
 649         LOG_DEBUG("Valid SMI on device %s at address 0x%" PRIx32,
 650                 target_device->name, bank->base);
 651
 652         /* read and decode flash ID; returns in SW mode */
 653         retval = read_flash_id(bank, &id);
 654         SMI_SET_HW_MODE();
 655         if (retval != ERROR_OK)
 656                 return retval;
 657
 658         spearsmi_info->dev = NULL;
 659         for (struct flash_device *p = flash_devices; p->name ; p++)
 660                 if (p->device_id == id) {
 661                         spearsmi_info->dev = p;
 662                         break;
 663                 }
 664
 665         if (!spearsmi_info->dev)
 666         {
 667                 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
 668                 return ERROR_FAIL;
 669         }
 670
 671         LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
 672                 spearsmi_info->dev->name, spearsmi_info->dev->device_id);
 673
 674         /* Set correct size value */
 675         bank->size = spearsmi_info->dev->size_in_bytes;
 676
 677         /* create and fill sectors array */
 678         bank->num_sectors =
 679                 spearsmi_info->dev->size_in_bytes / spearsmi_info->dev->sectorsize;
 680         sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 681         if (sectors == NULL)
 682         {
 683                 LOG_ERROR("not enough memory");
 684                 return ERROR_FAIL;
 685         }
 686
 687         for (int sector = 0; sector < bank->num_sectors; sector++)
 688         {
 689                 sectors[sector].offset = sector * spearsmi_info->dev->sectorsize;
 690                 sectors[sector].size = spearsmi_info->dev->sectorsize;
 691                 sectors[sector].is_erased = -1;
 692                 sectors[sector].is_protected = 1;
 693         }
 694
 695         bank->sectors = sectors;
 696         spearsmi_info->probed = 1;
 697         return ERROR_OK;
 698 }
 699
 700 static int spearsmi_auto_probe(struct flash_bank *bank)
 701 {
 702         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 703         if (spearsmi_info->probed)
 704                 return ERROR_OK;
 705         return spearsmi_probe(bank);
 706 }
 707
 708 static int spearsmi_protect_check(struct flash_bank *bank)
 709 {
 710         /* Nothing to do. Protection is only handled in SW. */
 711         return ERROR_OK;
 712 }
 713
 714 static int get_spearsmi_info(struct flash_bank *bank, char *buf, int buf_size)
 715 {
 716         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 717         int printed;
 718
 719         if (!(spearsmi_info->probed))
 720         {
 721                 printed = snprintf(buf, buf_size,
 722                         "\nSPEAr SMI flash bank not probed yet\n");
 723                 return ERROR_OK;
 724         }
 725
 726         printed = snprintf(buf, buf_size, "\nSPEAr SMI flash information:\n"
 727                 "  Device \'%s\' (ID 0x%08x)\n",
 728                 spearsmi_info->dev->name, spearsmi_info->dev->device_id);
 729         buf += printed;
 730         buf_size -= printed;
 731
 732         return ERROR_OK;
 733 }
 734
 735 struct flash_driver spearsmi_flash = {
 736         .name = "spearsmi",
 737         .flash_bank_command = spearsmi_flash_bank_command,
 738         .erase = spearsmi_erase,
 739         .protect = spearsmi_protect,
 740         .write = spearsmi_write,
 741         .read = default_flash_read,
 742         .probe = spearsmi_probe,
 743         .auto_probe = spearsmi_auto_probe,
 744         .erase_check = default_flash_blank_check,
 745         .protect_check = spearsmi_protect_check,
 746         .info = get_spearsmi_info,
 747 };