git.sur5r.net Git - openocd/blob - src/flash/nor/spearsmi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 /* SPEAr Serial Memory Interface (SMI) controller is a SPI bus controller
  21  * specifically designed for SPI memories.
  22  * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
  23  * Two working modes are available:
  24  * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
  25  *   on the bus.
  26  * - HW mode: the SPI but is under SMI control. Memory content is directly
  27  *   accessible in CPU memory space. CPU can read, write and execute memory
  28  *   content. */
  29
  30 /* ATTENTION:
  31  * To have flash memory mapped in CPU memory space, the SMI controller
  32  * have to be in "HW mode". This requires following constraints:
  33  * 1) The command "reset init" have to initialize SMI controller and put
  34  *    it in HW mode;
  35  * 2) every command in this file have to return to prompt in HW mode. */
  36
  37 #ifdef HAVE_CONFIG_H
  38 #include "config.h"
  39 #endif
  40
  41 #include "imp.h"
  42 #include "spearsmi.h"
  43 #include <jtag/jtag.h>
  44 #include <helper/time_support.h>
  45
  46 #define JTAG_ID_3XX_6XX  (0x07926041)
  47
  48 #define SMI_READ_REG(a) (_SMI_READ_REG(a))
  49 #define _SMI_READ_REG(a)                \
  50 {                                       \
  51         int __a;                        \
  52         uint32_t __v;                   \
  53                                         \
  54         __a = target_read_u32(target, io_base + (a), &__v); \
  55         if (__a != ERROR_OK)            \
  56             return __a;                 \
  57         __v;                            \
  58 }
  59
  60 #define SMI_WRITE_REG(a,v)              \
  61 {                                       \
  62         int __r;                        \
  63                                         \
  64         __r = target_write_u32(target, io_base + (a), (v)); \
  65         if (__r != ERROR_OK)            \
  66             return __r;                 \
  67 }
  68
  69 #define SMI_POLL_TFF(timeout)           \
  70 {                                       \
  71         int __r;                        \
  72                                         \
  73         __r = poll_tff(target, io_base, timeout); \
  74         if (__r != ERROR_OK)            \
  75             return __r;                 \
  76 }
  77
  78 #define SMI_SET_SW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  79         SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
  80 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
  81         (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
  82 #define SMI_SET_HW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  83         SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
  84 #define SMI_CLEAR_TFF()         SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
  85
  86 #define SMI_BANK_SIZE      (0x01000000)
  87
  88 #define SMI_BASE_3XX_6XX   (0xf8000000)
  89 #define SMI_CFGREG_3XX_6XX (0xfc000000)
  90
  91 /* #define SMI_BASE_13XX      (0xe6000000) */
  92 /* #define SMI_CFGREG_13XX    (0xea000000) */
  93
  94 #define SMI_CR1 (0x00) /* Control register 1 */
  95 #define SMI_CR2 (0x04) /* Control register 2 */
  96 #define SMI_SR  (0x08) /* Status register */
  97 #define SMI_TR  (0x0c) /* TX */
  98 #define SMI_RR  (0x10) /* RX */
  99
 100 /* fields in SMI_CR1 */
 101 #define SMI_SW_MODE       0x10000000 /* set to enable SW Mode */
 102 #define SMI_WB_MODE       0x20000000 /* Write Burst Mode */
 103
 104 /* fields in SMI_CR2 */
 105 #define SMI_TX_LEN_1      0x00000001 /* data length = 1 byte */
 106 #define SMI_TX_LEN_4      0x00000004 /* data length = 4 byte */
 107 #define SMI_RX_LEN_3      0x00000030 /* data length = 3 byte */
 108 #define SMI_SEND          0x00000080 /* Send data */
 109 #define SMI_RSR           0x00000400 /* reads status reg */
 110 #define SMI_WE            0x00000800 /* Write Enable */
 111 #define SMI_SEL_BANK0     0x00000000 /* Select Bank0 */
 112 #define SMI_SEL_BANK1     0x00001000 /* Select Bank1 */
 113 #define SMI_SEL_BANK2     0x00002000 /* Select Bank2 */
 114 #define SMI_SEL_BANK3     0x00003000 /* Select Bank3 */
 115
 116 /* fields in SMI_SR */
 117 #define SMI_WIP_BIT       0x00000001 /* WIP Bit of SPI SR on SMI SR */
 118 #define SMI_WEL_BIT       0x00000002 /* WEL Bit of SPI SR on SMI SR */
 119 #define SMI_TFF           0x00000100 /* Transfer Finished Flag */
 120
 121 /* Commands */
 122 #define SMI_READ_ID       0x0000009F /* Read Flash Identification */
 123
 124 /* Timeout in ms */
 125 #define SMI_CMD_TIMEOUT   (100)
 126 #define SMI_PROBE_TIMEOUT (100)
 127 #define SMI_MAX_TIMEOUT  (3000)
 128
 129 /* data structure to maintain flash ids from different vendors */
 130 struct flash_device {
 131         char *name;
 132         uint8_t erase_cmd;
 133         uint32_t device_id;
 134         uint32_t pagesize;
 135         unsigned long sectorsize;
 136         unsigned long size_in_bytes;
 137 };
 138
 139 #define FLASH_ID(n, es, id, psize, ssize, size) \
 140 {                               \
 141         .name = n,              \
 142         .erase_cmd = es,        \
 143         .device_id = id,        \
 144         .pagesize = psize,      \
 145         .sectorsize = ssize,    \
 146         .size_in_bytes = size   \
 147 }
 148
 149 /* List below is taken from Linux driver. It is not exhaustive of all the
 150  * possible SPI memories, nor exclusive for SMI. Could be shared with
 151  * other SPI drivers. */
 152 static struct flash_device flash_devices[] = {
 153         /* name, erase_cmd, device_id, pagesize, sectorsize, size_in_bytes */
 154         FLASH_ID("st m25p05",      0xd8, 0x00102020, 0x80,  0x8000,  0x10000),
 155         FLASH_ID("st m25p10",      0xd8, 0x00112020, 0x80,  0x8000,  0x20000),
 156         FLASH_ID("st m25p20",      0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
 157         FLASH_ID("st m25p40",      0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
 158         FLASH_ID("st m25p80",      0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
 159         FLASH_ID("st m25p16",      0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
 160         FLASH_ID("st m25p32",      0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
 161         FLASH_ID("st m25p64",      0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
 162         FLASH_ID("st m25p128",     0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
 163         FLASH_ID("st m45pe10",     0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
 164         FLASH_ID("st m45pe20",     0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
 165         FLASH_ID("st m45pe40",     0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
 166         FLASH_ID("st m45pe80",     0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
 167         FLASH_ID("sp s25fl004",    0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
 168         FLASH_ID("sp s25fl008",    0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
 169         FLASH_ID("sp s25fl016",    0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
 170         FLASH_ID("sp s25fl032",    0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
 171         FLASH_ID("sp s25fl064",    0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
 172         FLASH_ID("atmel 25f512",   0x52, 0x0065001f, 0x80,  0x8000,  0x10000),
 173         FLASH_ID("atmel 25f1024",  0x52, 0x0060001f, 0x100, 0x8000,  0x20000),
 174         FLASH_ID("atmel 25f2048",  0x52, 0x0063001f, 0x100, 0x10000, 0x40000),
 175         FLASH_ID("atmel 25f4096",  0x52, 0x0064001f, 0x100, 0x10000, 0x80000),
 176         FLASH_ID("atmel 25fs040",  0xd7, 0x0004661f, 0x100, 0x10000, 0x80000),
 177         FLASH_ID("mac 25l512",     0xd8, 0x001020c2, 0x010, 0x10000, 0x10000),
 178         FLASH_ID("mac 25l1005",    0xd8, 0x001120c2, 0x010, 0x10000, 0x20000),
 179         FLASH_ID("mac 25l2005",    0xd8, 0x001220c2, 0x010, 0x10000, 0x40000),
 180         FLASH_ID("mac 25l4005",    0xd8, 0x001320c2, 0x010, 0x10000, 0x80000),
 181         FLASH_ID("mac 25l8005",    0xd8, 0x001420c2, 0x010, 0x10000, 0x100000),
 182         FLASH_ID("mac 25l1605",    0xd8, 0x001520c2, 0x100, 0x10000, 0x200000),
 183         FLASH_ID("mac 25l3205",    0xd8, 0x001620c2, 0x100, 0x10000, 0x400000),
 184         FLASH_ID("mac 25l6405",    0xd8, 0x001720c2, 0x100, 0x10000, 0x800000),
 185         FLASH_ID(NULL,             0,    0,          0,     0,       0)
 186 };
 187
 188 FLASH_BANK_COMMAND_HANDLER(spearsmi_flash_bank_command)
 189 {
 190         struct spearsmi_flash_bank *spearsmi_info;
 191
 192         LOG_DEBUG(__FUNCTION__);
 193
 194         if (CMD_ARGC < 6)
 195         {
 196                 LOG_WARNING("incomplete flash_bank spearsmi configuration");
 197                 return ERROR_FLASH_BANK_INVALID;
 198         }
 199
 200         spearsmi_info = malloc(sizeof(struct spearsmi_flash_bank));
 201         if (spearsmi_info == NULL)
 202         {
 203                 LOG_ERROR("not enough memory");
 204                 return ERROR_FAIL;
 205         }
 206
 207         bank->driver_priv = spearsmi_info;
 208         spearsmi_info->probed = 0;
 209
 210         return ERROR_OK;
 211 }
 212
 213 /* Poll transmit finished flag */
 214 /* timeout in ms */
 215 static int poll_tff(struct target *target, uint32_t io_base, int timeout)
 216 {
 217         long long endtime;
 218
 219         if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 220                 return ERROR_OK;
 221
 222         endtime = timeval_ms() + timeout;
 223         do {
 224                 alive_sleep(1);
 225                 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 226                         return ERROR_OK;
 227         } while (timeval_ms() < endtime);
 228
 229         LOG_ERROR("Timeout while polling TFF");
 230         return ERROR_FLASH_OPERATION_FAILED;
 231 }
 232
 233 /* Read the status register of the external SPI flash chip.
 234  * The operation is triggered by setting SMI_RSR bit.
 235  * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
 236 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
 237 {
 238         struct target *target = bank->target;
 239         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 240         uint32_t io_base = spearsmi_info->io_base;
 241
 242         /* clear transmit finished flag */
 243         SMI_CLEAR_TFF();
 244
 245         /* Read status */
 246         SMI_WRITE_REG(SMI_CR2, spearsmi_info->bank_num | SMI_RSR);
 247
 248         /* Poll transmit finished flag */
 249         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 250
 251         /* clear transmit finished flag */
 252         SMI_CLEAR_TFF();
 253
 254         *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
 255
 256         /* clean-up SMI_CR2 */
 257         SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
 258
 259         return ERROR_OK;
 260 }
 261
 262 /* check for WIP (write in progress) bit in status register */
 263 /* timeout in ms */
 264 static int wait_till_ready(struct flash_bank *bank, int timeout)
 265 {
 266         uint32_t status;
 267         int retval;
 268         long long endtime;
 269
 270     endtime = timeval_ms() + timeout;
 271     do {
 272         /* read flash status register */
 273         retval = read_status_reg(bank, &status);
 274         if (retval != ERROR_OK)
 275             return retval;
 276
 277                 if ((status & SMI_WIP_BIT) == 0)
 278                         return ERROR_OK;
 279                 alive_sleep(1);
 280     } while (timeval_ms() < endtime);
 281
 282         LOG_ERROR("timeout");
 283         return ERROR_FAIL;
 284 }
 285
 286 /* Send "write enable" command to SPI flash chip.
 287  * The operation is triggered by setting SMI_WE bit, and SMI sends
 288  * the proper SPI command (0x06) */
 289 static int smi_write_enable(struct flash_bank *bank)
 290 {
 291         struct target *target = bank->target;
 292         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 293         uint32_t io_base = spearsmi_info->io_base;
 294         uint32_t status;
 295         int retval;
 296
 297         /* Enter in HW mode */
 298         SMI_SET_HW_MODE(); /* AB: is this correct ?*/
 299
 300         /* clear transmit finished flag */
 301         SMI_CLEAR_TFF();
 302
 303         /* Send write enable command */
 304         SMI_WRITE_REG(SMI_CR2, spearsmi_info->bank_num | SMI_WE);
 305
 306         /* Poll transmit finished flag */
 307         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 308
 309         /* read flash status register */
 310         retval = read_status_reg(bank, &status);
 311         if (retval != ERROR_OK)
 312                 return retval;
 313
 314         /* Check write enabled */
 315         if ((status & SMI_WEL_BIT) == 0)
 316         {
 317                 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
 318                 return ERROR_FAIL;
 319         }
 320
 321         return ERROR_OK;
 322 }
 323
 324 static uint32_t erase_command(struct spearsmi_flash_bank *spearsmi_info,
 325         uint32_t offset)
 326 {
 327         union {
 328                 uint32_t command;
 329                 uint8_t x[4];
 330         } cmd;
 331
 332         cmd.x[0] = spearsmi_info->dev->erase_cmd;
 333         cmd.x[1] = offset >> 16;
 334         cmd.x[2] = offset >> 8;
 335         cmd.x[3] = offset;
 336
 337         return cmd.command;
 338 }
 339
 340 static int smi_erase_sector(struct flash_bank *bank, int sector)
 341 {
 342         struct target *target = bank->target;
 343         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 344         uint32_t io_base = spearsmi_info->io_base;
 345         uint32_t cmd;
 346         int retval;
 347
 348         retval = smi_write_enable(bank);
 349         if (retval != ERROR_OK)
 350                 return retval;
 351
 352         /* Switch to SW mode to send sector erase command */
 353         SMI_SET_SW_MODE();
 354
 355         /* clear transmit finished flag */
 356         SMI_CLEAR_TFF();
 357
 358         /* send SPI command "block erase" */
 359         cmd = erase_command(spearsmi_info, bank->sectors[sector].offset);
 360         SMI_WRITE_REG(SMI_TR, cmd);
 361         SMI_WRITE_REG(SMI_CR2, spearsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
 362
 363         /* Poll transmit finished flag */
 364         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 365
 366         /* poll WIP for end of self timed Sector Erase cycle */
 367         retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
 368         if (retval != ERROR_OK)
 369                 return retval;
 370
 371         return ERROR_OK;
 372 }
 373
 374 static int spearsmi_erase(struct flash_bank *bank, int first, int last)
 375 {
 376         struct target *target = bank->target;
 377         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 378         uint32_t io_base = spearsmi_info->io_base;
 379         int retval = ERROR_OK;
 380         int sector;
 381
 382         LOG_DEBUG("%s: from sector %d to sector %d", __FUNCTION__, first, last);
 383
 384         if (target->state != TARGET_HALTED)
 385         {
 386                 LOG_ERROR("Target not halted");
 387                 return ERROR_TARGET_NOT_HALTED;
 388         }
 389
 390         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 391         {
 392                 LOG_ERROR("Flash sector invalid");
 393                 return ERROR_FLASH_SECTOR_INVALID;
 394         }
 395
 396         if (!(spearsmi_info->probed))
 397         {
 398                 LOG_ERROR("Flash bank not probed");
 399                 return ERROR_FLASH_BANK_NOT_PROBED;
 400         }
 401
 402         for (sector = first; sector <= last; sector++)
 403         {
 404                 if (bank->sectors[sector].is_protected)
 405                 {
 406                         LOG_ERROR("Flash sector %d protected", sector);
 407                         return ERROR_FAIL;
 408                 }
 409         }
 410
 411         for (sector = first; sector <= last; sector++)
 412         {
 413                 retval = smi_erase_sector(bank, sector);
 414                 if (retval != ERROR_OK)
 415                         break;
 416                 keep_alive();
 417         }
 418
 419         /* Switch to HW mode before return to prompt */
 420         SMI_SET_HW_MODE();
 421         return retval;
 422 }
 423
 424 static int spearsmi_protect(struct flash_bank *bank, int set,
 425         int first, int last)
 426 {
 427         int sector;
 428
 429         for (sector = first; sector <= last; sector++)
 430                 bank->sectors[sector].is_protected = set;
 431         return ERROR_OK;
 432 }
 433
 434 static int smi_write_buffer(struct flash_bank *bank, uint8_t *buffer,
 435         uint32_t address, uint32_t len)
 436 {
 437         struct target *target = bank->target;
 438         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 439         uint32_t io_base = spearsmi_info->io_base;
 440         int retval;
 441
 442         LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
 443                 __FUNCTION__, address, len);
 444
 445         retval = smi_write_enable(bank);
 446         if (retval != ERROR_OK)
 447                 return retval;
 448
 449         /* HW mode, write burst mode */
 450         SMI_SET_HWWB_MODE();
 451
 452         retval = target_write_buffer(target, address, len, buffer);
 453         if (retval != ERROR_OK)
 454                 return retval;
 455
 456         return ERROR_OK;
 457 }
 458
 459 static int spearsmi_write(struct flash_bank *bank, uint8_t *buffer,
 460         uint32_t offset, uint32_t count)
 461 {
 462         struct target *target = bank->target;
 463         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 464         uint32_t io_base = spearsmi_info->io_base;
 465         uint32_t cur_count, page_size, page_offset;
 466         int sector;
 467         int retval = ERROR_OK;
 468
 469         LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
 470                 __FUNCTION__, offset, count);
 471
 472         if (target->state != TARGET_HALTED)
 473         {
 474                 LOG_ERROR("Target not halted");
 475                 return ERROR_TARGET_NOT_HALTED;
 476         }
 477
 478         if (offset + count > spearsmi_info->dev->size_in_bytes)
 479         {
 480                 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
 481                 count = spearsmi_info->dev->size_in_bytes - offset;
 482         }
 483
 484         /* Check sector protection */
 485         for (sector = 0; sector < bank->num_sectors; sector++)
 486         {
 487                 /* Start offset in or before this sector? */
 488                 /* End offset in or behind this sector? */
 489                 if ( (offset <
 490                                 (bank->sectors[sector].offset + bank->sectors[sector].size))
 491                         && ((offset + count - 1) >= bank->sectors[sector].offset)
 492                         && bank->sectors[sector].is_protected )
 493                 {
 494                         LOG_ERROR("Flash sector %d protected", sector);
 495                         return ERROR_FAIL;
 496                 }
 497         }
 498
 499         page_size = spearsmi_info->dev->pagesize;
 500
 501         /* unaligned buffer head */
 502         if (count > 0 && (offset & 3) != 0)
 503         {
 504                 cur_count = 4 - (offset & 3);
 505                 if (cur_count > count)
 506                         cur_count = count;
 507                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 508                         cur_count);
 509                 if (retval != ERROR_OK)
 510                         goto err;
 511                 offset += cur_count;
 512                 buffer += cur_count;
 513                 count -= cur_count;
 514         }
 515
 516         page_offset = offset % page_size;
 517         /* central part, aligned words */
 518         while (count >= 4)
 519         {
 520                 /* clip block at page boundary */
 521                 if (page_offset + count > page_size)
 522                         cur_count = page_size - page_offset;
 523                 else
 524                         cur_count = count & ~3;
 525
 526                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 527                         cur_count);
 528                 if (retval != ERROR_OK)
 529                         goto err;
 530
 531                 page_offset = 0;
 532                 buffer += cur_count;
 533                 offset += cur_count;
 534                 count -= cur_count;
 535
 536                 keep_alive();
 537         }
 538
 539         /* buffer tail */
 540         if (count > 0)
 541                 retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
 542
 543 err:
 544         /* Switch to HW mode before return to prompt */
 545         SMI_SET_HW_MODE();
 546         return retval;
 547 }
 548
 549 /* Return ID of flash device */
 550 /* On exit, SW mode is kept */
 551 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
 552 {
 553         struct target *target = bank->target;
 554         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 555         uint32_t io_base = spearsmi_info->io_base;
 556         int retval;
 557
 558         if (target->state != TARGET_HALTED)
 559         {
 560                 LOG_ERROR("Target not halted");
 561                 return ERROR_TARGET_NOT_HALTED;
 562         }
 563
 564         /* poll WIP */
 565         retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
 566         if (retval != ERROR_OK)
 567                 return retval;
 568
 569         /* enter in SW mode */
 570         SMI_SET_SW_MODE();
 571
 572         /* clear transmit finished flag */
 573         SMI_CLEAR_TFF();
 574
 575         /* Send SPI command "read ID" */
 576         SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
 577         SMI_WRITE_REG(SMI_CR2,
 578                 spearsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
 579
 580         /* Poll transmit finished flag */
 581         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 582
 583         /* clear transmit finished flag */
 584         SMI_CLEAR_TFF();
 585
 586         /* read ID from Receive Register */
 587         *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
 588         return ERROR_OK;
 589 }
 590
 591 static int spearsmi_probe(struct flash_bank *bank)
 592 {
 593         struct target *target = bank->target;
 594         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 595         uint32_t io_base;
 596         struct flash_sector *sectors;
 597         uint32_t id = 0; /* silence uninitialized warning */
 598         int retval;
 599
 600         if (spearsmi_info->probed)
 601                 free(bank->sectors);
 602         spearsmi_info->probed = 0;
 603
 604         /* check for SPEAr device */
 605         switch (target->tap->idcode)
 606         {
 607                 case JTAG_ID_3XX_6XX:
 608                         /* SPEAr3xx/6xx */
 609                         spearsmi_info->io_base = SMI_CFGREG_3XX_6XX;
 610                         switch (bank->base)
 611                         {
 612                                 case SMI_BASE_3XX_6XX:
 613                                         spearsmi_info->bank_num = SMI_SEL_BANK0;
 614                                         break;
 615                                 case SMI_BASE_3XX_6XX + SMI_BANK_SIZE:
 616                                         spearsmi_info->bank_num = SMI_SEL_BANK1;
 617                                         break;
 618                                 case SMI_BASE_3XX_6XX + 2*SMI_BANK_SIZE:
 619                                         spearsmi_info->bank_num = SMI_SEL_BANK2;
 620                                         break;
 621                                 case SMI_BASE_3XX_6XX + 3*SMI_BANK_SIZE:
 622                                         spearsmi_info->bank_num = SMI_SEL_BANK3;
 623                                         break;
 624                                 default:
 625                                         LOG_ERROR("Invalid base address 0x%" PRIx32, bank->base);
 626                                         return ERROR_FAIL;
 627                         }
 628                         break;
 629
 630                 default:
 631                         LOG_ERROR("0x%" PRIx32 " is invalid id for SPEAr device",
 632                                 target->tap->idcode);
 633                         return ERROR_FAIL;
 634         }
 635         io_base = spearsmi_info->io_base;
 636
 637         /* read and decode flash ID; returns in SW mode */
 638         retval = read_flash_id(bank, &id);
 639         SMI_SET_HW_MODE();
 640         if (retval != ERROR_OK)
 641                 return retval;
 642
 643         for (struct flash_device *p = flash_devices; p->name ; p++)
 644                 if (p->device_id == id) {
 645                         spearsmi_info->dev = p;
 646                         break;
 647                 }
 648
 649         if (!spearsmi_info->dev)
 650         {
 651                 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
 652                 return ERROR_FAIL;
 653         }
 654
 655         LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
 656                 spearsmi_info->dev->name, spearsmi_info->dev->device_id);
 657
 658         /* Set correct size value */
 659         bank->size = spearsmi_info->dev->size_in_bytes;
 660
 661         /* create and fill sectors array */
 662         bank->num_sectors =
 663                 spearsmi_info->dev->size_in_bytes / spearsmi_info->dev->sectorsize;
 664         sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 665         if (sectors == NULL)
 666         {
 667                 LOG_ERROR("not enough memory");
 668                 return ERROR_FAIL;
 669         }
 670
 671         for (int sector = 0; sector < bank->num_sectors; sector++)
 672         {
 673                 sectors[sector].offset = sector * spearsmi_info->dev->sectorsize;
 674                 sectors[sector].size = spearsmi_info->dev->sectorsize;
 675                 sectors[sector].is_erased = -1;
 676                 sectors[sector].is_protected = 1;
 677         }
 678
 679         bank->sectors = sectors;
 680         spearsmi_info->probed = 1;
 681         return ERROR_OK;
 682 }
 683
 684 static int spearsmi_auto_probe(struct flash_bank *bank)
 685 {
 686         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 687         if (spearsmi_info->probed)
 688                 return ERROR_OK;
 689         return spearsmi_probe(bank);
 690 }
 691
 692 static int spearsmi_protect_check(struct flash_bank *bank)
 693 {
 694         /* Nothing to do. Protection is only handled in SW. */
 695         return ERROR_OK;
 696 }
 697
 698 static int get_spearsmi_info(struct flash_bank *bank, char *buf, int buf_size)
 699 {
 700         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 701         int printed;
 702
 703         if (!(spearsmi_info->probed))
 704         {
 705                 printed = snprintf(buf, buf_size,
 706                         "\nSPEAr SMI flash bank not probed yet\n");
 707                 return ERROR_OK;
 708         }
 709
 710         printed = snprintf(buf, buf_size, "\nSPEAr SMI flash information:\n"
 711                 "  Device \'%s\' (ID 0x%08x)\n",
 712                 spearsmi_info->dev->name, spearsmi_info->dev->device_id);
 713         buf += printed;
 714         buf_size -= printed;
 715
 716         return ERROR_OK;
 717 }
 718
 719 struct flash_driver spearsmi_flash = {
 720         .name = "spearsmi",
 721         .flash_bank_command = spearsmi_flash_bank_command,
 722         .erase = spearsmi_erase,
 723         .protect = spearsmi_protect,
 724         .write = spearsmi_write,
 725         .read = default_flash_read,
 726         .probe = spearsmi_probe,
 727         .auto_probe = spearsmi_auto_probe,
 728         .erase_check = default_flash_blank_check,
 729         .protect_check = spearsmi_protect_check,
 730         .info = get_spearsmi_info,
 731 };