git.sur5r.net Git - openocd/blob - src/flash/nor/stm32f1x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "imp.h"
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34 #include <target/armv7m.h>
  35
  36 /* stm32x register locations */
  37
  38 #define FLASH_REG_BASE_B0 0x40022000
  39 #define FLASH_REG_BASE_B1 0x40022040
  40
  41 #define STM32_FLASH_ACR     0x00
  42 #define STM32_FLASH_KEYR    0x04
  43 #define STM32_FLASH_OPTKEYR 0x08
  44 #define STM32_FLASH_SR      0x0C
  45 #define STM32_FLASH_CR      0x10
  46 #define STM32_FLASH_AR      0x14
  47 #define STM32_FLASH_OBR     0x1C
  48 #define STM32_FLASH_WRPR    0x20
  49
  50 /* TODO: Check if code using these really should be hard coded to bank 0.
  51  * There are valid cases, on dual flash devices the protection of the
  52  * second bank is done on the bank0 reg's. */
  53 #define STM32_FLASH_ACR_B0     0x40022000
  54 #define STM32_FLASH_KEYR_B0    0x40022004
  55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  56 #define STM32_FLASH_SR_B0      0x4002200C
  57 #define STM32_FLASH_CR_B0      0x40022010
  58 #define STM32_FLASH_AR_B0      0x40022014
  59 #define STM32_FLASH_OBR_B0     0x4002201C
  60 #define STM32_FLASH_WRPR_B0    0x40022020
  61
  62 /* option byte location */
  63
  64 #define STM32_OB_RDP            0x1FFFF800
  65 #define STM32_OB_USER           0x1FFFF802
  66 #define STM32_OB_DATA0          0x1FFFF804
  67 #define STM32_OB_DATA1          0x1FFFF806
  68 #define STM32_OB_WRP0           0x1FFFF808
  69 #define STM32_OB_WRP1           0x1FFFF80A
  70 #define STM32_OB_WRP2           0x1FFFF80C
  71 #define STM32_OB_WRP3           0x1FFFF80E
  72
  73 /* FLASH_CR register bits */
  74
  75 #define FLASH_PG                (1 << 0)
  76 #define FLASH_PER               (1 << 1)
  77 #define FLASH_MER               (1 << 2)
  78 #define FLASH_OPTPG             (1 << 4)
  79 #define FLASH_OPTER             (1 << 5)
  80 #define FLASH_STRT              (1 << 6)
  81 #define FLASH_LOCK              (1 << 7)
  82 #define FLASH_OPTWRE    (1 << 9)
  83
  84 /* FLASH_SR register bits */
  85
  86 #define FLASH_BSY               (1 << 0)
  87 #define FLASH_PGERR             (1 << 2)
  88 #define FLASH_WRPRTERR  (1 << 4)
  89 #define FLASH_EOP               (1 << 5)
  90
  91 /* STM32_FLASH_OBR bit definitions (reading) */
  92
  93 #define OPT_ERROR               0
  94 #define OPT_READOUT             1
  95 #define OPT_RDWDGSW             2
  96 #define OPT_RDRSTSTOP   3
  97 #define OPT_RDRSTSTDBY  4
  98 #define OPT_BFB2                5       /* dual flash bank only */
  99
 100 /* register unlock keys */
 101
 102 #define KEY1                    0x45670123
 103 #define KEY2                    0xCDEF89AB
 104
 105 /* timeout values */
 106
 107 #define FLASH_WRITE_TIMEOUT 10
 108 #define FLASH_ERASE_TIMEOUT 100
 109
 110 struct stm32x_options {
 111         uint16_t RDP;
 112         uint16_t user_options;
 113         uint16_t user_data;
 114         uint16_t protection[4];
 115 };
 116
 117 struct stm32x_flash_bank {
 118         struct stm32x_options option_bytes;
 119         int ppage_size;
 120         int probed;
 121
 122         bool has_dual_banks;
 123         /* used to access dual flash bank stm32xl */
 124         uint32_t register_base;
 125         uint16_t default_rdp;
 126         int user_data_offset;
 127         int option_offset;
 128         uint32_t user_bank_size;
 129 };
 130
 131 static int stm32x_mass_erase(struct flash_bank *bank);
 132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
 133 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 134                 uint32_t offset, uint32_t count);
 135
 136 /* flash bank stm32x <base> <size> 0 0 <target#>
 137  */
 138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 139 {
 140         struct stm32x_flash_bank *stm32x_info;
 141
 142         if (CMD_ARGC < 6)
 143                 return ERROR_COMMAND_SYNTAX_ERROR;
 144
 145         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 146
 147         bank->driver_priv = stm32x_info;
 148         stm32x_info->probed = 0;
 149         stm32x_info->has_dual_banks = false;
 150         stm32x_info->register_base = FLASH_REG_BASE_B0;
 151         stm32x_info->user_bank_size = bank->size;
 152
 153         return ERROR_OK;
 154 }
 155
 156 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 157 {
 158         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 159         return reg + stm32x_info->register_base;
 160 }
 161
 162 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 163 {
 164         struct target *target = bank->target;
 165         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 166 }
 167
 168 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 169 {
 170         struct target *target = bank->target;
 171         uint32_t status;
 172         int retval = ERROR_OK;
 173
 174         /* wait for busy to clear */
 175         for (;;) {
 176                 retval = stm32x_get_flash_status(bank, &status);
 177                 if (retval != ERROR_OK)
 178                         return retval;
 179                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 180                 if ((status & FLASH_BSY) == 0)
 181                         break;
 182                 if (timeout-- <= 0) {
 183                         LOG_ERROR("timed out waiting for flash");
 184                         return ERROR_FAIL;
 185                 }
 186                 alive_sleep(1);
 187         }
 188
 189         if (status & FLASH_WRPRTERR) {
 190                 LOG_ERROR("stm32x device protected");
 191                 retval = ERROR_FAIL;
 192         }
 193
 194         if (status & FLASH_PGERR) {
 195                 LOG_ERROR("stm32x device programming failed");
 196                 retval = ERROR_FAIL;
 197         }
 198
 199         /* Clear but report errors */
 200         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 201                 /* If this operation fails, we ignore it and report the original
 202                  * retval
 203                  */
 204                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 205                                 FLASH_WRPRTERR | FLASH_PGERR);
 206         }
 207         return retval;
 208 }
 209
 210 static int stm32x_check_operation_supported(struct flash_bank *bank)
 211 {
 212         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 213
 214         /* if we have a dual flash bank device then
 215          * we need to perform option byte stuff on bank0 only */
 216         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 217                 LOG_ERROR("Option Byte Operation's must use bank0");
 218                 return ERROR_FLASH_OPERATION_FAILED;
 219         }
 220
 221         return ERROR_OK;
 222 }
 223
 224 static int stm32x_read_options(struct flash_bank *bank)
 225 {
 226         uint32_t optiondata;
 227         struct stm32x_flash_bank *stm32x_info = NULL;
 228         struct target *target = bank->target;
 229
 230         stm32x_info = bank->driver_priv;
 231
 232         /* read current option bytes */
 233         int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
 234         if (retval != ERROR_OK)
 235                 return retval;
 236
 237         stm32x_info->option_bytes.user_options = (optiondata >> stm32x_info->option_offset >> 2) & 0xffff;
 238         stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
 239         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 240
 241         if (optiondata & (1 << OPT_READOUT))
 242                 LOG_INFO("Device Security Bit Set");
 243
 244         /* each bit refers to a 4bank protection */
 245         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
 246         if (retval != ERROR_OK)
 247                 return retval;
 248
 249         stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
 250         stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
 251         stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
 252         stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
 253
 254         return ERROR_OK;
 255 }
 256
 257 static int stm32x_erase_options(struct flash_bank *bank)
 258 {
 259         struct stm32x_flash_bank *stm32x_info = NULL;
 260         struct target *target = bank->target;
 261
 262         stm32x_info = bank->driver_priv;
 263
 264         /* read current options */
 265         stm32x_read_options(bank);
 266
 267         /* unlock flash registers */
 268         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 269         if (retval != ERROR_OK)
 270                 return retval;
 271
 272         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 273         if (retval != ERROR_OK)
 274                 return retval;
 275
 276         /* unlock option flash registers */
 277         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 278         if (retval != ERROR_OK)
 279                 return retval;
 280         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 281         if (retval != ERROR_OK)
 282                 return retval;
 283
 284         /* erase option bytes */
 285         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 286         if (retval != ERROR_OK)
 287                 return retval;
 288         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 289         if (retval != ERROR_OK)
 290                 return retval;
 291
 292         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 293         if (retval != ERROR_OK)
 294                 return retval;
 295
 296         /* clear readout protection and complementary option bytes
 297          * this will also force a device unlock if set */
 298         stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
 299
 300         return ERROR_OK;
 301 }
 302
 303 static int stm32x_write_options(struct flash_bank *bank)
 304 {
 305         struct stm32x_flash_bank *stm32x_info = NULL;
 306         struct target *target = bank->target;
 307
 308         stm32x_info = bank->driver_priv;
 309
 310         /* unlock flash registers */
 311         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 312         if (retval != ERROR_OK)
 313                 return retval;
 314         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 315         if (retval != ERROR_OK)
 316                 return retval;
 317
 318         /* unlock option flash registers */
 319         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 320         if (retval != ERROR_OK)
 321                 return retval;
 322         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 323         if (retval != ERROR_OK)
 324                 return retval;
 325
 326         /* program option bytes */
 327         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 328         if (retval != ERROR_OK)
 329                 return retval;
 330
 331         uint8_t opt_bytes[16];
 332
 333         target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
 334         target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
 335         target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
 336         target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
 337         target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
 338         target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
 339         target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
 340         target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
 341
 342         uint32_t offset = STM32_OB_RDP - bank->base;
 343         retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
 344         if (retval != ERROR_OK) {
 345                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 346                         LOG_ERROR("working area required to erase options bytes");
 347                 return retval;
 348         }
 349
 350         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 351         if (retval != ERROR_OK)
 352                 return retval;
 353
 354         return ERROR_OK;
 355 }
 356
 357 static int stm32x_protect_check(struct flash_bank *bank)
 358 {
 359         struct target *target = bank->target;
 360         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 361
 362         uint32_t protection;
 363         int i, s;
 364         int num_bits;
 365         int set;
 366
 367         if (target->state != TARGET_HALTED) {
 368                 LOG_ERROR("Target not halted");
 369                 return ERROR_TARGET_NOT_HALTED;
 370         }
 371
 372         int retval = stm32x_check_operation_supported(bank);
 373         if (ERROR_OK != retval)
 374                 return retval;
 375
 376         /* medium density - each bit refers to a 4bank protection
 377          * high density - each bit refers to a 2bank protection */
 378         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 379         if (retval != ERROR_OK)
 380                 return retval;
 381
 382         /* medium density - each protection bit is for 4 * 1K pages
 383          * high density - each protection bit is for 2 * 2K pages */
 384         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 385
 386         if (stm32x_info->ppage_size == 2) {
 387                 /* high density flash/connectivity line protection */
 388
 389                 set = 1;
 390
 391                 if (protection & (1 << 31))
 392                         set = 0;
 393
 394                 /* bit 31 controls sector 62 - 255 protection for high density
 395                  * bit 31 controls sector 62 - 127 protection for connectivity line */
 396                 for (s = 62; s < bank->num_sectors; s++)
 397                         bank->sectors[s].is_protected = set;
 398
 399                 if (bank->num_sectors > 61)
 400                         num_bits = 31;
 401
 402                 for (i = 0; i < num_bits; i++) {
 403                         set = 1;
 404
 405                         if (protection & (1 << i))
 406                                 set = 0;
 407
 408                         for (s = 0; s < stm32x_info->ppage_size; s++)
 409                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 410                 }
 411         } else {
 412                 /* low/medium density flash protection */
 413                 for (i = 0; i < num_bits; i++) {
 414                         set = 1;
 415
 416                         if (protection & (1 << i))
 417                                 set = 0;
 418
 419                         for (s = 0; s < stm32x_info->ppage_size; s++)
 420                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 421                 }
 422         }
 423
 424         return ERROR_OK;
 425 }
 426
 427 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 428 {
 429         struct target *target = bank->target;
 430         int i;
 431
 432         if (bank->target->state != TARGET_HALTED) {
 433                 LOG_ERROR("Target not halted");
 434                 return ERROR_TARGET_NOT_HALTED;
 435         }
 436
 437         if ((first == 0) && (last == (bank->num_sectors - 1)))
 438                 return stm32x_mass_erase(bank);
 439
 440         /* unlock flash registers */
 441         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 442         if (retval != ERROR_OK)
 443                 return retval;
 444         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 445         if (retval != ERROR_OK)
 446                 return retval;
 447
 448         for (i = first; i <= last; i++) {
 449                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 450                 if (retval != ERROR_OK)
 451                         return retval;
 452                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 453                                 bank->base + bank->sectors[i].offset);
 454                 if (retval != ERROR_OK)
 455                         return retval;
 456                 retval = target_write_u32(target,
 457                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 458                 if (retval != ERROR_OK)
 459                         return retval;
 460
 461                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 462                 if (retval != ERROR_OK)
 463                         return retval;
 464
 465                 bank->sectors[i].is_erased = 1;
 466         }
 467
 468         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 469         if (retval != ERROR_OK)
 470                 return retval;
 471
 472         return ERROR_OK;
 473 }
 474
 475 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 476 {
 477         struct stm32x_flash_bank *stm32x_info = NULL;
 478         struct target *target = bank->target;
 479         uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 480         int i, reg, bit;
 481         int status;
 482         uint32_t protection;
 483
 484         stm32x_info = bank->driver_priv;
 485
 486         if (target->state != TARGET_HALTED) {
 487                 LOG_ERROR("Target not halted");
 488                 return ERROR_TARGET_NOT_HALTED;
 489         }
 490
 491         int retval = stm32x_check_operation_supported(bank);
 492         if (ERROR_OK != retval)
 493                 return retval;
 494
 495         if ((first % stm32x_info->ppage_size) != 0) {
 496                 LOG_WARNING("aligned start protect sector to a %d sector boundary",
 497                                 stm32x_info->ppage_size);
 498                 first = first - (first % stm32x_info->ppage_size);
 499         }
 500         if (((last + 1) % stm32x_info->ppage_size) != 0) {
 501                 LOG_WARNING("aligned end protect sector to a %d sector boundary",
 502                                 stm32x_info->ppage_size);
 503                 last++;
 504                 last = last - (last % stm32x_info->ppage_size);
 505                 last--;
 506         }
 507
 508         /* medium density - each bit refers to a 4bank protection
 509          * high density - each bit refers to a 2bank protection */
 510         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 511         if (retval != ERROR_OK)
 512                 return retval;
 513
 514         prot_reg[0] = (uint16_t)protection;
 515         prot_reg[1] = (uint16_t)(protection >> 8);
 516         prot_reg[2] = (uint16_t)(protection >> 16);
 517         prot_reg[3] = (uint16_t)(protection >> 24);
 518
 519         if (stm32x_info->ppage_size == 2) {
 520                 /* high density flash */
 521
 522                 /* bit 7 controls sector 62 - 255 protection */
 523                 if (last > 61) {
 524                         if (set)
 525                                 prot_reg[3] &= ~(1 << 7);
 526                         else
 527                                 prot_reg[3] |= (1 << 7);
 528                 }
 529
 530                 if (first > 61)
 531                         first = 62;
 532                 if (last > 61)
 533                         last = 61;
 534
 535                 for (i = first; i <= last; i++) {
 536                         reg = (i / stm32x_info->ppage_size) / 8;
 537                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 538
 539                         if (set)
 540                                 prot_reg[reg] &= ~(1 << bit);
 541                         else
 542                                 prot_reg[reg] |= (1 << bit);
 543                 }
 544         } else {
 545                 /* medium density flash */
 546                 for (i = first; i <= last; i++) {
 547                         reg = (i / stm32x_info->ppage_size) / 8;
 548                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 549
 550                         if (set)
 551                                 prot_reg[reg] &= ~(1 << bit);
 552                         else
 553                                 prot_reg[reg] |= (1 << bit);
 554                 }
 555         }
 556
 557         status = stm32x_erase_options(bank);
 558         if (status != ERROR_OK)
 559                 return status;
 560
 561         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 562         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 563         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 564         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 565
 566         return stm32x_write_options(bank);
 567 }
 568
 569 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 570                 uint32_t offset, uint32_t count)
 571 {
 572         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 573         struct target *target = bank->target;
 574         uint32_t buffer_size = 16384;
 575         struct working_area *write_algorithm;
 576         struct working_area *source;
 577         uint32_t address = bank->base + offset;
 578         struct reg_param reg_params[5];
 579         struct armv7m_algorithm armv7m_info;
 580         int retval = ERROR_OK;
 581
 582         /* see contrib/loaders/flash/stm32f1x.S for src */
 583
 584         static const uint8_t stm32x_flash_write_code[] = {
 585                 /* #define STM32_FLASH_SR_OFFSET 0x0C */
 586                 /* wait_fifo: */
 587                         0x16, 0x68,   /* ldr   r6, [r2, #0] */
 588                         0x00, 0x2e,   /* cmp   r6, #0 */
 589                         0x18, 0xd0,   /* beq   exit */
 590                         0x55, 0x68,   /* ldr   r5, [r2, #4] */
 591                         0xb5, 0x42,   /* cmp   r5, r6 */
 592                         0xf9, 0xd0,   /* beq   wait_fifo */
 593                         0x2e, 0x88,   /* ldrh  r6, [r5, #0] */
 594                         0x26, 0x80,   /* strh  r6, [r4, #0] */
 595                         0x02, 0x35,   /* adds  r5, #2 */
 596                         0x02, 0x34,   /* adds  r4, #2 */
 597                 /* busy: */
 598                         0xc6, 0x68,   /* ldr   r6, [r0, #STM32_FLASH_SR_OFFSET] */
 599                         0x01, 0x27,   /* movs  r7, #1 */
 600                         0x3e, 0x42,   /* tst   r6, r7 */
 601                         0xfb, 0xd1,   /* bne   busy */
 602                         0x14, 0x27,   /* movs  r7, #0x14 */
 603                         0x3e, 0x42,   /* tst   r6, r7 */
 604                         0x08, 0xd1,   /* bne   error */
 605                         0x9d, 0x42,   /* cmp   r5, r3 */
 606                         0x01, 0xd3,   /* bcc   no_wrap */
 607                         0x15, 0x46,   /* mov   r5, r2 */
 608                         0x08, 0x35,   /* adds  r5, #8 */
 609                 /* no_wrap: */
 610                         0x55, 0x60,   /* str   r5, [r2, #4] */
 611                         0x01, 0x39,   /* subs  r1, r1, #1 */
 612                         0x00, 0x29,   /* cmp   r1, #0 */
 613                         0x02, 0xd0,   /* beq   exit */
 614                         0xe5, 0xe7,   /* b     wait_fifo */
 615                 /* error: */
 616                         0x00, 0x20,   /* movs  r0, #0 */
 617                         0x50, 0x60,   /* str   r0, [r2, #4] */
 618                 /* exit: */
 619                         0x30, 0x46,   /* mov   r0, r6 */
 620                         0x00, 0xbe,   /* bkpt  #0 */
 621         };
 622
 623         /* flash write code */
 624         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 625                         &write_algorithm) != ERROR_OK) {
 626                 LOG_WARNING("no working area available, can't do block memory writes");
 627                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 628         };
 629
 630         retval = target_write_buffer(target, write_algorithm->address,
 631                         sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
 632         if (retval != ERROR_OK)
 633                 return retval;
 634
 635         /* memory buffer */
 636         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 637                 buffer_size /= 2;
 638                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 639                 if (buffer_size <= 256) {
 640                         /* we already allocated the writing code, but failed to get a
 641                          * buffer, free the algorithm */
 642                         target_free_working_area(target, write_algorithm);
 643
 644                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 645                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 646                 }
 647         };
 648
 649         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 650         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 651         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 652         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 653         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 654
 655         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 656         buf_set_u32(reg_params[1].value, 0, 32, count);
 657         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 658         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 659         buf_set_u32(reg_params[4].value, 0, 32, address);
 660
 661         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 662         armv7m_info.core_mode = ARM_MODE_THREAD;
 663
 664         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 665                         0, NULL,
 666                         5, reg_params,
 667                         source->address, source->size,
 668                         write_algorithm->address, 0,
 669                         &armv7m_info);
 670
 671         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 672                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 673                                 buf_get_u32(reg_params[4].value, 0, 32));
 674
 675                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
 676                         LOG_ERROR("flash memory not erased before writing");
 677                         /* Clear but report errors */
 678                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
 679                 }
 680
 681                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
 682                         LOG_ERROR("flash memory write protected");
 683                         /* Clear but report errors */
 684                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
 685                 }
 686         }
 687
 688         target_free_working_area(target, source);
 689         target_free_working_area(target, write_algorithm);
 690
 691         destroy_reg_param(&reg_params[0]);
 692         destroy_reg_param(&reg_params[1]);
 693         destroy_reg_param(&reg_params[2]);
 694         destroy_reg_param(&reg_params[3]);
 695         destroy_reg_param(&reg_params[4]);
 696
 697         return retval;
 698 }
 699
 700 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
 701                 uint32_t offset, uint32_t count)
 702 {
 703         struct target *target = bank->target;
 704         uint8_t *new_buffer = NULL;
 705
 706         if (bank->target->state != TARGET_HALTED) {
 707                 LOG_ERROR("Target not halted");
 708                 return ERROR_TARGET_NOT_HALTED;
 709         }
 710
 711         if (offset & 0x1) {
 712                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 713                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 714         }
 715
 716         /* If there's an odd number of bytes, the data has to be padded. Duplicate
 717          * the buffer and use the normal code path with a single block write since
 718          * it's probably cheaper than to special case the last odd write using
 719          * discrete accesses. */
 720         if (count & 1) {
 721                 new_buffer = malloc(count + 1);
 722                 if (new_buffer == NULL) {
 723                         LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
 724                         return ERROR_FAIL;
 725                 }
 726                 LOG_INFO("odd number of bytes to write, padding with 0xff");
 727                 buffer = memcpy(new_buffer, buffer, count);
 728                 buffer[count++] = 0xff;
 729         }
 730
 731         uint32_t words_remaining = count / 2;
 732         int retval, retval2;
 733
 734         /* unlock flash registers */
 735         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 736         if (retval != ERROR_OK)
 737                 goto cleanup;
 738         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 739         if (retval != ERROR_OK)
 740                 goto cleanup;
 741
 742         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 743         if (retval != ERROR_OK)
 744                 goto cleanup;
 745
 746         /* try using a block write */
 747         retval = stm32x_write_block(bank, buffer, offset, words_remaining);
 748
 749         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 750                 /* if block write failed (no sufficient working area),
 751                  * we use normal (slow) single halfword accesses */
 752                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 753
 754                 while (words_remaining > 0) {
 755                         uint16_t value;
 756                         memcpy(&value, buffer, sizeof(uint16_t));
 757
 758                         retval = target_write_u16(target, bank->base + offset, value);
 759                         if (retval != ERROR_OK)
 760                                 goto reset_pg_and_lock;
 761
 762                         retval = stm32x_wait_status_busy(bank, 5);
 763                         if (retval != ERROR_OK)
 764                                 goto reset_pg_and_lock;
 765
 766                         words_remaining--;
 767                         buffer += 2;
 768                         offset += 2;
 769                 }
 770         }
 771
 772 reset_pg_and_lock:
 773         retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 774         if (retval == ERROR_OK)
 775                 retval = retval2;
 776
 777 cleanup:
 778         if (new_buffer)
 779                 free(new_buffer);
 780
 781         return retval;
 782 }
 783
 784 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 785 {
 786         /* This check the device CPUID core register to detect
 787          * the M0 from the M3 devices. */
 788
 789         struct target *target = bank->target;
 790         uint32_t cpuid, device_id_register = 0;
 791
 792         /* Get the CPUID from the ARM Core
 793          * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
 794         int retval = target_read_u32(target, 0xE000ED00, &cpuid);
 795         if (retval != ERROR_OK)
 796                 return retval;
 797
 798         if (((cpuid >> 4) & 0xFFF) == 0xC20) {
 799                 /* 0xC20 is M0 devices */
 800                 device_id_register = 0x40015800;
 801         } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
 802                 /* 0xC23 is M3 devices */
 803                 device_id_register = 0xE0042000;
 804         } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 805                 /* 0xC24 is M4 devices */
 806                 device_id_register = 0xE0042000;
 807         } else {
 808                 LOG_ERROR("Cannot identify target as a stm32x");
 809                 return ERROR_FAIL;
 810         }
 811
 812         /* read stm32 device id register */
 813         retval = target_read_u32(target, device_id_register, device_id);
 814         if (retval != ERROR_OK)
 815                 return retval;
 816
 817         return retval;
 818 }
 819
 820 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 821 {
 822         struct target *target = bank->target;
 823         uint32_t cpuid, flash_size_reg;
 824
 825         int retval = target_read_u32(target, 0xE000ED00, &cpuid);
 826         if (retval != ERROR_OK)
 827                 return retval;
 828
 829         if (((cpuid >> 4) & 0xFFF) == 0xC20) {
 830                 /* 0xC20 is M0 devices */
 831                 flash_size_reg = 0x1FFFF7CC;
 832         } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
 833                 /* 0xC23 is M3 devices */
 834                 flash_size_reg = 0x1FFFF7E0;
 835         } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 836                 /* 0xC24 is M4 devices */
 837                 flash_size_reg = 0x1FFFF7CC;
 838         } else {
 839                 LOG_ERROR("Cannot identify target as a stm32x");
 840                 return ERROR_FAIL;
 841         }
 842
 843         retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
 844         if (retval != ERROR_OK)
 845                 return retval;
 846
 847         return retval;
 848 }
 849
 850 static int stm32x_probe(struct flash_bank *bank)
 851 {
 852         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 853         int i;
 854         uint16_t flash_size_in_kb;
 855         uint16_t max_flash_size_in_kb;
 856         uint32_t device_id;
 857         int page_size;
 858         uint32_t base_address = 0x08000000;
 859
 860         stm32x_info->probed = 0;
 861         stm32x_info->register_base = FLASH_REG_BASE_B0;
 862         stm32x_info->user_data_offset = 10;
 863         stm32x_info->option_offset = 0;
 864
 865         /* default factory protection level */
 866         stm32x_info->default_rdp = 0x5AA5;
 867
 868         /* read stm32 device id register */
 869         int retval = stm32x_get_device_id(bank, &device_id);
 870         if (retval != ERROR_OK)
 871                 return retval;
 872
 873         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 874
 875         /* set page size, protection granularity and max flash size depending on family */
 876         switch (device_id & 0xfff) {
 877         case 0x410: /* medium density */
 878                 page_size = 1024;
 879                 stm32x_info->ppage_size = 4;
 880                 max_flash_size_in_kb = 128;
 881                 break;
 882         case 0x412: /* low density */
 883                 page_size = 1024;
 884                 stm32x_info->ppage_size = 4;
 885                 max_flash_size_in_kb = 32;
 886                 break;
 887         case 0x414: /* high density */
 888                 page_size = 2048;
 889                 stm32x_info->ppage_size = 2;
 890                 max_flash_size_in_kb = 512;
 891                 break;
 892         case 0x418: /* connectivity line density */
 893                 page_size = 2048;
 894                 stm32x_info->ppage_size = 2;
 895                 max_flash_size_in_kb = 256;
 896                 break;
 897         case 0x420: /* value line density */
 898                 page_size = 1024;
 899                 stm32x_info->ppage_size = 4;
 900                 max_flash_size_in_kb = 128;
 901                 break;
 902         case 0x422: /* stm32f30x */
 903                 page_size = 2048;
 904                 stm32x_info->ppage_size = 2;
 905                 max_flash_size_in_kb = 256;
 906                 stm32x_info->user_data_offset = 16;
 907                 stm32x_info->option_offset = 6;
 908                 stm32x_info->default_rdp = 0x55AA;
 909                 break;
 910         case 0x428: /* value line High density */
 911                 page_size = 2048;
 912                 stm32x_info->ppage_size = 4;
 913                 max_flash_size_in_kb = 128;
 914                 break;
 915         case 0x430: /* xl line density (dual flash banks) */
 916                 page_size = 2048;
 917                 stm32x_info->ppage_size = 2;
 918                 max_flash_size_in_kb = 1024;
 919                 stm32x_info->has_dual_banks = true;
 920                 break;
 921         case 0x432: /* stm32f37x */
 922                 page_size = 2048;
 923                 stm32x_info->ppage_size = 2;
 924                 max_flash_size_in_kb = 256;
 925                 stm32x_info->user_data_offset = 16;
 926                 stm32x_info->option_offset = 6;
 927                 stm32x_info->default_rdp = 0x55AA;
 928                 break;
 929         case 0x440: /* stm32f0x */
 930                 page_size = 1024;
 931                 stm32x_info->ppage_size = 4;
 932                 max_flash_size_in_kb = 64;
 933                 stm32x_info->user_data_offset = 16;
 934                 stm32x_info->option_offset = 6;
 935                 stm32x_info->default_rdp = 0x55AA;
 936                 break;
 937         default:
 938                 LOG_WARNING("Cannot identify target as a STM32 family.");
 939                 return ERROR_FAIL;
 940         }
 941
 942         /* get flash size from target. */
 943         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 944
 945         /* failed reading flash size or flash size invalid (early silicon),
 946          * default to max target family */
 947         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 948                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 949                         max_flash_size_in_kb);
 950                 flash_size_in_kb = max_flash_size_in_kb;
 951         }
 952
 953         if (stm32x_info->has_dual_banks) {
 954                 /* split reported size into matching bank */
 955                 if (bank->base != 0x08080000) {
 956                         /* bank 0 will be fixed 512k */
 957                         flash_size_in_kb = 512;
 958                 } else {
 959                         flash_size_in_kb -= 512;
 960                         /* bank1 also uses a register offset */
 961                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 962                         base_address = 0x08080000;
 963                 }
 964         }
 965
 966         /* if the user sets the size manually then ignore the probed value
 967          * this allows us to work around devices that have a invalid flash size register value */
 968         if (stm32x_info->user_bank_size) {
 969                 LOG_INFO("ignoring flash probed value, using configured bank size");
 970                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
 971         }
 972
 973         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 974
 975         /* did we assign flash size? */
 976         assert(flash_size_in_kb != 0xffff);
 977
 978         /* calculate numbers of pages */
 979         int num_pages = flash_size_in_kb * 1024 / page_size;
 980
 981         /* check that calculation result makes sense */
 982         assert(num_pages > 0);
 983
 984         if (bank->sectors) {
 985                 free(bank->sectors);
 986                 bank->sectors = NULL;
 987         }
 988
 989         bank->base = base_address;
 990         bank->size = (num_pages * page_size);
 991         bank->num_sectors = num_pages;
 992         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 993
 994         for (i = 0; i < num_pages; i++) {
 995                 bank->sectors[i].offset = i * page_size;
 996                 bank->sectors[i].size = page_size;
 997                 bank->sectors[i].is_erased = -1;
 998                 bank->sectors[i].is_protected = 1;
 999         }
1000
1001         stm32x_info->probed = 1;
1002
1003         return ERROR_OK;
1004 }
1005
1006 static int stm32x_auto_probe(struct flash_bank *bank)
1007 {
1008         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1009         if (stm32x_info->probed)
1010                 return ERROR_OK;
1011         return stm32x_probe(bank);
1012 }
1013
1014 #if 0
1015 COMMAND_HANDLER(stm32x_handle_part_id_command)
1016 {
1017         return ERROR_OK;
1018 }
1019 #endif
1020
1021 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1022 {
1023         uint32_t device_id;
1024         int printed;
1025
1026                 /* read stm32 device id register */
1027         int retval = stm32x_get_device_id(bank, &device_id);
1028         if (retval != ERROR_OK)
1029                 return retval;
1030
1031         if ((device_id & 0xfff) == 0x410) {
1032                 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1033                 buf += printed;
1034                 buf_size -= printed;
1035
1036                 switch (device_id >> 16) {
1037                         case 0x0000:
1038                                 snprintf(buf, buf_size, "A");
1039                                 break;
1040
1041                         case 0x2000:
1042                                 snprintf(buf, buf_size, "B");
1043                                 break;
1044
1045                         case 0x2001:
1046                                 snprintf(buf, buf_size, "Z");
1047                                 break;
1048
1049                         case 0x2003:
1050                                 snprintf(buf, buf_size, "Y");
1051                                 break;
1052
1053                         default:
1054                                 snprintf(buf, buf_size, "unknown");
1055                                 break;
1056                 }
1057         } else if ((device_id & 0xfff) == 0x412) {
1058                 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1059                 buf += printed;
1060                 buf_size -= printed;
1061
1062                 switch (device_id >> 16) {
1063                         case 0x1000:
1064                                 snprintf(buf, buf_size, "A");
1065                                 break;
1066
1067                         default:
1068                                 snprintf(buf, buf_size, "unknown");
1069                                 break;
1070                 }
1071         } else if ((device_id & 0xfff) == 0x414) {
1072                 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1073                 buf += printed;
1074                 buf_size -= printed;
1075
1076                 switch (device_id >> 16) {
1077                         case 0x1000:
1078                                 snprintf(buf, buf_size, "A");
1079                                 break;
1080
1081                         case 0x1001:
1082                                 snprintf(buf, buf_size, "Z");
1083                                 break;
1084
1085                         default:
1086                                 snprintf(buf, buf_size, "unknown");
1087                                 break;
1088                 }
1089         } else if ((device_id & 0xfff) == 0x418) {
1090                 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1091                 buf += printed;
1092                 buf_size -= printed;
1093
1094                 switch (device_id >> 16) {
1095                         case 0x1000:
1096                                 snprintf(buf, buf_size, "A");
1097                                 break;
1098
1099                         case 0x1001:
1100                                 snprintf(buf, buf_size, "Z");
1101                                 break;
1102
1103                         default:
1104                                 snprintf(buf, buf_size, "unknown");
1105                                 break;
1106                 }
1107         } else if ((device_id & 0xfff) == 0x420) {
1108                 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1109                 buf += printed;
1110                 buf_size -= printed;
1111
1112                 switch (device_id >> 16) {
1113                         case 0x1000:
1114                                 snprintf(buf, buf_size, "A");
1115                                 break;
1116
1117                         case 0x1001:
1118                                 snprintf(buf, buf_size, "Z");
1119                                 break;
1120
1121                         default:
1122                                 snprintf(buf, buf_size, "unknown");
1123                                 break;
1124                 }
1125         } else if ((device_id & 0xfff) == 0x422) {
1126                 printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
1127                 buf += printed;
1128                 buf_size -= printed;
1129
1130                 switch (device_id >> 16) {
1131                         case 0x1000:
1132                                 snprintf(buf, buf_size, "A");
1133                                 break;
1134
1135                         case 0x1001:
1136                                 snprintf(buf, buf_size, "Z");
1137                                 break;
1138
1139                         case 0x2000:
1140                                 snprintf(buf, buf_size, "B");
1141                                 break;
1142
1143                         default:
1144                                 snprintf(buf, buf_size, "unknown");
1145                                 break;
1146                 }
1147         } else if ((device_id & 0xfff) == 0x428) {
1148                 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1149                 buf += printed;
1150                 buf_size -= printed;
1151
1152                 switch (device_id >> 16) {
1153                         case 0x1000:
1154                                 snprintf(buf, buf_size, "A");
1155                                 break;
1156
1157                         case 0x1001:
1158                                 snprintf(buf, buf_size, "Z");
1159                                 break;
1160
1161                         default:
1162                                 snprintf(buf, buf_size, "unknown");
1163                                 break;
1164                 }
1165         } else if ((device_id & 0xfff) == 0x430) {
1166                 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1167                 buf += printed;
1168                 buf_size -= printed;
1169
1170                 switch (device_id >> 16) {
1171                         case 0x1000:
1172                                 snprintf(buf, buf_size, "A");
1173                                 break;
1174
1175                         default:
1176                                 snprintf(buf, buf_size, "unknown");
1177                                 break;
1178                 }
1179         } else if ((device_id & 0xfff) == 0x432) {
1180                 printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
1181                 buf += printed;
1182                 buf_size -= printed;
1183
1184                 switch (device_id >> 16) {
1185                         case 0x1000:
1186                                 snprintf(buf, buf_size, "A");
1187                                 break;
1188
1189                         case 0x2000:
1190                                 snprintf(buf, buf_size, "B");
1191                                 break;
1192
1193                         default:
1194                                 snprintf(buf, buf_size, "unknown");
1195                                 break;
1196                 }
1197         } else if ((device_id & 0xfff) == 0x440) {
1198                 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1199                 buf += printed;
1200                 buf_size -= printed;
1201
1202                 switch (device_id >> 16) {
1203                         case 0x1000:
1204                                 snprintf(buf, buf_size, "1.0");
1205                                 break;
1206
1207                         case 0x2000:
1208                                 snprintf(buf, buf_size, "2.0");
1209                                 break;
1210
1211                         default:
1212                                 snprintf(buf, buf_size, "unknown");
1213                                 break;
1214                 }
1215         } else {
1216                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1217                 return ERROR_FAIL;
1218         }
1219
1220         return ERROR_OK;
1221 }
1222
1223 COMMAND_HANDLER(stm32x_handle_lock_command)
1224 {
1225         struct target *target = NULL;
1226         struct stm32x_flash_bank *stm32x_info = NULL;
1227
1228         if (CMD_ARGC < 1)
1229                 return ERROR_COMMAND_SYNTAX_ERROR;
1230
1231         struct flash_bank *bank;
1232         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1233         if (ERROR_OK != retval)
1234                 return retval;
1235
1236         stm32x_info = bank->driver_priv;
1237
1238         target = bank->target;
1239
1240         if (target->state != TARGET_HALTED) {
1241                 LOG_ERROR("Target not halted");
1242                 return ERROR_TARGET_NOT_HALTED;
1243         }
1244
1245         retval = stm32x_check_operation_supported(bank);
1246         if (ERROR_OK != retval)
1247                 return retval;
1248
1249         if (stm32x_erase_options(bank) != ERROR_OK) {
1250                 command_print(CMD_CTX, "stm32x failed to erase options");
1251                 return ERROR_OK;
1252         }
1253
1254         /* set readout protection */
1255         stm32x_info->option_bytes.RDP = 0;
1256
1257         if (stm32x_write_options(bank) != ERROR_OK) {
1258                 command_print(CMD_CTX, "stm32x failed to lock device");
1259                 return ERROR_OK;
1260         }
1261
1262         command_print(CMD_CTX, "stm32x locked");
1263
1264         return ERROR_OK;
1265 }
1266
1267 COMMAND_HANDLER(stm32x_handle_unlock_command)
1268 {
1269         struct target *target = NULL;
1270
1271         if (CMD_ARGC < 1)
1272                 return ERROR_COMMAND_SYNTAX_ERROR;
1273
1274         struct flash_bank *bank;
1275         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1276         if (ERROR_OK != retval)
1277                 return retval;
1278
1279         target = bank->target;
1280
1281         if (target->state != TARGET_HALTED) {
1282                 LOG_ERROR("Target not halted");
1283                 return ERROR_TARGET_NOT_HALTED;
1284         }
1285
1286         retval = stm32x_check_operation_supported(bank);
1287         if (ERROR_OK != retval)
1288                 return retval;
1289
1290         if (stm32x_erase_options(bank) != ERROR_OK) {
1291                 command_print(CMD_CTX, "stm32x failed to unlock device");
1292                 return ERROR_OK;
1293         }
1294
1295         if (stm32x_write_options(bank) != ERROR_OK) {
1296                 command_print(CMD_CTX, "stm32x failed to lock device");
1297                 return ERROR_OK;
1298         }
1299
1300         command_print(CMD_CTX, "stm32x unlocked.\n"
1301                         "INFO: a reset or power cycle is required "
1302                         "for the new settings to take effect.");
1303
1304         return ERROR_OK;
1305 }
1306
1307 COMMAND_HANDLER(stm32x_handle_options_read_command)
1308 {
1309         uint32_t optionbyte;
1310         struct target *target = NULL;
1311         struct stm32x_flash_bank *stm32x_info = NULL;
1312
1313         if (CMD_ARGC < 1)
1314                 return ERROR_COMMAND_SYNTAX_ERROR;
1315
1316         struct flash_bank *bank;
1317         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1318         if (ERROR_OK != retval)
1319                 return retval;
1320
1321         stm32x_info = bank->driver_priv;
1322
1323         target = bank->target;
1324
1325         if (target->state != TARGET_HALTED) {
1326                 LOG_ERROR("Target not halted");
1327                 return ERROR_TARGET_NOT_HALTED;
1328         }
1329
1330         retval = stm32x_check_operation_supported(bank);
1331         if (ERROR_OK != retval)
1332                 return retval;
1333
1334         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1335         if (retval != ERROR_OK)
1336                 return retval;
1337         command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1338
1339         int user_data = optionbyte;
1340
1341         if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1342                 command_print(CMD_CTX, "Option Byte Complement Error");
1343
1344         if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1345                 command_print(CMD_CTX, "Readout Protection On");
1346         else
1347                 command_print(CMD_CTX, "Readout Protection Off");
1348
1349         /* user option bytes are offset depending on variant */
1350         optionbyte >>= stm32x_info->option_offset;
1351
1352         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1353                 command_print(CMD_CTX, "Software Watchdog");
1354         else
1355                 command_print(CMD_CTX, "Hardware Watchdog");
1356
1357         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1358                 command_print(CMD_CTX, "Stop: No reset generated");
1359         else
1360                 command_print(CMD_CTX, "Stop: Reset generated");
1361
1362         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1363                 command_print(CMD_CTX, "Standby: No reset generated");
1364         else
1365                 command_print(CMD_CTX, "Standby: Reset generated");
1366
1367         if (stm32x_info->has_dual_banks) {
1368                 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1369                         command_print(CMD_CTX, "Boot: Bank 0");
1370                 else
1371                         command_print(CMD_CTX, "Boot: Bank 1");
1372         }
1373
1374         command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
1375                         (user_data >> stm32x_info->user_data_offset) & 0xff);
1376         command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
1377                         (user_data >> (stm32x_info->user_data_offset + 8)) & 0xff);
1378
1379         return ERROR_OK;
1380 }
1381
1382 COMMAND_HANDLER(stm32x_handle_options_write_command)
1383 {
1384         struct target *target = NULL;
1385         struct stm32x_flash_bank *stm32x_info = NULL;
1386         uint16_t optionbyte;
1387
1388         if (CMD_ARGC < 2)
1389                 return ERROR_COMMAND_SYNTAX_ERROR;
1390
1391         struct flash_bank *bank;
1392         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1393         if (ERROR_OK != retval)
1394                 return retval;
1395
1396         stm32x_info = bank->driver_priv;
1397
1398         target = bank->target;
1399
1400         if (target->state != TARGET_HALTED) {
1401                 LOG_ERROR("Target not halted");
1402                 return ERROR_TARGET_NOT_HALTED;
1403         }
1404
1405         retval = stm32x_check_operation_supported(bank);
1406         if (ERROR_OK != retval)
1407                 return retval;
1408
1409         retval = stm32x_read_options(bank);
1410         if (ERROR_OK != retval)
1411                 return retval;
1412
1413         /* start with current options */
1414         optionbyte = stm32x_info->option_bytes.user_options;
1415
1416         /* skip over flash bank */
1417         CMD_ARGC--;
1418         CMD_ARGV++;
1419
1420         while (CMD_ARGC) {
1421                 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1422                         optionbyte |= (1 << 0);
1423                 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1424                         optionbyte &= ~(1 << 0);
1425                 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1426                         optionbyte &= ~(1 << 1);
1427                 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1428                         optionbyte &= ~(1 << 1);
1429                 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1430                         optionbyte &= ~(1 << 2);
1431                 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1432                         optionbyte &= ~(1 << 2);
1433                 else if (stm32x_info->has_dual_banks) {
1434                         if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1435                                 optionbyte |= (1 << 3);
1436                         else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1437                                 optionbyte &= ~(1 << 3);
1438                         else
1439                                 return ERROR_COMMAND_SYNTAX_ERROR;
1440                 } else
1441                         return ERROR_COMMAND_SYNTAX_ERROR;
1442                 CMD_ARGC--;
1443                 CMD_ARGV++;
1444         }
1445
1446         if (stm32x_erase_options(bank) != ERROR_OK) {
1447                 command_print(CMD_CTX, "stm32x failed to erase options");
1448                 return ERROR_OK;
1449         }
1450
1451         stm32x_info->option_bytes.user_options = optionbyte;
1452
1453         if (stm32x_write_options(bank) != ERROR_OK) {
1454                 command_print(CMD_CTX, "stm32x failed to write options");
1455                 return ERROR_OK;
1456         }
1457
1458         command_print(CMD_CTX, "stm32x write options complete.\n"
1459                                 "INFO: a reset or power cycle is required "
1460                                 "for the new settings to take effect.");
1461
1462         return ERROR_OK;
1463 }
1464
1465 static int stm32x_mass_erase(struct flash_bank *bank)
1466 {
1467         struct target *target = bank->target;
1468
1469         if (target->state != TARGET_HALTED) {
1470                 LOG_ERROR("Target not halted");
1471                 return ERROR_TARGET_NOT_HALTED;
1472         }
1473
1474         /* unlock option flash registers */
1475         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1476         if (retval != ERROR_OK)
1477                 return retval;
1478         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1479         if (retval != ERROR_OK)
1480                 return retval;
1481
1482         /* mass erase flash memory */
1483         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1484         if (retval != ERROR_OK)
1485                 return retval;
1486         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1487                         FLASH_MER | FLASH_STRT);
1488         if (retval != ERROR_OK)
1489                 return retval;
1490
1491         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1492         if (retval != ERROR_OK)
1493                 return retval;
1494
1495         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1496         if (retval != ERROR_OK)
1497                 return retval;
1498
1499         return ERROR_OK;
1500 }
1501
1502 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1503 {
1504         int i;
1505
1506         if (CMD_ARGC < 1)
1507                 return ERROR_COMMAND_SYNTAX_ERROR;
1508
1509         struct flash_bank *bank;
1510         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1511         if (ERROR_OK != retval)
1512                 return retval;
1513
1514         retval = stm32x_mass_erase(bank);
1515         if (retval == ERROR_OK) {
1516                 /* set all sectors as erased */
1517                 for (i = 0; i < bank->num_sectors; i++)
1518                         bank->sectors[i].is_erased = 1;
1519
1520                 command_print(CMD_CTX, "stm32x mass erase complete");
1521         } else
1522                 command_print(CMD_CTX, "stm32x mass erase failed");
1523
1524         return retval;
1525 }
1526
1527 static const struct command_registration stm32x_exec_command_handlers[] = {
1528         {
1529                 .name = "lock",
1530                 .handler = stm32x_handle_lock_command,
1531                 .mode = COMMAND_EXEC,
1532                 .usage = "bank_id",
1533                 .help = "Lock entire flash device.",
1534         },
1535         {
1536                 .name = "unlock",
1537                 .handler = stm32x_handle_unlock_command,
1538                 .mode = COMMAND_EXEC,
1539                 .usage = "bank_id",
1540                 .help = "Unlock entire protected flash device.",
1541         },
1542         {
1543                 .name = "mass_erase",
1544                 .handler = stm32x_handle_mass_erase_command,
1545                 .mode = COMMAND_EXEC,
1546                 .usage = "bank_id",
1547                 .help = "Erase entire flash device.",
1548         },
1549         {
1550                 .name = "options_read",
1551                 .handler = stm32x_handle_options_read_command,
1552                 .mode = COMMAND_EXEC,
1553                 .usage = "bank_id",
1554                 .help = "Read and display device option byte.",
1555         },
1556         {
1557                 .name = "options_write",
1558                 .handler = stm32x_handle_options_write_command,
1559                 .mode = COMMAND_EXEC,
1560                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1561                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1562                         "('RSTSTOP'|'NORSTSTOP')",
1563                 .help = "Replace bits in device option byte.",
1564         },
1565         COMMAND_REGISTRATION_DONE
1566 };
1567
1568 static const struct command_registration stm32x_command_handlers[] = {
1569         {
1570                 .name = "stm32f1x",
1571                 .mode = COMMAND_ANY,
1572                 .help = "stm32f1x flash command group",
1573                 .usage = "",
1574                 .chain = stm32x_exec_command_handlers,
1575         },
1576         COMMAND_REGISTRATION_DONE
1577 };
1578
1579 struct flash_driver stm32f1x_flash = {
1580         .name = "stm32f1x",
1581         .commands = stm32x_command_handlers,
1582         .flash_bank_command = stm32x_flash_bank_command,
1583         .erase = stm32x_erase,
1584         .protect = stm32x_protect,
1585         .write = stm32x_write,
1586         .read = default_flash_read,
1587         .probe = stm32x_probe,
1588         .auto_probe = stm32x_auto_probe,
1589         .erase_check = default_flash_blank_check,
1590         .protect_check = stm32x_protect_check,
1591         .info = get_stm32x_info,
1592 };