git.sur5r.net Git - openocd/blob - src/rtos/rtos_ucos_iii_stackings.c

   1 /***************************************************************************
   2  *   Copyright (C) 2017 by Square, Inc.                                    *
   3  *   Steven Stallion <stallion@squareup.com>                               *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifdef HAVE_CONFIG_H
  20 #include "config.h"
  21 #endif
  22
  23 #include <helper/types.h>
  24 #include <rtos/rtos.h>
  25 #include <rtos/rtos_standard_stackings.h>
  26 #include <target/armv7m.h>
  27
  28 static const struct stack_register_offset rtos_uCOS_III_Cortex_M_stack_offsets[] = {
  29         { 0x20, 32 },   /* r0   */
  30         { 0x24, 32 },   /* r1   */
  31         { 0x28, 32 },   /* r2   */
  32         { 0x2c, 32 },   /* r3   */
  33         { 0x00, 32 },   /* r4   */
  34         { 0x04, 32 },   /* r5   */
  35         { 0x08, 32 },   /* r6   */
  36         { 0x0c, 32 },   /* r7   */
  37         { 0x10, 32 },   /* r8   */
  38         { 0x14, 32 },   /* r9   */
  39         { 0x18, 32 },   /* r10  */
  40         { 0x1c, 32 },   /* r11  */
  41         { 0x30, 32 },   /* r12  */
  42         { -2,   32 },   /* sp   */
  43         { 0x34, 32 },   /* lr   */
  44         { 0x38, 32 },   /* pc   */
  45         { 0x3c, 32 },   /* xPSR */
  46 };
  47
  48 const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking = {
  49         0x40,                                                                                           /* stack_registers_size */
  50         -1,                                                                                                     /* stack_growth_direction */
  51         ARRAY_SIZE(rtos_uCOS_III_Cortex_M_stack_offsets),       /* num_output_registers */
  52         rtos_generic_stack_align8,                                                      /* stack_alignment */
  53         rtos_uCOS_III_Cortex_M_stack_offsets                            /* register_offsets */
  54 };