git.sur5r.net Git - openocd/blob - src/target/mips_m4k.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
  10  *   drasko.draskovic@gmail.com                                            *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program; if not, write to the                         *
  24  *   Free Software Foundation, Inc.,                                       *
  25  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  26  ***************************************************************************/
  27
  28 #ifdef HAVE_CONFIG_H
  29 #include "config.h"
  30 #endif
  31
  32 #include "breakpoints.h"
  33 #include "mips32.h"
  34 #include "mips_m4k.h"
  35 #include "mips32_dmaacc.h"
  36 #include "target_type.h"
  37 #include "register.h"
  38
  39 static void mips_m4k_enable_breakpoints(struct target *target);
  40 static void mips_m4k_enable_watchpoints(struct target *target);
  41 static int mips_m4k_set_breakpoint(struct target *target,
  42                 struct breakpoint *breakpoint);
  43 static int mips_m4k_unset_breakpoint(struct target *target,
  44                 struct breakpoint *breakpoint);
  45 static int mips_m4k_internal_restore(struct target *target, int current,
  46                 uint32_t address, int handle_breakpoints,
  47                 int debug_execution);
  48 static int mips_m4k_halt(struct target *target);
  49 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
  50                 uint32_t count, const uint8_t *buffer);
  51
  52 static int mips_m4k_examine_debug_reason(struct target *target)
  53 {
  54         struct mips32_common *mips32 = target_to_mips32(target);
  55         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  56         uint32_t break_status;
  57         int retval;
  58
  59         if ((target->debug_reason != DBG_REASON_DBGRQ)
  60                         && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
  61                 if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
  62                         /* get info about inst breakpoint support */
  63                         retval = target_read_u32(target,
  64                                 ejtag_info->ejtag_ibs_addr, &break_status);
  65                         if (retval != ERROR_OK)
  66                                 return retval;
  67                         if (break_status & 0x1f) {
  68                                 /* we have halted on a  breakpoint */
  69                                 retval = target_write_u32(target,
  70                                         ejtag_info->ejtag_ibs_addr, 0);
  71                                 if (retval != ERROR_OK)
  72                                         return retval;
  73                                 target->debug_reason = DBG_REASON_BREAKPOINT;
  74                         }
  75                 }
  76
  77                 if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
  78                         /* get info about data breakpoint support */
  79                         retval = target_read_u32(target,
  80                                 ejtag_info->ejtag_dbs_addr, &break_status);
  81                         if (retval != ERROR_OK)
  82                                 return retval;
  83                         if (break_status & 0x1f) {
  84                                 /* we have halted on a  breakpoint */
  85                                 retval = target_write_u32(target,
  86                                         ejtag_info->ejtag_dbs_addr, 0);
  87                                 if (retval != ERROR_OK)
  88                                         return retval;
  89                                 target->debug_reason = DBG_REASON_WATCHPOINT;
  90                         }
  91                 }
  92         }
  93
  94         return ERROR_OK;
  95 }
  96
  97 static int mips_m4k_debug_entry(struct target *target)
  98 {
  99         struct mips32_common *mips32 = target_to_mips32(target);
 100         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 101
 102         mips32_save_context(target);
 103
 104         /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
 105         mips_ejtag_config_step(ejtag_info, 0);
 106
 107         /* make sure break unit configured */
 108         mips32_configure_break_unit(target);
 109
 110         /* attempt to find halt reason */
 111         mips_m4k_examine_debug_reason(target);
 112
 113         /* default to mips32 isa, it will be changed below if required */
 114         mips32->isa_mode = MIPS32_ISA_MIPS32;
 115
 116         if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
 117                 mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
 118
 119         LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
 120                         buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
 121                         target_state_name(target));
 122
 123         return ERROR_OK;
 124 }
 125
 126 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
 127 {
 128         struct target_list *head;
 129         struct target *curr;
 130
 131         head = target->head;
 132         while (head != (struct target_list *)NULL) {
 133                 curr = head->target;
 134                 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
 135                         return curr;
 136                 head = head->next;
 137         }
 138         return target;
 139 }
 140
 141 static int mips_m4k_halt_smp(struct target *target)
 142 {
 143         int retval = ERROR_OK;
 144         struct target_list *head;
 145         struct target *curr;
 146         head = target->head;
 147         while (head != (struct target_list *)NULL) {
 148                 int ret = ERROR_OK;
 149                 curr = head->target;
 150                 if ((curr != target) && (curr->state != TARGET_HALTED))
 151                         ret = mips_m4k_halt(curr);
 152
 153                 if (ret != ERROR_OK) {
 154                         LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
 155                         retval = ret;
 156                 }
 157                 head = head->next;
 158         }
 159         return retval;
 160 }
 161
 162 static int update_halt_gdb(struct target *target)
 163 {
 164         int retval = ERROR_OK;
 165         if (target->gdb_service->core[0] == -1) {
 166                 target->gdb_service->target = target;
 167                 target->gdb_service->core[0] = target->coreid;
 168                 retval = mips_m4k_halt_smp(target);
 169         }
 170         return retval;
 171 }
 172
 173 static int mips_m4k_poll(struct target *target)
 174 {
 175         int retval = ERROR_OK;
 176         struct mips32_common *mips32 = target_to_mips32(target);
 177         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 178         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 179         enum target_state prev_target_state = target->state;
 180
 181         /*  toggle to another core is done by gdb as follow */
 182         /*  maint packet J core_id */
 183         /*  continue */
 184         /*  the next polling trigger an halt event sent to gdb */
 185         if ((target->state == TARGET_HALTED) && (target->smp) &&
 186                 (target->gdb_service) &&
 187                 (target->gdb_service->target == NULL)) {
 188                 target->gdb_service->target =
 189                         get_mips_m4k(target, target->gdb_service->core[1]);
 190                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 191                 return retval;
 192         }
 193
 194         /* read ejtag control reg */
 195         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 196         retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 197         if (retval != ERROR_OK)
 198                 return retval;
 199
 200         /* clear this bit before handling polling
 201          * as after reset registers will read zero */
 202         if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
 203                 /* we have detected a reset, clear flag
 204                  * otherwise ejtag will not work */
 205                 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 206
 207                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 208                 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 209                 if (retval != ERROR_OK)
 210                         return retval;
 211                 LOG_DEBUG("Reset Detected");
 212         }
 213
 214         /* check for processor halted */
 215         if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
 216                 if ((target->state != TARGET_HALTED)
 217                     && (target->state != TARGET_DEBUG_RUNNING)) {
 218                         if (target->state == TARGET_UNKNOWN)
 219                                 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
 220
 221                         /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
 222                          * (maybe put on by HALT-ing the board in the previous session).
 223                          *
 224                          * Force enable debug entry for this session.
 225                          */
 226                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 227                         target->state = TARGET_HALTED;
 228                         retval = mips_m4k_debug_entry(target);
 229                         if (retval != ERROR_OK)
 230                                 return retval;
 231
 232                         if (target->smp &&
 233                                 ((prev_target_state == TARGET_RUNNING)
 234                              || (prev_target_state == TARGET_RESET))) {
 235                                 retval = update_halt_gdb(target);
 236                                 if (retval != ERROR_OK)
 237                                         return retval;
 238                         }
 239                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 240                 } else if (target->state == TARGET_DEBUG_RUNNING) {
 241                         target->state = TARGET_HALTED;
 242
 243                         retval = mips_m4k_debug_entry(target);
 244                         if (retval != ERROR_OK)
 245                                 return retval;
 246
 247                         if (target->smp) {
 248                                 retval = update_halt_gdb(target);
 249                                 if (retval != ERROR_OK)
 250                                         return retval;
 251                         }
 252
 253                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 254                 }
 255         } else
 256                 target->state = TARGET_RUNNING;
 257
 258 /*      LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
 259
 260         return ERROR_OK;
 261 }
 262
 263 static int mips_m4k_halt(struct target *target)
 264 {
 265         struct mips32_common *mips32 = target_to_mips32(target);
 266         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 267
 268         LOG_DEBUG("target->state: %s", target_state_name(target));
 269
 270         if (target->state == TARGET_HALTED) {
 271                 LOG_DEBUG("target was already halted");
 272                 return ERROR_OK;
 273         }
 274
 275         if (target->state == TARGET_UNKNOWN)
 276                 LOG_WARNING("target was in unknown state when halt was requested");
 277
 278         if (target->state == TARGET_RESET) {
 279                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 280                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 281                         return ERROR_TARGET_FAILURE;
 282                 } else {
 283                         /* we came here in a reset_halt or reset_init sequence
 284                          * debug entry was already prepared in mips_m4k_assert_reset()
 285                          */
 286                         target->debug_reason = DBG_REASON_DBGRQ;
 287
 288                         return ERROR_OK;
 289                 }
 290         }
 291
 292         /* break processor */
 293         mips_ejtag_enter_debug(ejtag_info);
 294
 295         target->debug_reason = DBG_REASON_DBGRQ;
 296
 297         return ERROR_OK;
 298 }
 299
 300 static int mips_m4k_assert_reset(struct target *target)
 301 {
 302         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
 303         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 304
 305         LOG_DEBUG("target->state: %s",
 306                 target_state_name(target));
 307
 308         enum reset_types jtag_reset_config = jtag_get_reset_config();
 309
 310         /* some cores support connecting while srst is asserted
 311          * use that mode is it has been configured */
 312
 313         bool srst_asserted = false;
 314
 315         if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
 316                         (jtag_reset_config & RESET_SRST_NO_GATING)) {
 317                 jtag_add_reset(0, 1);
 318                 srst_asserted = true;
 319         }
 320
 321         if (target->reset_halt) {
 322                 /* use hardware to catch reset */
 323                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
 324         } else
 325                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 326
 327         if (jtag_reset_config & RESET_HAS_SRST) {
 328                 /* here we should issue a srst only, but we may have to assert trst as well */
 329                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 330                         jtag_add_reset(1, 1);
 331                 else if (!srst_asserted)
 332                         jtag_add_reset(0, 1);
 333         } else {
 334                 if (mips_m4k->is_pic32mx) {
 335                         LOG_DEBUG("Using MTAP reset to reset processor...");
 336
 337                         /* use microchip specific MTAP reset */
 338                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
 339                         mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
 340
 341                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
 342                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
 343                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 344                 } else {
 345                         /* use ejtag reset - not supported by all cores */
 346                         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 347                         LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 348                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 349                         mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
 350                 }
 351         }
 352
 353         target->state = TARGET_RESET;
 354         jtag_add_sleep(50000);
 355
 356         register_cache_invalidate(mips_m4k->mips32.core_cache);
 357
 358         if (target->reset_halt) {
 359                 int retval = target_halt(target);
 360                 if (retval != ERROR_OK)
 361                         return retval;
 362         }
 363
 364         return ERROR_OK;
 365 }
 366
 367 static int mips_m4k_deassert_reset(struct target *target)
 368 {
 369         LOG_DEBUG("target->state: %s", target_state_name(target));
 370
 371         /* deassert reset lines */
 372         jtag_add_reset(0, 0);
 373
 374         return ERROR_OK;
 375 }
 376
 377 static int mips_m4k_single_step_core(struct target *target)
 378 {
 379         struct mips32_common *mips32 = target_to_mips32(target);
 380         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 381
 382         /* configure single step mode */
 383         mips_ejtag_config_step(ejtag_info, 1);
 384
 385         /* disable interrupts while stepping */
 386         mips32_enable_interrupts(target, 0);
 387
 388         /* exit debug mode */
 389         mips_ejtag_exit_debug(ejtag_info);
 390
 391         mips_m4k_debug_entry(target);
 392
 393         return ERROR_OK;
 394 }
 395
 396 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
 397 {
 398         int retval = ERROR_OK;
 399         struct target_list *head;
 400         struct target *curr;
 401
 402         head = target->head;
 403         while (head != (struct target_list *)NULL) {
 404                 int ret = ERROR_OK;
 405                 curr = head->target;
 406                 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
 407                         /*  resume current address , not in step mode */
 408                         ret = mips_m4k_internal_restore(curr, 1, address,
 409                                                    handle_breakpoints, 0);
 410
 411                         if (ret != ERROR_OK) {
 412                                 LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
 413                                                   curr->coreid, address);
 414                                 retval = ret;
 415                         }
 416                 }
 417                 head = head->next;
 418         }
 419         return retval;
 420 }
 421
 422 static int mips_m4k_internal_restore(struct target *target, int current,
 423                 uint32_t address, int handle_breakpoints, int debug_execution)
 424 {
 425         struct mips32_common *mips32 = target_to_mips32(target);
 426         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 427         struct breakpoint *breakpoint = NULL;
 428         uint32_t resume_pc;
 429
 430         if (target->state != TARGET_HALTED) {
 431                 LOG_WARNING("target not halted");
 432                 return ERROR_TARGET_NOT_HALTED;
 433         }
 434
 435         if (!debug_execution) {
 436                 target_free_all_working_areas(target);
 437                 mips_m4k_enable_breakpoints(target);
 438                 mips_m4k_enable_watchpoints(target);
 439         }
 440
 441         /* current = 1: continue on current pc, otherwise continue at <address> */
 442         if (!current) {
 443                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 444                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 445                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 446         }
 447
 448         if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
 449                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
 450
 451         if (!current)
 452                 resume_pc = address;
 453         else
 454                 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 455
 456         mips32_restore_context(target);
 457
 458         /* the front-end may request us not to handle breakpoints */
 459         if (handle_breakpoints) {
 460                 /* Single step past breakpoint at current address */
 461                 breakpoint = breakpoint_find(target, resume_pc);
 462                 if (breakpoint) {
 463                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
 464                         mips_m4k_unset_breakpoint(target, breakpoint);
 465                         mips_m4k_single_step_core(target);
 466                         mips_m4k_set_breakpoint(target, breakpoint);
 467                 }
 468         }
 469
 470         /* enable interrupts if we are running */
 471         mips32_enable_interrupts(target, !debug_execution);
 472
 473         /* exit debug mode */
 474         mips_ejtag_exit_debug(ejtag_info);
 475         target->debug_reason = DBG_REASON_NOTHALTED;
 476
 477         /* registers are now invalid */
 478         register_cache_invalidate(mips32->core_cache);
 479
 480         if (!debug_execution) {
 481                 target->state = TARGET_RUNNING;
 482                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 483                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 484         } else {
 485                 target->state = TARGET_DEBUG_RUNNING;
 486                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 487                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 488         }
 489
 490         return ERROR_OK;
 491 }
 492
 493 static int mips_m4k_resume(struct target *target, int current,
 494                 uint32_t address, int handle_breakpoints, int debug_execution)
 495 {
 496         int retval = ERROR_OK;
 497
 498         /* dummy resume for smp toggle in order to reduce gdb impact  */
 499         if ((target->smp) && (target->gdb_service->core[1] != -1)) {
 500                 /*   simulate a start and halt of target */
 501                 target->gdb_service->target = NULL;
 502                 target->gdb_service->core[0] = target->gdb_service->core[1];
 503                 /*  fake resume at next poll we play the  target core[1], see poll*/
 504                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 505                 return retval;
 506         }
 507
 508         retval = mips_m4k_internal_restore(target, current, address,
 509                                 handle_breakpoints,
 510                                 debug_execution);
 511
 512         if (retval == ERROR_OK && target->smp) {
 513                 target->gdb_service->core[0] = -1;
 514                 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
 515         }
 516
 517         return retval;
 518 }
 519
 520 static int mips_m4k_step(struct target *target, int current,
 521                 uint32_t address, int handle_breakpoints)
 522 {
 523         /* get pointers to arch-specific information */
 524         struct mips32_common *mips32 = target_to_mips32(target);
 525         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 526         struct breakpoint *breakpoint = NULL;
 527
 528         if (target->state != TARGET_HALTED) {
 529                 LOG_WARNING("target not halted");
 530                 return ERROR_TARGET_NOT_HALTED;
 531         }
 532
 533         /* current = 1: continue on current pc, otherwise continue at <address> */
 534         if (!current) {
 535                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 536                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 537                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 538         }
 539
 540         /* the front-end may request us not to handle breakpoints */
 541         if (handle_breakpoints) {
 542                 breakpoint = breakpoint_find(target,
 543                                 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 544                 if (breakpoint)
 545                         mips_m4k_unset_breakpoint(target, breakpoint);
 546         }
 547
 548         /* restore context */
 549         mips32_restore_context(target);
 550
 551         /* configure single step mode */
 552         mips_ejtag_config_step(ejtag_info, 1);
 553
 554         target->debug_reason = DBG_REASON_SINGLESTEP;
 555
 556         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 557
 558         /* disable interrupts while stepping */
 559         mips32_enable_interrupts(target, 0);
 560
 561         /* exit debug mode */
 562         mips_ejtag_exit_debug(ejtag_info);
 563
 564         /* registers are now invalid */
 565         register_cache_invalidate(mips32->core_cache);
 566
 567         LOG_DEBUG("target stepped ");
 568         mips_m4k_debug_entry(target);
 569
 570         if (breakpoint)
 571                 mips_m4k_set_breakpoint(target, breakpoint);
 572
 573         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 574
 575         return ERROR_OK;
 576 }
 577
 578 static void mips_m4k_enable_breakpoints(struct target *target)
 579 {
 580         struct breakpoint *breakpoint = target->breakpoints;
 581
 582         /* set any pending breakpoints */
 583         while (breakpoint) {
 584                 if (breakpoint->set == 0)
 585                         mips_m4k_set_breakpoint(target, breakpoint);
 586                 breakpoint = breakpoint->next;
 587         }
 588 }
 589
 590 static int mips_m4k_set_breakpoint(struct target *target,
 591                 struct breakpoint *breakpoint)
 592 {
 593         struct mips32_common *mips32 = target_to_mips32(target);
 594         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 595         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 596         int retval;
 597
 598         if (breakpoint->set) {
 599                 LOG_WARNING("breakpoint already set");
 600                 return ERROR_OK;
 601         }
 602
 603         if (breakpoint->type == BKPT_HARD) {
 604                 int bp_num = 0;
 605
 606                 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
 607                         bp_num++;
 608                 if (bp_num >= mips32->num_inst_bpoints) {
 609                         LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
 610                                         breakpoint->unique_id);
 611                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 612                 }
 613                 breakpoint->set = bp_num + 1;
 614                 comparator_list[bp_num].used = 1;
 615                 comparator_list[bp_num].bp_value = breakpoint->address;
 616
 617                 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
 618                  * Warning: there is no IB ASID registers in 2.0.
 619                  * Do not set it! :) */
 620                 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 621                         comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
 622
 623                 target_write_u32(target, comparator_list[bp_num].reg_address,
 624                                 comparator_list[bp_num].bp_value);
 625                 target_write_u32(target, comparator_list[bp_num].reg_address +
 626                                  ejtag_info->ejtag_ibm_offs, 0x00000000);
 627                 target_write_u32(target, comparator_list[bp_num].reg_address +
 628                                  ejtag_info->ejtag_ibc_offs, 1);
 629                 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
 630                                   breakpoint->unique_id,
 631                                   bp_num, comparator_list[bp_num].bp_value);
 632         } else if (breakpoint->type == BKPT_SOFT) {
 633                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
 634                 if (breakpoint->length == 4) {
 635                         uint32_t verify = 0xffffffff;
 636
 637                         retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 638                                         breakpoint->orig_instr);
 639                         if (retval != ERROR_OK)
 640                                 return retval;
 641                         retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP);
 642                         if (retval != ERROR_OK)
 643                                 return retval;
 644
 645                         retval = target_read_u32(target, breakpoint->address, &verify);
 646                         if (retval != ERROR_OK)
 647                                 return retval;
 648                         if (verify != MIPS32_SDBBP) {
 649                                 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
 650                                                 " - check that memory is read/writable", breakpoint->address);
 651                                 return ERROR_OK;
 652                         }
 653                 } else {
 654                         uint16_t verify = 0xffff;
 655
 656                         retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 657                                         breakpoint->orig_instr);
 658                         if (retval != ERROR_OK)
 659                                 return retval;
 660                         retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP);
 661                         if (retval != ERROR_OK)
 662                                 return retval;
 663
 664                         retval = target_read_u16(target, breakpoint->address, &verify);
 665                         if (retval != ERROR_OK)
 666                                 return retval;
 667                         if (verify != MIPS16_SDBBP) {
 668                                 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
 669                                                 " - check that memory is read/writable", breakpoint->address);
 670                                 return ERROR_OK;
 671                         }
 672                 }
 673
 674                 breakpoint->set = 20; /* Any nice value but 0 */
 675         }
 676
 677         return ERROR_OK;
 678 }
 679
 680 static int mips_m4k_unset_breakpoint(struct target *target,
 681                 struct breakpoint *breakpoint)
 682 {
 683         /* get pointers to arch-specific information */
 684         struct mips32_common *mips32 = target_to_mips32(target);
 685         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 686         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 687         int retval;
 688
 689         if (!breakpoint->set) {
 690                 LOG_WARNING("breakpoint not set");
 691                 return ERROR_OK;
 692         }
 693
 694         if (breakpoint->type == BKPT_HARD) {
 695                 int bp_num = breakpoint->set - 1;
 696                 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {
 697                         LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
 698                                           breakpoint->unique_id);
 699                         return ERROR_OK;
 700                 }
 701                 LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
 702                                 breakpoint->unique_id,
 703                                 bp_num);
 704                 comparator_list[bp_num].used = 0;
 705                 comparator_list[bp_num].bp_value = 0;
 706                 target_write_u32(target, comparator_list[bp_num].reg_address +
 707                                  ejtag_info->ejtag_ibc_offs, 0);
 708
 709         } else {
 710                 /* restore original instruction (kept in target endianness) */
 711                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
 712                 if (breakpoint->length == 4) {
 713                         uint32_t current_instr;
 714
 715                         /* check that user program has not modified breakpoint instruction */
 716                         retval = target_read_memory(target, breakpoint->address, 4, 1,
 717                                         (uint8_t *)&current_instr);
 718                         if (retval != ERROR_OK)
 719                                 return retval;
 720
 721                         /**
 722                          * target_read_memory() gets us data in _target_ endianess.
 723                          * If we want to use this data on the host for comparisons with some macros
 724                          * we must first transform it to _host_ endianess using target_buffer_get_u32().
 725                          */
 726                         current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
 727
 728                         if (current_instr == MIPS32_SDBBP) {
 729                                 retval = target_write_memory(target, breakpoint->address, 4, 1,
 730                                                 breakpoint->orig_instr);
 731                                 if (retval != ERROR_OK)
 732                                         return retval;
 733                         }
 734                 } else {
 735                         uint16_t current_instr;
 736
 737                         /* check that user program has not modified breakpoint instruction */
 738                         retval = target_read_memory(target, breakpoint->address, 2, 1,
 739                                         (uint8_t *)&current_instr);
 740                         if (retval != ERROR_OK)
 741                                 return retval;
 742                         current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
 743                         if (current_instr == MIPS16_SDBBP) {
 744                                 retval = target_write_memory(target, breakpoint->address, 2, 1,
 745                                                 breakpoint->orig_instr);
 746                                 if (retval != ERROR_OK)
 747                                         return retval;
 748                         }
 749                 }
 750         }
 751         breakpoint->set = 0;
 752
 753         return ERROR_OK;
 754 }
 755
 756 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 757 {
 758         struct mips32_common *mips32 = target_to_mips32(target);
 759
 760         if (breakpoint->type == BKPT_HARD) {
 761                 if (mips32->num_inst_bpoints_avail < 1) {
 762                         LOG_INFO("no hardware breakpoint available");
 763                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 764                 }
 765
 766                 mips32->num_inst_bpoints_avail--;
 767         }
 768
 769         return mips_m4k_set_breakpoint(target, breakpoint);
 770 }
 771
 772 static int mips_m4k_remove_breakpoint(struct target *target,
 773                 struct breakpoint *breakpoint)
 774 {
 775         /* get pointers to arch-specific information */
 776         struct mips32_common *mips32 = target_to_mips32(target);
 777
 778         if (target->state != TARGET_HALTED) {
 779                 LOG_WARNING("target not halted");
 780                 return ERROR_TARGET_NOT_HALTED;
 781         }
 782
 783         if (breakpoint->set)
 784                 mips_m4k_unset_breakpoint(target, breakpoint);
 785
 786         if (breakpoint->type == BKPT_HARD)
 787                 mips32->num_inst_bpoints_avail++;
 788
 789         return ERROR_OK;
 790 }
 791
 792 static int mips_m4k_set_watchpoint(struct target *target,
 793                 struct watchpoint *watchpoint)
 794 {
 795         struct mips32_common *mips32 = target_to_mips32(target);
 796         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 797         struct mips32_comparator *comparator_list = mips32->data_break_list;
 798         int wp_num = 0;
 799         /*
 800          * watchpoint enabled, ignore all byte lanes in value register
 801          * and exclude both load and store accesses from  watchpoint
 802          * condition evaluation
 803         */
 804         int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
 805                         (0xff << EJTAG_DBCn_BLM_SHIFT);
 806
 807         if (watchpoint->set) {
 808                 LOG_WARNING("watchpoint already set");
 809                 return ERROR_OK;
 810         }
 811
 812         while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
 813                 wp_num++;
 814         if (wp_num >= mips32->num_data_bpoints) {
 815                 LOG_ERROR("Can not find free FP Comparator");
 816                 return ERROR_FAIL;
 817         }
 818
 819         if (watchpoint->length != 4) {
 820                 LOG_ERROR("Only watchpoints of length 4 are supported");
 821                 return ERROR_TARGET_UNALIGNED_ACCESS;
 822         }
 823
 824         if (watchpoint->address % 4) {
 825                 LOG_ERROR("Watchpoints address should be word aligned");
 826                 return ERROR_TARGET_UNALIGNED_ACCESS;
 827         }
 828
 829         switch (watchpoint->rw) {
 830                 case WPT_READ:
 831                         enable &= ~EJTAG_DBCn_NOLB;
 832                         break;
 833                 case WPT_WRITE:
 834                         enable &= ~EJTAG_DBCn_NOSB;
 835                         break;
 836                 case WPT_ACCESS:
 837                         enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
 838                         break;
 839                 default:
 840                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
 841         }
 842
 843         watchpoint->set = wp_num + 1;
 844         comparator_list[wp_num].used = 1;
 845         comparator_list[wp_num].bp_value = watchpoint->address;
 846
 847         /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
 848          * There is as well no ASID register support. */
 849         if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 850                 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
 851         else
 852                 target_write_u32(target, comparator_list[wp_num].reg_address +
 853                          ejtag_info->ejtag_dbasid_offs, 0x00000000);
 854
 855         target_write_u32(target, comparator_list[wp_num].reg_address,
 856                          comparator_list[wp_num].bp_value);
 857         target_write_u32(target, comparator_list[wp_num].reg_address +
 858                          ejtag_info->ejtag_dbm_offs, 0x00000000);
 859
 860         target_write_u32(target, comparator_list[wp_num].reg_address +
 861                          ejtag_info->ejtag_dbc_offs, enable);
 862         /* TODO: probably this value is ignored on 2.0 */
 863         target_write_u32(target, comparator_list[wp_num].reg_address +
 864                          ejtag_info->ejtag_dbv_offs, 0);
 865         LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
 866
 867         return ERROR_OK;
 868 }
 869
 870 static int mips_m4k_unset_watchpoint(struct target *target,
 871                 struct watchpoint *watchpoint)
 872 {
 873         /* get pointers to arch-specific information */
 874         struct mips32_common *mips32 = target_to_mips32(target);
 875         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 876         struct mips32_comparator *comparator_list = mips32->data_break_list;
 877
 878         if (!watchpoint->set) {
 879                 LOG_WARNING("watchpoint not set");
 880                 return ERROR_OK;
 881         }
 882
 883         int wp_num = watchpoint->set - 1;
 884         if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) {
 885                 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
 886                 return ERROR_OK;
 887         }
 888         comparator_list[wp_num].used = 0;
 889         comparator_list[wp_num].bp_value = 0;
 890         target_write_u32(target, comparator_list[wp_num].reg_address +
 891                          ejtag_info->ejtag_dbc_offs, 0);
 892         watchpoint->set = 0;
 893
 894         return ERROR_OK;
 895 }
 896
 897 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 898 {
 899         struct mips32_common *mips32 = target_to_mips32(target);
 900
 901         if (mips32->num_data_bpoints_avail < 1) {
 902                 LOG_INFO("no hardware watchpoints available");
 903                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 904         }
 905
 906         mips32->num_data_bpoints_avail--;
 907
 908         mips_m4k_set_watchpoint(target, watchpoint);
 909         return ERROR_OK;
 910 }
 911
 912 static int mips_m4k_remove_watchpoint(struct target *target,
 913                 struct watchpoint *watchpoint)
 914 {
 915         /* get pointers to arch-specific information */
 916         struct mips32_common *mips32 = target_to_mips32(target);
 917
 918         if (target->state != TARGET_HALTED) {
 919                 LOG_WARNING("target not halted");
 920                 return ERROR_TARGET_NOT_HALTED;
 921         }
 922
 923         if (watchpoint->set)
 924                 mips_m4k_unset_watchpoint(target, watchpoint);
 925
 926         mips32->num_data_bpoints_avail++;
 927
 928         return ERROR_OK;
 929 }
 930
 931 static void mips_m4k_enable_watchpoints(struct target *target)
 932 {
 933         struct watchpoint *watchpoint = target->watchpoints;
 934
 935         /* set any pending watchpoints */
 936         while (watchpoint) {
 937                 if (watchpoint->set == 0)
 938                         mips_m4k_set_watchpoint(target, watchpoint);
 939                 watchpoint = watchpoint->next;
 940         }
 941 }
 942
 943 static int mips_m4k_read_memory(struct target *target, uint32_t address,
 944                 uint32_t size, uint32_t count, uint8_t *buffer)
 945 {
 946         struct mips32_common *mips32 = target_to_mips32(target);
 947         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 948
 949         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
 950                         address, size, count);
 951
 952         if (target->state != TARGET_HALTED) {
 953                 LOG_WARNING("target not halted");
 954                 return ERROR_TARGET_NOT_HALTED;
 955         }
 956
 957         /* sanitize arguments */
 958         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 959                 return ERROR_COMMAND_SYNTAX_ERROR;
 960
 961         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 962                 return ERROR_TARGET_UNALIGNED_ACCESS;
 963
 964         /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
 965         void *t = NULL;
 966
 967         if (size > 1) {
 968                 t = malloc(count * size * sizeof(uint8_t));
 969                 if (t == NULL) {
 970                         LOG_ERROR("Out of memory");
 971                         return ERROR_FAIL;
 972                 }
 973         } else
 974                 t = buffer;
 975
 976         /* if noDMA off, use DMAACC mode for memory read */
 977         int retval;
 978         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
 979                 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
 980         else
 981                 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
 982
 983         /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
 984         /* endianness, but byte array should represent target endianness       */
 985         if (ERROR_OK == retval) {
 986                 switch (size) {
 987                 case 4:
 988                         target_buffer_set_u32_array(target, buffer, count, t);
 989                         break;
 990                 case 2:
 991                         target_buffer_set_u16_array(target, buffer, count, t);
 992                         break;
 993                 }
 994         }
 995
 996         if ((size > 1) && (t != NULL))
 997                 free(t);
 998
 999         return retval;
1000 }
1001
1002 static int mips_m4k_write_memory(struct target *target, uint32_t address,
1003                 uint32_t size, uint32_t count, const uint8_t *buffer)
1004 {
1005         struct mips32_common *mips32 = target_to_mips32(target);
1006         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1007
1008         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1009                         address, size, count);
1010
1011         if (target->state != TARGET_HALTED) {
1012                 LOG_WARNING("target not halted");
1013                 return ERROR_TARGET_NOT_HALTED;
1014         }
1015
1016         if (size == 4 && count > 32) {
1017                 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1018                 if (retval == ERROR_OK)
1019                         return ERROR_OK;
1020                 LOG_WARNING("Falling back to non-bulk write");
1021         }
1022
1023         /* sanitize arguments */
1024         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1025                 return ERROR_COMMAND_SYNTAX_ERROR;
1026
1027         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1028                 return ERROR_TARGET_UNALIGNED_ACCESS;
1029
1030         /** correct endianess if we have word or hword access */
1031         void *t = NULL;
1032         if (size > 1) {
1033                 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1034                 /* endianness, but byte array represents target endianness               */
1035                 t = malloc(count * size * sizeof(uint8_t));
1036                 if (t == NULL) {
1037                         LOG_ERROR("Out of memory");
1038                         return ERROR_FAIL;
1039                 }
1040
1041                 switch (size) {
1042                 case 4:
1043                         target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1044                         break;
1045                 case 2:
1046                         target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1047                         break;
1048                 }
1049                 buffer = t;
1050         }
1051
1052         /* if noDMA off, use DMAACC mode for memory write */
1053         int retval;
1054         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1055                 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
1056         else
1057                 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
1058
1059         if (t != NULL)
1060                 free(t);
1061
1062         if (ERROR_OK != retval)
1063                 return retval;
1064
1065         return ERROR_OK;
1066 }
1067
1068 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1069                 struct target *target)
1070 {
1071         mips32_build_reg_cache(target);
1072
1073         return ERROR_OK;
1074 }
1075
1076 static int mips_m4k_init_arch_info(struct target *target,
1077                 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1078 {
1079         struct mips32_common *mips32 = &mips_m4k->mips32;
1080
1081         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1082
1083         /* initialize mips4k specific info */
1084         mips32_init_arch_info(target, mips32, tap);
1085         mips32->arch_info = mips_m4k;
1086
1087         return ERROR_OK;
1088 }
1089
1090 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1091 {
1092         struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1093
1094         mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1095
1096         return ERROR_OK;
1097 }
1098
1099 static int mips_m4k_examine(struct target *target)
1100 {
1101         int retval;
1102         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1103         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1104         uint32_t idcode = 0;
1105
1106         if (!target_was_examined(target)) {
1107                 retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
1108                 if (retval != ERROR_OK)
1109                         return retval;
1110                 ejtag_info->idcode = idcode;
1111
1112                 if (((idcode >> 1) & 0x7FF) == 0x29) {
1113                         /* we are using a pic32mx so select ejtag port
1114                          * as it is not selected by default */
1115                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1116                         LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1117                         mips_m4k->is_pic32mx = true;
1118                 }
1119         }
1120
1121         /* init rest of ejtag interface */
1122         retval = mips_ejtag_init(ejtag_info);
1123         if (retval != ERROR_OK)
1124                 return retval;
1125
1126         retval = mips32_examine(target);
1127         if (retval != ERROR_OK)
1128                 return retval;
1129
1130         return ERROR_OK;
1131 }
1132
1133 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
1134                 uint32_t count, const uint8_t *buffer)
1135 {
1136         struct mips32_common *mips32 = target_to_mips32(target);
1137         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1138         struct working_area *fast_data_area;
1139         int retval;
1140         int write_t = 1;
1141
1142         LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
1143
1144         /* check alignment */
1145         if (address & 0x3u)
1146                 return ERROR_TARGET_UNALIGNED_ACCESS;
1147
1148         if (mips32->fast_data_area == NULL) {
1149                 /* Get memory for block write handler
1150                  * we preserve this area between calls and gain a speed increase
1151                  * of about 3kb/sec when writing flash
1152                  * this will be released/nulled by the system when the target is resumed or reset */
1153                 retval = target_alloc_working_area(target,
1154                                 MIPS32_FASTDATA_HANDLER_SIZE,
1155                                 &mips32->fast_data_area);
1156                 if (retval != ERROR_OK) {
1157                         LOG_ERROR("No working area available");
1158                         return retval;
1159                 }
1160
1161                 /* reset fastadata state so the algo get reloaded */
1162                 ejtag_info->fast_access_save = -1;
1163         }
1164
1165         fast_data_area = mips32->fast_data_area;
1166
1167         if (address <= fast_data_area->address + fast_data_area->size &&
1168                         fast_data_area->address <= address + count) {
1169                 LOG_ERROR("fast_data (0x%8.8" PRIx32 ") is within write area "
1170                           "(0x%8.8" PRIx32 "-0x%8.8" PRIx32 ").",
1171                           fast_data_area->address, address, address + count);
1172                 LOG_ERROR("Change work-area-phys or load_image address!");
1173                 return ERROR_FAIL;
1174         }
1175
1176         /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1177         /* but byte array represents target endianness                      */
1178         uint32_t *t = NULL;
1179         t = malloc(count * sizeof(uint32_t));
1180         if (t == NULL) {
1181                 LOG_ERROR("Out of memory");
1182                 return ERROR_FAIL;
1183         }
1184
1185         target_buffer_get_u32_array(target, buffer, count, t);
1186
1187         retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1188                         count, t);
1189
1190         if (t != NULL)
1191                 free(t);
1192
1193         if (retval != ERROR_OK)
1194                 LOG_ERROR("Fastdata access Failed");
1195
1196         return retval;
1197 }
1198
1199 static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
1200                 struct mips_m4k_common *mips_m4k)
1201 {
1202         if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1203                 command_print(cmd_ctx, "target is not an MIPS_M4K");
1204                 return ERROR_TARGET_INVALID;
1205         }
1206         return ERROR_OK;
1207 }
1208
1209 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1210 {
1211         int retval;
1212         struct target *target = get_current_target(CMD_CTX);
1213         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1214         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1215
1216         retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
1217         if (retval != ERROR_OK)
1218                 return retval;
1219
1220         if (target->state != TARGET_HALTED) {
1221                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1222                 return ERROR_OK;
1223         }
1224
1225         /* two or more argument, access a single register/select (write if third argument is given) */
1226         if (CMD_ARGC < 2)
1227                 return ERROR_COMMAND_SYNTAX_ERROR;
1228         else {
1229                 uint32_t cp0_reg, cp0_sel;
1230                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1231                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1232
1233                 if (CMD_ARGC == 2) {
1234                         uint32_t value;
1235                         retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1236                         if (retval != ERROR_OK) {
1237                                 command_print(CMD_CTX,
1238                                                 "couldn't access reg %" PRIi32,
1239                                                 cp0_reg);
1240                                 return ERROR_OK;
1241                         }
1242                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1243                                         cp0_reg, cp0_sel, value);
1244
1245                 } else if (CMD_ARGC == 3) {
1246                         uint32_t value;
1247                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1248                         retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1249                         if (retval != ERROR_OK) {
1250                                 command_print(CMD_CTX,
1251                                                 "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
1252                                                 cp0_reg,  cp0_sel);
1253                                 return ERROR_OK;
1254                         }
1255                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1256                                         cp0_reg, cp0_sel, value);
1257                 }
1258         }
1259
1260         return ERROR_OK;
1261 }
1262
1263 COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
1264 {
1265         struct target *target = get_current_target(CMD_CTX);
1266         /* check target is an smp target */
1267         struct target_list *head;
1268         struct target *curr;
1269         head = target->head;
1270         target->smp = 0;
1271         if (head != (struct target_list *)NULL) {
1272                 while (head != (struct target_list *)NULL) {
1273                         curr = head->target;
1274                         curr->smp = 0;
1275                         head = head->next;
1276                 }
1277                 /*  fixes the target display to the debugger */
1278                 target->gdb_service->target = target;
1279         }
1280         return ERROR_OK;
1281 }
1282
1283 COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
1284 {
1285         struct target *target = get_current_target(CMD_CTX);
1286         struct target_list *head;
1287         struct target *curr;
1288         head = target->head;
1289         if (head != (struct target_list *)NULL) {
1290                 target->smp = 1;
1291                 while (head != (struct target_list *)NULL) {
1292                         curr = head->target;
1293                         curr->smp = 1;
1294                         head = head->next;
1295                 }
1296         }
1297         return ERROR_OK;
1298 }
1299
1300 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
1301 {
1302         struct target *target = get_current_target(CMD_CTX);
1303         int retval = ERROR_OK;
1304         struct target_list *head;
1305         head = target->head;
1306         if (head != (struct target_list *)NULL) {
1307                 if (CMD_ARGC == 1) {
1308                         int coreid = 0;
1309                         COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
1310                         if (ERROR_OK != retval)
1311                                 return retval;
1312                         target->gdb_service->core[1] = coreid;
1313
1314                 }
1315                 command_print(CMD_CTX, "gdb coreid  %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
1316                         , target->gdb_service->core[1]);
1317         }
1318         return ERROR_OK;
1319 }
1320
1321 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1322 {
1323         struct target *target = get_current_target(CMD_CTX);
1324         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1325         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1326
1327         if (CMD_ARGC == 1)
1328                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
1329         else if (CMD_ARGC > 1)
1330                         return ERROR_COMMAND_SYNTAX_ERROR;
1331
1332         command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
1333         if (ejtag_info->scan_delay >= 20000000) {
1334                 ejtag_info->mode = 0;
1335                 command_print(CMD_CTX, "running in legacy mode");
1336         } else {
1337                 ejtag_info->mode = 1;
1338                 command_print(CMD_CTX, "running in fast queued mode");
1339         }
1340
1341         return ERROR_OK;
1342 }
1343
1344 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1345         {
1346                 .name = "cp0",
1347                 .handler = mips_m4k_handle_cp0_command,
1348                 .mode = COMMAND_EXEC,
1349                 .usage = "regnum [value]",
1350                 .help = "display/modify cp0 register",
1351         },
1352         {
1353                 .name = "smp_off",
1354                 .handler = mips_m4k_handle_smp_off_command,
1355                 .mode = COMMAND_EXEC,
1356                 .help = "Stop smp handling",
1357                 .usage = "",},
1358
1359         {
1360                 .name = "smp_on",
1361                 .handler = mips_m4k_handle_smp_on_command,
1362                 .mode = COMMAND_EXEC,
1363                 .help = "Restart smp handling",
1364                 .usage = "",
1365         },
1366         {
1367                 .name = "smp_gdb",
1368                 .handler = mips_m4k_handle_smp_gdb_command,
1369                 .mode = COMMAND_EXEC,
1370                 .help = "display/fix current core played to gdb",
1371                 .usage = "",
1372         },
1373         {
1374                 .name = "scan_delay",
1375                 .handler = mips_m4k_handle_scan_delay_command,
1376                 .mode = COMMAND_ANY,
1377                 .help = "display/set scan delay in nano seconds",
1378                 .usage = "[value]",
1379         },
1380         COMMAND_REGISTRATION_DONE
1381 };
1382
1383 const struct command_registration mips_m4k_command_handlers[] = {
1384         {
1385                 .chain = mips32_command_handlers,
1386         },
1387         {
1388                 .name = "mips_m4k",
1389                 .mode = COMMAND_ANY,
1390                 .help = "mips_m4k command group",
1391                 .usage = "",
1392                 .chain = mips_m4k_exec_command_handlers,
1393         },
1394         COMMAND_REGISTRATION_DONE
1395 };
1396
1397 struct target_type mips_m4k_target = {
1398         .name = "mips_m4k",
1399
1400         .poll = mips_m4k_poll,
1401         .arch_state = mips32_arch_state,
1402
1403         .halt = mips_m4k_halt,
1404         .resume = mips_m4k_resume,
1405         .step = mips_m4k_step,
1406
1407         .assert_reset = mips_m4k_assert_reset,
1408         .deassert_reset = mips_m4k_deassert_reset,
1409
1410         .get_gdb_reg_list = mips32_get_gdb_reg_list,
1411
1412         .read_memory = mips_m4k_read_memory,
1413         .write_memory = mips_m4k_write_memory,
1414         .checksum_memory = mips32_checksum_memory,
1415         .blank_check_memory = mips32_blank_check_memory,
1416
1417         .run_algorithm = mips32_run_algorithm,
1418
1419         .add_breakpoint = mips_m4k_add_breakpoint,
1420         .remove_breakpoint = mips_m4k_remove_breakpoint,
1421         .add_watchpoint = mips_m4k_add_watchpoint,
1422         .remove_watchpoint = mips_m4k_remove_watchpoint,
1423
1424         .commands = mips_m4k_command_handlers,
1425         .target_create = mips_m4k_target_create,
1426         .init_target = mips_m4k_init_target,
1427         .examine = mips_m4k_examine,
1428 };