git.sur5r.net Git - openocd/blob - src/target/mips_m4k.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
  10  *   drasko.draskovic@gmail.com                                            *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program; if not, write to the                         *
  24  *   Free Software Foundation, Inc.,                                       *
  25  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  26  ***************************************************************************/
  27
  28 #ifdef HAVE_CONFIG_H
  29 #include "config.h"
  30 #endif
  31
  32 #include "breakpoints.h"
  33 #include "mips32.h"
  34 #include "mips_m4k.h"
  35 #include "mips32_dmaacc.h"
  36 #include "target_type.h"
  37 #include "register.h"
  38
  39 static void mips_m4k_enable_breakpoints(struct target *target);
  40 static void mips_m4k_enable_watchpoints(struct target *target);
  41 static int mips_m4k_set_breakpoint(struct target *target,
  42                 struct breakpoint *breakpoint);
  43 static int mips_m4k_unset_breakpoint(struct target *target,
  44                 struct breakpoint *breakpoint);
  45 static int mips_m4k_internal_restore(struct target *target, int current,
  46                 uint32_t address, int handle_breakpoints,
  47                 int debug_execution);
  48 static int mips_m4k_halt(struct target *target);
  49 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
  50                 uint32_t count, const uint8_t *buffer);
  51
  52 static int mips_m4k_examine_debug_reason(struct target *target)
  53 {
  54         struct mips32_common *mips32 = target_to_mips32(target);
  55         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  56         uint32_t break_status;
  57         int retval;
  58
  59         if ((target->debug_reason != DBG_REASON_DBGRQ)
  60                 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
  61                 /* get info about inst breakpoint support */
  62                 retval = target_read_u32(target,
  63                         ejtag_info->ejtag_ibs_addr, &break_status);
  64                 if (retval != ERROR_OK)
  65                         return retval;
  66                 if (break_status & 0x1f) {
  67                         /* we have halted on a  breakpoint */
  68                         retval = target_write_u32(target,
  69                                 ejtag_info->ejtag_ibs_addr, 0);
  70                         if (retval != ERROR_OK)
  71                                 return retval;
  72                         target->debug_reason = DBG_REASON_BREAKPOINT;
  73                 }
  74
  75                 /* get info about data breakpoint support */
  76                 retval = target_read_u32(target,
  77                         ejtag_info->ejtag_dbs_addr, &break_status);
  78                 if (retval != ERROR_OK)
  79                         return retval;
  80                 if (break_status & 0x1f) {
  81                         /* we have halted on a  breakpoint */
  82                         retval = target_write_u32(target,
  83                                 ejtag_info->ejtag_dbs_addr, 0);
  84                         if (retval != ERROR_OK)
  85                                 return retval;
  86                         target->debug_reason = DBG_REASON_WATCHPOINT;
  87                 }
  88         }
  89
  90         return ERROR_OK;
  91 }
  92
  93 static int mips_m4k_debug_entry(struct target *target)
  94 {
  95         struct mips32_common *mips32 = target_to_mips32(target);
  96         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  97
  98         mips32_save_context(target);
  99
 100         /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
 101         mips_ejtag_config_step(ejtag_info, 0);
 102
 103         /* make sure break unit configured */
 104         mips32_configure_break_unit(target);
 105
 106         /* attempt to find halt reason */
 107         mips_m4k_examine_debug_reason(target);
 108
 109         /* default to mips32 isa, it will be changed below if required */
 110         mips32->isa_mode = MIPS32_ISA_MIPS32;
 111
 112         if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
 113                 mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
 114
 115         LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
 116                         buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
 117                         target_state_name(target));
 118
 119         return ERROR_OK;
 120 }
 121
 122 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
 123 {
 124         struct target_list *head;
 125         struct target *curr;
 126
 127         head = target->head;
 128         while (head != (struct target_list *)NULL) {
 129                 curr = head->target;
 130                 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
 131                         return curr;
 132                 head = head->next;
 133         }
 134         return target;
 135 }
 136
 137 static int mips_m4k_halt_smp(struct target *target)
 138 {
 139         int retval = ERROR_OK;
 140         struct target_list *head;
 141         struct target *curr;
 142         head = target->head;
 143         while (head != (struct target_list *)NULL) {
 144                 int ret = ERROR_OK;
 145                 curr = head->target;
 146                 if ((curr != target) && (curr->state != TARGET_HALTED))
 147                         ret = mips_m4k_halt(curr);
 148
 149                 if (ret != ERROR_OK) {
 150                         LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
 151                         retval = ret;
 152                 }
 153                 head = head->next;
 154         }
 155         return retval;
 156 }
 157
 158 static int update_halt_gdb(struct target *target)
 159 {
 160         int retval = ERROR_OK;
 161         if (target->gdb_service->core[0] == -1) {
 162                 target->gdb_service->target = target;
 163                 target->gdb_service->core[0] = target->coreid;
 164                 retval = mips_m4k_halt_smp(target);
 165         }
 166         return retval;
 167 }
 168
 169 static int mips_m4k_poll(struct target *target)
 170 {
 171         int retval = ERROR_OK;
 172         struct mips32_common *mips32 = target_to_mips32(target);
 173         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 174         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 175         enum target_state prev_target_state = target->state;
 176
 177         /*  toggle to another core is done by gdb as follow */
 178         /*  maint packet J core_id */
 179         /*  continue */
 180         /*  the next polling trigger an halt event sent to gdb */
 181         if ((target->state == TARGET_HALTED) && (target->smp) &&
 182                 (target->gdb_service) &&
 183                 (target->gdb_service->target == NULL)) {
 184                 target->gdb_service->target =
 185                         get_mips_m4k(target, target->gdb_service->core[1]);
 186                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 187                 return retval;
 188         }
 189
 190         /* read ejtag control reg */
 191         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 192         retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 193         if (retval != ERROR_OK)
 194                 return retval;
 195
 196         /* clear this bit before handling polling
 197          * as after reset registers will read zero */
 198         if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
 199                 /* we have detected a reset, clear flag
 200                  * otherwise ejtag will not work */
 201                 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 202
 203                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 204                 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 205                 if (retval != ERROR_OK)
 206                         return retval;
 207                 LOG_DEBUG("Reset Detected");
 208         }
 209
 210         /* check for processor halted */
 211         if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
 212                 if ((target->state != TARGET_HALTED)
 213                     && (target->state != TARGET_DEBUG_RUNNING)) {
 214                         if (target->state == TARGET_UNKNOWN)
 215                                 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
 216
 217                         /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
 218                          * (maybe put on by HALT-ing the board in the previous session).
 219                          *
 220                          * Force enable debug entry for this session.
 221                          */
 222                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 223                         target->state = TARGET_HALTED;
 224                         retval = mips_m4k_debug_entry(target);
 225                         if (retval != ERROR_OK)
 226                                 return retval;
 227
 228                         if (target->smp &&
 229                                 ((prev_target_state == TARGET_RUNNING)
 230                              || (prev_target_state == TARGET_RESET))) {
 231                                 retval = update_halt_gdb(target);
 232                                 if (retval != ERROR_OK)
 233                                         return retval;
 234                         }
 235                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 236                 } else if (target->state == TARGET_DEBUG_RUNNING) {
 237                         target->state = TARGET_HALTED;
 238
 239                         retval = mips_m4k_debug_entry(target);
 240                         if (retval != ERROR_OK)
 241                                 return retval;
 242
 243                         if (target->smp) {
 244                                 retval = update_halt_gdb(target);
 245                                 if (retval != ERROR_OK)
 246                                         return retval;
 247                         }
 248
 249                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 250                 }
 251         } else
 252                 target->state = TARGET_RUNNING;
 253
 254 /*      LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
 255
 256         return ERROR_OK;
 257 }
 258
 259 static int mips_m4k_halt(struct target *target)
 260 {
 261         struct mips32_common *mips32 = target_to_mips32(target);
 262         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 263
 264         LOG_DEBUG("target->state: %s", target_state_name(target));
 265
 266         if (target->state == TARGET_HALTED) {
 267                 LOG_DEBUG("target was already halted");
 268                 return ERROR_OK;
 269         }
 270
 271         if (target->state == TARGET_UNKNOWN)
 272                 LOG_WARNING("target was in unknown state when halt was requested");
 273
 274         if (target->state == TARGET_RESET) {
 275                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 276                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 277                         return ERROR_TARGET_FAILURE;
 278                 } else {
 279                         /* we came here in a reset_halt or reset_init sequence
 280                          * debug entry was already prepared in mips_m4k_assert_reset()
 281                          */
 282                         target->debug_reason = DBG_REASON_DBGRQ;
 283
 284                         return ERROR_OK;
 285                 }
 286         }
 287
 288         /* break processor */
 289         mips_ejtag_enter_debug(ejtag_info);
 290
 291         target->debug_reason = DBG_REASON_DBGRQ;
 292
 293         return ERROR_OK;
 294 }
 295
 296 static int mips_m4k_assert_reset(struct target *target)
 297 {
 298         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
 299         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 300
 301         LOG_DEBUG("target->state: %s",
 302                 target_state_name(target));
 303
 304         enum reset_types jtag_reset_config = jtag_get_reset_config();
 305
 306         /* some cores support connecting while srst is asserted
 307          * use that mode is it has been configured */
 308
 309         bool srst_asserted = false;
 310
 311         if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
 312                         (jtag_reset_config & RESET_SRST_NO_GATING)) {
 313                 jtag_add_reset(0, 1);
 314                 srst_asserted = true;
 315         }
 316
 317         if (target->reset_halt) {
 318                 /* use hardware to catch reset */
 319                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
 320         } else
 321                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 322
 323         if (jtag_reset_config & RESET_HAS_SRST) {
 324                 /* here we should issue a srst only, but we may have to assert trst as well */
 325                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 326                         jtag_add_reset(1, 1);
 327                 else if (!srst_asserted)
 328                         jtag_add_reset(0, 1);
 329         } else {
 330                 if (mips_m4k->is_pic32mx) {
 331                         LOG_DEBUG("Using MTAP reset to reset processor...");
 332
 333                         /* use microchip specific MTAP reset */
 334                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
 335                         mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
 336
 337                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
 338                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
 339                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 340                 } else {
 341                         /* use ejtag reset - not supported by all cores */
 342                         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 343                         LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 344                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 345                         mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
 346                 }
 347         }
 348
 349         target->state = TARGET_RESET;
 350         jtag_add_sleep(50000);
 351
 352         register_cache_invalidate(mips_m4k->mips32.core_cache);
 353
 354         if (target->reset_halt) {
 355                 int retval = target_halt(target);
 356                 if (retval != ERROR_OK)
 357                         return retval;
 358         }
 359
 360         return ERROR_OK;
 361 }
 362
 363 static int mips_m4k_deassert_reset(struct target *target)
 364 {
 365         LOG_DEBUG("target->state: %s", target_state_name(target));
 366
 367         /* deassert reset lines */
 368         jtag_add_reset(0, 0);
 369
 370         return ERROR_OK;
 371 }
 372
 373 static int mips_m4k_single_step_core(struct target *target)
 374 {
 375         struct mips32_common *mips32 = target_to_mips32(target);
 376         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 377
 378         /* configure single step mode */
 379         mips_ejtag_config_step(ejtag_info, 1);
 380
 381         /* disable interrupts while stepping */
 382         mips32_enable_interrupts(target, 0);
 383
 384         /* exit debug mode */
 385         mips_ejtag_exit_debug(ejtag_info);
 386
 387         mips_m4k_debug_entry(target);
 388
 389         return ERROR_OK;
 390 }
 391
 392 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
 393 {
 394         int retval = ERROR_OK;
 395         struct target_list *head;
 396         struct target *curr;
 397
 398         head = target->head;
 399         while (head != (struct target_list *)NULL) {
 400                 int ret = ERROR_OK;
 401                 curr = head->target;
 402                 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
 403                         /*  resume current address , not in step mode */
 404                         ret = mips_m4k_internal_restore(curr, 1, address,
 405                                                    handle_breakpoints, 0);
 406
 407                         if (ret != ERROR_OK) {
 408                                 LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
 409                                                   curr->coreid, address);
 410                                 retval = ret;
 411                         }
 412                 }
 413                 head = head->next;
 414         }
 415         return retval;
 416 }
 417
 418 static int mips_m4k_internal_restore(struct target *target, int current,
 419                 uint32_t address, int handle_breakpoints, int debug_execution)
 420 {
 421         struct mips32_common *mips32 = target_to_mips32(target);
 422         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 423         struct breakpoint *breakpoint = NULL;
 424         uint32_t resume_pc;
 425
 426         if (target->state != TARGET_HALTED) {
 427                 LOG_WARNING("target not halted");
 428                 return ERROR_TARGET_NOT_HALTED;
 429         }
 430
 431         if (!debug_execution) {
 432                 target_free_all_working_areas(target);
 433                 mips_m4k_enable_breakpoints(target);
 434                 mips_m4k_enable_watchpoints(target);
 435         }
 436
 437         /* current = 1: continue on current pc, otherwise continue at <address> */
 438         if (!current) {
 439                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 440                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 441                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 442         }
 443
 444         if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
 445                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
 446
 447         if (!current)
 448                 resume_pc = address;
 449         else
 450                 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 451
 452         mips32_restore_context(target);
 453
 454         /* the front-end may request us not to handle breakpoints */
 455         if (handle_breakpoints) {
 456                 /* Single step past breakpoint at current address */
 457                 breakpoint = breakpoint_find(target, resume_pc);
 458                 if (breakpoint) {
 459                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
 460                         mips_m4k_unset_breakpoint(target, breakpoint);
 461                         mips_m4k_single_step_core(target);
 462                         mips_m4k_set_breakpoint(target, breakpoint);
 463                 }
 464         }
 465
 466         /* enable interrupts if we are running */
 467         mips32_enable_interrupts(target, !debug_execution);
 468
 469         /* exit debug mode */
 470         mips_ejtag_exit_debug(ejtag_info);
 471         target->debug_reason = DBG_REASON_NOTHALTED;
 472
 473         /* registers are now invalid */
 474         register_cache_invalidate(mips32->core_cache);
 475
 476         if (!debug_execution) {
 477                 target->state = TARGET_RUNNING;
 478                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 479                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 480         } else {
 481                 target->state = TARGET_DEBUG_RUNNING;
 482                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 483                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 484         }
 485
 486         return ERROR_OK;
 487 }
 488
 489 static int mips_m4k_resume(struct target *target, int current,
 490                 uint32_t address, int handle_breakpoints, int debug_execution)
 491 {
 492         int retval = ERROR_OK;
 493
 494         /* dummy resume for smp toggle in order to reduce gdb impact  */
 495         if ((target->smp) && (target->gdb_service->core[1] != -1)) {
 496                 /*   simulate a start and halt of target */
 497                 target->gdb_service->target = NULL;
 498                 target->gdb_service->core[0] = target->gdb_service->core[1];
 499                 /*  fake resume at next poll we play the  target core[1], see poll*/
 500                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 501                 return retval;
 502         }
 503
 504         retval = mips_m4k_internal_restore(target, current, address,
 505                                 handle_breakpoints,
 506                                 debug_execution);
 507
 508         if (retval == ERROR_OK && target->smp) {
 509                 target->gdb_service->core[0] = -1;
 510                 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
 511         }
 512
 513         return retval;
 514 }
 515
 516 static int mips_m4k_step(struct target *target, int current,
 517                 uint32_t address, int handle_breakpoints)
 518 {
 519         /* get pointers to arch-specific information */
 520         struct mips32_common *mips32 = target_to_mips32(target);
 521         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 522         struct breakpoint *breakpoint = NULL;
 523
 524         if (target->state != TARGET_HALTED) {
 525                 LOG_WARNING("target not halted");
 526                 return ERROR_TARGET_NOT_HALTED;
 527         }
 528
 529         /* current = 1: continue on current pc, otherwise continue at <address> */
 530         if (!current) {
 531                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 532                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 533                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 534         }
 535
 536         /* the front-end may request us not to handle breakpoints */
 537         if (handle_breakpoints) {
 538                 breakpoint = breakpoint_find(target,
 539                                 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 540                 if (breakpoint)
 541                         mips_m4k_unset_breakpoint(target, breakpoint);
 542         }
 543
 544         /* restore context */
 545         mips32_restore_context(target);
 546
 547         /* configure single step mode */
 548         mips_ejtag_config_step(ejtag_info, 1);
 549
 550         target->debug_reason = DBG_REASON_SINGLESTEP;
 551
 552         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 553
 554         /* disable interrupts while stepping */
 555         mips32_enable_interrupts(target, 0);
 556
 557         /* exit debug mode */
 558         mips_ejtag_exit_debug(ejtag_info);
 559
 560         /* registers are now invalid */
 561         register_cache_invalidate(mips32->core_cache);
 562
 563         LOG_DEBUG("target stepped ");
 564         mips_m4k_debug_entry(target);
 565
 566         if (breakpoint)
 567                 mips_m4k_set_breakpoint(target, breakpoint);
 568
 569         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 570
 571         return ERROR_OK;
 572 }
 573
 574 static void mips_m4k_enable_breakpoints(struct target *target)
 575 {
 576         struct breakpoint *breakpoint = target->breakpoints;
 577
 578         /* set any pending breakpoints */
 579         while (breakpoint) {
 580                 if (breakpoint->set == 0)
 581                         mips_m4k_set_breakpoint(target, breakpoint);
 582                 breakpoint = breakpoint->next;
 583         }
 584 }
 585
 586 static int mips_m4k_set_breakpoint(struct target *target,
 587                 struct breakpoint *breakpoint)
 588 {
 589         struct mips32_common *mips32 = target_to_mips32(target);
 590         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 591         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 592         int retval;
 593
 594         if (breakpoint->set) {
 595                 LOG_WARNING("breakpoint already set");
 596                 return ERROR_OK;
 597         }
 598
 599         if (breakpoint->type == BKPT_HARD) {
 600                 int bp_num = 0;
 601
 602                 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
 603                         bp_num++;
 604                 if (bp_num >= mips32->num_inst_bpoints) {
 605                         LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
 606                                         breakpoint->unique_id);
 607                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 608                 }
 609                 breakpoint->set = bp_num + 1;
 610                 comparator_list[bp_num].used = 1;
 611                 comparator_list[bp_num].bp_value = breakpoint->address;
 612
 613                 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
 614                  * Warning: there is no IB ASID registers in 2.0.
 615                  * Do not set it! :) */
 616                 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 617                         comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
 618
 619                 target_write_u32(target, comparator_list[bp_num].reg_address,
 620                                 comparator_list[bp_num].bp_value);
 621                 target_write_u32(target, comparator_list[bp_num].reg_address +
 622                                  ejtag_info->ejtag_ibm_offs, 0x00000000);
 623                 target_write_u32(target, comparator_list[bp_num].reg_address +
 624                                  ejtag_info->ejtag_ibc_offs, 1);
 625                 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
 626                                   breakpoint->unique_id,
 627                                   bp_num, comparator_list[bp_num].bp_value);
 628         } else if (breakpoint->type == BKPT_SOFT) {
 629                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
 630                 if (breakpoint->length == 4) {
 631                         uint32_t verify = 0xffffffff;
 632
 633                         retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 634                                         breakpoint->orig_instr);
 635                         if (retval != ERROR_OK)
 636                                 return retval;
 637                         retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP);
 638                         if (retval != ERROR_OK)
 639                                 return retval;
 640
 641                         retval = target_read_u32(target, breakpoint->address, &verify);
 642                         if (retval != ERROR_OK)
 643                                 return retval;
 644                         if (verify != MIPS32_SDBBP) {
 645                                 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
 646                                                 " - check that memory is read/writable", breakpoint->address);
 647                                 return ERROR_OK;
 648                         }
 649                 } else {
 650                         uint16_t verify = 0xffff;
 651
 652                         retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 653                                         breakpoint->orig_instr);
 654                         if (retval != ERROR_OK)
 655                                 return retval;
 656                         retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP);
 657                         if (retval != ERROR_OK)
 658                                 return retval;
 659
 660                         retval = target_read_u16(target, breakpoint->address, &verify);
 661                         if (retval != ERROR_OK)
 662                                 return retval;
 663                         if (verify != MIPS16_SDBBP) {
 664                                 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
 665                                                 " - check that memory is read/writable", breakpoint->address);
 666                                 return ERROR_OK;
 667                         }
 668                 }
 669
 670                 breakpoint->set = 20; /* Any nice value but 0 */
 671         }
 672
 673         return ERROR_OK;
 674 }
 675
 676 static int mips_m4k_unset_breakpoint(struct target *target,
 677                 struct breakpoint *breakpoint)
 678 {
 679         /* get pointers to arch-specific information */
 680         struct mips32_common *mips32 = target_to_mips32(target);
 681         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 682         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 683         int retval;
 684
 685         if (!breakpoint->set) {
 686                 LOG_WARNING("breakpoint not set");
 687                 return ERROR_OK;
 688         }
 689
 690         if (breakpoint->type == BKPT_HARD) {
 691                 int bp_num = breakpoint->set - 1;
 692                 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {
 693                         LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
 694                                           breakpoint->unique_id);
 695                         return ERROR_OK;
 696                 }
 697                 LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
 698                                 breakpoint->unique_id,
 699                                 bp_num);
 700                 comparator_list[bp_num].used = 0;
 701                 comparator_list[bp_num].bp_value = 0;
 702                 target_write_u32(target, comparator_list[bp_num].reg_address +
 703                                  ejtag_info->ejtag_ibc_offs, 0);
 704
 705         } else {
 706                 /* restore original instruction (kept in target endianness) */
 707                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
 708                 if (breakpoint->length == 4) {
 709                         uint32_t current_instr;
 710
 711                         /* check that user program has not modified breakpoint instruction */
 712                         retval = target_read_memory(target, breakpoint->address, 4, 1,
 713                                         (uint8_t *)&current_instr);
 714                         if (retval != ERROR_OK)
 715                                 return retval;
 716
 717                         /**
 718                          * target_read_memory() gets us data in _target_ endianess.
 719                          * If we want to use this data on the host for comparisons with some macros
 720                          * we must first transform it to _host_ endianess using target_buffer_get_u32().
 721                          */
 722                         current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
 723
 724                         if (current_instr == MIPS32_SDBBP) {
 725                                 retval = target_write_memory(target, breakpoint->address, 4, 1,
 726                                                 breakpoint->orig_instr);
 727                                 if (retval != ERROR_OK)
 728                                         return retval;
 729                         }
 730                 } else {
 731                         uint16_t current_instr;
 732
 733                         /* check that user program has not modified breakpoint instruction */
 734                         retval = target_read_memory(target, breakpoint->address, 2, 1,
 735                                         (uint8_t *)&current_instr);
 736                         if (retval != ERROR_OK)
 737                                 return retval;
 738                         current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
 739                         if (current_instr == MIPS16_SDBBP) {
 740                                 retval = target_write_memory(target, breakpoint->address, 2, 1,
 741                                                 breakpoint->orig_instr);
 742                                 if (retval != ERROR_OK)
 743                                         return retval;
 744                         }
 745                 }
 746         }
 747         breakpoint->set = 0;
 748
 749         return ERROR_OK;
 750 }
 751
 752 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 753 {
 754         struct mips32_common *mips32 = target_to_mips32(target);
 755
 756         if (breakpoint->type == BKPT_HARD) {
 757                 if (mips32->num_inst_bpoints_avail < 1) {
 758                         LOG_INFO("no hardware breakpoint available");
 759                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 760                 }
 761
 762                 mips32->num_inst_bpoints_avail--;
 763         }
 764
 765         return mips_m4k_set_breakpoint(target, breakpoint);
 766 }
 767
 768 static int mips_m4k_remove_breakpoint(struct target *target,
 769                 struct breakpoint *breakpoint)
 770 {
 771         /* get pointers to arch-specific information */
 772         struct mips32_common *mips32 = target_to_mips32(target);
 773
 774         if (target->state != TARGET_HALTED) {
 775                 LOG_WARNING("target not halted");
 776                 return ERROR_TARGET_NOT_HALTED;
 777         }
 778
 779         if (breakpoint->set)
 780                 mips_m4k_unset_breakpoint(target, breakpoint);
 781
 782         if (breakpoint->type == BKPT_HARD)
 783                 mips32->num_inst_bpoints_avail++;
 784
 785         return ERROR_OK;
 786 }
 787
 788 static int mips_m4k_set_watchpoint(struct target *target,
 789                 struct watchpoint *watchpoint)
 790 {
 791         struct mips32_common *mips32 = target_to_mips32(target);
 792         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 793         struct mips32_comparator *comparator_list = mips32->data_break_list;
 794         int wp_num = 0;
 795         /*
 796          * watchpoint enabled, ignore all byte lanes in value register
 797          * and exclude both load and store accesses from  watchpoint
 798          * condition evaluation
 799         */
 800         int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
 801                         (0xff << EJTAG_DBCn_BLM_SHIFT);
 802
 803         if (watchpoint->set) {
 804                 LOG_WARNING("watchpoint already set");
 805                 return ERROR_OK;
 806         }
 807
 808         while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
 809                 wp_num++;
 810         if (wp_num >= mips32->num_data_bpoints) {
 811                 LOG_ERROR("Can not find free FP Comparator");
 812                 return ERROR_FAIL;
 813         }
 814
 815         if (watchpoint->length != 4) {
 816                 LOG_ERROR("Only watchpoints of length 4 are supported");
 817                 return ERROR_TARGET_UNALIGNED_ACCESS;
 818         }
 819
 820         if (watchpoint->address % 4) {
 821                 LOG_ERROR("Watchpoints address should be word aligned");
 822                 return ERROR_TARGET_UNALIGNED_ACCESS;
 823         }
 824
 825         switch (watchpoint->rw) {
 826                 case WPT_READ:
 827                         enable &= ~EJTAG_DBCn_NOLB;
 828                         break;
 829                 case WPT_WRITE:
 830                         enable &= ~EJTAG_DBCn_NOSB;
 831                         break;
 832                 case WPT_ACCESS:
 833                         enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
 834                         break;
 835                 default:
 836                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
 837         }
 838
 839         watchpoint->set = wp_num + 1;
 840         comparator_list[wp_num].used = 1;
 841         comparator_list[wp_num].bp_value = watchpoint->address;
 842
 843         /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
 844          * There is as well no ASID register support. */
 845         if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 846                 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
 847         else
 848                 target_write_u32(target, comparator_list[wp_num].reg_address +
 849                          ejtag_info->ejtag_dbasid_offs, 0x00000000);
 850
 851         target_write_u32(target, comparator_list[wp_num].reg_address,
 852                          comparator_list[wp_num].bp_value);
 853         target_write_u32(target, comparator_list[wp_num].reg_address +
 854                          ejtag_info->ejtag_dbm_offs, 0x00000000);
 855
 856         target_write_u32(target, comparator_list[wp_num].reg_address +
 857                          ejtag_info->ejtag_dbc_offs, enable);
 858         /* TODO: probably this value is ignored on 2.0 */
 859         target_write_u32(target, comparator_list[wp_num].reg_address +
 860                          ejtag_info->ejtag_dbv_offs, 0);
 861         LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
 862
 863         return ERROR_OK;
 864 }
 865
 866 static int mips_m4k_unset_watchpoint(struct target *target,
 867                 struct watchpoint *watchpoint)
 868 {
 869         /* get pointers to arch-specific information */
 870         struct mips32_common *mips32 = target_to_mips32(target);
 871         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 872         struct mips32_comparator *comparator_list = mips32->data_break_list;
 873
 874         if (!watchpoint->set) {
 875                 LOG_WARNING("watchpoint not set");
 876                 return ERROR_OK;
 877         }
 878
 879         int wp_num = watchpoint->set - 1;
 880         if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) {
 881                 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
 882                 return ERROR_OK;
 883         }
 884         comparator_list[wp_num].used = 0;
 885         comparator_list[wp_num].bp_value = 0;
 886         target_write_u32(target, comparator_list[wp_num].reg_address +
 887                          ejtag_info->ejtag_dbc_offs, 0);
 888         watchpoint->set = 0;
 889
 890         return ERROR_OK;
 891 }
 892
 893 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 894 {
 895         struct mips32_common *mips32 = target_to_mips32(target);
 896
 897         if (mips32->num_data_bpoints_avail < 1) {
 898                 LOG_INFO("no hardware watchpoints available");
 899                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 900         }
 901
 902         mips32->num_data_bpoints_avail--;
 903
 904         mips_m4k_set_watchpoint(target, watchpoint);
 905         return ERROR_OK;
 906 }
 907
 908 static int mips_m4k_remove_watchpoint(struct target *target,
 909                 struct watchpoint *watchpoint)
 910 {
 911         /* get pointers to arch-specific information */
 912         struct mips32_common *mips32 = target_to_mips32(target);
 913
 914         if (target->state != TARGET_HALTED) {
 915                 LOG_WARNING("target not halted");
 916                 return ERROR_TARGET_NOT_HALTED;
 917         }
 918
 919         if (watchpoint->set)
 920                 mips_m4k_unset_watchpoint(target, watchpoint);
 921
 922         mips32->num_data_bpoints_avail++;
 923
 924         return ERROR_OK;
 925 }
 926
 927 static void mips_m4k_enable_watchpoints(struct target *target)
 928 {
 929         struct watchpoint *watchpoint = target->watchpoints;
 930
 931         /* set any pending watchpoints */
 932         while (watchpoint) {
 933                 if (watchpoint->set == 0)
 934                         mips_m4k_set_watchpoint(target, watchpoint);
 935                 watchpoint = watchpoint->next;
 936         }
 937 }
 938
 939 static int mips_m4k_read_memory(struct target *target, uint32_t address,
 940                 uint32_t size, uint32_t count, uint8_t *buffer)
 941 {
 942         struct mips32_common *mips32 = target_to_mips32(target);
 943         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 944
 945         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
 946                         address, size, count);
 947
 948         if (target->state != TARGET_HALTED) {
 949                 LOG_WARNING("target not halted");
 950                 return ERROR_TARGET_NOT_HALTED;
 951         }
 952
 953         /* sanitize arguments */
 954         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 955                 return ERROR_COMMAND_SYNTAX_ERROR;
 956
 957         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 958                 return ERROR_TARGET_UNALIGNED_ACCESS;
 959
 960         /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
 961         void *t = NULL;
 962
 963         if (size > 1) {
 964                 t = malloc(count * size * sizeof(uint8_t));
 965                 if (t == NULL) {
 966                         LOG_ERROR("Out of memory");
 967                         return ERROR_FAIL;
 968                 }
 969         } else
 970                 t = buffer;
 971
 972         /* if noDMA off, use DMAACC mode for memory read */
 973         int retval;
 974         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
 975                 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
 976         else
 977                 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
 978
 979         /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
 980         /* endianness, but byte array should represent target endianness       */
 981         if (ERROR_OK == retval) {
 982                 switch (size) {
 983                 case 4:
 984                         target_buffer_set_u32_array(target, buffer, count, t);
 985                         break;
 986                 case 2:
 987                         target_buffer_set_u16_array(target, buffer, count, t);
 988                         break;
 989                 }
 990         }
 991
 992         if ((size > 1) && (t != NULL))
 993                 free(t);
 994
 995         return retval;
 996 }
 997
 998 static int mips_m4k_write_memory(struct target *target, uint32_t address,
 999                 uint32_t size, uint32_t count, const uint8_t *buffer)
1000 {
1001         struct mips32_common *mips32 = target_to_mips32(target);
1002         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1003
1004         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1005                         address, size, count);
1006
1007         if (target->state != TARGET_HALTED) {
1008                 LOG_WARNING("target not halted");
1009                 return ERROR_TARGET_NOT_HALTED;
1010         }
1011
1012         if (size == 4 && count > 32) {
1013                 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1014                 if (retval == ERROR_OK)
1015                         return ERROR_OK;
1016                 LOG_WARNING("Falling back to non-bulk write");
1017         }
1018
1019         /* sanitize arguments */
1020         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1021                 return ERROR_COMMAND_SYNTAX_ERROR;
1022
1023         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1024                 return ERROR_TARGET_UNALIGNED_ACCESS;
1025
1026         /** correct endianess if we have word or hword access */
1027         void *t = NULL;
1028         if (size > 1) {
1029                 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1030                 /* endianness, but byte array represents target endianness               */
1031                 t = malloc(count * size * sizeof(uint8_t));
1032                 if (t == NULL) {
1033                         LOG_ERROR("Out of memory");
1034                         return ERROR_FAIL;
1035                 }
1036
1037                 switch (size) {
1038                 case 4:
1039                         target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1040                         break;
1041                 case 2:
1042                         target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1043                         break;
1044                 }
1045                 buffer = t;
1046         }
1047
1048         /* if noDMA off, use DMAACC mode for memory write */
1049         int retval;
1050         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1051                 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
1052         else
1053                 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
1054
1055         if (t != NULL)
1056                 free(t);
1057
1058         if (ERROR_OK != retval)
1059                 return retval;
1060
1061         return ERROR_OK;
1062 }
1063
1064 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1065                 struct target *target)
1066 {
1067         mips32_build_reg_cache(target);
1068
1069         return ERROR_OK;
1070 }
1071
1072 static int mips_m4k_init_arch_info(struct target *target,
1073                 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1074 {
1075         struct mips32_common *mips32 = &mips_m4k->mips32;
1076
1077         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1078
1079         /* initialize mips4k specific info */
1080         mips32_init_arch_info(target, mips32, tap);
1081         mips32->arch_info = mips_m4k;
1082
1083         return ERROR_OK;
1084 }
1085
1086 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1087 {
1088         struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1089
1090         mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1091
1092         return ERROR_OK;
1093 }
1094
1095 static int mips_m4k_examine(struct target *target)
1096 {
1097         int retval;
1098         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1099         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1100         uint32_t idcode = 0;
1101
1102         if (!target_was_examined(target)) {
1103                 retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
1104                 if (retval != ERROR_OK)
1105                         return retval;
1106                 ejtag_info->idcode = idcode;
1107
1108                 if (((idcode >> 1) & 0x7FF) == 0x29) {
1109                         /* we are using a pic32mx so select ejtag port
1110                          * as it is not selected by default */
1111                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1112                         LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1113                         mips_m4k->is_pic32mx = true;
1114                 }
1115         }
1116
1117         /* init rest of ejtag interface */
1118         retval = mips_ejtag_init(ejtag_info);
1119         if (retval != ERROR_OK)
1120                 return retval;
1121
1122         retval = mips32_examine(target);
1123         if (retval != ERROR_OK)
1124                 return retval;
1125
1126         return ERROR_OK;
1127 }
1128
1129 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
1130                 uint32_t count, const uint8_t *buffer)
1131 {
1132         struct mips32_common *mips32 = target_to_mips32(target);
1133         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1134         struct working_area *fast_data_area;
1135         int retval;
1136         int write_t = 1;
1137
1138         LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
1139
1140         /* check alignment */
1141         if (address & 0x3u)
1142                 return ERROR_TARGET_UNALIGNED_ACCESS;
1143
1144         if (mips32->fast_data_area == NULL) {
1145                 /* Get memory for block write handler
1146                  * we preserve this area between calls and gain a speed increase
1147                  * of about 3kb/sec when writing flash
1148                  * this will be released/nulled by the system when the target is resumed or reset */
1149                 retval = target_alloc_working_area(target,
1150                                 MIPS32_FASTDATA_HANDLER_SIZE,
1151                                 &mips32->fast_data_area);
1152                 if (retval != ERROR_OK) {
1153                         LOG_ERROR("No working area available");
1154                         return retval;
1155                 }
1156
1157                 /* reset fastadata state so the algo get reloaded */
1158                 ejtag_info->fast_access_save = -1;
1159         }
1160
1161         fast_data_area = mips32->fast_data_area;
1162
1163         if (address <= fast_data_area->address + fast_data_area->size &&
1164                         fast_data_area->address <= address + count) {
1165                 LOG_ERROR("fast_data (0x%8.8" PRIx32 ") is within write area "
1166                           "(0x%8.8" PRIx32 "-0x%8.8" PRIx32 ").",
1167                           fast_data_area->address, address, address + count);
1168                 LOG_ERROR("Change work-area-phys or load_image address!");
1169                 return ERROR_FAIL;
1170         }
1171
1172         /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1173         /* but byte array represents target endianness                      */
1174         uint32_t *t = NULL;
1175         t = malloc(count * sizeof(uint32_t));
1176         if (t == NULL) {
1177                 LOG_ERROR("Out of memory");
1178                 return ERROR_FAIL;
1179         }
1180
1181         target_buffer_get_u32_array(target, buffer, count, t);
1182
1183         retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1184                         count, t);
1185
1186         if (t != NULL)
1187                 free(t);
1188
1189         if (retval != ERROR_OK)
1190                 LOG_ERROR("Fastdata access Failed");
1191
1192         return retval;
1193 }
1194
1195 static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
1196                 struct mips_m4k_common *mips_m4k)
1197 {
1198         if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1199                 command_print(cmd_ctx, "target is not an MIPS_M4K");
1200                 return ERROR_TARGET_INVALID;
1201         }
1202         return ERROR_OK;
1203 }
1204
1205 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1206 {
1207         int retval;
1208         struct target *target = get_current_target(CMD_CTX);
1209         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1210         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1211
1212         retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
1213         if (retval != ERROR_OK)
1214                 return retval;
1215
1216         if (target->state != TARGET_HALTED) {
1217                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1218                 return ERROR_OK;
1219         }
1220
1221         /* two or more argument, access a single register/select (write if third argument is given) */
1222         if (CMD_ARGC < 2)
1223                 return ERROR_COMMAND_SYNTAX_ERROR;
1224         else {
1225                 uint32_t cp0_reg, cp0_sel;
1226                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1227                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1228
1229                 if (CMD_ARGC == 2) {
1230                         uint32_t value;
1231                         retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1232                         if (retval != ERROR_OK) {
1233                                 command_print(CMD_CTX,
1234                                                 "couldn't access reg %" PRIi32,
1235                                                 cp0_reg);
1236                                 return ERROR_OK;
1237                         }
1238                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1239                                         cp0_reg, cp0_sel, value);
1240
1241                 } else if (CMD_ARGC == 3) {
1242                         uint32_t value;
1243                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1244                         retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1245                         if (retval != ERROR_OK) {
1246                                 command_print(CMD_CTX,
1247                                                 "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
1248                                                 cp0_reg,  cp0_sel);
1249                                 return ERROR_OK;
1250                         }
1251                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1252                                         cp0_reg, cp0_sel, value);
1253                 }
1254         }
1255
1256         return ERROR_OK;
1257 }
1258
1259 COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
1260 {
1261         struct target *target = get_current_target(CMD_CTX);
1262         /* check target is an smp target */
1263         struct target_list *head;
1264         struct target *curr;
1265         head = target->head;
1266         target->smp = 0;
1267         if (head != (struct target_list *)NULL) {
1268                 while (head != (struct target_list *)NULL) {
1269                         curr = head->target;
1270                         curr->smp = 0;
1271                         head = head->next;
1272                 }
1273                 /*  fixes the target display to the debugger */
1274                 target->gdb_service->target = target;
1275         }
1276         return ERROR_OK;
1277 }
1278
1279 COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
1280 {
1281         struct target *target = get_current_target(CMD_CTX);
1282         struct target_list *head;
1283         struct target *curr;
1284         head = target->head;
1285         if (head != (struct target_list *)NULL) {
1286                 target->smp = 1;
1287                 while (head != (struct target_list *)NULL) {
1288                         curr = head->target;
1289                         curr->smp = 1;
1290                         head = head->next;
1291                 }
1292         }
1293         return ERROR_OK;
1294 }
1295
1296 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
1297 {
1298         struct target *target = get_current_target(CMD_CTX);
1299         int retval = ERROR_OK;
1300         struct target_list *head;
1301         head = target->head;
1302         if (head != (struct target_list *)NULL) {
1303                 if (CMD_ARGC == 1) {
1304                         int coreid = 0;
1305                         COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
1306                         if (ERROR_OK != retval)
1307                                 return retval;
1308                         target->gdb_service->core[1] = coreid;
1309
1310                 }
1311                 command_print(CMD_CTX, "gdb coreid  %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
1312                         , target->gdb_service->core[1]);
1313         }
1314         return ERROR_OK;
1315 }
1316
1317 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1318 {
1319         struct target *target = get_current_target(CMD_CTX);
1320         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1321         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1322
1323         if (CMD_ARGC == 1)
1324                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
1325         else if (CMD_ARGC > 1)
1326                         return ERROR_COMMAND_SYNTAX_ERROR;
1327
1328         command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
1329         if (ejtag_info->scan_delay >= 20000000) {
1330                 ejtag_info->mode = 0;
1331                 command_print(CMD_CTX, "running in legacy mode");
1332         } else {
1333                 ejtag_info->mode = 1;
1334                 command_print(CMD_CTX, "running in fast queued mode");
1335         }
1336
1337         return ERROR_OK;
1338 }
1339
1340 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1341         {
1342                 .name = "cp0",
1343                 .handler = mips_m4k_handle_cp0_command,
1344                 .mode = COMMAND_EXEC,
1345                 .usage = "regnum [value]",
1346                 .help = "display/modify cp0 register",
1347         },
1348         {
1349                 .name = "smp_off",
1350                 .handler = mips_m4k_handle_smp_off_command,
1351                 .mode = COMMAND_EXEC,
1352                 .help = "Stop smp handling",
1353                 .usage = "",},
1354
1355         {
1356                 .name = "smp_on",
1357                 .handler = mips_m4k_handle_smp_on_command,
1358                 .mode = COMMAND_EXEC,
1359                 .help = "Restart smp handling",
1360                 .usage = "",
1361         },
1362         {
1363                 .name = "smp_gdb",
1364                 .handler = mips_m4k_handle_smp_gdb_command,
1365                 .mode = COMMAND_EXEC,
1366                 .help = "display/fix current core played to gdb",
1367                 .usage = "",
1368         },
1369         {
1370                 .name = "scan_delay",
1371                 .handler = mips_m4k_handle_scan_delay_command,
1372                 .mode = COMMAND_ANY,
1373                 .help = "display/set scan delay in nano seconds",
1374                 .usage = "[value]",
1375         },
1376         COMMAND_REGISTRATION_DONE
1377 };
1378
1379 const struct command_registration mips_m4k_command_handlers[] = {
1380         {
1381                 .chain = mips32_command_handlers,
1382         },
1383         {
1384                 .name = "mips_m4k",
1385                 .mode = COMMAND_ANY,
1386                 .help = "mips_m4k command group",
1387                 .usage = "",
1388                 .chain = mips_m4k_exec_command_handlers,
1389         },
1390         COMMAND_REGISTRATION_DONE
1391 };
1392
1393 struct target_type mips_m4k_target = {
1394         .name = "mips_m4k",
1395
1396         .poll = mips_m4k_poll,
1397         .arch_state = mips32_arch_state,
1398
1399         .halt = mips_m4k_halt,
1400         .resume = mips_m4k_resume,
1401         .step = mips_m4k_step,
1402
1403         .assert_reset = mips_m4k_assert_reset,
1404         .deassert_reset = mips_m4k_deassert_reset,
1405
1406         .get_gdb_reg_list = mips32_get_gdb_reg_list,
1407
1408         .read_memory = mips_m4k_read_memory,
1409         .write_memory = mips_m4k_write_memory,
1410         .checksum_memory = mips32_checksum_memory,
1411         .blank_check_memory = mips32_blank_check_memory,
1412
1413         .run_algorithm = mips32_run_algorithm,
1414
1415         .add_breakpoint = mips_m4k_add_breakpoint,
1416         .remove_breakpoint = mips_m4k_remove_breakpoint,
1417         .add_watchpoint = mips_m4k_add_watchpoint,
1418         .remove_watchpoint = mips_m4k_remove_watchpoint,
1419
1420         .commands = mips_m4k_command_handlers,
1421         .target_create = mips_m4k_target_create,
1422         .init_target = mips_m4k_init_target,
1423         .examine = mips_m4k_examine,
1424 };