esirisc: support eSi-RISC targets

[openocd] / src / target / Makefile.am

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index d2aab0a5e3590d78170dc75c5f425f8b6b6c762e..05f174870015938ee355d0c94ccf83c1f2d20c87 100644 (file)
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -4,7 +4,9 @@ else
 OOCD_TRACE_FILES =
 endif
 
-%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
+%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
+       %D%/riscv/libriscv.la
+
 
 STARTUP_TCL_SRCS += %D%/startup.tcl
 
@@ -21,6 +23,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
        $(NDS32_SRC) \
        $(STM8_SRC) \
        $(INTEL_IA32_SRC) \
+       $(ESIRISC_SRC) \
        %D%/avrt.c \
        %D%/dsp563xx.c \
        %D%/dsp563xx_once.c \
@@ -39,6 +42,7 @@ TARGET_CORE_SRC = \
        %D%/target.c \
        %D%/target_request.c \
        %D%/testee.c \
+       %D%/semihosting_common.c \
        %D%/smp.c
 
 ARMV4_5_SRC = \
@@ -72,7 +76,8 @@ ARMV7_SRC = \
        %D%/cortex_m.c \
        %D%/armv7a.c \
        %D%/cortex_a.c \
-       %D%/ls1_sap.c
+       %D%/ls1_sap.c \
+       %D%/mem_ap.c
 
 ARMV8_SRC = \
        %D%/armv8_dpm.c \
@@ -88,6 +93,7 @@ ARM_DEBUG_SRC = \
        %D%/arm_simulator.c \
        %D%/arm_semihosting.c \
        %D%/arm_adi_v5.c \
+       %D%/arm_dap.c \
        %D%/armv7a_cache.c \
        %D%/armv7a_cache_l2x.c \
        %D%/adi_v5_jtag.c \
@@ -134,6 +140,10 @@ INTEL_IA32_SRC = \
        %D%/lakemont.c \
        %D%/x86_32_common.c
 
+ESIRISC_SRC = \
+       %D%/esirisc.c \
+       %D%/esirisc_jtag.c
+
 %C%_libtarget_la_SOURCES += \
        %D%/algorithm.h \
        %D%/arm.h \
@@ -209,9 +219,14 @@ INTEL_IA32_SRC = \
        %D%/nds32_v3.h \
        %D%/nds32_v3m.h \
        %D%/nds32_aice.h \
+       %D%/semihosting_common.h \
        %D%/stm8.h \
        %D%/lakemont.h \
        %D%/x86_32_common.h \
-       %D%/arm_cti.h
+       %D%/arm_cti.h \
+       %D%/esirisc.h \
+       %D%/esirisc_jtag.h \
+       %D%/esirisc_regs.h
 
 include %D%/openrisc/Makefile.am
+include %D%/riscv/Makefile.am