Add RISC-V support.

[openocd] / src / target / Makefile.am

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 206b28148c1829559950f159a47241fa57959f36..b1119e7df0e5fbe3bc2a6d9eb2ce6c7cb4ab2326 100644 (file)
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -4,7 +4,9 @@ else
 OOCD_TRACE_FILES =
 endif
 
-%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
+%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
+       %D%/riscv/libriscv.la
+
 
 STARTUP_TCL_SRCS += %D%/startup.tcl
 
@@ -39,6 +41,7 @@ TARGET_CORE_SRC = \
        %D%/target.c \
        %D%/target_request.c \
        %D%/testee.c \
+       %D%/semihosting_common.c \
        %D%/smp.c
 
 ARMV4_5_SRC = \
@@ -210,9 +213,11 @@ INTEL_IA32_SRC = \
        %D%/nds32_v3.h \
        %D%/nds32_v3m.h \
        %D%/nds32_aice.h \
+       %D%/semihosting_common.h \
        %D%/stm8.h \
        %D%/lakemont.h \
        %D%/x86_32_common.h \
        %D%/arm_cti.h
 
 include %D%/openrisc/Makefile.am
+include %D%/riscv/Makefile.am