* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
/**
#include <helper/jep106.h>
#include <helper/time_support.h>
#include <helper/list.h>
+#include <helper/jim-nvp.h>
/* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
{
- csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
- ap->csw_default;
+ csw |= ap->csw_default;
if (csw != ap->csw_value) {
/* LOG_DEBUG("DAP: Set CSW %x",csw); */
int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ ap->csw_value = 0;
return retval;
+ }
ap->csw_value = csw;
}
return ERROR_OK;
static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
{
- if (tar != ap->tar_value ||
- (ap->csw_value & CSW_ADDRINC_MASK)) {
+ if (!ap->tar_valid || tar != ap->tar_value) {
/* LOG_DEBUG("DAP: Set TAR %x",tar); */
int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ ap->tar_valid = false;
return retval;
+ }
ap->tar_value = tar;
+ ap->tar_valid = true;
+ }
+ return ERROR_OK;
+}
+
+static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
+{
+ int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
+ if (retval != ERROR_OK) {
+ ap->tar_valid = false;
+ return retval;
+ }
+
+ retval = dap_run(ap->dap);
+ if (retval != ERROR_OK) {
+ ap->tar_valid = false;
+ return retval;
}
+
+ ap->tar_value = *tar;
+ ap->tar_valid = true;
return ERROR_OK;
}
+static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
+{
+ switch (ap->csw_value & CSW_ADDRINC_MASK) {
+ case CSW_ADDRINC_SINGLE:
+ switch (ap->csw_value & CSW_SIZE_MASK) {
+ case CSW_8BIT:
+ return 1;
+ case CSW_16BIT:
+ return 2;
+ case CSW_32BIT:
+ return 4;
+ default:
+ return 0;
+ }
+ case CSW_ADDRINC_PACKED:
+ return 4;
+ }
+ return 0;
+}
+
+/* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
+ */
+static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
+{
+ if (!ap->tar_valid)
+ return;
+
+ uint32_t inc = mem_ap_get_tar_increment(ap);
+ if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
+ ap->tar_valid = false;
+ else
+ ap->tar_value += inc;
+}
+
/**
* Queue transactions setting up transfer parameters for the
* currently selected MEM-AP.
/* Use banked addressing (REG_BDx) to avoid some link traffic
* (updating TAR) when reading several consecutive addresses.
*/
- retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
+ retval = mem_ap_setup_transfer(ap,
+ CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
address & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
/* Use banked addressing (REG_BDx) to avoid some link traffic
* (updating TAR) when writing several consecutive addresses.
*/
- retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
+ retval = mem_ap_setup_transfer(ap,
+ CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
address & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
uint32_t addr_xor;
- int retval;
+ int retval = ERROR_OK;
/* TI BE-32 Quirks mode:
* Writes on big-endian TMS570 behave very strangely. Observed behavior:
if (ap->unaligned_access_bad && (address % size != 0))
return ERROR_TARGET_UNALIGNED_ACCESS;
- retval = mem_ap_setup_tar(ap, address ^ addr_xor);
- if (retval != ERROR_OK)
- return retval;
-
while (nbytes > 0) {
uint32_t this_size = size;
if (retval != ERROR_OK)
break;
+ retval = mem_ap_setup_tar(ap, address ^ addr_xor);
+ if (retval != ERROR_OK)
+ return retval;
+
/* How many source bytes each transfer will consume, and their location in the DRW,
* depends on the type of transfer and alignment. See ARM document IHI0031C. */
uint32_t outvalue = 0;
+ uint32_t drw_byte_idx = address;
if (dap->ti_be_32_quirks) {
switch (this_size) {
case 4:
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
break;
case 2:
- outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
break;
case 1:
- outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
break;
}
} else {
switch (this_size) {
case 4:
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
+ /* fallthrough */
case 2:
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
+ /* fallthrough */
case 1:
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
}
}
if (retval != ERROR_OK)
break;
- /* Rewrite TAR if it wrapped or we're xoring addresses */
- if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
- retval = mem_ap_setup_tar(ap, address ^ addr_xor);
- if (retval != ERROR_OK)
- break;
- }
+ mem_ap_update_tar_cache(ap);
+ if (addrinc)
+ address += this_size;
}
/* REVISIT: Might want to have a queued version of this function that does not run. */
if (retval != ERROR_OK) {
uint32_t tar;
- if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
- && dap_run(dap) == ERROR_OK)
+ if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
else
LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
uint32_t address = adr;
- int retval;
+ int retval = ERROR_OK;
/* TI BE-32 Quirks mode:
* Reads on big-endian TMS570 behave strangely differently than writes.
/* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
* over-allocation if packed transfers are going to be used, but determining the real need at
* this point would be messy. */
- uint32_t *read_buf = malloc(count * sizeof(uint32_t));
+ uint32_t *read_buf = calloc(count, sizeof(uint32_t));
+ /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
uint32_t *read_ptr = read_buf;
if (read_buf == NULL) {
LOG_ERROR("Failed to allocate read buffer");
return ERROR_FAIL;
}
- retval = mem_ap_setup_tar(ap, address);
- if (retval != ERROR_OK) {
- free(read_buf);
- return retval;
- }
-
/* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
* useful bytes it contains, and their location in the word, depends on the type of transfer
* and alignment. */
if (retval != ERROR_OK)
break;
+ retval = mem_ap_setup_tar(ap, address);
+ if (retval != ERROR_OK)
+ break;
+
retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
if (retval != ERROR_OK)
break;
nbytes -= this_size;
- address += this_size;
+ if (addrinc)
+ address += this_size;
- /* Rewrite TAR if it wrapped */
- if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
- retval = mem_ap_setup_tar(ap, address);
- if (retval != ERROR_OK)
- break;
- }
+ mem_ap_update_tar_cache(ap);
}
if (retval == ERROR_OK)
* at least give the caller what we have. */
if (retval != ERROR_OK) {
uint32_t tar;
- if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
- && dap_run(dap) == ERROR_OK) {
+ if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
+ /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
if (nbytes > tar - address)
nbytes = tar - address;
case 4:
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
+ /* fallthrough */
case 2:
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
+ /* fallthrough */
case 1:
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
}
case 4:
*buffer++ = *read_ptr >> 8 * (address++ & 3);
*buffer++ = *read_ptr >> 8 * (address++ & 3);
+ /* fallthrough */
case 2:
*buffer++ = *read_ptr >> 8 * (address++ & 3);
+ /* fallthrough */
case 1:
*buffer++ = *read_ptr >> 8 * (address++ & 3);
}
#define DAP_POWER_DOMAIN_TIMEOUT (10)
-/* FIXME don't import ... just initialize as
- * part of DAP transport setup
-*/
-extern const struct dap_ops jtag_dp_ops;
-
/*--------------------------------------------------------------------------*/
/**
- * Create a new DAP
+ * Invalidate cached DP select and cached TAR and CSW of all APs
*/
-struct adiv5_dap *dap_init(void)
+void dap_invalidate_cache(struct adiv5_dap *dap)
{
- struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
+ dap->select = DP_SELECT_INVALID;
+ dap->last_read = NULL;
+
int i;
- /* Set up with safe defaults */
for (i = 0; i <= 255; i++) {
- dap->ap[i].dap = dap;
- dap->ap[i].ap_num = i;
- /* memaccess_tck max is 255 */
- dap->ap[i].memaccess_tck = 255;
- /* Number of bits for tar autoincrement, impl. dep. at least 10 */
- dap->ap[i].tar_autoincr_block = (1<<10);
+ /* force csw and tar write on the next mem-ap access */
+ dap->ap[i].tar_valid = false;
+ dap->ap[i].csw_value = 0;
}
- INIT_LIST_HEAD(&dap->cmd_journal);
- return dap;
}
/**
{
int retval;
- LOG_DEBUG(" ");
- /* JTAG-DP or SWJ-DP, in JTAG mode
- * ... for SWD mode this is patched as part
- * of link switchover
- * FIXME: This should already be setup by the respective transport specific DAP creation.
- */
- if (!dap->ops)
- dap->ops = &jtag_dp_ops;
+ LOG_DEBUG("%s", adiv5_dap_name(dap));
- dap->select = DP_SELECT_INVALID;
- dap->last_read = NULL;
+ dap_invalidate_cache(dap);
- for (size_t i = 0; i < 10; i++) {
+ for (size_t i = 0; i < 30; i++) {
/* DP initialization */
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- continue;
+ retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
+ if (retval == ERROR_OK)
+ break;
+ }
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
- if (retval != ERROR_OK)
- continue;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
+ if (retval != ERROR_OK)
+ return retval;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- continue;
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
+ if (retval != ERROR_OK)
+ return retval;
- dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
- if (retval != ERROR_OK)
- continue;
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
+ if (retval != ERROR_OK)
+ return retval;
- /* Check that we have debug power domains activated */
- LOG_DEBUG("DAP: wait CDBGPWRUPACK");
- retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
- CDBGPWRUPACK, CDBGPWRUPACK,
- DAP_POWER_DOMAIN_TIMEOUT);
- if (retval != ERROR_OK)
- continue;
+ /* Check that we have debug power domains activated */
+ LOG_DEBUG("DAP: wait CDBGPWRUPACK");
+ retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
+ CDBGPWRUPACK, CDBGPWRUPACK,
+ DAP_POWER_DOMAIN_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+ if (!dap->ignore_syspwrupack) {
LOG_DEBUG("DAP: wait CSYSPWRUPACK");
retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
CSYSPWRUPACK, CSYSPWRUPACK,
DAP_POWER_DOMAIN_TIMEOUT);
if (retval != ERROR_OK)
- continue;
-
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- continue;
+ return retval;
+ }
- /* With debug power on we can activate OVERRUN checking */
- dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
- if (retval != ERROR_OK)
- continue;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- continue;
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
+ if (retval != ERROR_OK)
+ return retval;
- retval = dap_run(dap);
- if (retval != ERROR_OK)
- continue;
+ /* With debug power on we can activate OVERRUN checking */
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
+ if (retval != ERROR_OK)
+ return retval;
- break;
- }
+ retval = dap_run(dap);
+ if (retval != ERROR_OK)
+ return retval;
return retval;
}
int retval;
struct adiv5_dap *dap = ap->dap;
+ ap->tar_valid = false;
+ ap->csw_value = 0; /* force csw and tar write */
retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
if (retval != ERROR_OK)
return retval;
int ap_num;
/* Maximum AP number is 255 since the SELECT register is 8 bits */
- for (ap_num = 0; ap_num <= 255; ap_num++) {
+ for (ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
/* read the IDR register of the Access Port */
uint32_t id_val = 0;
const char *type;
const char *full;
} dap_partnums[] = {
- { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
- { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
- { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
- { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
- { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
- { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
- { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
- { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
- { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
- { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
- { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
- { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
- { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
- { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
- { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
- { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
- { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
- { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
- { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
- { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
- { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
- { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
- { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
- { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
- { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
- { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
- { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
- { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
- { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
- { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
- { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
- { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
- { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
- { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
- { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
- { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
- { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
- { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
- { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
- { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
- { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
- { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
- { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
- { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
- { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
- { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
- { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
- { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
- { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
- { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
- { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
- { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
- { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
- { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
- { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
- { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
- { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
- { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
- { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
- { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
- { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
- { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitoring Unit)", },
- { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
- { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
- { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
- { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
- { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
- { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
- { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
- { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
- { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
- { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
- { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
- { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
- { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
- { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
- { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
- { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
+ { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
+ { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
+ { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
+ { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
+ { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
+ { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
+ { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
+ { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
+ { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
+ { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
+ { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
+ { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
+ { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
+ { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
+ { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
+ { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
+ { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
+ { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
+ { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
+ { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
+ { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
+ { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
+ { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
+ { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
+ { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
+ { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
+ { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
+ { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
+ { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
+ { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
+ { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
+ { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
+ { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
+ { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
+ { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
+ { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
+ { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
+ { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
+ { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
+ { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
+ { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
+ { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
+ { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
+ { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
+ { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
+ { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
{ 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
+ { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
+ { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
+ { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
+ { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
+ { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
/* legacy comment: 0x113: what? */
- { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
- { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
- /* Atmel */
- { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
+ { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
+ { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
};
static int dap_rom_display(struct command_context *cmd_ctx,
int retval;
uint64_t pid;
uint32_t cid;
- char tabs[7] = "";
+ char tabs[16] = "";
if (depth > 16) {
command_print(cmd_ctx, "\tTables too deep");
return ERROR_OK;
}
-static int dap_info_command(struct command_context *cmd_ctx,
+int dap_info_command(struct command_context *cmd_ctx,
struct adiv5_ap *ap)
{
int retval;
return ERROR_OK;
}
+enum adiv5_cfg_param {
+ CFG_DAP,
+ CFG_AP_NUM
+};
+
+static const Jim_Nvp nvp_config_opts[] = {
+ { .name = "-dap", .value = CFG_DAP },
+ { .name = "-ap-num", .value = CFG_AP_NUM },
+ { .name = NULL, .value = -1 }
+};
+
+int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
+{
+ struct adiv5_private_config *pc;
+ int e;
+
+ pc = (struct adiv5_private_config *)target->private_config;
+ if (pc == NULL) {
+ pc = calloc(1, sizeof(struct adiv5_private_config));
+ pc->ap_num = DP_APSEL_INVALID;
+ target->private_config = pc;
+ }
+
+ target->has_dap = true;
+
+ if (goi->argc > 0) {
+ Jim_Nvp *n;
+
+ Jim_SetEmptyResult(goi->interp);
+
+ /* check first if topmost item is for us */
+ e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts,
+ goi->argv[0], &n);
+ if (e != JIM_OK)
+ return JIM_CONTINUE;
+
+ e = Jim_GetOpt_Obj(goi, NULL);
+ if (e != JIM_OK)
+ return e;
+
+ switch (n->value) {
+ case CFG_DAP:
+ if (goi->isconfigure) {
+ Jim_Obj *o_t;
+ struct adiv5_dap *dap;
+ e = Jim_GetOpt_Obj(goi, &o_t);
+ if (e != JIM_OK)
+ return e;
+ dap = dap_instance_by_jim_obj(goi->interp, o_t);
+ if (dap == NULL) {
+ Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
+ return JIM_ERR;
+ }
+ if (pc->dap != NULL && pc->dap != dap) {
+ Jim_SetResultString(goi->interp,
+ "DAP assignment cannot be changed after target was created!", -1);
+ return JIM_ERR;
+ }
+ if (target->tap_configured) {
+ Jim_SetResultString(goi->interp,
+ "-chain-position and -dap configparams are mutually exclusive!", -1);
+ return JIM_ERR;
+ }
+ pc->dap = dap;
+ target->tap = dap->tap;
+ target->dap_configured = true;
+ } else {
+ if (goi->argc != 0) {
+ Jim_WrongNumArgs(goi->interp,
+ goi->argc, goi->argv,
+ "NO PARAMS");
+ return JIM_ERR;
+ }
+
+ if (pc->dap == NULL) {
+ Jim_SetResultString(goi->interp, "DAP not configured", -1);
+ return JIM_ERR;
+ }
+ Jim_SetResultString(goi->interp, adiv5_dap_name(pc->dap), -1);
+ }
+ break;
+
+ case CFG_AP_NUM:
+ if (goi->isconfigure) {
+ jim_wide ap_num;
+ e = Jim_GetOpt_Wide(goi, &ap_num);
+ if (e != JIM_OK)
+ return e;
+ if (ap_num < 0 || ap_num > DP_APSEL_MAX) {
+ Jim_SetResultString(goi->interp, "Invalid AP number!", -1);
+ return JIM_ERR;
+ }
+ pc->ap_num = ap_num;
+ } else {
+ if (goi->argc != 0) {
+ Jim_WrongNumArgs(goi->interp,
+ goi->argc, goi->argv,
+ "NO PARAMS");
+ return JIM_ERR;
+ }
+
+ if (pc->ap_num == DP_APSEL_INVALID) {
+ Jim_SetResultString(goi->interp, "AP number not configured", -1);
+ return JIM_ERR;
+ }
+ Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, pc->ap_num));
+ }
+ break;
+ }
+ }
+
+ return JIM_OK;
+}
+
+int adiv5_verify_config(struct adiv5_private_config *pc)
+{
+ if (pc == NULL)
+ return ERROR_FAIL;
+
+ if (pc->dap == NULL)
+ return ERROR_FAIL;
+
+ return ERROR_OK;
+}
+
+
COMMAND_HANDLER(handle_dap_info_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
uint32_t apsel;
switch (CMD_ARGC) {
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
- if (apsel >= 256)
+ if (apsel > DP_APSEL_MAX)
return ERROR_COMMAND_SYNTAX_ERROR;
break;
default:
COMMAND_HANDLER(dap_baseaddr_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
uint32_t apsel, baseaddr;
int retval;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel >= 256)
+ if (apsel > DP_APSEL_MAX)
return ERROR_COMMAND_SYNTAX_ERROR;
break;
default:
COMMAND_HANDLER(dap_memaccess_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
uint32_t memaccess_tck;
switch (CMD_ARGC) {
COMMAND_HANDLER(dap_apsel_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
- uint32_t apsel, apid;
- int retval;
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
+ uint32_t apsel;
switch (CMD_ARGC) {
case 0:
- apsel = dap->apsel;
- break;
+ command_print(CMD_CTX, "%" PRIi32, dap->apsel);
+ return ERROR_OK;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel >= 256)
+ if (apsel > DP_APSEL_MAX)
return ERROR_COMMAND_SYNTAX_ERROR;
break;
default:
}
dap->apsel = apsel;
-
- retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
- if (retval != ERROR_OK)
- return retval;
- retval = dap_run(dap);
- if (retval != ERROR_OK)
- return retval;
-
- command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
- apsel, apid);
-
- return retval;
+ return ERROR_OK;
}
COMMAND_HANDLER(dap_apcsw_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
- uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
+ uint32_t apcsw = dap->ap[dap->apsel].csw_default;
+ uint32_t csw_val, csw_mask;
switch (CMD_ARGC) {
case 0:
- command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
- (dap->apsel), apcsw);
- break;
+ command_print(CMD_CTX, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
+ dap->apsel, apcsw);
+ return ERROR_OK;
case 1:
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
- /* AP address is in bits 31:24 of DP_SELECT */
- if (sprot > 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
- if (sprot)
- apcsw |= CSW_SPROT;
+ if (strcmp(CMD_ARGV[0], "default") == 0)
+ csw_val = CSW_DEFAULT;
else
- apcsw &= ~CSW_SPROT;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
+
+ if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
+ LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ apcsw = csw_val;
+ break;
+ case 2:
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
+ if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
+ LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_HANDLER(dap_apid_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
uint32_t apsel, apid;
int retval;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel >= 256)
+ if (apsel > DP_APSEL_MAX)
return ERROR_COMMAND_SYNTAX_ERROR;
break;
default:
return retval;
}
-COMMAND_HANDLER(dap_ti_be_32_quirks_command)
+COMMAND_HANDLER(dap_apreg_command)
+{
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
+ uint32_t apsel, reg, value;
+ struct adiv5_ap *ap;
+ int retval;
+
+ if (CMD_ARGC < 2 || CMD_ARGC > 3)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel > DP_APSEL_MAX)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ ap = dap_ap(dap, apsel);
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
+ if (reg >= 256 || (reg & 3))
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (CMD_ARGC == 3) {
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
+ switch (reg) {
+ case MEM_AP_REG_CSW:
+ ap->csw_value = 0; /* invalid, in case write fails */
+ retval = dap_queue_ap_write(ap, reg, value);
+ if (retval == ERROR_OK)
+ ap->csw_value = value;
+ break;
+ case MEM_AP_REG_TAR:
+ ap->tar_valid = false; /* invalid, force write */
+ retval = mem_ap_setup_tar(ap, value);
+ break;
+ default:
+ retval = dap_queue_ap_write(ap, reg, value);
+ break;
+ }
+ } else {
+ retval = dap_queue_ap_read(ap, reg, &value);
+ }
+ if (retval == ERROR_OK)
+ retval = dap_run(dap);
+
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (CMD_ARGC == 2)
+ command_print(CMD_CTX, "0x%08" PRIx32, value);
+
+ return retval;
+}
+
+COMMAND_HANDLER(dap_dpreg_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
+ uint32_t reg, value;
+ int retval;
+
+ if (CMD_ARGC < 1 || CMD_ARGC > 2)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg);
+ if (reg >= 256 || (reg & 3))
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (CMD_ARGC == 2) {
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
+ retval = dap_queue_dp_write(dap, reg, value);
+ } else {
+ retval = dap_queue_dp_read(dap, reg, &value);
+ }
+ if (retval == ERROR_OK)
+ retval = dap_run(dap);
+
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (CMD_ARGC == 1)
+ command_print(CMD_CTX, "0x%08" PRIx32, value);
+
+ return retval;
+}
+
+COMMAND_HANDLER(dap_ti_be_32_quirks_command)
+{
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
uint32_t enable = dap->ti_be_32_quirks;
switch (CMD_ARGC) {
return 0;
}
-static const struct command_registration dap_commands[] = {
+const struct command_registration dap_instance_commands[] = {
{
.name = "info",
.handler = handle_dap_info_command,
{
.name = "apsel",
.handler = dap_apsel_command,
- .mode = COMMAND_EXEC,
+ .mode = COMMAND_ANY,
.help = "Set the currently selected AP (default 0) "
"and display the result",
.usage = "[ap_num]",
{
.name = "apcsw",
.handler = dap_apcsw_command,
- .mode = COMMAND_EXEC,
- .help = "Set csw access bit ",
- .usage = "[sprot]",
+ .mode = COMMAND_ANY,
+ .help = "Set CSW default bits",
+ .usage = "[value [mask]]",
},
{
"(default currently selected AP)",
.usage = "[ap_num]",
},
+ {
+ .name = "apreg",
+ .handler = dap_apreg_command,
+ .mode = COMMAND_EXEC,
+ .help = "read/write a register from AP "
+ "(reg is byte address of a word register, like 0 4 8...)",
+ .usage = "ap_num reg [value]",
+ },
+ {
+ .name = "dpreg",
+ .handler = dap_dpreg_command,
+ .mode = COMMAND_EXEC,
+ .help = "read/write a register from DP "
+ "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
+ .usage = "reg [value]",
+ },
{
.name = "baseaddr",
.handler = dap_baseaddr_command,
},
COMMAND_REGISTRATION_DONE
};
-
-const struct command_registration dap_command_handlers[] = {
- {
- .name = "dap",
- .mode = COMMAND_EXEC,
- .help = "DAP command group",
- .usage = "",
- .chain = dap_commands,
- },
- COMMAND_REGISTRATION_DONE
-};
projects / openocd / blobdiff