#include "target_type.h"
#include "arm_opcodes.h"
#include "arm_semihosting.h"
-#include "jtag/swd.h"
+#include "transport/transport.h"
#include <helper/time_support.h>
static int cortex_a_poll(struct target *target);
/* lock memory-mapped access to debug registers to prevent
* software interference */
- retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ retval = mem_ap_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_LOCKACCESS, 0);
if (retval != ERROR_OK)
return retval;
/* Disable cacheline fills and force cache write-through in debug state */
- retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ retval = mem_ap_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCCR, 0);
if (retval != ERROR_OK)
return retval;
/* Disable TLB lookup and refill/eviction in debug state */
- retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ retval = mem_ap_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSMCR, 0);
if (retval != ERROR_OK)
return retval;
+ retval = dap_run(armv7a->debug_ap->dap);
+ if (retval != ERROR_OK)
+ return retval;
+
/* Enabling of instruction execution in debug mode is done in debug_entry code */
/* Resync breakpoint registers */
TARGET_EVENT_DEBUG_HALTED);
}
}
- } else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED)
+ } else
target->state = TARGET_RUNNING;
- else {
- LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
- target->state = TARGET_UNKNOWN;
- }
return retval;
}
case ARM_STATE_JAZELLE:
LOG_ERROR("How do I resume into Jazelle state??");
return ERROR_FAIL;
+ case ARM_STATE_AARCH64:
+ LOG_ERROR("Shoudn't be in AARCH64 state");
+ return ERROR_FAIL;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
buf_set_u32(arm->pc->value, 0, 32, resume_pc);
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg);
cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
+ if (!armv7a->is_armv7r)
+ armv7a_read_ttbcr(target);
+
if (armv7a->armv7a_mmu.armv7a_cache.info == -1)
armv7a_identify_cache(target);
brp_list[brp_i].value);
} else if (breakpoint->type == BKPT_SOFT) {
uint8_t code[4];
+ /* length == 2: Thumb breakpoint */
if (breakpoint->length == 2)
buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
else
+ /* length == 3: Thumb-2 breakpoint, actual encoding is
+ * a regular Thumb BKPT instruction but we replace a
+ * 32bit Thumb-2 instruction, so fix-up the breakpoint
+ * length
+ */
+ if (breakpoint->length == 3) {
+ buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
+ breakpoint->length = 4;
+ } else
+ /* length == 4, normal ARM breakpoint */
buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
+
retval = target_read_memory(target,
breakpoint->address & 0xFFFFFFFE,
breakpoint->length, 1,
int retval = ERROR_OK;
uint32_t didr, cpuid, dbg_osreg;
- retval = dap_dp_init(swjdp);
- if (retval != ERROR_OK) {
- LOG_ERROR("Could not initialize the debug port");
- return retval;
- }
-
/* Search for the APB-AP - it is needed for access to debug registers */
retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
if (retval != ERROR_OK) {
}
static int cortex_a_init_arch_info(struct target *target,
- struct cortex_a_common *cortex_a, struct jtag_tap *tap)
+ struct cortex_a_common *cortex_a, struct adiv5_dap *dap)
{
struct armv7a_common *armv7a = &cortex_a->armv7a_common;
/* Setup struct cortex_a_common */
cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
-
- /* tap has no dap initialized */
- if (!tap->dap) {
- tap->dap = dap_init();
-
- /* Leave (only) generic DAP stuff for debugport_init() */
- tap->dap->tap = tap;
- }
-
- armv7a->arm.dap = tap->dap;
+ armv7a->arm.dap = dap;
cortex_a->fast_reg_read = 0;
static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
{
struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
+ cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
+ struct adiv5_private_config *pc;
+
+ if (target->private_config == NULL)
+ return ERROR_FAIL;
+
+ pc = (struct adiv5_private_config *)target->private_config;
cortex_a->armv7a_common.is_armv7r = false;
- return cortex_a_init_arch_info(target, cortex_a, target->tap);
+ cortex_a->armv7a_common.arm.arm_vfp_version = ARM_VFP_V3;
+
+ return cortex_a_init_arch_info(target, cortex_a, pc->dap);
}
static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
{
struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
+ cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
+ struct adiv5_private_config *pc;
+
+ pc = (struct adiv5_private_config *)target->private_config;
+ if (adiv5_verify_config(pc) != ERROR_OK)
+ return ERROR_FAIL;
cortex_a->armv7a_common.is_armv7r = true;
- return cortex_a_init_arch_info(target, cortex_a, target->tap);
+ return cortex_a_init_arch_info(target, cortex_a, pc->dap);
}
static void cortex_a_deinit_target(struct target *target)
free(cortex_a->brp_list);
free(dpm->dbp);
free(dpm->dwp);
+ free(target->private_config);
free(cortex_a);
}
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
uint8_t apsel = swjdp->apsel;
+ int mmu_enabled = 0;
+
+ /*
+ * If the MMU was not enabled at debug entry, there is no
+ * way of knowing if there was ever a valid configuration
+ * for it and thus it's not safe to enable it. In this case,
+ * just return the virtual address as physical.
+ */
+ cortex_a_mmu(target, &mmu_enabled);
+ if (!mmu_enabled) {
+ *phys = virt;
+ return ERROR_OK;
+ }
+
if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap->ap_num)) {
uint32_t ret;
retval = armv7a_mmu_translate_va(target,
{
.name = "dacrfixup",
.handler = handle_cortex_a_dacrfixup_command,
- .mode = COMMAND_EXEC,
+ .mode = COMMAND_ANY,
.help = "set domain access control (DACR) to all-manager "
"on memory access",
.usage = "['on'|'off']",
.commands = cortex_a_command_handlers,
.target_create = cortex_a_target_create,
+ .target_jim_configure = adiv5_jim_configure,
.init_target = cortex_a_init_target,
.examine = cortex_a_examine,
.deinit_target = cortex_a_deinit_target,
};
static const struct command_registration cortex_r4_exec_command_handlers[] = {
- {
- .name = "cache_info",
- .handler = cortex_a_handle_cache_info_command,
- .mode = COMMAND_EXEC,
- .help = "display information about target caches",
- .usage = "",
- },
{
.name = "dbginit",
.handler = cortex_a_handle_dbginit_command,
{
.chain = arm_command_handlers,
},
- {
- .chain = armv7a_command_handlers,
- },
{
.name = "cortex_r4",
.mode = COMMAND_ANY,
.commands = cortex_r4_command_handlers,
.target_create = cortex_r4_target_create,
+ .target_jim_configure = adiv5_jim_configure,
.init_target = cortex_a_init_target,
.examine = cortex_a_examine,
.deinit_target = cortex_a_deinit_target,
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