target/cortex_m: make a variable local

[openocd] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index a356350a2837f218435650e32b005d1fedf3f965..03dc515729bacad85fae0177f06acf0e9a8f8019 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -51,11 +51,6 @@
  * any longer.
  */
 
-/**
- * Returns the type of a break point required by address location
- */
-#define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
-
 /* forward declarations */
 static int cortex_m_store_core_reg_u32(struct target *target,
                uint32_t num, uint32_t value);
@@ -868,7 +863,7 @@ static int cortex_m_step(struct target *target, int current,
                                if (breakpoint)
                                        retval = cortex_m_set_breakpoint(target, breakpoint);
                                else
-                                       retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
+                                       retval = breakpoint_add(target, pc_value, 2, BKPT_HARD);
                                bool tmp_bp_set = (retval == ERROR_OK);
 
                                /* No more breakpoints left, just do a step */
@@ -1131,9 +1126,6 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
                return ERROR_OK;
        }
 
-       if (cortex_m->auto_bp_type)
-               breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
-
        if (breakpoint->type == BKPT_HARD) {
                uint32_t fpcr_value;
                while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
@@ -1145,6 +1137,10 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
                breakpoint->set = fp_num + 1;
                fpcr_value = breakpoint->address | 1;
                if (cortex_m->fp_rev == 0) {
+                       if (breakpoint->address > 0x1FFFFFFF) {
+                               LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
+                               return ERROR_FAIL;
+                       }
                        uint32_t hilo;
                        hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
                        fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
@@ -1253,21 +1249,6 @@ int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
 
-       if (cortex_m->auto_bp_type)
-               breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
-
-       if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
-               if (breakpoint->type == BKPT_HARD) {
-                       LOG_INFO("flash patch comparator requested outside code memory region");
-                       return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-               }
-
-               if (breakpoint->type == BKPT_SOFT) {
-                       LOG_INFO("soft breakpoint requested in code (flash) memory region");
-                       return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-               }
-       }
-
        if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
                LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
@@ -1299,9 +1280,6 @@ int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpo
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       if (cortex_m->auto_bp_type)
-               breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
-
        if (breakpoint->set)
                cortex_m_unset_breakpoint(target, breakpoint);
 
@@ -1832,11 +1810,11 @@ static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
 
 struct dwt_reg {
        uint32_t addr;
-       char *name;
+       const char *name;
        unsigned size;
 };
 
-static struct dwt_reg dwt_base_regs[] = {
+static const struct dwt_reg dwt_base_regs[] = {
        { DWT_CTRL, "dwt_ctrl", 32, },
        /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
         * increments while the core is asleep.
@@ -1845,7 +1823,7 @@ static struct dwt_reg dwt_base_regs[] = {
        /* plus some 8 bit counters, useful for profiling with TPIU */
 };
 
-static struct dwt_reg dwt_comp[] = {
+static const struct dwt_reg dwt_comp[] = {
 #define DWT_COMPARATOR(i) \
                { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
                { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
@@ -1874,7 +1852,7 @@ static const struct reg_arch_type dwt_reg_type = {
        .set = cortex_m_dwt_set_reg,
 };
 
-static void cortex_m_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
+static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
 {
        struct dwt_reg_state *state;
 
@@ -2102,7 +2080,7 @@ int cortex_m_examine(struct target *target)
                if (retval != ERROR_OK)
                        return retval;
 
-               if (armv7m->trace_config.config_type != DISABLED) {
+               if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
                        armv7m_trace_tpiu_config(target);
                        armv7m_trace_itm_config(target);
                }
@@ -2111,7 +2089,6 @@ int cortex_m_examine(struct target *target)
 
                /* Setup FPB */
                target_read_u32(target, FP_CTRL, &fpcr);
-               cortex_m->auto_bp_type = 1;
                /* bits [14:12] and [7:4] */
                cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
                cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
@@ -2297,20 +2274,6 @@ static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
  * cortexm3_target structure, which is only used with CM3 targets.
  */
 
-static const struct {
-       char name[10];
-       unsigned mask;
-} vec_ids[] = {
-       { "hard_err",   VC_HARDERR, },
-       { "int_err",    VC_INTERR, },
-       { "bus_err",    VC_BUSERR, },
-       { "state_err",  VC_STATERR, },
-       { "chk_err",    VC_CHKERR, },
-       { "nocp_err",   VC_NOCPERR, },
-       { "mm_err",     VC_MMERR, },
-       { "reset",      VC_CORERESET, },
-};
-
 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
 {
        struct target *target = get_current_target(CMD_CTX);
@@ -2319,6 +2282,20 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
        uint32_t demcr = 0;
        int retval;
 
+       static const struct {
+               char name[10];
+               unsigned mask;
+       } vec_ids[] = {
+               { "hard_err",   VC_HARDERR, },
+               { "int_err",    VC_INTERR, },
+               { "bus_err",    VC_BUSERR, },
+               { "state_err",  VC_STATERR, },
+               { "chk_err",    VC_CHKERR, },
+               { "nocp_err",   VC_NOCPERR, },
+               { "mm_err",     VC_MMERR, },
+               { "reset",      VC_CORERESET, },
+       };
+
        retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
        if (retval != ERROR_OK)
                return retval;