* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
-#ifndef CORTEX_M3_H
-#define CORTEX_M3_H
+#ifndef OPENOCD_TARGET_CORTEX_M_H
+#define OPENOCD_TARGET_CORTEX_M_H
#include "armv7m.h"
-#define CORTEX_M3_COMMON_MAGIC 0x1A451A45
+#define CORTEX_M_COMMON_MAGIC 0x1A451A45
#define SYSTEM_CONTROL_BASE 0x400FE000
+#define ITM_TER0 0xE0000E00
+#define ITM_TPR 0xE0000E40
+#define ITM_TCR 0xE0000E80
+#define ITM_LAR 0xE0000FB0
+#define ITM_LAR_KEY 0xC5ACCE55
+
#define CPUID 0xE000ED00
/* Debug Control Block */
#define DCB_DHCSR 0xE000EDF0
#define FPU_FPCAR 0xE000EF38
#define FPU_FPDSCR 0xE000EF3C
+#define TPIU_SSPSR 0xE0040000
+#define TPIU_CSPSR 0xE0040004
+#define TPIU_ACPR 0xE0040010
+#define TPIU_SPPR 0xE00400F0
+#define TPIU_FFSR 0xE0040300
+#define TPIU_FFCR 0xE0040304
+#define TPIU_FSCR 0xE0040308
+
/* DCB_DHCSR bit and field definitions */
#define DBGKEY (0xA05F << 16)
#define C_DEBUGEN (1 << 0)
#define S_RESET_ST (1 << 25)
/* DCB_DEMCR bit and field definitions */
-#define TRCENA (1 << 24)
-#define VC_HARDERR (1 << 10)
-#define VC_INTERR (1 << 9)
-#define VC_BUSERR (1 << 8)
-#define VC_STATERR (1 << 7)
-#define VC_CHKERR (1 << 6)
-#define VC_NOCPERR (1 << 5)
-#define VC_MMERR (1 << 4)
-#define VC_CORERESET (1 << 0)
+#define TRCENA (1 << 24)
+#define VC_HARDERR (1 << 10)
+#define VC_INTERR (1 << 9)
+#define VC_BUSERR (1 << 8)
+#define VC_STATERR (1 << 7)
+#define VC_CHKERR (1 << 6)
+#define VC_NOCPERR (1 << 5)
+#define VC_MMERR (1 << 4)
+#define VC_CORERESET (1 << 0)
#define NVIC_ICTR 0xE000E004
#define NVIC_ISE0 0xE000E100
#define FPCR_REPLACE_BKPT_HIGH (2 << 30)
#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
-struct cortex_m3_fp_comparator {
+struct cortex_m_fp_comparator {
int used;
int type;
uint32_t fpcr_value;
uint32_t fpcr_address;
};
-struct cortex_m3_dwt_comparator {
+struct cortex_m_dwt_comparator {
int used;
uint32_t comp;
uint32_t mask;
uint32_t dwt_comparator_address;
};
-enum cortex_m3_soft_reset_config {
- CORTEX_M3_RESET_SYSRESETREQ,
- CORTEX_M3_RESET_VECTRESET,
+enum cortex_m_soft_reset_config {
+ CORTEX_M_RESET_SYSRESETREQ,
+ CORTEX_M_RESET_VECTRESET,
};
-enum cortex_m3_isrmasking_mode {
- CORTEX_M3_ISRMASK_AUTO,
- CORTEX_M3_ISRMASK_OFF,
- CORTEX_M3_ISRMASK_ON,
+enum cortex_m_isrmasking_mode {
+ CORTEX_M_ISRMASK_AUTO,
+ CORTEX_M_ISRMASK_OFF,
+ CORTEX_M_ISRMASK_ON,
};
-struct cortex_m3_common {
+struct cortex_m_common {
int common_magic;
- struct arm_jtag jtag_info;
/* Context information */
uint32_t dcb_dhcsr;
int fp_num_lit;
int fp_num_code;
int fp_code_available;
+ int fp_rev;
int fpb_enabled;
int auto_bp_type;
- struct cortex_m3_fp_comparator *fp_comparator_list;
+ struct cortex_m_fp_comparator *fp_comparator_list;
/* Data Watchpoint and Trace (DWT) */
int dwt_num_comp;
int dwt_comp_available;
- struct cortex_m3_dwt_comparator *dwt_comparator_list;
+ struct cortex_m_dwt_comparator *dwt_comparator_list;
struct reg_cache *dwt_cache;
- enum cortex_m3_soft_reset_config soft_reset_config;
+ enum cortex_m_soft_reset_config soft_reset_config;
- enum cortex_m3_isrmasking_mode isrmasking_mode;
+ enum cortex_m_isrmasking_mode isrmasking_mode;
struct armv7m_common armv7m;
+
+ int apsel;
};
-static inline struct cortex_m3_common *
-target_to_cm3(struct target *target)
+static inline struct cortex_m_common *
+target_to_cm(struct target *target)
{
return container_of(target->arch_info,
- struct cortex_m3_common, armv7m);
+ struct cortex_m_common, armv7m);
}
-int cortex_m3_examine(struct target *target);
-int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
-int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
-int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
-int cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
-int cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint);
-int cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint);
-int cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
-int cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
-void cortex_m3_enable_watchpoints(struct target *target);
-void cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target);
-
-#endif /* CORTEX_M3_H */
+int cortex_m_examine(struct target *target);
+int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
+int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
+int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
+int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
+int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint);
+int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint);
+int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
+int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
+void cortex_m_enable_breakpoints(struct target *target);
+void cortex_m_enable_watchpoints(struct target *target);
+void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target);
+void cortex_m_deinit_target(struct target *target);
+
+#endif /* OPENOCD_TARGET_CORTEX_M_H */
projects / openocd / blobdiff