target: restructure dap support

[openocd] / tcl / target / lpc4370.cfg

diff --git a/tcl/target/lpc4370.cfg b/tcl/target/lpc4370.cfg
index 67bff0adcacd47722d35b6de030454ac3e42b9b5..1374ef275f6f58fb591828a2a9780f06efb1d9e0 100644 (file)
--- a/tcl/target/lpc4370.cfg
+++ b/tcl/target/lpc4370.cfg
@@ -47,8 +47,8 @@ if { [info exists M0_JTAG_TAPID] } {
 
 swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
                                -expected-id $_M4_TAPID
-
-target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
 
 # LPC4370 has 96+32 KB contiguous SRAM
 if { [info exists WORKAREASIZE] } {
@@ -65,8 +65,10 @@ if { [using_jtag] } {
        jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
                                        -expected-id $_M0_JTAG_TAPID
 
-       target create $_CHIPNAME.m0app cortex_m -chain-position $_CHIPNAME.m0app
-       target create $_CHIPNAME.m0sub cortex_m -chain-position $_CHIPNAME.m0sub
+       dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
+       dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
+       target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
+       target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
 
        # 32+8+32 KB SRAM
        $_CHIPNAME.m0app configure -work-area-phys 0x10080000 \