Add config files for STM32F7-DISCO and STM327[4|5]6G-EVAL.

Change-Id: I0803939f0ab1de97e544ca0f1257daac11fb50de
Signed-off-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com>
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2754
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>

diff --git a/tcl/board/stm327x6g_eval.cfg b/tcl/board/stm327x6g_eval.cfg
new file mode 100644 (file)
index 0000000..a5e5896
--- /dev/null
+++ b/tcl/board/stm327x6g_eval.cfg
@@ -0,0 +1,10 @@
+# STM327[4|5]6G-EVAL: This is for the STM32F7 eval boards.
+# STM32746G-EVAL
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261639
+# STM32756G-EVAL
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261640
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+source [find target/stm32f7x.cfg]

diff --git a/tcl/board/stm32f7discovery.cfg b/tcl/board/stm32f7discovery.cfg
new file mode 100755 (executable)
index 0000000..085340f
--- /dev/null
+++ b/tcl/board/stm32f7discovery.cfg
@@ -0,0 +1,12 @@
+# This is an STM32F7 discovery board with a single STM32F756NGH6 chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261641
+
+# This is for using the onboard STLINK/V2-1
+source [find interface/stlink-v2-1.cfg]
+
+transport select hla_swd
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+source [find target/stm32f7x.cfg]

diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
new file mode 100755 (executable)
index 0000000..833ef94
--- /dev/null
+++ b/tcl/target/stm32f7x.cfg
@@ -0,0 +1,92 @@
+# script for stm32f7x family
+
+#
+# stm32f7 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f7x
+}
+
+   set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 128kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x20000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0385
+      # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
+      set _CPUTAPID 0x5ba00477
+   } {
+      set _CPUTAPID 0x5ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0385
+  # Section 40.6.1
+  # STM32F75xxG
+  set _BSTAPID1 0x06449071
+}
+
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
+# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
+adapter_khz 2000
+
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+# use hardware reset, connect under reset
+reset_config srst_only srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+       mmw 0xE0042004 0x00000007 0
+
+       # Stop watchdog counters during halt
+       # DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
+       mww 0xE0042008 0x00001800
+}
+
+$_TARGETNAME configure -event trace-config {
+       # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+       # change this value accordingly to configure trace pins
+       # assignment
+       mmw 0xE0042004 0x00000020 0
+}