]> git.sur5r.net Git - openocd/commitdiff
cortex_a: fix reset for SWD transport
authorMatthias Welwarsky <matthias.welwarsky@sysgo.com>
Thu, 10 Nov 2016 19:33:02 +0000 (20:33 +0100)
committerPaul Fertser <fercerpav@gmail.com>
Thu, 8 Dec 2016 13:03:49 +0000 (13:03 +0000)
Change b0698501b0e789091e9f9f1427b32af304888769 fixed
reset for i.MX6 and TI Sitara SoCs but broke reset for
cortex-a targets that use SWD. This patch is a work-
around that forces asserting SRST when SWD is used.

Change-Id: I7e39f2a469b9b4b2b74ad48ba49f2eeb58528921
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3641
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
src/target/cortex_a.c

index ed2f6137705fd5e96925d05993f29876ed040b16..d0eac751f6df3acbb0428126d3e3e7509586917e 100644 (file)
@@ -54,6 +54,7 @@
 #include "target_type.h"
 #include "arm_opcodes.h"
 #include "arm_semihosting.h"
+#include "jtag/swd.h"
 #include <helper/time_support.h>
 
 static int cortex_a_poll(struct target *target);
@@ -1867,9 +1868,15 @@ static int cortex_a_assert_reset(struct target *target)
                /* REVISIT handle "pulls" cases, if there's
                 * hardware that needs them to work.
                 */
-               if (target->reset_halt)
-                       if (jtag_get_reset_config() & RESET_SRST_NO_GATING)
-                               jtag_add_reset(0, 1);
+
+               /*
+                * FIXME: fix reset when transport is SWD. This is a temporary
+                * work-around for release v0.10 that is not intended to stay!
+                */
+               if (transport_is_swd() ||
+                               (target->reset_halt && (jtag_get_reset_config() & RESET_SRST_NO_GATING)))
+                       jtag_add_reset(0, 1);
+
        } else {
                LOG_ERROR("%s: how to reset?", target_name(target));
                return ERROR_FAIL;