]> git.sur5r.net Git - openocd/commitdiff
projects / openocd / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: c591f10)
at91sam4: Add missing SAM4S family CHIPIDs and remove FWS=6.
authorOwen Kirby <oskirby@gmail.com>
Wed, 26 Oct 2016 03:49:04 +0000 (20:49 -0700)
committerPaul Fertser <fercerpav@gmail.com>
Thu, 8 Dec 2016 12:31:42 +0000 (12:31 +0000)
Add missing CHIPID values for all SAM4S parts listed in revision K of
Atmel-11100-32-bit Cortex-M4-Microcontroller-SAM4S_Datasheet.pdf. I have
also removed the FWS=6 workaround, as this appears to be a copy-paste error
from the SAM3X family.

Change-Id: I1ce1d82911f39d6fcb8f04034f5c9c9bf2818466
Signed-off-by: Owen Kirby <oskirby@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3837
Tested-by: jenkins
src/flash/nor/at91sam4.c patch | blob | history

diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index 51198af00b3645efc9ddd6f0a2a860a8907f2f6b..94d5bfda4e663e0b24259b92163fd224d2ae5733 100644 (file)
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -666,7 +666,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                        .bank_number = 0,
                        .base_address = FLASH_BANK_BASE_S,
                        .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .flash_wait_states = 5,
                        .present = 1,
                        .size_bytes =  1024 * 1024,
                        .nsectors   =  128,
@@ -682,7 +682,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                  },
                },
        },
-       /*atsam4s16b - LQFP64/QFN64*/
+       /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
        {
                .chipid_cidr    = 0x289C0CE0,
                .name           = "at91sam4s16b",
@@ -699,7 +699,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                        .bank_number = 0,
                        .base_address = FLASH_BANK_BASE_S,
                        .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .flash_wait_states = 5,
                        .present = 1,
                        .size_bytes =  1024 * 1024,
                        .nsectors   =  128,
@@ -732,7 +732,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                        .bank_number = 0,
                        .base_address = FLASH_BANK_BASE_S,
                        .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .flash_wait_states = 5,
                        .present = 1,
                        .size_bytes =  1024 * 1024,
                        .nsectors   =  128,
@@ -765,7 +765,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                        .bank_number = 0,
                        .base_address = FLASH_BANK_BASE_S,
                        .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .flash_wait_states = 5,
                        .present = 1,
                        .size_bytes =  1024 * 1024,
                        .nsectors   =  128,
@@ -798,7 +798,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                        .bank_number = 0,
                        .base_address = FLASH_BANK_BASE_S,
                        .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .flash_wait_states = 5,
                        .present = 1,
                        .size_bytes =  512 * 1024,
                        .nsectors   =  64,
@@ -814,7 +814,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                  },
                },
        },
-       /*atsam4s8b - LQFP64/BGA64*/
+       /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
        {
                .chipid_cidr    = 0x289C0AE0,
                .name           = "at91sam4s8b",
@@ -831,7 +831,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                        .bank_number = 0,
                        .base_address = FLASH_BANK_BASE_S,
                        .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .flash_wait_states = 5,
                        .present = 1,
                        .size_bytes =  512 * 1024,
                        .nsectors   =  64,
@@ -864,7 +864,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                        .bank_number = 0,
                        .base_address = FLASH_BANK_BASE_S,
                        .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .flash_wait_states = 5,
                        .present = 1,
                        .size_bytes =  512 * 1024,
                        .nsectors   =  64,
@@ -881,7 +881,75 @@ static const struct sam4_chip_details all_sam4_details[] = {
                },
        },
 
-       /*atsam4s4a - LQFP48/BGA48*/
+       /*atsam4s4c - LQFP100/BGA100*/
+       {
+               .chipid_cidr    = 0x28ab09e0,
+               .name           = "at91sam4s4c",
+               .total_flash_size     = 256 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 5,
+                       .present = 1,
+                       .size_bytes =  256 * 1024,
+                       .nsectors   =  32,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+
+       /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
+       {
+               .chipid_cidr    = 0x289b09e0,
+               .name           = "at91sam4s4b",
+               .total_flash_size     = 256 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 5,
+                       .present = 1,
+                       .size_bytes =  256 * 1024,
+                       .nsectors   =  32,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+
+       /*atsam4s4a - LQFP48/QFN48*/
        {
                .chipid_cidr    = 0x288b09e0,
                .name           = "at91sam4s4a",
@@ -898,7 +966,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                        .bank_number = 0,
                        .base_address = FLASH_BANK_BASE_S,
                        .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .flash_wait_states = 5,
                        .present = 1,
                        .size_bytes =  256 * 1024,
                        .nsectors   =  32,
@@ -915,7 +983,109 @@ static const struct sam4_chip_details all_sam4_details[] = {
                },
        },
 
-       /*at91sam4sd32c*/
+       /*atsam4s2c - LQFP100/BGA100*/
+       {
+               .chipid_cidr    = 0x28ab07e0,
+               .name           = "at91sam4s2c",
+               .total_flash_size     = 128 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 5,
+                       .present = 1,
+                       .size_bytes =  128 * 1024,
+                       .nsectors   =  16,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+
+       /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
+       {
+               .chipid_cidr    = 0x289b07e0,
+               .name           = "at91sam4s2b",
+               .total_flash_size     = 128 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 5,
+                       .present = 1,
+                       .size_bytes =  128 * 1024,
+                       .nsectors   =  16,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+
+       /*atsam4s2a - LQFP48/QFN48*/
+       {
+               .chipid_cidr    = 0x288b07e0,
+               .name           = "at91sam4s2a",
+               .total_flash_size     = 128 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 5,
+                       .present = 1,
+                       .size_bytes =  128 * 1024,
+                       .nsectors   =  16,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+
+       /*at91sam4sd32c  - LQFP100/BGA100*/
        {
                .chipid_cidr    = 0x29a70ee0,
                .name           = "at91sam4sd32c",
@@ -933,7 +1103,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                                .bank_number = 0,
                                .base_address = FLASH_BANK0_BASE_SD,
                                .controller_address = 0x400e0a00,
-                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .flash_wait_states = 5,
                                .present = 1,
                                .size_bytes =  1024 * 1024,
                                .nsectors   =  128,
@@ -949,7 +1119,51 @@ static const struct sam4_chip_details all_sam4_details[] = {
                                .bank_number = 1,
                                .base_address = FLASH_BANK1_BASE_2048K_SD,
                                .controller_address = 0x400e0c00,
-                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .flash_wait_states = 5,
+                               .present = 1,
+                               .size_bytes =  1024 * 1024,
+                               .nsectors   =  128,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+               },
+       },
+
+       /*at91sam4sd32b  - LQFP64/BGA64*/
+       {
+               .chipid_cidr    = 0x29970ee0,
+               .name           = "at91sam4sd32b",
+               .total_flash_size     = 2048 * 1024,
+               .total_sram_size      = 160 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+
+/*             .bank[0] = { */
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 5,
+                               .present = 1,
+                               .size_bytes =  1024 * 1024,
+                               .nsectors   =  128,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_2048K_SD,
+                               .controller_address = 0x400e0c00,
+                               .flash_wait_states = 5,
                                .present = 1,
                                .size_bytes =  1024 * 1024,
                                .nsectors   =  128,
@@ -959,7 +1173,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                },
        },
 
-       /*at91sam4sd16c*/
+       /*at91sam4sd16c - LQFP100/BGA100*/
        {
                .chipid_cidr    = 0x29a70ce0,
                .name           = "at91sam4sd16c",
@@ -977,7 +1191,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
                                .bank_number = 0,
                                .base_address = FLASH_BANK0_BASE_SD,
                                .controller_address = 0x400e0a00,
-                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .flash_wait_states = 5,
                                .present = 1,
                                .size_bytes =  512 * 1024,
                                .nsectors   =  64,
@@ -993,7 +1207,51 @@ static const struct sam4_chip_details all_sam4_details[] = {
                                .bank_number = 1,
                                .base_address = FLASH_BANK1_BASE_1024K_SD,
                                .controller_address = 0x400e0c00,
-                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .flash_wait_states = 5,
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+               },
+       },
+
+       /*at91sam4sd16b - LQFP64/BGA64*/
+       {
+               .chipid_cidr    = 0x29970ce0,
+               .name           = "at91sam4sd16b",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 160 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+
+/*             .bank[0] = { */
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 5,
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_1024K_SD,
+                               .controller_address = 0x400e0c00,
+                               .flash_wait_states = 5,
                                .present = 1,
                                .size_bytes =  512 * 1024,
                                .nsectors   =  64,
Cloned from https://git.code.sf.net/p/openocd/code