git.sur5r.net Git - u-boot/blob - arch/arm/dts/r8a7792.dtsi

   1 /*
   2  * Device Tree Source for the r8a7792 SoC
   3  *
   4  * Copyright (C) 2016 Cogent Embedded Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0
   7  */
   8
   9 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/power/r8a7792-sysc.h>
  13
  14 / {
  15         compatible = "renesas,r8a7792";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 i2c3 = &i2c3;
  24                 i2c4 = &i2c4;
  25                 i2c5 = &i2c5;
  26                 spi0 = &qspi;
  27                 spi1 = &msiof0;
  28                 spi2 = &msiof1;
  29                 vin0 = &vin0;
  30                 vin1 = &vin1;
  31                 vin2 = &vin2;
  32                 vin3 = &vin3;
  33                 vin4 = &vin4;
  34                 vin5 = &vin5;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40                 enable-method = "renesas,apmu";
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a15";
  45                         reg = <0>;
  46                         clock-frequency = <1000000000>;
  47                         clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
  48                         power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
  49                         next-level-cache = <&L2_CA15>;
  50                 };
  51
  52                 cpu1: cpu@1 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a15";
  55                         reg = <1>;
  56                         clock-frequency = <1000000000>;
  57                         clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
  58                         power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
  59                         next-level-cache = <&L2_CA15>;
  60                 };
  61
  62                 L2_CA15: cache-controller-0 {
  63                         compatible = "cache";
  64                         cache-unified;
  65                         cache-level = <2>;
  66                         power-domains = <&sysc R8A7792_PD_CA15_SCU>;
  67                 };
  68         };
  69
  70         soc {
  71                 compatible = "simple-bus";
  72                 interrupt-parent = <&gic>;
  73
  74                 #address-cells = <2>;
  75                 #size-cells = <2>;
  76                 ranges;
  77
  78                 apmu@e6152000 {
  79                         compatible = "renesas,r8a7792-apmu", "renesas,apmu";
  80                         reg = <0 0xe6152000 0 0x188>;
  81                         cpus = <&cpu0 &cpu1>;
  82                 };
  83
  84                 gic: interrupt-controller@f1001000 {
  85                         compatible = "arm,gic-400";
  86                         #interrupt-cells = <3>;
  87                         interrupt-controller;
  88                         reg = <0 0xf1001000 0 0x1000>,
  89                               <0 0xf1002000 0 0x2000>,
  90                               <0 0xf1004000 0 0x2000>,
  91                               <0 0xf1006000 0 0x2000>;
  92                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  93                                       IRQ_TYPE_LEVEL_HIGH)>;
  94                         clocks = <&cpg CPG_MOD 408>;
  95                         clock-names = "clk";
  96                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
  97                         resets = <&cpg 408>;
  98                 };
  99
 100                 irqc: interrupt-controller@e61c0000 {
 101                         compatible = "renesas,irqc-r8a7792", "renesas,irqc";
 102                         #interrupt-cells = <2>;
 103                         interrupt-controller;
 104                         reg = <0 0xe61c0000 0 0x200>;
 105                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 106                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 108                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 109                         clocks = <&cpg CPG_MOD 407>;
 110                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 111                         resets = <&cpg 407>;
 112                 };
 113
 114                 timer {
 115                         compatible = "arm,armv7-timer";
 116                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 117                                       IRQ_TYPE_LEVEL_LOW)>,
 118                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 119                                       IRQ_TYPE_LEVEL_LOW)>,
 120                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 121                                       IRQ_TYPE_LEVEL_LOW)>,
 122                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 123                                       IRQ_TYPE_LEVEL_LOW)>;
 124                 };
 125
 126                 rst: reset-controller@e6160000 {
 127                         compatible = "renesas,r8a7792-rst";
 128                         reg = <0 0xe6160000 0 0x0100>;
 129                 };
 130
 131                 prr: chipid@ff000044 {
 132                         compatible = "renesas,prr";
 133                         reg = <0 0xff000044 0 4>;
 134                 };
 135
 136                 sysc: system-controller@e6180000 {
 137                         compatible = "renesas,r8a7792-sysc";
 138                         reg = <0 0xe6180000 0 0x0200>;
 139                         #power-domain-cells = <1>;
 140                 };
 141
 142                 pfc: pin-controller@e6060000 {
 143                         compatible = "renesas,pfc-r8a7792";
 144                         reg = <0 0xe6060000 0 0x144>;
 145                 };
 146
 147                 gpio0: gpio@e6050000 {
 148                         compatible = "renesas,gpio-r8a7792",
 149                                      "renesas,rcar-gen2-gpio";
 150                         reg = <0 0xe6050000 0 0x50>;
 151                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 152                         #gpio-cells = <2>;
 153                         gpio-controller;
 154                         gpio-ranges = <&pfc 0 0 29>;
 155                         #interrupt-cells = <2>;
 156                         interrupt-controller;
 157                         clocks = <&cpg CPG_MOD 912>;
 158                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 159                         resets = <&cpg 912>;
 160                 };
 161
 162                 gpio1: gpio@e6051000 {
 163                         compatible = "renesas,gpio-r8a7792",
 164                                      "renesas,rcar-gen2-gpio";
 165                         reg = <0 0xe6051000 0 0x50>;
 166                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 167                         #gpio-cells = <2>;
 168                         gpio-controller;
 169                         gpio-ranges = <&pfc 0 32 23>;
 170                         #interrupt-cells = <2>;
 171                         interrupt-controller;
 172                         clocks = <&cpg CPG_MOD 911>;
 173                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 174                         resets = <&cpg 911>;
 175                 };
 176
 177                 gpio2: gpio@e6052000 {
 178                         compatible = "renesas,gpio-r8a7792",
 179                                      "renesas,rcar-gen2-gpio";
 180                         reg = <0 0xe6052000 0 0x50>;
 181                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 182                         #gpio-cells = <2>;
 183                         gpio-controller;
 184                         gpio-ranges = <&pfc 0 64 32>;
 185                         #interrupt-cells = <2>;
 186                         interrupt-controller;
 187                         clocks = <&cpg CPG_MOD 910>;
 188                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 189                         resets = <&cpg 910>;
 190                 };
 191
 192                 gpio3: gpio@e6053000 {
 193                         compatible = "renesas,gpio-r8a7792",
 194                                      "renesas,rcar-gen2-gpio";
 195                         reg = <0 0xe6053000 0 0x50>;
 196                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 197                         #gpio-cells = <2>;
 198                         gpio-controller;
 199                         gpio-ranges = <&pfc 0 96 28>;
 200                         #interrupt-cells = <2>;
 201                         interrupt-controller;
 202                         clocks = <&cpg CPG_MOD 909>;
 203                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 204                         resets = <&cpg 909>;
 205                 };
 206
 207                 gpio4: gpio@e6054000 {
 208                         compatible = "renesas,gpio-r8a7792",
 209                                      "renesas,rcar-gen2-gpio";
 210                         reg = <0 0xe6054000 0 0x50>;
 211                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 212                         #gpio-cells = <2>;
 213                         gpio-controller;
 214                         gpio-ranges = <&pfc 0 128 17>;
 215                         #interrupt-cells = <2>;
 216                         interrupt-controller;
 217                         clocks = <&cpg CPG_MOD 908>;
 218                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 219                         resets = <&cpg 908>;
 220                 };
 221
 222                 gpio5: gpio@e6055000 {
 223                         compatible = "renesas,gpio-r8a7792",
 224                                      "renesas,rcar-gen2-gpio";
 225                         reg = <0 0xe6055000 0 0x50>;
 226                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 227                         #gpio-cells = <2>;
 228                         gpio-controller;
 229                         gpio-ranges = <&pfc 0 160 17>;
 230                         #interrupt-cells = <2>;
 231                         interrupt-controller;
 232                         clocks = <&cpg CPG_MOD 907>;
 233                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 234                         resets = <&cpg 907>;
 235                 };
 236
 237                 gpio6: gpio@e6055100 {
 238                         compatible = "renesas,gpio-r8a7792",
 239                                      "renesas,rcar-gen2-gpio";
 240                         reg = <0 0xe6055100 0 0x50>;
 241                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 242                         #gpio-cells = <2>;
 243                         gpio-controller;
 244                         gpio-ranges = <&pfc 0 192 17>;
 245                         #interrupt-cells = <2>;
 246                         interrupt-controller;
 247                         clocks = <&cpg CPG_MOD 905>;
 248                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 249                         resets = <&cpg 905>;
 250                 };
 251
 252                 gpio7: gpio@e6055200 {
 253                         compatible = "renesas,gpio-r8a7792",
 254                                      "renesas,rcar-gen2-gpio";
 255                         reg = <0 0xe6055200 0 0x50>;
 256                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 257                         #gpio-cells = <2>;
 258                         gpio-controller;
 259                         gpio-ranges = <&pfc 0 224 17>;
 260                         #interrupt-cells = <2>;
 261                         interrupt-controller;
 262                         clocks = <&cpg CPG_MOD 904>;
 263                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 264                         resets = <&cpg 904>;
 265                 };
 266
 267                 gpio8: gpio@e6055300 {
 268                         compatible = "renesas,gpio-r8a7792",
 269                                      "renesas,rcar-gen2-gpio";
 270                         reg = <0 0xe6055300 0 0x50>;
 271                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 272                         #gpio-cells = <2>;
 273                         gpio-controller;
 274                         gpio-ranges = <&pfc 0 256 17>;
 275                         #interrupt-cells = <2>;
 276                         interrupt-controller;
 277                         clocks = <&cpg CPG_MOD 921>;
 278                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 279                         resets = <&cpg 921>;
 280                 };
 281
 282                 gpio9: gpio@e6055400 {
 283                         compatible = "renesas,gpio-r8a7792",
 284                                      "renesas,rcar-gen2-gpio";
 285                         reg = <0 0xe6055400 0 0x50>;
 286                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 287                         #gpio-cells = <2>;
 288                         gpio-controller;
 289                         gpio-ranges = <&pfc 0 288 17>;
 290                         #interrupt-cells = <2>;
 291                         interrupt-controller;
 292                         clocks = <&cpg CPG_MOD 919>;
 293                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 294                         resets = <&cpg 919>;
 295                 };
 296
 297                 gpio10: gpio@e6055500 {
 298                         compatible = "renesas,gpio-r8a7792",
 299                                      "renesas,rcar-gen2-gpio";
 300                         reg = <0 0xe6055500 0 0x50>;
 301                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 302                         #gpio-cells = <2>;
 303                         gpio-controller;
 304                         gpio-ranges = <&pfc 0 320 32>;
 305                         #interrupt-cells = <2>;
 306                         interrupt-controller;
 307                         clocks = <&cpg CPG_MOD 914>;
 308                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 309                         resets = <&cpg 914>;
 310                 };
 311
 312                 gpio11: gpio@e6055600 {
 313                         compatible = "renesas,gpio-r8a7792",
 314                                      "renesas,rcar-gen2-gpio";
 315                         reg = <0 0xe6055600 0 0x50>;
 316                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 317                         #gpio-cells = <2>;
 318                         gpio-controller;
 319                         gpio-ranges = <&pfc 0 352 30>;
 320                         #interrupt-cells = <2>;
 321                         interrupt-controller;
 322                         clocks = <&cpg CPG_MOD 913>;
 323                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 324                         resets = <&cpg 913>;
 325                 };
 326
 327                 dmac0: dma-controller@e6700000 {
 328                         compatible = "renesas,dmac-r8a7792",
 329                                      "renesas,rcar-dmac";
 330                         reg = <0 0xe6700000 0 0x20000>;
 331                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 332                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 333                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 334                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 335                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 336                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 337                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 338                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 339                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 340                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 341                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 342                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 343                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 344                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 345                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 346                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 347                         interrupt-names = "error",
 348                                           "ch0", "ch1", "ch2", "ch3",
 349                                           "ch4", "ch5", "ch6", "ch7",
 350                                           "ch8", "ch9", "ch10", "ch11",
 351                                           "ch12", "ch13", "ch14";
 352                         clocks = <&cpg CPG_MOD 219>;
 353                         clock-names = "fck";
 354                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 355                         resets = <&cpg 219>;
 356                         #dma-cells = <1>;
 357                         dma-channels = <15>;
 358                 };
 359
 360                 dmac1: dma-controller@e6720000 {
 361                         compatible = "renesas,dmac-r8a7792",
 362                                      "renesas,rcar-dmac";
 363                         reg = <0 0xe6720000 0 0x20000>;
 364                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 365                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 366                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 367                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 368                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 369                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 370                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 371                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 372                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 373                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 374                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 375                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 376                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 377                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 378                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 379                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 380                         interrupt-names = "error",
 381                                           "ch0", "ch1", "ch2", "ch3",
 382                                           "ch4", "ch5", "ch6", "ch7",
 383                                           "ch8", "ch9", "ch10", "ch11",
 384                                           "ch12", "ch13", "ch14";
 385                         clocks = <&cpg CPG_MOD 218>;
 386                         clock-names = "fck";
 387                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 388                         resets = <&cpg 218>;
 389                         #dma-cells = <1>;
 390                         dma-channels = <15>;
 391                 };
 392
 393                 scif0: serial@e6e60000 {
 394                         compatible = "renesas,scif-r8a7792",
 395                                      "renesas,rcar-gen2-scif", "renesas,scif";
 396                         reg = <0 0xe6e60000 0 64>;
 397                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 398                         clocks = <&cpg CPG_MOD 721>,
 399                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 400                         clock-names = "fck", "brg_int", "scif_clk";
 401                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 402                                <&dmac1 0x29>, <&dmac1 0x2a>;
 403                         dma-names = "tx", "rx", "tx", "rx";
 404                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 405                         resets = <&cpg 721>;
 406                         status = "disabled";
 407                 };
 408
 409                 scif1: serial@e6e68000 {
 410                         compatible = "renesas,scif-r8a7792",
 411                                      "renesas,rcar-gen2-scif", "renesas,scif";
 412                         reg = <0 0xe6e68000 0 64>;
 413                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&cpg CPG_MOD 720>,
 415                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 416                         clock-names = "fck", "brg_int", "scif_clk";
 417                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 418                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 419                         dma-names = "tx", "rx", "tx", "rx";
 420                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 421                         resets = <&cpg 720>;
 422                         status = "disabled";
 423                 };
 424
 425                 scif2: serial@e6e58000 {
 426                         compatible = "renesas,scif-r8a7792",
 427                                      "renesas,rcar-gen2-scif", "renesas,scif";
 428                         reg = <0 0xe6e58000 0 64>;
 429                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 430                         clocks = <&cpg CPG_MOD 719>,
 431                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 432                         clock-names = "fck", "brg_int", "scif_clk";
 433                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 434                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 435                         dma-names = "tx", "rx", "tx", "rx";
 436                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 437                         resets = <&cpg 719>;
 438                         status = "disabled";
 439                 };
 440
 441                 scif3: serial@e6ea8000 {
 442                         compatible = "renesas,scif-r8a7792",
 443                                      "renesas,rcar-gen2-scif", "renesas,scif";
 444                         reg = <0 0xe6ea8000 0 64>;
 445                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 446                         clocks = <&cpg CPG_MOD 718>,
 447                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 448                         clock-names = "fck", "brg_int", "scif_clk";
 449                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 450                                <&dmac1 0x2f>, <&dmac1 0x30>;
 451                         dma-names = "tx", "rx", "tx", "rx";
 452                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 453                         resets = <&cpg 718>;
 454                         status = "disabled";
 455                 };
 456
 457                 hscif0: serial@e62c0000 {
 458                         compatible = "renesas,hscif-r8a7792",
 459                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 460                         reg = <0 0xe62c0000 0 96>;
 461                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 462                         clocks = <&cpg CPG_MOD 717>,
 463                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 464                         clock-names = "fck", "brg_int", "scif_clk";
 465                         dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 466                                <&dmac1 0x39>, <&dmac1 0x3a>;
 467                         dma-names = "tx", "rx", "tx", "rx";
 468                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 469                         resets = <&cpg 717>;
 470                         status = "disabled";
 471                 };
 472
 473                 hscif1: serial@e62c8000 {
 474                         compatible = "renesas,hscif-r8a7792",
 475                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 476                         reg = <0 0xe62c8000 0 96>;
 477                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 478                         clocks = <&cpg CPG_MOD 716>,
 479                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 480                         clock-names = "fck", "brg_int", "scif_clk";
 481                         dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 482                                <&dmac1 0x4d>, <&dmac1 0x4e>;
 483                         dma-names = "tx", "rx", "tx", "rx";
 484                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 485                         resets = <&cpg 716>;
 486                         status = "disabled";
 487                 };
 488
 489                 icram0: sram@e63a0000 {
 490                         compatible = "mmio-sram";
 491                         reg = <0 0xe63a0000 0 0x12000>;
 492                 };
 493
 494                 icram1: sram@e63c0000 {
 495                         compatible = "mmio-sram";
 496                         reg = <0 0xe63c0000 0 0x1000>;
 497                         #address-cells = <1>;
 498                         #size-cells = <1>;
 499                         ranges = <0 0 0xe63c0000 0x1000>;
 500
 501                         smp-sram@0 {
 502                                 compatible = "renesas,smp-sram";
 503                                 reg = <0 0x10>;
 504                         };
 505                 };
 506
 507                 sdhi0: sd@ee100000 {
 508                         compatible = "renesas,sdhi-r8a7792";
 509                         reg = <0 0xee100000 0 0x328>;
 510                         interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 511                         dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 512                                <&dmac1 0xcd>, <&dmac1 0xce>;
 513                         dma-names = "tx", "rx", "tx", "rx";
 514                         clocks = <&cpg CPG_MOD 314>;
 515                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 516                         resets = <&cpg 314>;
 517                         status = "disabled";
 518                 };
 519
 520                 jpu: jpeg-codec@fe980000 {
 521                         compatible = "renesas,jpu-r8a7792",
 522                                      "renesas,rcar-gen2-jpu";
 523                         reg = <0 0xfe980000 0 0x10300>;
 524                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&cpg CPG_MOD 106>;
 526                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 527                         resets = <&cpg 106>;
 528                 };
 529
 530                 avb: ethernet@e6800000 {
 531                         compatible = "renesas,etheravb-r8a7792",
 532                                      "renesas,etheravb-rcar-gen2";
 533                         reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 534                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 535                         clocks = <&cpg CPG_MOD 812>;
 536                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 537                         resets = <&cpg 812>;
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         status = "disabled";
 541                 };
 542
 543                 /* I2C doesn't need pinmux */
 544                 i2c0: i2c@e6508000 {
 545                         compatible = "renesas,i2c-r8a7792",
 546                                      "renesas,rcar-gen2-i2c";
 547                         reg = <0 0xe6508000 0 0x40>;
 548                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 549                         clocks = <&cpg CPG_MOD 931>;
 550                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 551                         resets = <&cpg 931>;
 552                         i2c-scl-internal-delay-ns = <6>;
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         status = "disabled";
 556                 };
 557
 558                 i2c1: i2c@e6518000 {
 559                         compatible = "renesas,i2c-r8a7792",
 560                                      "renesas,rcar-gen2-i2c";
 561                         reg = <0 0xe6518000 0 0x40>;
 562                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 563                         clocks = <&cpg CPG_MOD 930>;
 564                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 565                         resets = <&cpg 930>;
 566                         i2c-scl-internal-delay-ns = <6>;
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         status = "disabled";
 570                 };
 571
 572                 i2c2: i2c@e6530000 {
 573                         compatible = "renesas,i2c-r8a7792",
 574                                      "renesas,rcar-gen2-i2c";
 575                         reg = <0 0xe6530000 0 0x40>;
 576                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 577                         clocks = <&cpg CPG_MOD 929>;
 578                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 579                         resets = <&cpg 929>;
 580                         i2c-scl-internal-delay-ns = <6>;
 581                         #address-cells = <1>;
 582                         #size-cells = <0>;
 583                         status = "disabled";
 584                 };
 585
 586                 i2c3: i2c@e6540000 {
 587                         compatible = "renesas,i2c-r8a7792",
 588                                      "renesas,rcar-gen2-i2c";
 589                         reg = <0 0xe6540000 0 0x40>;
 590                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&cpg CPG_MOD 928>;
 592                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 593                         resets = <&cpg 928>;
 594                         i2c-scl-internal-delay-ns = <6>;
 595                         #address-cells = <1>;
 596                         #size-cells = <0>;
 597                         status = "disabled";
 598                 };
 599
 600                 i2c4: i2c@e6520000 {
 601                         compatible = "renesas,i2c-r8a7792",
 602                                      "renesas,rcar-gen2-i2c";
 603                         reg = <0 0xe6520000 0 0x40>;
 604                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 605                         clocks = <&cpg CPG_MOD 927>;
 606                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 607                         resets = <&cpg 927>;
 608                         i2c-scl-internal-delay-ns = <6>;
 609                         #address-cells = <1>;
 610                         #size-cells = <0>;
 611                         status = "disabled";
 612                 };
 613
 614                 i2c5: i2c@e6528000 {
 615                         compatible = "renesas,i2c-r8a7792",
 616                                      "renesas,rcar-gen2-i2c";
 617                         reg = <0 0xe6528000 0 0x40>;
 618                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 619                         clocks = <&cpg CPG_MOD 925>;
 620                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 621                         resets = <&cpg 925>;
 622                         i2c-scl-internal-delay-ns = <110>;
 623                         #address-cells = <1>;
 624                         #size-cells = <0>;
 625                         status = "disabled";
 626                 };
 627
 628                 qspi: spi@e6b10000 {
 629                         compatible = "renesas,qspi-r8a7792", "renesas,qspi";
 630                         reg = <0 0xe6b10000 0 0x2c>;
 631                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 632                         clocks = <&cpg CPG_MOD 917>;
 633                         dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 634                                <&dmac1 0x17>, <&dmac1 0x18>;
 635                         dma-names = "tx", "rx", "tx", "rx";
 636                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 637                         resets = <&cpg 917>;
 638                         num-cs = <1>;
 639                         #address-cells = <1>;
 640                         #size-cells = <0>;
 641                         status = "disabled";
 642                 };
 643
 644                 msiof0: spi@e6e20000 {
 645                         compatible = "renesas,msiof-r8a7792",
 646                                      "renesas,rcar-gen2-msiof";
 647                         reg = <0 0xe6e20000 0 0x0064>;
 648                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 649                         clocks = <&cpg CPG_MOD 000>;
 650                         dmas = <&dmac0 0x51>, <&dmac0 0x52>,
 651                                <&dmac1 0x51>, <&dmac1 0x52>;
 652                         dma-names = "tx", "rx", "tx", "rx";
 653                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 654                         resets = <&cpg 000>;
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                         status = "disabled";
 658                 };
 659
 660                 msiof1: spi@e6e10000 {
 661                         compatible = "renesas,msiof-r8a7792",
 662                                      "renesas,rcar-gen2-msiof";
 663                         reg = <0 0xe6e10000 0 0x0064>;
 664                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 665                         clocks = <&cpg CPG_MOD 208>;
 666                         dmas = <&dmac0 0x55>, <&dmac0 0x56>,
 667                                <&dmac1 0x55>, <&dmac1 0x56>;
 668                         dma-names = "tx", "rx", "tx", "rx";
 669                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 670                         resets = <&cpg 208>;
 671                         #address-cells = <1>;
 672                         #size-cells = <0>;
 673                         status = "disabled";
 674                 };
 675
 676                 du: display@feb00000 {
 677                         compatible = "renesas,du-r8a7792";
 678                         reg = <0 0xfeb00000 0 0x40000>;
 679                         reg-names = "du";
 680                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 681                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 682                         clocks = <&cpg CPG_MOD 724>,
 683                                  <&cpg CPG_MOD 723>;
 684                         clock-names = "du.0", "du.1";
 685                         status = "disabled";
 686
 687                         ports {
 688                                 #address-cells = <1>;
 689                                 #size-cells = <0>;
 690
 691                                 port@0 {
 692                                         reg = <0>;
 693                                         du_out_rgb0: endpoint {
 694                                         };
 695                                 };
 696                                 port@1 {
 697                                         reg = <1>;
 698                                         du_out_rgb1: endpoint {
 699                                         };
 700                                 };
 701                         };
 702                 };
 703
 704                 can0: can@e6e80000 {
 705                         compatible = "renesas,can-r8a7792",
 706                                      "renesas,rcar-gen2-can";
 707                         reg = <0 0xe6e80000 0 0x1000>;
 708                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 709                         clocks = <&cpg CPG_MOD 916>,
 710                                  <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
 711                         clock-names = "clkp1", "clkp2", "can_clk";
 712                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 713                         resets = <&cpg 916>;
 714                         status = "disabled";
 715                 };
 716
 717                 can1: can@e6e88000 {
 718                         compatible = "renesas,can-r8a7792",
 719                                      "renesas,rcar-gen2-can";
 720                         reg = <0 0xe6e88000 0 0x1000>;
 721                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 722                         clocks = <&cpg CPG_MOD 915>,
 723                                  <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
 724                         clock-names = "clkp1", "clkp2", "can_clk";
 725                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 726                         resets = <&cpg 915>;
 727                         status = "disabled";
 728                 };
 729
 730                 vin0: video@e6ef0000 {
 731                         compatible = "renesas,vin-r8a7792",
 732                                      "renesas,rcar-gen2-vin";
 733                         reg = <0 0xe6ef0000 0 0x1000>;
 734                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 735                         clocks = <&cpg CPG_MOD 811>;
 736                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 737                         resets = <&cpg 811>;
 738                         status = "disabled";
 739                 };
 740
 741                 vin1: video@e6ef1000 {
 742                         compatible = "renesas,vin-r8a7792",
 743                                      "renesas,rcar-gen2-vin";
 744                         reg = <0 0xe6ef1000 0 0x1000>;
 745                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 746                         clocks = <&cpg CPG_MOD 810>;
 747                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 748                         resets = <&cpg 810>;
 749                         status = "disabled";
 750                 };
 751
 752                 vin2: video@e6ef2000 {
 753                         compatible = "renesas,vin-r8a7792",
 754                                      "renesas,rcar-gen2-vin";
 755                         reg = <0 0xe6ef2000 0 0x1000>;
 756                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 757                         clocks = <&cpg CPG_MOD 809>;
 758                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 759                         resets = <&cpg 809>;
 760                         status = "disabled";
 761                 };
 762
 763                 vin3: video@e6ef3000 {
 764                         compatible = "renesas,vin-r8a7792",
 765                                      "renesas,rcar-gen2-vin";
 766                         reg = <0 0xe6ef3000 0 0x1000>;
 767                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 768                         clocks = <&cpg CPG_MOD 808>;
 769                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 770                         resets = <&cpg 808>;
 771                         status = "disabled";
 772                 };
 773
 774                 vin4: video@e6ef4000 {
 775                         compatible = "renesas,vin-r8a7792",
 776                                      "renesas,rcar-gen2-vin";
 777                         reg = <0 0xe6ef4000 0 0x1000>;
 778                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 779                         clocks = <&cpg CPG_MOD 805>;
 780                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 781                         resets = <&cpg 805>;
 782                         status = "disabled";
 783                 };
 784
 785                 vin5: video@e6ef5000 {
 786                         compatible = "renesas,vin-r8a7792",
 787                                      "renesas,rcar-gen2-vin";
 788                         reg = <0 0xe6ef5000 0 0x1000>;
 789                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 790                         clocks = <&cpg CPG_MOD 804>;
 791                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 792                         resets = <&cpg 804>;
 793                         status = "disabled";
 794                 };
 795
 796                 vsp@fe928000 {
 797                         compatible = "renesas,vsp1";
 798                         reg = <0 0xfe928000 0 0x8000>;
 799                         interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 800                         clocks = <&cpg CPG_MOD 131>;
 801                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 802                         resets = <&cpg 131>;
 803                 };
 804
 805                 vsp@fe930000 {
 806                         compatible = "renesas,vsp1";
 807                         reg = <0 0xfe930000 0 0x8000>;
 808                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 809                         clocks = <&cpg CPG_MOD 128>;
 810                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 811                         resets = <&cpg 128>;
 812                 };
 813
 814                 vsp@fe938000 {
 815                         compatible = "renesas,vsp1";
 816                         reg = <0 0xfe938000 0 0x8000>;
 817                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 818                         clocks = <&cpg CPG_MOD 127>;
 819                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 820                         resets = <&cpg 127>;
 821                 };
 822
 823                 cpg: clock-controller@e6150000 {
 824                         compatible = "renesas,r8a7792-cpg-mssr";
 825                         reg = <0 0xe6150000 0 0x1000>;
 826                         clocks = <&extal_clk>;
 827                         clock-names = "extal";
 828                         #clock-cells = <2>;
 829                         #power-domain-cells = <0>;
 830                         #reset-cells = <1>;
 831                 };
 832         };
 833
 834         /* External root clock */
 835         extal_clk: extal {
 836                 compatible = "fixed-clock";
 837                 #clock-cells = <0>;
 838                 /* This value must be overridden by the board. */
 839                 clock-frequency = <0>;
 840         };
 841
 842         /* External SCIF clock */
 843         scif_clk: scif {
 844                 compatible = "fixed-clock";
 845                 #clock-cells = <0>;
 846                 /* This value must be overridden by the board. */
 847                 clock-frequency = <0>;
 848         };
 849
 850         /* External CAN clock */
 851         can_clk: can {
 852                 compatible = "fixed-clock";
 853                 #clock-cells = <0>;
 854                 /* This value must be overridden by the board. */
 855                 clock-frequency = <0>;
 856         };
 857 };