git.sur5r.net Git - u-boot/blob - arch/arm/dts/r8a77970-eagle.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the Eagle board
   4  *
   5  * Copyright (C) 2016-2017 Renesas Electronics Corp.
   6  * Copyright (C) 2017 Cogent Embedded, Inc.
   7  */
   8
   9 /dts-v1/;
  10 #include "r8a77970.dtsi"
  11
  12 / {
  13         model = "Renesas Eagle board based on r8a77970";
  14         compatible = "renesas,eagle", "renesas,r8a77970";
  15
  16         aliases {
  17                 serial0 = &scif0;
  18                 ethernet0 = &avb;
  19                 spi0 = &rpc;
  20         };
  21
  22         chosen {
  23                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  24                 stdout-path = "serial0:115200n8";
  25         };
  26
  27         memory@48000000 {
  28                 device_type = "memory";
  29                 /* first 128MB is reserved for secure area. */
  30                 reg = <0x0 0x48000000 0x0 0x38000000>;
  31         };
  32 };
  33
  34 &avb {
  35         pinctrl-0 = <&avb0_pins>;
  36         pinctrl-names = "default";
  37         renesas,no-ether-link;
  38         phy-handle = <&phy0>;
  39         phy-mode = "rgmii-id";
  40         status = "okay";
  41
  42         phy0: ethernet-phy@0 {
  43                 rxc-skew-ps = <1500>;
  44                 reg = <0>;
  45                 interrupt-parent = <&gpio1>;
  46                 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
  47         };
  48 };
  49
  50 &extal_clk {
  51         clock-frequency = <16666666>;
  52 };
  53
  54 &extalr_clk {
  55         clock-frequency = <32768>;
  56 };
  57
  58 &i2c0 {
  59         pinctrl-0 = <&i2c0_pins>;
  60         pinctrl-names = "default";
  61
  62         status = "okay";
  63         clock-frequency = <400000>;
  64
  65         io_expander: gpio@20 {
  66                 compatible = "onnn,pca9654";
  67                 reg = <0x20>;
  68                 gpio-controller;
  69                 #gpio-cells = <2>;
  70         };
  71 };
  72
  73 &pfc {
  74         avb0_pins: avb {
  75                 mux {
  76                         groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
  77                         function = "avb0";
  78                 };
  79         };
  80
  81         i2c0_pins: i2c0 {
  82                 groups = "i2c0";
  83                 function = "i2c0";
  84         };
  85
  86         scif0_pins: scif0 {
  87                 groups = "scif0_data";
  88                 function = "scif0";
  89         };
  90 };
  91
  92 &rpc {
  93         num-cs = <1>;
  94         status = "okay";
  95         spi-max-frequency = <50000000>;
  96         #address-cells = <1>;
  97         #size-cells = <0>;
  98
  99         flash0: spi-flash@0 {
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
 103                 spi-max-frequency = <50000000>;
 104                 spi-tx-bus-width = <1>;
 105                 spi-rx-bus-width = <1>;
 106                 reg = <0>;
 107                 status = "okay";
 108         };
 109 };
 110
 111 &rwdt {
 112         timeout-sec = <60>;
 113         status = "okay";
 114 };
 115
 116 &scif0 {
 117         pinctrl-0 = <&scif0_pins>;
 118         pinctrl-names = "default";
 119
 120         status = "okay";
 121 };