git.sur5r.net Git - u-boot/blob - arch/arm/dts/r8a77990-ebisu.dts

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Device Tree Source for the ebisu board
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  */
   7
   8 /dts-v1/;
   9 #include "r8a77990.dtsi"
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         model = "Renesas Ebisu board based on r8a77990";
  14         compatible = "renesas,ebisu", "renesas,r8a77990";
  15
  16         aliases {
  17                 serial0 = &scif2;
  18                 ethernet0 = &avb;
  19         };
  20
  21         chosen {
  22                 bootargs = "ignore_loglevel";
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26         memory@48000000 {
  27                 device_type = "memory";
  28                 /* first 128MB is reserved for secure area. */
  29                 reg = <0x0 0x48000000 0x0 0x38000000>;
  30         };
  31 };
  32
  33 &avb {
  34         pinctrl-0 = <&avb_pins>;
  35         pinctrl-names = "default";
  36         renesas,no-ether-link;
  37         phy-handle = <&phy0>;
  38         phy-mode = "rgmii-txid";
  39         status = "okay";
  40
  41         phy0: ethernet-phy@0 {
  42                 rxc-skew-ps = <1500>;
  43                 reg = <0>;
  44                 interrupt-parent = <&gpio2>;
  45                 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
  46                 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
  47         };
  48 };
  49
  50 &extal_clk {
  51         clock-frequency = <48000000>;
  52 };
  53
  54 &pfc {
  55         pinctrl-0 = <&scif_clk_pins>;
  56         pinctrl-names = "default";
  57
  58         avb_pins: avb {
  59                 mux {
  60                         groups = "avb_link", "avb_mii";
  61                         function = "avb";
  62                 };
  63         };
  64
  65         scif2_pins: scif2 {
  66                 groups = "scif2_data_a";
  67                 function = "scif2";
  68         };
  69
  70         scif_clk_pins: scif_clk {
  71                 groups = "scif_clk_a";
  72                 function = "scif_clk";
  73         };
  74 };
  75
  76 &sdhi0 {
  77         status = "okay";
  78 };
  79
  80 &sdhi1 {
  81         status = "okay";
  82 };
  83
  84 &sdhi3 {
  85         bus-width = <8>;
  86         non-removable;
  87         status = "okay";
  88 };
  89
  90 &scif2 {
  91         pinctrl-0 = <&scif2_pins>;
  92         pinctrl-names = "default";
  93
  94         status = "okay";
  95 };