git.sur5r.net Git - u-boot/blob - arch/arm/dts/rk3188.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+ or X11
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/pinctrl/rockchip.h>
  10 #include <dt-bindings/clock/rk3188-cru.h>
  11 #include "rk3xxx.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3188";
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 enable-method = "rockchip,rk3066-smp";
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         next-level-cache = <&L2>;
  25                         reg = <0x0>;
  26                         operating-points = <
  27                                 /* kHz    uV */
  28                                 1608000 1350000
  29                                 1416000 1250000
  30                                 1200000 1150000
  31                                 1008000 1075000
  32                                  816000  975000
  33                                  600000  950000
  34                                  504000  925000
  35                                  312000  875000
  36                         >;
  37                         clock-latency = <40000>;
  38                         clocks = <&cru ARMCLK>;
  39                 };
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a9";
  43                         next-level-cache = <&L2>;
  44                         reg = <0x1>;
  45                 };
  46                 cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a9";
  49                         next-level-cache = <&L2>;
  50                         reg = <0x2>;
  51                 };
  52                 cpu@3 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a9";
  55                         next-level-cache = <&L2>;
  56                         reg = <0x3>;
  57                 };
  58         };
  59
  60         sram: sram@10080000 {
  61                 compatible = "mmio-sram";
  62                 reg = <0x10080000 0x8000>;
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 ranges = <0 0x10080000 0x8000>;
  66
  67                 smp-sram@0 {
  68                         compatible = "rockchip,rk3066-smp-sram";
  69                         reg = <0x0 0x50>;
  70                 };
  71         };
  72
  73         i2s0: i2s@1011a000 {
  74                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
  75                 reg = <0x1011a000 0x2000>;
  76                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79                 pinctrl-names = "default";
  80                 pinctrl-0 = <&i2s0_bus>;
  81                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
  82                 dma-names = "tx", "rx";
  83                 clock-names = "i2s_hclk", "i2s_clk";
  84                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
  85                 rockchip,playback-channels = <2>;
  86                 rockchip,capture-channels = <2>;
  87                 status = "disabled";
  88         };
  89
  90         spdif: sound@1011e000 {
  91                 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
  92                 reg = <0x1011e000 0x2000>;
  93                 #sound-dai-cells = <0>;
  94                 clock-names = "hclk", "mclk";
  95                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
  96                 dmas = <&dmac1_s 8>;
  97                 dma-names = "tx";
  98                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  99                 pinctrl-names = "default";
 100                 pinctrl-0 = <&spdif_tx>;
 101                 status = "disabled";
 102         };
 103
 104         cru: clock-controller@20000000 {
 105                 compatible = "rockchip,rk3188-cru";
 106                 reg = <0x20000000 0x1000>;
 107                 rockchip,grf = <&grf>;
 108
 109                 #clock-cells = <1>;
 110                 #reset-cells = <1>;
 111         };
 112
 113         efuse: efuse@20010000 {
 114                 compatible = "rockchip,rockchip-efuse";
 115                 reg = <0x20010000 0x4000>;
 116                 #address-cells = <1>;
 117                 #size-cells = <1>;
 118                 clocks = <&cru PCLK_EFUSE>;
 119                 clock-names = "pclk_efuse";
 120
 121                 cpu_leakage: cpu_leakage@17 {
 122                         reg = <0x17 0x1>;
 123                 };
 124         };
 125
 126         timer3: timer@2000e000 {
 127                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 128                 reg = <0x2000e000 0x20>;
 129                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 130         };
 131
 132         usbphy: phy {
 133                 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 134                 rockchip,grf = <&grf>;
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137                 status = "disabled";
 138
 139                 usbphy0: usb-phy@10c {
 140                         #phy-cells = <0>;
 141                         reg = <0x10c>;
 142                         clocks = <&cru SCLK_OTGPHY0>;
 143                         clock-names = "phyclk";
 144                         #clock-cells = <0>;
 145                 };
 146
 147                 usbphy1: usb-phy@11c {
 148                         #phy-cells = <0>;
 149                         reg = <0x11c>;
 150                         clocks = <&cru SCLK_OTGPHY1>;
 151                         clock-names = "phyclk";
 152                         #clock-cells = <0>;
 153                 };
 154         };
 155
 156         pinctrl: pinctrl {
 157                 compatible = "rockchip,rk3188-pinctrl";
 158                 rockchip,grf = <&grf>;
 159                 rockchip,pmu = <&pmu>;
 160
 161                 #address-cells = <1>;
 162                 #size-cells = <1>;
 163                 ranges;
 164
 165                 gpio0: gpio0@2000a000 {
 166                         compatible = "rockchip,gpio-bank";
 167                         reg = <0x2000a000 0x100>;
 168                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 169                         clocks = <&cru PCLK_GPIO0>;
 170
 171                         gpio-controller;
 172                         #gpio-cells = <2>;
 173
 174                         interrupt-controller;
 175                         #interrupt-cells = <2>;
 176                 };
 177
 178                 gpio1: gpio1@2003c000 {
 179                         compatible = "rockchip,gpio-bank";
 180                         reg = <0x2003c000 0x100>;
 181                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 182                         clocks = <&cru PCLK_GPIO1>;
 183
 184                         gpio-controller;
 185                         #gpio-cells = <2>;
 186
 187                         interrupt-controller;
 188                         #interrupt-cells = <2>;
 189                 };
 190
 191                 gpio2: gpio2@2003e000 {
 192                         compatible = "rockchip,gpio-bank";
 193                         reg = <0x2003e000 0x100>;
 194                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 195                         clocks = <&cru PCLK_GPIO2>;
 196
 197                         gpio-controller;
 198                         #gpio-cells = <2>;
 199
 200                         interrupt-controller;
 201                         #interrupt-cells = <2>;
 202                 };
 203
 204                 gpio3: gpio3@20080000 {
 205                         compatible = "rockchip,gpio-bank";
 206                         reg = <0x20080000 0x100>;
 207                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 208                         clocks = <&cru PCLK_GPIO3>;
 209
 210                         gpio-controller;
 211                         #gpio-cells = <2>;
 212
 213                         interrupt-controller;
 214                         #interrupt-cells = <2>;
 215                 };
 216
 217                 pcfg_pull_up: pcfg_pull_up {
 218                         bias-pull-up;
 219                 };
 220
 221                 pcfg_pull_down: pcfg_pull_down {
 222                         bias-pull-down;
 223                 };
 224
 225                 pcfg_pull_none: pcfg_pull_none {
 226                         bias-disable;
 227                 };
 228
 229                 emmc {
 230                         emmc_clk: emmc-clk {
 231                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
 232                         };
 233
 234                         emmc_cmd: emmc-cmd {
 235                                 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
 236                         };
 237
 238                         emmc_rst: emmc-rst {
 239                                 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
 240                         };
 241
 242                         /*
 243                          * The data pins are shared between nandc and emmc and
 244                          * not accessible through pinctrl. Also they should've
 245                          * been already set correctly by firmware, as
 246                          * flash/emmc is the boot-device.
 247                          */
 248                 };
 249
 250                 emac {
 251                         emac_xfer: emac-xfer {
 252                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 253                                                 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 254                                                 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 255                                                 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
 256                                                 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 257                                                 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 258                                                 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 259                                                 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
 260                         };
 261
 262                         emac_mdio: emac-mdio {
 263                                 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
 264                                                 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
 265                         };
 266                 };
 267
 268                 i2c0 {
 269                         i2c0_xfer: i2c0-xfer {
 270                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
 271                                                 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
 272                         };
 273                 };
 274
 275                 i2c1 {
 276                         i2c1_xfer: i2c1-xfer {
 277                                 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
 278                                                 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
 279                         };
 280                 };
 281
 282                 i2c2 {
 283                         i2c2_xfer: i2c2-xfer {
 284                                 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
 285                                                 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
 286                         };
 287                 };
 288
 289                 i2c3 {
 290                         i2c3_xfer: i2c3-xfer {
 291                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
 292                                                 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
 293                         };
 294                 };
 295
 296                 i2c4 {
 297                         i2c4_xfer: i2c4-xfer {
 298                                 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
 299                                                 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
 300                         };
 301                 };
 302
 303                 pwm0 {
 304                         pwm0_out: pwm0-out {
 305                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
 306                         };
 307                 };
 308
 309                 pwm1 {
 310                         pwm1_out: pwm1-out {
 311                                 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
 312                         };
 313                 };
 314
 315                 pwm2 {
 316                         pwm2_out: pwm2-out {
 317                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
 318                         };
 319                 };
 320
 321                 pwm3 {
 322                         pwm3_out: pwm3-out {
 323                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
 324                         };
 325                 };
 326
 327                 spi0 {
 328                         spi0_clk: spi0-clk {
 329                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
 330                         };
 331                         spi0_cs0: spi0-cs0 {
 332                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
 333                         };
 334                         spi0_tx: spi0-tx {
 335                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
 336                         };
 337                         spi0_rx: spi0-rx {
 338                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
 339                         };
 340                         spi0_cs1: spi0-cs1 {
 341                                 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
 342                         };
 343                 };
 344
 345                 spi1 {
 346                         spi1_clk: spi1-clk {
 347                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
 348                         };
 349                         spi1_cs0: spi1-cs0 {
 350                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
 351                         };
 352                         spi1_rx: spi1-rx {
 353                                 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
 354                         };
 355                         spi1_tx: spi1-tx {
 356                                 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
 357                         };
 358                         spi1_cs1: spi1-cs1 {
 359                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
 360                         };
 361                 };
 362
 363                 uart0 {
 364                         uart0_xfer: uart0-xfer {
 365                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 366                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 367                         };
 368
 369                         uart0_cts: uart0-cts {
 370                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 371                         };
 372
 373                         uart0_rts: uart0-rts {
 374                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 375                         };
 376                 };
 377
 378                 uart1 {
 379                         uart1_xfer: uart1-xfer {
 380                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 381                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 382                         };
 383
 384                         uart1_cts: uart1-cts {
 385                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 386                         };
 387
 388                         uart1_rts: uart1-rts {
 389                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 390                         };
 391                 };
 392
 393                 uart2 {
 394                         uart2_xfer: uart2-xfer {
 395                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 396                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 397                         };
 398                         /* no rts / cts for uart2 */
 399                 };
 400
 401                 uart3 {
 402                         uart3_xfer: uart3-xfer {
 403                                 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 404                                                 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 405                         };
 406
 407                         uart3_cts: uart3-cts {
 408                                 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 409                         };
 410
 411                         uart3_rts: uart3-rts {
 412                                 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 413                         };
 414                 };
 415
 416                 sd0 {
 417                         sd0_clk: sd0-clk {
 418                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 419                         };
 420
 421                         sd0_cmd: sd0-cmd {
 422                                 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 423                         };
 424
 425                         sd0_cd: sd0-cd {
 426                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 427                         };
 428
 429                         sd0_wp: sd0-wp {
 430                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 431                         };
 432
 433                         sd0_pwr: sd0-pwr {
 434                                 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 435                         };
 436
 437                         sd0_bus1: sd0-bus-width1 {
 438                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 439                         };
 440
 441                         sd0_bus4: sd0-bus-width4 {
 442                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 443                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 444                                                 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 445                                                 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 446                         };
 447                 };
 448
 449                 sd1 {
 450                         sd1_clk: sd1-clk {
 451                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 452                         };
 453
 454                         sd1_cmd: sd1-cmd {
 455                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 456                         };
 457
 458                         sd1_cd: sd1-cd {
 459                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 460                         };
 461
 462                         sd1_wp: sd1-wp {
 463                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 464                         };
 465
 466                         sd1_bus1: sd1-bus-width1 {
 467                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 468                         };
 469
 470                         sd1_bus4: sd1-bus-width4 {
 471                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 472                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 473                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 474                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 475                         };
 476                 };
 477
 478                 i2s0 {
 479                         i2s0_bus: i2s0-bus {
 480                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
 481                                                 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
 482                                                 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
 483                                                 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
 484                                                 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
 485                                                 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
 486                         };
 487                 };
 488
 489                 spdif {
 490                         spdif_tx: spdif-tx {
 491                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
 492                         };
 493                 };
 494         };
 495 };
 496
 497 &emac {
 498         compatible = "rockchip,rk3188-emac";
 499 };
 500
 501 &global_timer {
 502         interrupts = <GIC_PPI 11 0xf04>;
 503 };
 504
 505 &grf {
 506         compatible = "rockchip,rk3188-grf", "syscon";
 507 };
 508
 509 &local_timer {
 510         interrupts = <GIC_PPI 13 0xf04>;
 511 };
 512
 513 &i2c0 {
 514         compatible = "rockchip,rk3188-i2c";
 515         pinctrl-names = "default";
 516         pinctrl-0 = <&i2c0_xfer>;
 517 };
 518
 519 &i2c1 {
 520         compatible = "rockchip,rk3188-i2c";
 521         pinctrl-names = "default";
 522         pinctrl-0 = <&i2c1_xfer>;
 523 };
 524
 525 &i2c2 {
 526         compatible = "rockchip,rk3188-i2c";
 527         pinctrl-names = "default";
 528         pinctrl-0 = <&i2c2_xfer>;
 529 };
 530
 531 &i2c3 {
 532         compatible = "rockchip,rk3188-i2c";
 533         pinctrl-names = "default";
 534         pinctrl-0 = <&i2c3_xfer>;
 535 };
 536
 537 &i2c4 {
 538         compatible = "rockchip,rk3188-i2c";
 539         pinctrl-names = "default";
 540         pinctrl-0 = <&i2c4_xfer>;
 541 };
 542
 543 &pmu {
 544         compatible = "rockchip,rk3188-pmu", "syscon";
 545 };
 546
 547 &pwm0 {
 548         pinctrl-names = "default";
 549         pinctrl-0 = <&pwm0_out>;
 550 };
 551
 552 &pwm1 {
 553         pinctrl-names = "default";
 554         pinctrl-0 = <&pwm1_out>;
 555 };
 556
 557 &pwm2 {
 558         pinctrl-names = "default";
 559         pinctrl-0 = <&pwm2_out>;
 560 };
 561
 562 &pwm3 {
 563         pinctrl-names = "default";
 564         pinctrl-0 = <&pwm3_out>;
 565 };
 566
 567 &spi0 {
 568         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 569         pinctrl-names = "default";
 570         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 571 };
 572
 573 &spi1 {
 574         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 575         pinctrl-names = "default";
 576         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 577 };
 578
 579 &uart0 {
 580         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 581         pinctrl-names = "default";
 582         pinctrl-0 = <&uart0_xfer>;
 583 };
 584
 585 &uart1 {
 586         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 587         pinctrl-names = "default";
 588         pinctrl-0 = <&uart1_xfer>;
 589 };
 590
 591 &uart2 {
 592         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 593         pinctrl-names = "default";
 594         pinctrl-0 = <&uart2_xfer>;
 595 };
 596
 597 &uart3 {
 598         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 599         pinctrl-names = "default";
 600         pinctrl-0 = <&uart3_xfer>;
 601 };
 602
 603 &wdt {
 604         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 605 };