git.sur5r.net Git - u-boot/blob - arch/arm/dts/rk3328.dtsi

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/clock/rk3328-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12
  13 / {
  14         compatible = "rockchip,rk3328";
  15
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 mmc0 = &emmc;
  29                 mmc1 = &sdmmc;
  30                 mmc2 = &sdmmc_ext;
  31         };
  32
  33         cpus {
  34                 #address-cells = <2>;
  35                 #size-cells = <0>;
  36
  37                 cpu0: cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         reg = <0x0 0x0>;
  41                         enable-method = "psci";
  42 //                      clocks = <&cru ARMCLK>;
  43                         operating-points-v2 = <&cpu0_opp_table>;
  44                 };
  45                 cpu1: cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a53", "arm,armv8";
  48                         reg = <0x0 0x1>;
  49                         enable-method = "psci";
  50                 };
  51                 cpu2: cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0x0 0x2>;
  55                         enable-method = "psci";
  56                 };
  57                 cpu3: cpu@3 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a53", "arm,armv8";
  60                         reg = <0x0 0x3>;
  61                         enable-method = "psci";
  62                 };
  63         };
  64
  65         cpu0_opp_table: opp_table0 {
  66                 compatible = "operating-points-v2";
  67                 opp-shared;
  68
  69                 opp@408000000 {
  70                         opp-hz = /bits/ 64 <408000000>;
  71                         opp-microvolt = <950000>;
  72                         clock-latency-ns = <40000>;
  73                         opp-suspend;
  74                 };
  75                 opp@600000000 {
  76                         opp-hz = /bits/ 64 <600000000>;
  77                         opp-microvolt = <950000>;
  78                         clock-latency-ns = <40000>;
  79                 };
  80                 opp@816000000 {
  81                         opp-hz = /bits/ 64 <816000000>;
  82                         opp-microvolt = <1000000>;
  83                         clock-latency-ns = <40000>;
  84                 };
  85                 opp@1008000000 {
  86                         opp-hz = /bits/ 64 <1008000000>;
  87                         opp-microvolt = <1100000>;
  88                         clock-latency-ns = <40000>;
  89                 };
  90                 opp@1200000000 {
  91                         opp-hz = /bits/ 64 <1200000000>;
  92                         opp-microvolt = <1225000>;
  93                         clock-latency-ns = <40000>;
  94                 };
  95                 opp@1296000000 {
  96                         opp-hz = /bits/ 64 <1296000000>;
  97                         opp-microvolt = <1300000>;
  98                         clock-latency-ns = <40000>;
  99                 };
 100         };
 101
 102         arm-pmu {
 103                 compatible = "arm,cortex-a53-pmu";
 104                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 107                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 108                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 109         };
 110
 111         psci {
 112                 compatible = "arm,psci-1.0";
 113                 method = "smc";
 114         };
 115
 116         timer {
 117                 compatible = "arm,armv8-timer";
 118                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 119                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 120                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 121                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 122         };
 123
 124         xin24m: xin24m {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <24000000>;
 128                 clock-output-names = "xin24m";
 129         };
 130
 131         i2s0: i2s@ff000000 {
 132                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 133                 reg = <0x0 0xff000000 0x0 0x1000>;
 134                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 135                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 136                 clock-names = "i2s_clk", "i2s_hclk";
 137                 dmas = <&dmac 11>, <&dmac 12>;
 138                 #dma-cells = <2>;
 139                 dma-names = "tx", "rx";
 140                 status = "disabled";
 141         };
 142
 143         i2s1: i2s@ff010000 {
 144                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 145                 reg = <0x0 0xff010000 0x0 0x1000>;
 146                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 147                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 148                 clock-names = "i2s_clk", "i2s_hclk";
 149                 dmas = <&dmac 14>, <&dmac 15>;
 150                 #dma-cells = <2>;
 151                 dma-names = "tx", "rx";
 152                 status = "disabled";
 153         };
 154
 155         i2s2: i2s@ff020000 {
 156                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 157                 reg = <0x0 0xff020000 0x0 0x1000>;
 158                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 159                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 160                 clock-names = "i2s_clk", "i2s_hclk";
 161                 dmas = <&dmac 0>, <&dmac 1>;
 162                 #dma-cells = <2>;
 163                 dma-names = "tx", "rx";
 164                 pinctrl-names = "default", "sleep";
 165                 pinctrl-0 = <&i2s2m0_mclk
 166                              &i2s2m0_sclk
 167                              &i2s2m0_lrcktx
 168                              &i2s2m0_lrckrx
 169                              &i2s2m0_sdo
 170                              &i2s2m0_sdi>;
 171                 pinctrl-1 = <&i2s2m0_sleep>;
 172                 status = "disabled";
 173         };
 174
 175         spdif: spdif@ff030000 {
 176                 compatible = "rockchip,rk3328-spdif";
 177                 reg = <0x0 0xff030000 0x0 0x1000>;
 178                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 180                 clock-names = "mclk", "hclk";
 181                 dmas = <&dmac 10>;
 182                 #dma-cells = <1>;
 183                 dma-names = "tx";
 184                 pinctrl-names = "default";
 185                 pinctrl-0 = <&spdifm2_tx>;
 186                 status = "disabled";
 187         };
 188
 189         grf: syscon@ff100000 {
 190                 u-boot,dm-pre-reloc;
 191                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 192                 reg = <0x0 0xff100000 0x0 0x1000>;
 193                 #address-cells = <1>;
 194                 #size-cells = <1>;
 195
 196                 io_domains: io-domains {
 197                         compatible = "rockchip,rk3328-io-voltage-domain";
 198                         status = "disabled";
 199                 };
 200         };
 201
 202         uart0: serial@ff110000 {
 203                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 204                 reg = <0x0 0xff110000 0x0 0x100>;
 205                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 206                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 207                 clock-names = "baudclk", "apb_pclk";
 208                 reg-shift = <2>;
 209                 reg-io-width = <4>;
 210                 dmas = <&dmac 2>, <&dmac 3>;
 211                 #dma-cells = <2>;
 212                 pinctrl-names = "default";
 213                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 214                 status = "disabled";
 215         };
 216
 217         uart1: serial@ff120000 {
 218                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 219                 reg = <0x0 0xff120000 0x0 0x100>;
 220                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 222                 clock-names = "sclk_uart", "pclk_uart";
 223                 reg-shift = <2>;
 224                 reg-io-width = <4>;
 225                 dmas = <&dmac 4>, <&dmac 5>;
 226                 #dma-cells = <2>;
 227                 pinctrl-names = "default";
 228                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 229                 status = "disabled";
 230         };
 231
 232         uart2: serial@ff130000 {
 233                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 234                 reg = <0x0 0xff130000 0x0 0x100>;
 235                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 237                 clock-names = "baudclk", "apb_pclk";
 238                 clock-frequency = <24000000>;
 239                 reg-shift = <2>;
 240                 reg-io-width = <4>;
 241                 dmas = <&dmac 6>, <&dmac 7>;
 242                 #dma-cells = <2>;
 243                 pinctrl-names = "default";
 244                 pinctrl-0 = <&uart2m1_xfer>;
 245                 status = "disabled";
 246         };
 247
 248         pmu: power-management@ff140000 {
 249                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 250                 reg = <0x0 0xff140000 0x0 0x1000>;
 251         };
 252
 253         i2c0: i2c@ff150000 {
 254                 compatible = "rockchip,rk3328-i2c";
 255                 reg = <0x0 0xff150000 0x0 0x1000>;
 256                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 257                 #address-cells = <1>;
 258                 #size-cells = <0>;
 259                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 260                 clock-names = "i2c", "pclk";
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&i2c0_xfer>;
 263                 status = "disabled";
 264         };
 265
 266         i2c1: i2c@ff160000 {
 267                 compatible = "rockchip,rk3328-i2c";
 268                 reg = <0x0 0xff160000 0x0 0x1000>;
 269                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 270                 #address-cells = <1>;
 271                 #size-cells = <0>;
 272                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 273                 clock-names = "i2c", "pclk";
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&i2c1_xfer>;
 276                 status = "disabled";
 277         };
 278
 279         i2c2: i2c@ff170000 {
 280                 compatible = "rockchip,rk3328-i2c";
 281                 reg = <0x0 0xff170000 0x0 0x1000>;
 282                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 286                 clock-names = "i2c", "pclk";
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&i2c2_xfer>;
 289                 status = "disabled";
 290         };
 291
 292         i2c3: i2c@ff180000 {
 293                 compatible = "rockchip,rk3328-i2c";
 294                 reg = <0x0 0xff180000 0x0 0x1000>;
 295                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 296                 #address-cells = <1>;
 297                 #size-cells = <0>;
 298                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 299                 clock-names = "i2c", "pclk";
 300                 pinctrl-names = "default";
 301                 pinctrl-0 = <&i2c3_xfer>;
 302                 status = "disabled";
 303         };
 304
 305         spi0: spi@ff190000 {
 306                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 307                 reg = <0x0 0xff190000 0x0 0x1000>;
 308                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 312                 clock-names = "spiclk", "apb_pclk";
 313                 dmas = <&dmac 8>, <&dmac 9>;
 314                 #dma-cells = <2>;
 315                 dma-names = "tx", "rx";
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 318                 status = "disabled";
 319         };
 320
 321         wdt: watchdog@ff1a0000 {
 322                 compatible = "snps,dw-wdt";
 323                 reg = <0x0 0xff1a0000 0x0 0x100>;
 324                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 325                 status = "disabled";
 326         };
 327
 328         amba {
 329                 compatible = "simple-bus";
 330                 #address-cells = <2>;
 331                 #size-cells = <2>;
 332                 ranges;
 333
 334                 dmac: dmac@ff1f0000 {
 335                         compatible = "arm,pl330", "arm,primecell";
 336                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 337                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 338                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 339                         clocks = <&cru ACLK_DMAC>;
 340                         clock-names = "apb_pclk";
 341                         #dma-cells = <1>;
 342                 };
 343         };
 344
 345         saradc: saradc@ff280000 {
 346                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 347                 reg = <0x0 0xff280000 0x0 0x100>;
 348                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 349                 #io-channel-cells = <1>;
 350                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 351                 clock-names = "saradc", "apb_pclk";
 352                 resets = <&cru SRST_SARADC_P>;
 353                 reset-names = "saradc-apb";
 354                 status = "disabled";
 355         };
 356
 357         dmc: dmc@ff400000 {
 358                 u-boot,dm-pre-reloc;
 359                 compatible = "rockchip,rk3328-dmc", "syscon";
 360                 reg = <0x0 0xff400000 0x0 0x1000>;
 361         };
 362
 363         cru: clock-controller@ff440000 {
 364                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 365                 reg = <0x0 0xff440000 0x0 0x1000>;
 366                 rockchip,grf = <&grf>;
 367                 #clock-cells = <1>;
 368                 #reset-cells = <1>;
 369                 assigned-clocks =
 370                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 371                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 372                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 373                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 374                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 375                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 376                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 377                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 378                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 379                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 380                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 381                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 382                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 383                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 384                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 385                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 386                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 387                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 388                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 389                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 390                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 391                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 392                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 393                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 394                 assigned-clock-parents =
 395                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 396                         <&cru PLL_GPLL>, <&xin24m>,
 397                         <&xin24m>, <&xin24m>;
 398                 assigned-clock-rates =
 399                         <0>, <61440000>,
 400                         <0>, <24000000>,
 401                         <24000000>, <24000000>,
 402                         <15000000>, <15000000>,
 403                         <100000000>, <100000000>,
 404                         <100000000>, <100000000>,
 405                         <50000000>, <100000000>,
 406                         <100000000>, <100000000>,
 407                         <50000000>, <50000000>,
 408                         <50000000>, <50000000>,
 409                         <24000000>, <600000000>,
 410                         <491520000>, <1200000000>,
 411                         <150000000>, <75000000>,
 412                         <75000000>, <150000000>,
 413                         <75000000>, <75000000>,
 414                         <300000000>, <100000000>,
 415                         <300000000>, <200000000>,
 416                         <400000000>, <500000000>,
 417                         <200000000>, <300000000>,
 418                         <300000000>, <250000000>,
 419                         <200000000>, <100000000>,
 420                         <24000000>, <100000000>,
 421                         <150000000>, <50000000>,
 422                         <32768>, <32768>;
 423         };
 424
 425         sdmmc: rksdmmc@ff500000 {
 426                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 427                 reg = <0x0 0xff500000 0x0 0x4000>;
 428                 max-frequency = <150000000>;
 429                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 430                 clock-names = "biu", "ciu";
 431                 fifo-depth = <0x100>;
 432                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 433                 status = "disabled";
 434         };
 435
 436         sdio: dwmmc@ff510000 {
 437                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 438                 reg = <0x0 0xff510000 0x0 0x4000>;
 439                 max-frequency = <150000000>;
 440                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 441                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 442                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 443                 fifo-depth = <0x100>;
 444                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 445                 status = "disabled";
 446         };
 447
 448         emmc: rksdmmc@ff520000 {
 449                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 450                 reg = <0x0 0xff520000 0x0 0x4000>;
 451                 max-frequency = <150000000>;
 452                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 453                 clock-names = "biu", "ciu";
 454                 fifo-depth = <0x100>;
 455                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 456                 status = "disabled";
 457         };
 458
 459         gmac2io: ethernet@ff540000 {
 460                 compatible = "rockchip,rk3328-gmac";
 461                 reg = <0x0 0xff540000 0x0 0x10000>;
 462                 rockchip,grf = <&grf>;
 463                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 464                 interrupt-names = "macirq";
 465                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 466                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 467                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 468                          <&cru PCLK_MAC2IO>;
 469                 clock-names = "stmmaceth", "mac_clk_rx",
 470                               "mac_clk_tx", "clk_mac_ref",
 471                               "clk_mac_refout", "aclk_mac",
 472                               "pclk_mac";
 473                 resets = <&cru SRST_GMAC2IO_A>;
 474                 reset-names = "stmmaceth";
 475                 status = "disabled";
 476         };
 477
 478         usb_host0_ehci: usb@ff5c0000 {
 479                 compatible = "generic-ehci";
 480                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 481                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 482                 status = "disabled";
 483         };
 484
 485         usb_host0_ohci: usb@ff5d0000 {
 486                 compatible = "generic-ohci";
 487                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 488                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 489                 status = "disabled";
 490         };
 491
 492         usb20_otg: usb@ff580000 {
 493                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 494                              "snps,dwc2";
 495                 reg = <0x0 0xff580000 0x0 0x40000>;
 496                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 497                 hnp-srp-disable;
 498                 dr_mode = "otg";
 499                 status = "disabled";
 500         };
 501
 502         sdmmc_ext: rksdmmc@ff5f0000 {
 503                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 504                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 505                 max-frequency = <150000000>;
 506                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 507                 clock-names = "biu", "ciu";
 508                 fifo-depth = <0x100>;
 509                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 510                 status = "disabled";
 511         };
 512
 513         usb_host0_xhci: usb@ff600000 {
 514                 compatible = "rockchip,rk3328-xhci";
 515                 reg = <0x0 0xff600000 0x0 0x100000>;
 516                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 517                 snps,dis-enblslpm-quirk;
 518                 snps,phyif-utmi-bits = <16>;
 519                 snps,dis-u2-freeclk-exists-quirk;
 520                 snps,dis-u2-susphy-quirk;
 521                 status = "disabled";
 522         };
 523
 524         gic: interrupt-controller@ffb70000 {
 525                 compatible = "arm,gic-400";
 526                 #interrupt-cells = <3>;
 527                 #address-cells = <0>;
 528                 interrupt-controller;
 529                 reg = <0x0 0xff811000 0 0x1000>,
 530                       <0x0 0xff812000 0 0x2000>,
 531                       <0x0 0xff814000 0 0x2000>,
 532                       <0x0 0xff816000 0 0x2000>;
 533                 interrupts = <GIC_PPI 9
 534                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 535         };
 536
 537         pinctrl: pinctrl {
 538                 compatible = "rockchip,rk3328-pinctrl";
 539                 rockchip,grf = <&grf>;
 540                 #address-cells = <2>;
 541                 #size-cells = <2>;
 542                 ranges;
 543
 544                 gpio0: gpio0@ff210000 {
 545                         compatible = "rockchip,gpio-bank";
 546                         reg = <0x0 0xff210000 0x0 0x100>;
 547                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 548                         clocks = <&cru PCLK_GPIO0>;
 549
 550                         gpio-controller;
 551                         #gpio-cells = <2>;
 552
 553                         interrupt-controller;
 554                         #interrupt-cells = <2>;
 555                 };
 556
 557                 gpio1: gpio1@ff220000 {
 558                         compatible = "rockchip,gpio-bank";
 559                         reg = <0x0 0xff220000 0x0 0x100>;
 560                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 561                         clocks = <&cru PCLK_GPIO1>;
 562
 563                         gpio-controller;
 564                         #gpio-cells = <2>;
 565
 566                         interrupt-controller;
 567                         #interrupt-cells = <2>;
 568                 };
 569
 570                 gpio2: gpio2@ff230000 {
 571                         compatible = "rockchip,gpio-bank";
 572                         reg = <0x0 0xff230000 0x0 0x100>;
 573                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&cru PCLK_GPIO2>;
 575
 576                         gpio-controller;
 577                         #gpio-cells = <2>;
 578
 579                         interrupt-controller;
 580                         #interrupt-cells = <2>;
 581                 };
 582
 583                 gpio3: gpio3@ff240000 {
 584                         compatible = "rockchip,gpio-bank";
 585                         reg = <0x0 0xff240000 0x0 0x100>;
 586                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 587                         clocks = <&cru PCLK_GPIO3>;
 588
 589                         gpio-controller;
 590                         #gpio-cells = <2>;
 591
 592                         interrupt-controller;
 593                         #interrupt-cells = <2>;
 594                 };
 595
 596                 pcfg_pull_up: pcfg-pull-up {
 597                         bias-pull-up;
 598                 };
 599
 600                 pcfg_pull_down: pcfg-pull-down {
 601                         bias-pull-down;
 602                 };
 603
 604                 pcfg_pull_none: pcfg-pull-none {
 605                         bias-disable;
 606                 };
 607
 608                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 609                         bias-disable;
 610                         drive-strength = <2>;
 611                 };
 612
 613                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 614                         bias-pull-up;
 615                         drive-strength = <2>;
 616                 };
 617
 618                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 619                         bias-pull-up;
 620                         drive-strength = <4>;
 621                 };
 622
 623                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 624                         bias-disable;
 625                         drive-strength = <4>;
 626                 };
 627
 628                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 629                         bias-pull-down;
 630                         drive-strength = <4>;
 631                 };
 632
 633                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 634                         bias-disable;
 635                         drive-strength = <8>;
 636                 };
 637
 638                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 639                         bias-pull-up;
 640                         drive-strength = <8>;
 641                 };
 642
 643                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 644                         bias-disable;
 645                         drive-strength = <12>;
 646                 };
 647
 648                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 649                         bias-pull-up;
 650                         drive-strength = <12>;
 651                 };
 652
 653                 pcfg_output_high: pcfg-output-high {
 654                         output-high;
 655                 };
 656
 657                 pcfg_output_low: pcfg-output-low {
 658                         output-low;
 659                 };
 660
 661                 pcfg_input_high: pcfg-input-high {
 662                         bias-pull-up;
 663                         input-enable;
 664                 };
 665
 666                 pcfg_input: pcfg-input {
 667                         input-enable;
 668                 };
 669
 670                 i2c0 {
 671                         i2c0_xfer: i2c0-xfer {
 672                                 rockchip,pins =
 673                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 674                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 675                         };
 676                 };
 677
 678                 i2c1 {
 679                         i2c1_xfer: i2c1-xfer {
 680                                 rockchip,pins =
 681                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 682                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 683                         };
 684                 };
 685
 686                 i2c2 {
 687                         i2c2_xfer: i2c2-xfer {
 688                                 rockchip,pins =
 689                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 690                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 691                         };
 692                 };
 693
 694                 i2c3 {
 695                         i2c3_xfer: i2c3-xfer {
 696                                 rockchip,pins =
 697                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 698                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 699                         };
 700                         i2c3_gpio: i2c3-gpio {
 701                                 rockchip,pins =
 702                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 703                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 704                         };
 705                 };
 706
 707                 hdmi_i2c {
 708                         hdmii2c_xfer: hdmii2c-xfer {
 709                                 rockchip,pins =
 710                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 711                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 712                         };
 713                 };
 714
 715                 uart0 {
 716                         uart0_xfer: uart0-xfer {
 717                                 rockchip,pins =
 718                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 719                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 720                         };
 721
 722                         uart0_cts: uart0-cts {
 723                                 rockchip,pins =
 724                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 725                         };
 726
 727                         uart0_rts: uart0-rts {
 728                                 rockchip,pins =
 729                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 730                         };
 731
 732                         uart0_rts_gpio: uart0-rts-gpio {
 733                                 rockchip,pins =
 734                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 735                         };
 736                 };
 737
 738                 uart1 {
 739                         uart1_xfer: uart1-xfer {
 740                                 rockchip,pins =
 741                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 742                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 743                         };
 744
 745                         uart1_cts: uart1-cts {
 746                                 rockchip,pins =
 747                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 748                         };
 749
 750                         uart1_rts: uart1-rts {
 751                                 rockchip,pins =
 752                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 753                         };
 754
 755                         uart1_rts_gpio: uart1-rts-gpio {
 756                                 rockchip,pins =
 757                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 758                         };
 759                 };
 760
 761                 uart2-0 {
 762                         uart2m0_xfer: uart2m0-xfer {
 763                                 rockchip,pins =
 764                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 765                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 766                         };
 767                 };
 768
 769                 uart2-1 {
 770                         uart2m1_xfer: uart2m1-xfer {
 771                                 rockchip,pins =
 772                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 773                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 774                         };
 775                 };
 776
 777                 spi0-0 {
 778                         spi0m0_clk: spi0m0-clk {
 779                                 rockchip,pins =
 780                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 781                         };
 782
 783                         spi0m0_cs0: spi0m0-cs0 {
 784                                 rockchip,pins =
 785                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 786                         };
 787
 788                         spi0m0_tx: spi0m0-tx {
 789                                 rockchip,pins =
 790                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 791                         };
 792
 793                         spi0m0_rx: spi0m0-rx {
 794                                 rockchip,pins =
 795                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 796                         };
 797
 798                         spi0m0_cs1: spi0m0-cs1 {
 799                                 rockchip,pins =
 800                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 801                         };
 802                 };
 803
 804                 spi0-1 {
 805                         spi0m1_clk: spi0m1-clk {
 806                                 rockchip,pins =
 807                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
 808                         };
 809
 810                         spi0m1_cs0: spi0m1-cs0 {
 811                                 rockchip,pins =
 812                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
 813                         };
 814
 815                         spi0m1_tx: spi0m1-tx {
 816                                 rockchip,pins =
 817                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
 818                         };
 819
 820                         spi0m1_rx: spi0m1-rx {
 821                                 rockchip,pins =
 822                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
 823                         };
 824
 825                         spi0m1_cs1: spi0m1-cs1 {
 826                                 rockchip,pins =
 827                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
 828                         };
 829                 };
 830
 831                 spi0-2 {
 832                         spi0m2_clk: spi0m2-clk {
 833                                 rockchip,pins =
 834                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
 835                         };
 836
 837                         spi0m2_cs0: spi0m2-cs0 {
 838                                 rockchip,pins =
 839                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
 840                         };
 841
 842                         spi0m2_tx: spi0m2-tx {
 843                                 rockchip,pins =
 844                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
 845                         };
 846
 847                         spi0m2_rx: spi0m2-rx {
 848                                 rockchip,pins =
 849                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
 850                         };
 851                 };
 852
 853                 i2s1 {
 854                         i2s1_mclk: i2s1-mclk {
 855                                 rockchip,pins =
 856                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
 857                         };
 858
 859                         i2s1_sclk: i2s1-sclk {
 860                                 rockchip,pins =
 861                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 862                         };
 863
 864                         i2s1_lrckrx: i2s1-lrckrx {
 865                                 rockchip,pins =
 866                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
 867                         };
 868
 869                         i2s1_lrcktx: i2s1-lrcktx {
 870                                 rockchip,pins =
 871                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 872                         };
 873
 874                         i2s1_sdi: i2s1-sdi {
 875                                 rockchip,pins =
 876                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 877                         };
 878
 879                         i2s1_sdo: i2s1-sdo {
 880                                 rockchip,pins =
 881                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
 882                         };
 883
 884                         i2s1_sdio1: i2s1-sdio1 {
 885                                 rockchip,pins =
 886                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
 887                         };
 888
 889                         i2s1_sdio2: i2s1-sdio2 {
 890                                 rockchip,pins =
 891                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
 892                         };
 893
 894                         i2s1_sdio3: i2s1-sdio3 {
 895                                 rockchip,pins =
 896                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
 897                         };
 898
 899                         i2s1_sleep: i2s1-sleep {
 900                                 rockchip,pins =
 901                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
 902                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
 903                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
 904                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
 905                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
 906                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
 907                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
 908                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
 909                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
 910                         };
 911                 };
 912
 913                 i2s2-0 {
 914                         i2s2m0_mclk: i2s2m0-mclk {
 915                                 rockchip,pins =
 916                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 917                         };
 918
 919                         i2s2m0_sclk: i2s2m0-sclk {
 920                                 rockchip,pins =
 921                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
 922                         };
 923
 924                         i2s2m0_lrckrx: i2s2m0-lrckrx {
 925                                 rockchip,pins =
 926                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
 927                         };
 928
 929                         i2s2m0_lrcktx: i2s2m0-lrcktx {
 930                                 rockchip,pins =
 931                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
 932                         };
 933
 934                         i2s2m0_sdi: i2s2m0-sdi {
 935                                 rockchip,pins =
 936                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
 937                         };
 938
 939                         i2s2m0_sdo: i2s2m0-sdo {
 940                                 rockchip,pins =
 941                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
 942                         };
 943
 944                         i2s2m0_sleep: i2s2m0-sleep {
 945                                 rockchip,pins =
 946                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 947                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
 948                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
 949                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
 950                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
 951                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
 952                         };
 953                 };
 954
 955                 i2s2-1 {
 956                         i2s2m1_mclk: i2s2m1-mclk {
 957                                 rockchip,pins =
 958                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 959                         };
 960
 961                         i2s2m1_sclk: i2s2m1-sclk {
 962                                 rockchip,pins =
 963                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
 964                         };
 965
 966                         i2s2m1_lrckrx: i2sm1-lrckrx {
 967                                 rockchip,pins =
 968                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
 969                         };
 970
 971                         i2s2m1_lrcktx: i2s2m1-lrcktx {
 972                                 rockchip,pins =
 973                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
 974                         };
 975
 976                         i2s2m1_sdi: i2s2m1-sdi {
 977                                 rockchip,pins =
 978                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
 979                         };
 980
 981                         i2s2m1_sdo: i2s2m1-sdo {
 982                                 rockchip,pins =
 983                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
 984                         };
 985
 986                         i2s2m1_sleep: i2s2m1-sleep {
 987                                 rockchip,pins =
 988                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 989                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
 990                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
 991                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
 992                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
 993                         };
 994                 };
 995
 996                 spdif-0 {
 997                         spdifm0_tx: spdifm0-tx {
 998                                 rockchip,pins =
 999                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
1000                         };
1001                 };
1002
1003                 spdif-1 {
1004                         spdifm1_tx: spdifm1-tx {
1005                                 rockchip,pins =
1006                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1007                         };
1008                 };
1009
1010                 spdif-2 {
1011                         spdifm2_tx: spdifm2-tx {
1012                                 rockchip,pins =
1013                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
1014                         };
1015                 };
1016
1017                 sdmmc0-0 {
1018                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1019                                 rockchip,pins =
1020                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1021                         };
1022
1023                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1024                                 rockchip,pins =
1025                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1026                         };
1027                 };
1028
1029                 sdmmc0-1 {
1030                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1031                                 rockchip,pins =
1032                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1033                         };
1034
1035                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1036                                 rockchip,pins =
1037                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1038                         };
1039                 };
1040
1041                 sdmmc0 {
1042                         sdmmc0_clk: sdmmc0-clk {
1043                                 rockchip,pins =
1044                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1045                         };
1046
1047                         sdmmc0_cmd: sdmmc0-cmd {
1048                                 rockchip,pins =
1049                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1050                         };
1051
1052                         sdmmc0_dectn: sdmmc0-dectn {
1053                                 rockchip,pins =
1054                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1055                         };
1056
1057                         sdmmc0_wrprt: sdmmc0-wrprt {
1058                                 rockchip,pins =
1059                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1060                         };
1061
1062                         sdmmc0_bus1: sdmmc0-bus1 {
1063                                 rockchip,pins =
1064                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1065                         };
1066
1067                         sdmmc0_bus4: sdmmc0-bus4 {
1068                                 rockchip,pins =
1069                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1070                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1071                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1072                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1073                         };
1074
1075                         sdmmc0_gpio: sdmmc0-gpio {
1076                                 rockchip,pins =
1077                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1078                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1079                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1080                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1081                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1082                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1083                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1084                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1085                         };
1086                 };
1087
1088                 sdmmc0ext {
1089                         sdmmc0ext_clk: sdmmc0ext-clk {
1090                                 rockchip,pins =
1091                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1092                         };
1093
1094                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1095                                 rockchip,pins =
1096                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1097                         };
1098
1099                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1100                                 rockchip,pins =
1101                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1102                         };
1103
1104                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1105                                 rockchip,pins =
1106                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1107                         };
1108
1109                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1110                                 rockchip,pins =
1111                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1112                         };
1113
1114                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1115                                 rockchip,pins =
1116                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1117                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1118                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1119                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1120                         };
1121
1122                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1123                                 rockchip,pins =
1124                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1125                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1126                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1127                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1128                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1129                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1130                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1131                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1132                         };
1133                 };
1134
1135                 sdmmc1 {
1136                         sdmmc1_clk: sdmmc1-clk {
1137                                 rockchip,pins =
1138                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1139                         };
1140
1141                         sdmmc1_cmd: sdmmc1-cmd {
1142                                 rockchip,pins =
1143                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1144                         };
1145
1146                         sdmmc1_pwren: sdmmc1-pwren {
1147                                 rockchip,pins =
1148                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1149                         };
1150
1151                         sdmmc1_wrprt: sdmmc1-wrprt {
1152                                 rockchip,pins =
1153                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1154                         };
1155
1156                         sdmmc1_dectn: sdmmc1-dectn {
1157                                 rockchip,pins =
1158                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1159                         };
1160
1161                         sdmmc1_bus1: sdmmc1-bus1 {
1162                                 rockchip,pins =
1163                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1164                         };
1165
1166                         sdmmc1_bus4: sdmmc1-bus4 {
1167                                 rockchip,pins =
1168                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1169                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1170                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1171                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1172                         };
1173
1174                         sdmmc1_gpio: sdmmc1-gpio {
1175                                 rockchip,pins =
1176                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1177                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1178                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1179                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1180                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1181                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1182                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1183                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1184                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1185                         };
1186                 };
1187
1188                 emmc {
1189                         emmc_clk: emmc-clk {
1190                                 rockchip,pins =
1191                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1192                         };
1193
1194                         emmc_cmd: emmc-cmd {
1195                                 rockchip,pins =
1196                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1197                         };
1198
1199                         emmc_pwren: emmc-pwren {
1200                                 rockchip,pins =
1201                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1202                         };
1203
1204                         emmc_rstnout: emmc-rstnout {
1205                                 rockchip,pins =
1206                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1207                         };
1208
1209                         emmc_bus1: emmc-bus1 {
1210                                 rockchip,pins =
1211                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1212                         };
1213
1214                         emmc_bus4: emmc-bus4 {
1215                                 rockchip,pins =
1216                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1217                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1218                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1219                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1220                         };
1221
1222                         emmc_bus8: emmc-bus8 {
1223                                 rockchip,pins =
1224                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1225                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1226                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1227                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1228                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1229                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1230                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1231                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1232                         };
1233                 };
1234
1235                 pwm0 {
1236                         pwm0_pin: pwm0-pin {
1237                                 rockchip,pins =
1238                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1239                         };
1240                 };
1241
1242                 pwm1 {
1243                         pwm1_pin: pwm1-pin {
1244                                 rockchip,pins =
1245                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1246                         };
1247                 };
1248
1249                 pwm2 {
1250                         pwm2_pin: pwm2-pin {
1251                                 rockchip,pins =
1252                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1253                         };
1254                 };
1255
1256                 pwmir {
1257                         pwmir_pin: pwmir-pin {
1258                                 rockchip,pins =
1259                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1260                         };
1261                 };
1262
1263                 gmac-0 {
1264                         rgmiim0_pins: rgmiim0-pins {
1265                                 rockchip,pins =
1266                                         /* mac_txclk */
1267                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1268                                         /* mac_rxclk */
1269                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1270                                         /* mac_mdio */
1271                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1272                                         /* mac_txen */
1273                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1274                                         /* mac_clk */
1275                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1276                                         /* mac_rxdv */
1277                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1278                                         /* mac_mdc */
1279                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1280                                         /* mac_rxd1 */
1281                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1282                                         /* mac_rxd0 */
1283                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1284                                         /* mac_txd1 */
1285                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1286                                         /* mac_txd0 */
1287                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1288                                         /* mac_rxd3 */
1289                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1290                                         /* mac_rxd2 */
1291                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1292                                         /* mac_txd3 */
1293                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1294                                         /* mac_txd2 */
1295                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1296                         };
1297
1298                         rmiim0_pins: rmiim0-pins {
1299                                 rockchip,pins =
1300                                         /* mac_mdio */
1301                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1302                                         /* mac_txen */
1303                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1304                                         /* mac_clk */
1305                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1306                                         /* mac_rxer */
1307                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1308                                         /* mac_rxdv */
1309                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1310                                         /* mac_mdc */
1311                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1312                                         /* mac_rxd1 */
1313                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1314                                         /* mac_rxd0 */
1315                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1316                                         /* mac_txd1 */
1317                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1318                                         /* mac_txd0 */
1319                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1320                         };
1321                 };
1322
1323                 gmac-1 {
1324                         rgmiim1_pins: rgmiim1-pins {
1325                                 rockchip,pins =
1326                                         /* mac_txclk */
1327                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1328                                         /* mac_rxclk */
1329                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1330                                         /* mac_mdio */
1331                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1332                                         /* mac_txen */
1333                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1334                                         /* mac_clk */
1335                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1336                                         /* mac_rxdv */
1337                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1338                                         /* mac_mdc */
1339                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1340                                         /* mac_rxd1 */
1341                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1342                                         /* mac_rxd0 */
1343                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1344                                         /* mac_txd1 */
1345                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1346                                         /* mac_txd0 */
1347                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1348                                         /* mac_rxd3 */
1349                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1350                                         /* mac_rxd2 */
1351                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1352                                         /* mac_txd3 */
1353                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1354                                         /* mac_txd2 */
1355                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1356
1357                                         /* mac_txclk */
1358                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1359                                         /* mac_txen */
1360                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1361                                         /* mac_clk */
1362                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1363                                         /* mac_txd1 */
1364                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1365                                         /* mac_txd0 */
1366                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1367                                         /* mac_txd3 */
1368                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1369                                         /* mac_txd2 */
1370                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1371                         };
1372
1373                         rmiim1_pins: rmiim1-pins {
1374                                 rockchip,pins =
1375                                         /* mac_mdio */
1376                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1377                                         /* mac_txen */
1378                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1379                                         /* mac_clk */
1380                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1381                                         /* mac_rxer */
1382                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1383                                         /* mac_rxdv */
1384                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1385                                         /* mac_mdc */
1386                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1387                                         /* mac_rxd1 */
1388                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1389                                         /* mac_rxd0 */
1390                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1391                                         /* mac_txd1 */
1392                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1393                                         /* mac_txd0 */
1394                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1395
1396                                         /* mac_mdio */
1397                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1398                                         /* mac_txen */
1399                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1400                                         /* mac_clk */
1401                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1402                                         /* mac_mdc */
1403                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1404                                         /* mac_txd1 */
1405                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1406                                         /* mac_txd0 */
1407                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1408                         };
1409                 };
1410
1411                 gmac2phy {
1412                         fephyled_speed100: fephyled-speed100 {
1413                                 rockchip,pins =
1414                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1415                         };
1416
1417                         fephyled_speed10: fephyled-speed10 {
1418                                 rockchip,pins =
1419                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1420                         };
1421
1422                         fephyled_duplex: fephyled-duplex {
1423                                 rockchip,pins =
1424                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1425                         };
1426
1427                         fephyled_rxm0: fephyled-rxm0 {
1428                                 rockchip,pins =
1429                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1430                         };
1431
1432                         fephyled_txm0: fephyled-txm0 {
1433                                 rockchip,pins =
1434                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1435                         };
1436
1437                         fephyled_linkm0: fephyled-linkm0 {
1438                                 rockchip,pins =
1439                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1440                         };
1441
1442                         fephyled_rxm1: fephyled-rxm1 {
1443                                 rockchip,pins =
1444                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1445                         };
1446
1447                         fephyled_txm1: fephyled-txm1 {
1448                                 rockchip,pins =
1449                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1450                         };
1451
1452                         fephyled_linkm1: fephyled-linkm1 {
1453                                 rockchip,pins =
1454                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1455                         };
1456                 };
1457
1458                 tsadc_pin {
1459                         tsadc_int: tsadc-int {
1460                                 rockchip,pins =
1461                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1462                         };
1463                         tsadc_gpio: tsadc-gpio {
1464                                 rockchip,pins =
1465                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1466                         };
1467                 };
1468
1469                 hdmi_pin {
1470                         hdmi_cec: hdmi-cec {
1471                                 rockchip,pins =
1472                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1473                         };
1474
1475                         hdmi_hpd: hdmi-hpd {
1476                                 rockchip,pins =
1477                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1478                         };
1479                 };
1480
1481                 cif-0 {
1482                         dvp_d2d9_m0:dvp-d2d9-m0 {
1483                                 rockchip,pins =
1484                                         /* cif_d0 */
1485                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1486                                         /* cif_d1 */
1487                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1488                                         /* cif_d2 */
1489                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1490                                         /* cif_d3 */
1491                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1492                                         /* cif_d4 */
1493                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1494                                         /* cif_d5m0 */
1495                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1496                                         /* cif_d6m0 */
1497                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1498                                         /* cif_d7m0 */
1499                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1500                                         /* cif_href */
1501                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1502                                         /* cif_vsync */
1503                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1504                                         /* cif_clkoutm0 */
1505                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1506                                         /* cif_clkin */
1507                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1508                         };
1509                 };
1510
1511                 cif-1 {
1512                         dvp_d2d9_m1:dvp-d2d9-m1 {
1513                                 rockchip,pins =
1514                                         /* cif_d0 */
1515                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1516                                         /* cif_d1 */
1517                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1518                                         /* cif_d2 */
1519                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1520                                         /* cif_d3 */
1521                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1522                                         /* cif_d4 */
1523                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1524                                         /* cif_d5m1 */
1525                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1526                                         /* cif_d6m1 */
1527                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1528                                         /* cif_d7m1 */
1529                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1530                                         /* cif_href */
1531                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1532                                         /* cif_vsync */
1533                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1534                                         /* cif_clkoutm1 */
1535                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1536                                         /* cif_clkin */
1537                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1538                         };
1539                 };
1540         };
1541 };