git.sur5r.net Git - u-boot/blob - arch/arm/dts/sun8i-h3.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "skeleton.dtsi"
  44
  45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/sun4i-a10.h>
  48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 ethernet0 = &emac;
  55         };
  56
  57         cpus {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 cpu@0 {
  62                         compatible = "arm,cortex-a7";
  63                         device_type = "cpu";
  64                         reg = <0>;
  65                 };
  66
  67                 cpu@1 {
  68                         compatible = "arm,cortex-a7";
  69                         device_type = "cpu";
  70                         reg = <1>;
  71                 };
  72
  73                 cpu@2 {
  74                         compatible = "arm,cortex-a7";
  75                         device_type = "cpu";
  76                         reg = <2>;
  77                 };
  78
  79                 cpu@3 {
  80                         compatible = "arm,cortex-a7";
  81                         device_type = "cpu";
  82                         reg = <3>;
  83                 };
  84         };
  85
  86         timer {
  87                 compatible = "arm,armv7-timer";
  88                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  89                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  92         };
  93
  94         clocks {
  95                 #address-cells = <1>;
  96                 #size-cells = <1>;
  97                 ranges;
  98
  99                 osc24M: osc24M_clk {
 100                         #clock-cells = <0>;
 101                         compatible = "fixed-clock";
 102                         clock-frequency = <24000000>;
 103                         clock-output-names = "osc24M";
 104                 };
 105
 106                 osc32k: osc32k_clk {
 107                         #clock-cells = <0>;
 108                         compatible = "fixed-clock";
 109                         clock-frequency = <32768>;
 110                         clock-output-names = "osc32k";
 111                 };
 112
 113                 apb0: apb0_clk {
 114                         compatible = "fixed-factor-clock";
 115                         #clock-cells = <0>;
 116                         clock-div = <1>;
 117                         clock-mult = <1>;
 118                         clocks = <&osc24M>;
 119                         clock-output-names = "apb0";
 120                 };
 121
 122                 apb0_gates: clk@01f01428 {
 123                         compatible = "allwinner,sun8i-h3-apb0-gates-clk",
 124                                      "allwinner,sun4i-a10-gates-clk";
 125                         reg = <0x01f01428 0x4>;
 126                         #clock-cells = <1>;
 127                         clocks = <&apb0>;
 128                         clock-indices = <0>, <1>;
 129                         clock-output-names = "apb0_pio", "apb0_ir";
 130                 };
 131
 132                 ir_clk: ir_clk@01f01454 {
 133                         compatible = "allwinner,sun4i-a10-mod0-clk";
 134                         reg = <0x01f01454 0x4>;
 135                         #clock-cells = <0>;
 136                         clocks = <&osc32k>, <&osc24M>;
 137                         clock-output-names = "ir";
 138                 };
 139         };
 140
 141         soc {
 142                 compatible = "simple-bus";
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 ranges;
 146
 147                 syscon: syscon@01c00000 {
 148                         compatible = "allwinner,sun8i-h3-syscon","syscon";
 149                         reg = <0x01c00000 0x34>;
 150                 };
 151
 152                 dma: dma-controller@01c02000 {
 153                         compatible = "allwinner,sun8i-h3-dma";
 154                         reg = <0x01c02000 0x1000>;
 155                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 156                         clocks = <&ccu CLK_BUS_DMA>;
 157                         resets = <&ccu RST_BUS_DMA>;
 158                         #dma-cells = <1>;
 159                 };
 160
 161                 mmc0: mmc@01c0f000 {
 162                         compatible = "allwinner,sun7i-a20-mmc",
 163                                      "allwinner,sun5i-a13-mmc";
 164                         reg = <0x01c0f000 0x1000>;
 165                         clocks = <&ccu CLK_BUS_MMC0>,
 166                                  <&ccu CLK_MMC0>,
 167                                  <&ccu CLK_MMC0_OUTPUT>,
 168                                  <&ccu CLK_MMC0_SAMPLE>;
 169                         clock-names = "ahb",
 170                                       "mmc",
 171                                       "output",
 172                                       "sample";
 173                         resets = <&ccu RST_BUS_MMC0>;
 174                         reset-names = "ahb";
 175                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 176                         status = "disabled";
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                 };
 180
 181                 mmc1: mmc@01c10000 {
 182                         compatible = "allwinner,sun7i-a20-mmc",
 183                                      "allwinner,sun5i-a13-mmc";
 184                         reg = <0x01c10000 0x1000>;
 185                         clocks = <&ccu CLK_BUS_MMC1>,
 186                                  <&ccu CLK_MMC1>,
 187                                  <&ccu CLK_MMC1_OUTPUT>,
 188                                  <&ccu CLK_MMC1_SAMPLE>;
 189                         clock-names = "ahb",
 190                                       "mmc",
 191                                       "output",
 192                                       "sample";
 193                         resets = <&ccu RST_BUS_MMC1>;
 194                         reset-names = "ahb";
 195                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 196                         status = "disabled";
 197                         #address-cells = <1>;
 198                         #size-cells = <0>;
 199                 };
 200
 201                 mmc2: mmc@01c11000 {
 202                         compatible = "allwinner,sun7i-a20-mmc",
 203                                      "allwinner,sun5i-a13-mmc";
 204                         reg = <0x01c11000 0x1000>;
 205                         clocks = <&ccu CLK_BUS_MMC2>,
 206                                  <&ccu CLK_MMC2>,
 207                                  <&ccu CLK_MMC2_OUTPUT>,
 208                                  <&ccu CLK_MMC2_SAMPLE>;
 209                         clock-names = "ahb",
 210                                       "mmc",
 211                                       "output",
 212                                       "sample";
 213                         resets = <&ccu RST_BUS_MMC2>;
 214                         reset-names = "ahb";
 215                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 216                         status = "disabled";
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                 };
 220
 221                 usbphy: phy@01c19400 {
 222                         compatible = "allwinner,sun8i-h3-usb-phy";
 223                         reg = <0x01c19400 0x2c>,
 224                               <0x01c1a800 0x4>,
 225                               <0x01c1b800 0x4>,
 226                               <0x01c1c800 0x4>,
 227                               <0x01c1d800 0x4>;
 228                         reg-names = "phy_ctrl",
 229                                     "pmu0",
 230                                     "pmu1",
 231                                     "pmu2",
 232                                     "pmu3";
 233                         clocks = <&ccu CLK_USB_PHY0>,
 234                                  <&ccu CLK_USB_PHY1>,
 235                                  <&ccu CLK_USB_PHY2>,
 236                                  <&ccu CLK_USB_PHY3>;
 237                         clock-names = "usb0_phy",
 238                                       "usb1_phy",
 239                                       "usb2_phy",
 240                                       "usb3_phy";
 241                         resets = <&ccu RST_USB_PHY0>,
 242                                  <&ccu RST_USB_PHY1>,
 243                                  <&ccu RST_USB_PHY2>,
 244                                  <&ccu RST_USB_PHY3>;
 245                         reset-names = "usb0_reset",
 246                                       "usb1_reset",
 247                                       "usb2_reset",
 248                                       "usb3_reset";
 249                         status = "disabled";
 250                         #phy-cells = <1>;
 251                 };
 252
 253                 ehci1: usb@01c1b000 {
 254                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 255                         reg = <0x01c1b000 0x100>;
 256                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
 258                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 259                         phys = <&usbphy 1>;
 260                         phy-names = "usb";
 261                         status = "disabled";
 262                 };
 263
 264                 ohci1: usb@01c1b400 {
 265                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 266                         reg = <0x01c1b400 0x100>;
 267                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 268                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
 269                                  <&ccu CLK_USB_OHCI1>;
 270                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 271                         phys = <&usbphy 1>;
 272                         phy-names = "usb";
 273                         status = "disabled";
 274                 };
 275
 276                 ehci2: usb@01c1c000 {
 277                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 278                         reg = <0x01c1c000 0x100>;
 279                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
 281                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 282                         phys = <&usbphy 2>;
 283                         phy-names = "usb";
 284                         status = "disabled";
 285                 };
 286
 287                 ohci2: usb@01c1c400 {
 288                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 289                         reg = <0x01c1c400 0x100>;
 290                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 291                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
 292                                  <&ccu CLK_USB_OHCI2>;
 293                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 294                         phys = <&usbphy 2>;
 295                         phy-names = "usb";
 296                         status = "disabled";
 297                 };
 298
 299                 ehci3: usb@01c1d000 {
 300                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 301                         reg = <0x01c1d000 0x100>;
 302                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 303                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
 304                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 305                         phys = <&usbphy 3>;
 306                         phy-names = "usb";
 307                         status = "disabled";
 308                 };
 309
 310                 ohci3: usb@01c1d400 {
 311                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 312                         reg = <0x01c1d400 0x100>;
 313                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 314                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
 315                                  <&ccu CLK_USB_OHCI3>;
 316                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 317                         phys = <&usbphy 3>;
 318                         phy-names = "usb";
 319                         status = "disabled";
 320                 };
 321
 322                 ccu: clock@01c20000 {
 323                         compatible = "allwinner,sun8i-h3-ccu";
 324                         reg = <0x01c20000 0x400>;
 325                         clocks = <&osc24M>, <&osc32k>;
 326                         clock-names = "hosc", "losc";
 327                         #clock-cells = <1>;
 328                         #reset-cells = <1>;
 329                 };
 330
 331                 pio: pinctrl@01c20800 {
 332                         compatible = "allwinner,sun8i-h3-pinctrl";
 333                         reg = <0x01c20800 0x400>;
 334                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 335                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 336                         clocks = <&ccu CLK_BUS_PIO>;
 337                         gpio-controller;
 338                         #gpio-cells = <3>;
 339                         interrupt-controller;
 340                         #interrupt-cells = <3>;
 341
 342                         emac_rgmii_pins: emac0@0 {
 343                                 allwinner,pins = "PD0", "PD1", "PD2", "PD3",
 344                                                 "PD4", "PD5", "PD7",
 345                                                 "PD8", "PD9", "PD10",
 346                                                 "PD12", "PD13", "PD15",
 347                                                 "PD16", "PD17";
 348                                 allwinner,function = "emac";
 349                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 350                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 351                         };
 352
 353                         mmc0_pins_a: mmc0@0 {
 354                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 355                                                  "PF4", "PF5";
 356                                 allwinner,function = "mmc0";
 357                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 358                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 359                         };
 360
 361                         mmc0_cd_pin: mmc0_cd_pin@0 {
 362                                 allwinner,pins = "PF6";
 363                                 allwinner,function = "gpio_in";
 364                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 365                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 366                         };
 367
 368                         mmc1_pins_a: mmc1@0 {
 369                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 370                                                  "PG4", "PG5";
 371                                 allwinner,function = "mmc1";
 372                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 373                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 374                         };
 375
 376                         mmc2_8bit_pins: mmc2_8bit {
 377                                 allwinner,pins = "PC5", "PC6", "PC8",
 378                                                  "PC9", "PC10", "PC11",
 379                                                  "PC12", "PC13", "PC14",
 380                                                  "PC15", "PC16";
 381                                 allwinner,function = "mmc2";
 382                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 383                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 384                         };
 385
 386                         uart0_pins_a: uart0@0 {
 387                                 allwinner,pins = "PA4", "PA5";
 388                                 allwinner,function = "uart0";
 389                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 390                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 391                         };
 392
 393                         uart1_pins_a: uart1@0 {
 394                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
 395                                 allwinner,function = "uart1";
 396                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 397                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 398                         };
 399                 };
 400
 401                 timer@01c20c00 {
 402                         compatible = "allwinner,sun4i-a10-timer";
 403                         reg = <0x01c20c00 0xa0>;
 404                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 405                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 406                         clocks = <&osc24M>;
 407                 };
 408
 409                 wdt0: watchdog@01c20ca0 {
 410                         compatible = "allwinner,sun6i-a31-wdt";
 411                         reg = <0x01c20ca0 0x20>;
 412                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 413                 };
 414
 415                 uart0: serial@01c28000 {
 416                         compatible = "snps,dw-apb-uart";
 417                         reg = <0x01c28000 0x400>;
 418                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 419                         reg-shift = <2>;
 420                         reg-io-width = <4>;
 421                         clocks = <&ccu CLK_BUS_UART0>;
 422                         resets = <&ccu RST_BUS_UART0>;
 423                         dmas = <&dma 6>, <&dma 6>;
 424                         dma-names = "rx", "tx";
 425                         status = "disabled";
 426                 };
 427
 428                 uart1: serial@01c28400 {
 429                         compatible = "snps,dw-apb-uart";
 430                         reg = <0x01c28400 0x400>;
 431                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 432                         reg-shift = <2>;
 433                         reg-io-width = <4>;
 434                         clocks = <&ccu CLK_BUS_UART1>;
 435                         resets = <&ccu RST_BUS_UART1>;
 436                         dmas = <&dma 7>, <&dma 7>;
 437                         dma-names = "rx", "tx";
 438                         status = "disabled";
 439                 };
 440
 441                 uart2: serial@01c28800 {
 442                         compatible = "snps,dw-apb-uart";
 443                         reg = <0x01c28800 0x400>;
 444                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 445                         reg-shift = <2>;
 446                         reg-io-width = <4>;
 447                         clocks = <&ccu CLK_BUS_UART2>;
 448                         resets = <&ccu RST_BUS_UART2>;
 449                         dmas = <&dma 8>, <&dma 8>;
 450                         dma-names = "rx", "tx";
 451                         status = "disabled";
 452                 };
 453
 454                 uart3: serial@01c28c00 {
 455                         compatible = "snps,dw-apb-uart";
 456                         reg = <0x01c28c00 0x400>;
 457                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 458                         reg-shift = <2>;
 459                         reg-io-width = <4>;
 460                         clocks = <&ccu CLK_BUS_UART3>;
 461                         resets = <&ccu RST_BUS_UART3>;
 462                         dmas = <&dma 9>, <&dma 9>;
 463                         dma-names = "rx", "tx";
 464                         status = "disabled";
 465                 };
 466
 467                 emac: ethernet@1c30000 {
 468                         compatible = "allwinner,sun8i-h3-emac";
 469                         syscon = <&syscon>;
 470                         reg = <0x01c30000 0x104>;
 471                         reg-names = "emac";
 472                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 473                         resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
 474                         reset-names = "ahb", "ephy";
 475                         clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
 476                         clock-names = "ahb", "ephy";
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                         status = "disabled";
 480                 };
 481
 482                 gic: interrupt-controller@01c81000 {
 483                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 484                         reg = <0x01c81000 0x1000>,
 485                               <0x01c82000 0x1000>,
 486                               <0x01c84000 0x2000>,
 487                               <0x01c86000 0x2000>;
 488                         interrupt-controller;
 489                         #interrupt-cells = <3>;
 490                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 491                 };
 492
 493                 rtc: rtc@01f00000 {
 494                         compatible = "allwinner,sun6i-a31-rtc";
 495                         reg = <0x01f00000 0x54>;
 496                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 497                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 498                 };
 499
 500                 apb0_reset: reset@01f014b0 {
 501                         reg = <0x01f014b0 0x4>;
 502                         compatible = "allwinner,sun6i-a31-clock-reset";
 503                         #reset-cells = <1>;
 504                 };
 505
 506                 ir: ir@01f02000 {
 507                         compatible = "allwinner,sun5i-a13-ir";
 508                         clocks = <&apb0_gates 1>, <&ir_clk>;
 509                         clock-names = "apb", "ir";
 510                         resets = <&apb0_reset 1>;
 511                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 512                         reg = <0x01f02000 0x40>;
 513                         status = "disabled";
 514                 };
 515
 516                 r_pio: pinctrl@01f02c00 {
 517                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 518                         reg = <0x01f02c00 0x400>;
 519                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 520                         clocks = <&apb0_gates 0>;
 521                         resets = <&apb0_reset 0>;
 522                         gpio-controller;
 523                         #gpio-cells = <3>;
 524                         interrupt-controller;
 525                         #interrupt-cells = <3>;
 526
 527                         ir_pins_a: ir@0 {
 528                                 allwinner,pins = "PL11";
 529                                 allwinner,function = "s_cir_rx";
 530                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 531                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 532                         };
 533                 };
 534         };
 535 };