git.sur5r.net Git - u-boot/blob - arch/arm/dts/sun8i-r40.dtsi

   1 /*
   2  * Copyright 2016 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
  47 #include <dt-bindings/reset/sun8i-r40-ccu.h>
  48
  49 / {
  50         #address-cells = <1>;
  51         #size-cells = <1>;
  52         interrupt-parent = <&gic>;
  53
  54         aliases {
  55         };
  56
  57         chosen {
  58         };
  59
  60         clocks {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 osc24M: osc24M_clk {
  66                         #clock-cells = <0>;
  67                         compatible = "fixed-clock";
  68                         clock-frequency = <24000000>;
  69                 };
  70
  71                 osc32k: osc32k_clk {
  72                         #clock-cells = <0>;
  73                         compatible = "fixed-clock";
  74                         clock-frequency = <32768>;
  75                         clock-output-names = "osc32k";
  76                 };
  77         };
  78
  79         cpus {
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82
  83                 cpu0: cpu@0 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <0>;
  87                 };
  88
  89                 cpu@1 {
  90                         compatible = "arm,cortex-a7";
  91                         device_type = "cpu";
  92                         reg = <1>;
  93                 };
  94
  95                 cpu@2 {
  96                         compatible = "arm,cortex-a7";
  97                         device_type = "cpu";
  98                         reg = <2>;
  99                 };
 100
 101                 cpu@3 {
 102                         compatible = "arm,cortex-a7";
 103                         device_type = "cpu";
 104                         reg = <3>;
 105                 };
 106         };
 107
 108         memory@40000000 {
 109                 device_type = "memory";
 110                 reg = <0x40000000 0x80000000>;
 111         };
 112
 113         soc {
 114                 compatible = "simple-bus";
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 ranges;
 118
 119                 nmi_intc: interrupt-controller@1c00030 {
 120                         compatible = "allwinner,sun7i-a20-sc-nmi";
 121                         interrupt-controller;
 122                         #interrupt-cells = <2>;
 123                         reg = <0x01c00030 0x0c>;
 124                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 125                 };
 126
 127                 mmc0: mmc@1c0f000 {
 128                         compatible = "allwinner,sun8i-r40-mmc",
 129                                      "allwinner,sun50i-a64-mmc";
 130                         reg = <0x01c0f000 0x1000>;
 131                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 132                         clock-names = "ahb", "mmc";
 133                         resets = <&ccu RST_BUS_MMC0>;
 134                         reset-names = "ahb";
 135                         pinctrl-0 = <&mmc0_pins>;
 136                         pinctrl-names = "default";
 137                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 138                         status = "disabled";
 139                         #address-cells = <1>;
 140                         #size-cells = <0>;
 141                 };
 142
 143                 ccu: clock@1c20000 {
 144                         compatible = "allwinner,sun8i-r40-ccu";
 145                         reg = <0x01c20000 0x400>;
 146                         clocks = <&osc24M>, <&osc32k>;
 147                         clock-names = "hosc", "losc";
 148                         #clock-cells = <1>;
 149                         #reset-cells = <1>;
 150                 };
 151
 152                 pio: pinctrl@1c20800 {
 153                         compatible = "allwinner,sun8i-r40-pinctrl";
 154                         reg = <0x01c20800 0x400>;
 155                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 156                         /* apb should be replaced once CCU is implemented */
 157                         clocks = <&osc24M>, <&osc24M>, <&osc32k>;
 158                         clock-names = "apb", "hosc", "losc";
 159                         gpio-controller;
 160                         interrupt-controller;
 161                         #interrupt-cells = <3>;
 162                         #gpio-cells = <3>;
 163
 164                         i2c0_pins: i2c0_pins {
 165                                 pins = "PB0", "PB1";
 166                                 function = "i2c0";
 167                                 bias-pull-up;
 168                         };
 169
 170                         mmc0_pins: mmc0-pins {
 171                                 pins = "PF0", "PF1", "PF2",
 172                                        "PF3", "PF4", "PF5";
 173                                 function = "mmc0";
 174                                 drive-strength = <30>;
 175                                 bias-pull-up;
 176                         };
 177
 178                         uart0_pb_pins: uart0_pb_pins {
 179                                 pins = "PB22", "PB23";
 180                                 function = "uart0";
 181                                 bias-pull-up;
 182                         };
 183                 };
 184
 185                 uart0: serial@1c28000 {
 186                         compatible = "snps,dw-apb-uart";
 187                         reg = <0x01c28000 0x400>;
 188                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 189                         reg-shift = <2>;
 190                         reg-io-width = <4>;
 191                         clocks = <&osc24M>;
 192                         status = "disabled";
 193                 };
 194
 195                 i2c0: i2c@1c2ac00 {
 196                         compatible = "allwinner,sun6i-a31-i2c";
 197                         reg = <0x01c2ac00 0x400>;
 198                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 199                         clocks = <&osc24M>;
 200                         status = "disabled";
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                 };
 204
 205                 gic: interrupt-controller@1c81000 {
 206                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 207                         reg = <0x01c81000 0x1000>,
 208                               <0x01c82000 0x1000>,
 209                               <0x01c84000 0x2000>,
 210                               <0x01c86000 0x2000>;
 211                         interrupt-controller;
 212                         #interrupt-cells = <3>;
 213                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 214                 };
 215         };
 216
 217         timer {
 218                 compatible = "arm,armv7-timer";
 219                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 220                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 221                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 222                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 223                 clock-frequency = <24000000>;
 224                 arm,cpu-registers-not-fw-configured;
 225         };
 226 };