git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ld11.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier LD11 SoC
   4 //
   5 // Copyright (C) 2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10
  11 /memreserve/ 0x80000000 0x02000000;
  12
  13 / {
  14         compatible = "socionext,uniphier-ld11";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&gic>;
  18
  19         cpus {
  20                 #address-cells = <2>;
  21                 #size-cells = <0>;
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&cpu0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&cpu1>;
  30                                 };
  31                         };
  32                 };
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53", "arm,armv8";
  37                         reg = <0 0x000>;
  38                         clocks = <&sys_clk 33>;
  39                         enable-method = "psci";
  40                         operating-points-v2 = <&cluster0_opp>;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53", "arm,armv8";
  46                         reg = <0 0x001>;
  47                         clocks = <&sys_clk 33>;
  48                         enable-method = "psci";
  49                         operating-points-v2 = <&cluster0_opp>;
  50                 };
  51         };
  52
  53         cluster0_opp: opp-table {
  54                 compatible = "operating-points-v2";
  55                 opp-shared;
  56
  57                 opp-245000000 {
  58                         opp-hz = /bits/ 64 <245000000>;
  59                         clock-latency-ns = <300>;
  60                 };
  61                 opp-250000000 {
  62                         opp-hz = /bits/ 64 <250000000>;
  63                         clock-latency-ns = <300>;
  64                 };
  65                 opp-490000000 {
  66                         opp-hz = /bits/ 64 <490000000>;
  67                         clock-latency-ns = <300>;
  68                 };
  69                 opp-500000000 {
  70                         opp-hz = /bits/ 64 <500000000>;
  71                         clock-latency-ns = <300>;
  72                 };
  73                 opp-653334000 {
  74                         opp-hz = /bits/ 64 <653334000>;
  75                         clock-latency-ns = <300>;
  76                 };
  77                 opp-666667000 {
  78                         opp-hz = /bits/ 64 <666667000>;
  79                         clock-latency-ns = <300>;
  80                 };
  81                 opp-980000000 {
  82                         opp-hz = /bits/ 64 <980000000>;
  83                         clock-latency-ns = <300>;
  84                 };
  85         };
  86
  87         psci {
  88                 compatible = "arm,psci-1.0";
  89                 method = "smc";
  90         };
  91
  92         clocks {
  93                 refclk: ref {
  94                         compatible = "fixed-clock";
  95                         #clock-cells = <0>;
  96                         clock-frequency = <25000000>;
  97                 };
  98         };
  99
 100         emmc_pwrseq: emmc-pwrseq {
 101                 compatible = "mmc-pwrseq-emmc";
 102                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
 103         };
 104
 105         timer {
 106                 compatible = "arm,armv8-timer";
 107                 interrupts = <1 13 4>,
 108                              <1 14 4>,
 109                              <1 11 4>,
 110                              <1 10 4>;
 111         };
 112
 113         soc@0 {
 114                 compatible = "simple-bus";
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 ranges = <0 0 0 0xffffffff>;
 118
 119                 serial0: serial@54006800 {
 120                         compatible = "socionext,uniphier-uart";
 121                         status = "disabled";
 122                         reg = <0x54006800 0x40>;
 123                         interrupts = <0 33 4>;
 124                         pinctrl-names = "default";
 125                         pinctrl-0 = <&pinctrl_uart0>;
 126                         clocks = <&peri_clk 0>;
 127                         clock-frequency = <58820000>;
 128                         resets = <&peri_rst 0>;
 129                 };
 130
 131                 serial1: serial@54006900 {
 132                         compatible = "socionext,uniphier-uart";
 133                         status = "disabled";
 134                         reg = <0x54006900 0x40>;
 135                         interrupts = <0 35 4>;
 136                         pinctrl-names = "default";
 137                         pinctrl-0 = <&pinctrl_uart1>;
 138                         clocks = <&peri_clk 1>;
 139                         clock-frequency = <58820000>;
 140                         resets = <&peri_rst 1>;
 141                 };
 142
 143                 serial2: serial@54006a00 {
 144                         compatible = "socionext,uniphier-uart";
 145                         status = "disabled";
 146                         reg = <0x54006a00 0x40>;
 147                         interrupts = <0 37 4>;
 148                         pinctrl-names = "default";
 149                         pinctrl-0 = <&pinctrl_uart2>;
 150                         clocks = <&peri_clk 2>;
 151                         clock-frequency = <58820000>;
 152                         resets = <&peri_rst 2>;
 153                 };
 154
 155                 serial3: serial@54006b00 {
 156                         compatible = "socionext,uniphier-uart";
 157                         status = "disabled";
 158                         reg = <0x54006b00 0x40>;
 159                         interrupts = <0 177 4>;
 160                         pinctrl-names = "default";
 161                         pinctrl-0 = <&pinctrl_uart3>;
 162                         clocks = <&peri_clk 3>;
 163                         clock-frequency = <58820000>;
 164                         resets = <&peri_rst 3>;
 165                 };
 166
 167                 gpio: gpio@55000000 {
 168                         compatible = "socionext,uniphier-gpio";
 169                         reg = <0x55000000 0x200>;
 170                         interrupt-parent = <&aidet>;
 171                         interrupt-controller;
 172                         #interrupt-cells = <2>;
 173                         gpio-controller;
 174                         #gpio-cells = <2>;
 175                         gpio-ranges = <&pinctrl 0 0 0>,
 176                                       <&pinctrl 43 0 0>,
 177                                       <&pinctrl 51 0 0>,
 178                                       <&pinctrl 96 0 0>,
 179                                       <&pinctrl 160 0 0>,
 180                                       <&pinctrl 184 0 0>;
 181                         gpio-ranges-group-names = "gpio_range0",
 182                                                   "gpio_range1",
 183                                                   "gpio_range2",
 184                                                   "gpio_range3",
 185                                                   "gpio_range4",
 186                                                   "gpio_range5";
 187                         ngpios = <200>;
 188                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 189                                                      <21 217 3>;
 190                 };
 191
 192                 audio@56000000 {
 193                         compatible = "socionext,uniphier-ld11-aio";
 194                         reg = <0x56000000 0x80000>;
 195                         interrupts = <0 144 4>;
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&pinctrl_aout1>,
 198                                     <&pinctrl_aoutiec1>;
 199                         clock-names = "aio";
 200                         clocks = <&sys_clk 40>;
 201                         reset-names = "aio";
 202                         resets = <&sys_rst 40>;
 203                         #sound-dai-cells = <1>;
 204                         socionext,syscon = <&soc_glue>;
 205
 206                         i2s_port0: port@0 {
 207                                 i2s_hdmi: endpoint {
 208                                 };
 209                         };
 210
 211                         i2s_port1: port@1 {
 212                                 i2s_pcmin2: endpoint {
 213                                 };
 214                         };
 215
 216                         i2s_port2: port@2 {
 217                                 i2s_line: endpoint {
 218                                         dai-format = "i2s";
 219                                         remote-endpoint = <&evea_line>;
 220                                 };
 221                         };
 222
 223                         i2s_port3: port@3 {
 224                                 i2s_hpcmout1: endpoint {
 225                                 };
 226                         };
 227
 228                         i2s_port4: port@4 {
 229                                 i2s_hp: endpoint {
 230                                         dai-format = "i2s";
 231                                         remote-endpoint = <&evea_hp>;
 232                                 };
 233                         };
 234
 235                         spdif_port0: port@5 {
 236                                 spdif_hiecout1: endpoint {
 237                                 };
 238                         };
 239
 240                         src_port0: port@6 {
 241                                 i2s_epcmout2: endpoint {
 242                                 };
 243                         };
 244
 245                         src_port1: port@7 {
 246                                 i2s_epcmout3: endpoint {
 247                                 };
 248                         };
 249
 250                         comp_spdif_port0: port@8 {
 251                                 comp_spdif_hiecout1: endpoint {
 252                                 };
 253                         };
 254                 };
 255
 256                 codec@57900000 {
 257                         compatible = "socionext,uniphier-evea";
 258                         reg = <0x57900000 0x1000>;
 259                         clock-names = "evea", "exiv";
 260                         clocks = <&sys_clk 41>, <&sys_clk 42>;
 261                         reset-names = "evea", "exiv", "adamv";
 262                         resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
 263                         #sound-dai-cells = <1>;
 264
 265                         port@0 {
 266                                 evea_line: endpoint {
 267                                         remote-endpoint = <&i2s_line>;
 268                                 };
 269                         };
 270
 271                         port@1 {
 272                                 evea_hp: endpoint {
 273                                         remote-endpoint = <&i2s_hp>;
 274                                 };
 275                         };
 276                 };
 277
 278                 adamv@57920000 {
 279                         compatible = "socionext,uniphier-ld11-adamv",
 280                                      "simple-mfd", "syscon";
 281                         reg = <0x57920000 0x1000>;
 282
 283                         adamv_rst: reset {
 284                                 compatible = "socionext,uniphier-ld11-adamv-reset";
 285                                 #reset-cells = <1>;
 286                         };
 287                 };
 288
 289                 i2c0: i2c@58780000 {
 290                         compatible = "socionext,uniphier-fi2c";
 291                         status = "disabled";
 292                         reg = <0x58780000 0x80>;
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                         interrupts = <0 41 4>;
 296                         pinctrl-names = "default";
 297                         pinctrl-0 = <&pinctrl_i2c0>;
 298                         clocks = <&peri_clk 4>;
 299                         resets = <&peri_rst 4>;
 300                         clock-frequency = <100000>;
 301                 };
 302
 303                 i2c1: i2c@58781000 {
 304                         compatible = "socionext,uniphier-fi2c";
 305                         status = "disabled";
 306                         reg = <0x58781000 0x80>;
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309                         interrupts = <0 42 4>;
 310                         pinctrl-names = "default";
 311                         pinctrl-0 = <&pinctrl_i2c1>;
 312                         clocks = <&peri_clk 5>;
 313                         resets = <&peri_rst 5>;
 314                         clock-frequency = <100000>;
 315                 };
 316
 317                 i2c2: i2c@58782000 {
 318                         compatible = "socionext,uniphier-fi2c";
 319                         reg = <0x58782000 0x80>;
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         interrupts = <0 43 4>;
 323                         clocks = <&peri_clk 6>;
 324                         resets = <&peri_rst 6>;
 325                         clock-frequency = <400000>;
 326                 };
 327
 328                 i2c3: i2c@58783000 {
 329                         compatible = "socionext,uniphier-fi2c";
 330                         status = "disabled";
 331                         reg = <0x58783000 0x80>;
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                         interrupts = <0 44 4>;
 335                         pinctrl-names = "default";
 336                         pinctrl-0 = <&pinctrl_i2c3>;
 337                         clocks = <&peri_clk 7>;
 338                         resets = <&peri_rst 7>;
 339                         clock-frequency = <100000>;
 340                 };
 341
 342                 i2c4: i2c@58784000 {
 343                         compatible = "socionext,uniphier-fi2c";
 344                         status = "disabled";
 345                         reg = <0x58784000 0x80>;
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         interrupts = <0 45 4>;
 349                         pinctrl-names = "default";
 350                         pinctrl-0 = <&pinctrl_i2c4>;
 351                         clocks = <&peri_clk 8>;
 352                         resets = <&peri_rst 8>;
 353                         clock-frequency = <100000>;
 354                 };
 355
 356                 i2c5: i2c@58785000 {
 357                         compatible = "socionext,uniphier-fi2c";
 358                         reg = <0x58785000 0x80>;
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         interrupts = <0 25 4>;
 362                         clocks = <&peri_clk 9>;
 363                         resets = <&peri_rst 9>;
 364                         clock-frequency = <400000>;
 365                 };
 366
 367                 system_bus: system-bus@58c00000 {
 368                         compatible = "socionext,uniphier-system-bus";
 369                         status = "disabled";
 370                         reg = <0x58c00000 0x400>;
 371                         #address-cells = <2>;
 372                         #size-cells = <1>;
 373                         pinctrl-names = "default";
 374                         pinctrl-0 = <&pinctrl_system_bus>;
 375                 };
 376
 377                 smpctrl@59801000 {
 378                         compatible = "socionext,uniphier-smpctrl";
 379                         reg = <0x59801000 0x400>;
 380                 };
 381
 382                 sdctrl@59810000 {
 383                         compatible = "socionext,uniphier-ld11-sdctrl",
 384                                      "simple-mfd", "syscon";
 385                         reg = <0x59810000 0x400>;
 386
 387                         sd_rst: reset {
 388                                 compatible = "socionext,uniphier-ld11-sd-reset";
 389                                 #reset-cells = <1>;
 390                         };
 391                 };
 392
 393                 perictrl@59820000 {
 394                         compatible = "socionext,uniphier-ld11-perictrl",
 395                                      "simple-mfd", "syscon";
 396                         reg = <0x59820000 0x200>;
 397
 398                         peri_clk: clock {
 399                                 compatible = "socionext,uniphier-ld11-peri-clock";
 400                                 #clock-cells = <1>;
 401                         };
 402
 403                         peri_rst: reset {
 404                                 compatible = "socionext,uniphier-ld11-peri-reset";
 405                                 #reset-cells = <1>;
 406                         };
 407                 };
 408
 409                 emmc: sdhc@5a000000 {
 410                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 411                         reg = <0x5a000000 0x400>;
 412                         interrupts = <0 78 4>;
 413                         pinctrl-names = "default";
 414                         pinctrl-0 = <&pinctrl_emmc_1v8>;
 415                         clocks = <&sys_clk 4>;
 416                         resets = <&sys_rst 4>;
 417                         bus-width = <8>;
 418                         mmc-ddr-1_8v;
 419                         mmc-hs200-1_8v;
 420                         mmc-pwrseq = <&emmc_pwrseq>;
 421                         cdns,phy-input-delay-legacy = <9>;
 422                         cdns,phy-input-delay-mmc-highspeed = <2>;
 423                         cdns,phy-input-delay-mmc-ddr = <3>;
 424                         cdns,phy-dll-delay-sdclk = <21>;
 425                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 426                 };
 427
 428                 usb0: usb@5a800100 {
 429                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 430                         status = "disabled";
 431                         reg = <0x5a800100 0x100>;
 432                         interrupts = <0 243 4>;
 433                         pinctrl-names = "default";
 434                         pinctrl-0 = <&pinctrl_usb0>;
 435                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 436                                  <&mio_clk 12>;
 437                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 438                                  <&mio_rst 12>;
 439                         has-transaction-translator;
 440                 };
 441
 442                 usb1: usb@5a810100 {
 443                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 444                         status = "disabled";
 445                         reg = <0x5a810100 0x100>;
 446                         interrupts = <0 244 4>;
 447                         pinctrl-names = "default";
 448                         pinctrl-0 = <&pinctrl_usb1>;
 449                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 450                                  <&mio_clk 13>;
 451                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 452                                  <&mio_rst 13>;
 453                         has-transaction-translator;
 454                 };
 455
 456                 usb2: usb@5a820100 {
 457                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 458                         status = "disabled";
 459                         reg = <0x5a820100 0x100>;
 460                         interrupts = <0 245 4>;
 461                         pinctrl-names = "default";
 462                         pinctrl-0 = <&pinctrl_usb2>;
 463                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 464                                  <&mio_clk 14>;
 465                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 466                                  <&mio_rst 14>;
 467                         has-transaction-translator;
 468                 };
 469
 470                 mioctrl@5b3e0000 {
 471                         compatible = "socionext,uniphier-ld11-mioctrl",
 472                                      "simple-mfd", "syscon";
 473                         reg = <0x5b3e0000 0x800>;
 474
 475                         mio_clk: clock {
 476                                 compatible = "socionext,uniphier-ld11-mio-clock";
 477                                 #clock-cells = <1>;
 478                         };
 479
 480                         mio_rst: reset {
 481                                 compatible = "socionext,uniphier-ld11-mio-reset";
 482                                 #reset-cells = <1>;
 483                                 resets = <&sys_rst 7>;
 484                         };
 485                 };
 486
 487                 soc_glue: soc-glue@5f800000 {
 488                         compatible = "socionext,uniphier-ld11-soc-glue",
 489                                      "simple-mfd", "syscon";
 490                         reg = <0x5f800000 0x2000>;
 491
 492                         pinctrl: pinctrl {
 493                                 compatible = "socionext,uniphier-ld11-pinctrl";
 494                         };
 495                 };
 496
 497                 soc-glue@5f900000 {
 498                         compatible = "socionext,uniphier-ld11-soc-glue-debug",
 499                                      "simple-mfd";
 500                         #address-cells = <1>;
 501                         #size-cells = <1>;
 502                         ranges = <0 0x5f900000 0x2000>;
 503
 504                         efuse@100 {
 505                                 compatible = "socionext,uniphier-efuse";
 506                                 reg = <0x100 0x28>;
 507                         };
 508
 509                         efuse@200 {
 510                                 compatible = "socionext,uniphier-efuse";
 511                                 reg = <0x200 0x68>;
 512                         };
 513                 };
 514
 515                 aidet: aidet@5fc20000 {
 516                         compatible = "socionext,uniphier-ld11-aidet";
 517                         reg = <0x5fc20000 0x200>;
 518                         interrupt-controller;
 519                         #interrupt-cells = <2>;
 520                 };
 521
 522                 gic: interrupt-controller@5fe00000 {
 523                         compatible = "arm,gic-v3";
 524                         reg = <0x5fe00000 0x10000>,     /* GICD */
 525                               <0x5fe40000 0x80000>;     /* GICR */
 526                         interrupt-controller;
 527                         #interrupt-cells = <3>;
 528                         interrupts = <1 9 4>;
 529                 };
 530
 531                 sysctrl@61840000 {
 532                         compatible = "socionext,uniphier-ld11-sysctrl",
 533                                      "simple-mfd", "syscon";
 534                         reg = <0x61840000 0x10000>;
 535
 536                         sys_clk: clock {
 537                                 compatible = "socionext,uniphier-ld11-clock";
 538                                 #clock-cells = <1>;
 539                         };
 540
 541                         sys_rst: reset {
 542                                 compatible = "socionext,uniphier-ld11-reset";
 543                                 #reset-cells = <1>;
 544                         };
 545
 546                         watchdog {
 547                                 compatible = "socionext,uniphier-wdt";
 548                         };
 549                 };
 550
 551                 eth: ethernet@65000000 {
 552                         compatible = "socionext,uniphier-ld11-ave4";
 553                         status = "disabled";
 554                         reg = <0x65000000 0x8500>;
 555                         interrupts = <0 66 4>;
 556                         clock-names = "ether";
 557                         clocks = <&sys_clk 6>;
 558                         reset-names = "ether";
 559                         resets = <&sys_rst 6>;
 560                         phy-mode = "internal";
 561                         local-mac-address = [00 00 00 00 00 00];
 562                         socionext,syscon-phy-mode = <&soc_glue 0>;
 563
 564                         mdio: mdio {
 565                                 #address-cells = <1>;
 566                                 #size-cells = <0>;
 567                         };
 568                 };
 569
 570                 nand: nand@68000000 {
 571                         compatible = "socionext,uniphier-denali-nand-v5b";
 572                         status = "disabled";
 573                         reg-names = "nand_data", "denali_reg";
 574                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 575                         interrupts = <0 65 4>;
 576                         pinctrl-names = "default";
 577                         pinctrl-0 = <&pinctrl_nand>;
 578                         clocks = <&sys_clk 2>;
 579                         resets = <&sys_rst 2>;
 580                 };
 581         };
 582 };
 583
 584 #include "uniphier-pinctrl.dtsi"
 585
 586 &pinctrl_aoutiec1 {
 587         drive-strength = <4>;   /* default: 4mA */
 588
 589         ao1arc {
 590                 pins = "AO1ARC";
 591                 drive-strength = <8>;   /* 8mA */
 592         };
 593 };