git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14
  15 / {
  16         model = "ZynqMP zc1751-xm015-dc1 RevA";
  17         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  18
  19         aliases {
  20                 ethernet0 = &gem3;
  21                 gpio0 = &gpio;
  22                 i2c0 = &i2c1;
  23                 mmc0 = &sdhci0;
  24                 mmc1 = &sdhci1;
  25                 rtc0 = &rtc;
  26                 serial0 = &uart0;
  27                 spi0 = &qspi;
  28                 usb0 = &usb0;
  29         };
  30
  31         chosen {
  32                 bootargs = "earlycon";
  33                 stdout-path = "serial0:115200n8";
  34         };
  35
  36         memory@0 {
  37                 device_type = "memory";
  38                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  39         };
  40 };
  41
  42 &fpd_dma_chan1 {
  43         status = "okay";
  44 };
  45
  46 &fpd_dma_chan2 {
  47         status = "okay";
  48 };
  49
  50 &fpd_dma_chan3 {
  51         status = "okay";
  52 };
  53
  54 &fpd_dma_chan4 {
  55         status = "okay";
  56 };
  57
  58 &fpd_dma_chan5 {
  59         status = "okay";
  60 };
  61
  62 &fpd_dma_chan6 {
  63         status = "okay";
  64 };
  65
  66 &fpd_dma_chan7 {
  67         status = "okay";
  68 };
  69
  70 &fpd_dma_chan8 {
  71         status = "okay";
  72 };
  73
  74 &gem3 {
  75         status = "okay";
  76         phy-handle = <&phy0>;
  77         phy-mode = "rgmii-id";
  78         phy0: phy@0 {
  79                 reg = <0>;
  80         };
  81 };
  82
  83 &gpio {
  84         status = "okay";
  85 };
  86
  87 &gpu {
  88         status = "okay";
  89 };
  90
  91 &i2c1 {
  92         status = "okay";
  93         clock-frequency = <400000>;
  94         eeprom@55 {
  95                 compatible = "atmel,24c64"; /* 24AA64 */
  96                 reg = <0x55>;
  97         };
  98 };
  99
 100 &qspi {
 101         status = "okay";
 102         flash@0 {
 103                 compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 reg = <0x0>;
 107                 spi-tx-bus-width = <1>;
 108                 spi-rx-bus-width = <4>;
 109                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 110                 partition@qspi-fsbl-uboot { /* for testing purpose */
 111                         label = "qspi-fsbl-uboot";
 112                         reg = <0x0 0x100000>;
 113                 };
 114                 partition@qspi-linux { /* for testing purpose */
 115                         label = "qspi-linux";
 116                         reg = <0x100000 0x500000>;
 117                 };
 118                 partition@qspi-device-tree { /* for testing purpose */
 119                         label = "qspi-device-tree";
 120                         reg = <0x600000 0x20000>;
 121                 };
 122                 partition@qspi-rootfs { /* for testing purpose */
 123                         label = "qspi-rootfs";
 124                         reg = <0x620000 0x5E0000>;
 125                 };
 126         };
 127 };
 128
 129 &rtc {
 130         status = "okay";
 131 };
 132
 133 &sata {
 134         status = "okay";
 135         /* SATA phy OOB timing settings */
 136         ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 137         ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 138         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 139         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 140         ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 141         ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 142         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 143         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 144 };
 145
 146 /* eMMC */
 147 &sdhci0 {
 148         status = "okay";
 149         bus-width = <8>;
 150         xlnx,mio_bank = <0>;
 151 };
 152
 153 /* SD1 with level shifter */
 154 &sdhci1 {
 155         status = "okay";
 156         no-1-8-v;       /* for 1.0 silicon */
 157         xlnx,mio_bank = <1>;
 158 };
 159
 160 &uart0 {
 161         status = "okay";
 162 };
 163
 164 /* ULPI SMSC USB3320 */
 165 &usb0 {
 166         status = "okay";
 167 };
 168
 169 &dwc3_0 {
 170         status = "okay";
 171         dr_mode = "host";
 172 };
 173
 174 &xilinx_drm {
 175         status = "okay";
 176 };
 177
 178 &xlnx_dp {
 179         status = "okay";
 180 };
 181
 182 &xlnx_dp_sub {
 183         status = "okay";
 184         xlnx,vid-clk-pl;
 185 };
 186
 187 &xlnx_dp_snd_pcm0 {
 188         status = "okay";
 189 };
 190
 191 &xlnx_dp_snd_pcm1 {
 192         status = "okay";
 193 };
 194
 195 &xlnx_dp_snd_card {
 196         status = "okay";
 197 };
 198
 199 &xlnx_dp_snd_codec0 {
 200         status = "okay";
 201 };
 202
 203 &xlnx_dpdma {
 204         status = "okay";
 205 };