git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp-zcu102-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU102 RevA
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17 #include <dt-bindings/phy/phy.h>
  18
  19 / {
  20         model = "ZynqMP ZCU102 RevA";
  21         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  22
  23         aliases {
  24                 ethernet0 = &gem3;
  25                 gpio0 = &gpio;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 mmc0 = &sdhci1;
  29                 rtc0 = &rtc;
  30                 serial0 = &uart0;
  31                 serial1 = &uart1;
  32                 serial2 = &dcc;
  33                 spi0 = &qspi;
  34                 usb0 = &usb0;
  35         };
  36
  37         chosen {
  38                 bootargs = "earlycon";
  39                 stdout-path = "serial0:115200n8";
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51                 autorepeat;
  52                 sw19 {
  53                         label = "sw19";
  54                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  55                         linux,code = <KEY_DOWN>;
  56                         gpio-key,wakeup;
  57                         autorepeat;
  58                 };
  59         };
  60
  61         leds {
  62                 compatible = "gpio-leds";
  63                 heartbeat_led {
  64                         label = "heartbeat";
  65                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  66                         linux,default-trigger = "heartbeat";
  67                 };
  68         };
  69 };
  70
  71 &can1 {
  72         status = "okay";
  73         pinctrl-names = "default";
  74         pinctrl-0 = <&pinctrl_can1_default>;
  75 };
  76
  77 &dcc {
  78         status = "okay";
  79 };
  80
  81 &fpd_dma_chan1 {
  82         status = "okay";
  83 };
  84
  85 &fpd_dma_chan2 {
  86         status = "okay";
  87 };
  88
  89 &fpd_dma_chan3 {
  90         status = "okay";
  91 };
  92
  93 &fpd_dma_chan4 {
  94         status = "okay";
  95 };
  96
  97 &fpd_dma_chan5 {
  98         status = "okay";
  99 };
 100
 101 &fpd_dma_chan6 {
 102         status = "okay";
 103 };
 104
 105 &fpd_dma_chan7 {
 106         status = "okay";
 107 };
 108
 109 &fpd_dma_chan8 {
 110         status = "okay";
 111 };
 112
 113 &gem3 {
 114         status = "okay";
 115         phy-handle = <&phy0>;
 116         phy-mode = "rgmii-id";
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_gem3_default>;
 119         phy0: phy@21 {
 120                 reg = <21>;
 121                 ti,rx-internal-delay = <0x8>;
 122                 ti,tx-internal-delay = <0xa>;
 123                 ti,fifo-depth = <0x1>;
 124         };
 125 };
 126
 127 &gpio {
 128         status = "okay";
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_gpio_default>;
 131 };
 132
 133 &gpu {
 134         status = "okay";
 135 };
 136
 137 &i2c0 {
 138         status = "okay";
 139         clock-frequency = <400000>;
 140         pinctrl-names = "default", "gpio";
 141         pinctrl-0 = <&pinctrl_i2c0_default>;
 142         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 143         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 144         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 145
 146         tca6416_u97: gpio@20 {
 147                 /*
 148                  * Enable all GTs to out from U-Boot
 149                  * i2c mw 20 6 0  - setup IO to output
 150                  * i2c mw 20 2 ef - setup output values on pins 0-7
 151                  * i2c mw 20 3 ff - setup output values on pins 10-17
 152                  */
 153                 compatible = "ti,tca6416";
 154                 reg = <0x20>;
 155                 gpio-controller;
 156                 #gpio-cells = <2>;
 157                 /*
 158                  * IRQ not connected
 159                  * Lines:
 160                  * 0 - PS_GTR_LAN_SEL0
 161                  * 1 - PS_GTR_LAN_SEL1
 162                  * 2 - PS_GTR_LAN_SEL2
 163                  * 3 - PS_GTR_LAN_SEL3
 164                  * 4 - PCI_CLK_DIR_SEL
 165                  * 5 - IIC_MUX_RESET_B
 166                  * 6 - GEM3_EXP_RESET_B
 167                  * 7, 10 - 17 - not connected
 168                  */
 169
 170                 gtr_sel0 {
 171                         gpio-hog;
 172                         gpios = <0 0>;
 173                         output-low; /* PCIE = 0, DP = 1 */
 174                         line-name = "sel0";
 175                 };
 176                 gtr_sel1 {
 177                         gpio-hog;
 178                         gpios = <1 0>;
 179                         output-high; /* PCIE = 0, DP = 1 */
 180                         line-name = "sel1";
 181                 };
 182                 gtr_sel2 {
 183                         gpio-hog;
 184                         gpios = <2 0>;
 185                         output-high; /* PCIE = 0, USB0 = 1 */
 186                         line-name = "sel2";
 187                 };
 188                 gtr_sel3 {
 189                         gpio-hog;
 190                         gpios = <3 0>;
 191                         output-high; /* PCIE = 0, SATA = 1 */
 192                         line-name = "sel3";
 193                 };
 194         };
 195
 196         tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
 197                 compatible = "ti,tca6416";
 198                 reg = <0x21>;
 199                 gpio-controller;
 200                 #gpio-cells = <2>;
 201                 /*
 202                  * IRQ not connected
 203                  * Lines:
 204                  * 0 - VCCPSPLL_EN
 205                  * 1 - MGTRAVCC_EN
 206                  * 2 - MGTRAVTT_EN
 207                  * 3 - VCCPSDDRPLL_EN
 208                  * 4 - MIO26_PMU_INPUT_LS
 209                  * 5 - PL_PMBUS_ALERT
 210                  * 6 - PS_PMBUS_ALERT
 211                  * 7 - MAXIM_PMBUS_ALERT
 212                  * 10 - PL_DDR4_VTERM_EN
 213                  * 11 - PL_DDR4_VPP_2V5_EN
 214                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 215                  * 13 - PS_DIMM_SUSPEND_EN
 216                  * 14 - PS_DDR4_VTERM_EN
 217                  * 15 - PS_DDR4_VPP_2V5_EN
 218                  * 16 - 17 - not connected
 219                  */
 220         };
 221
 222         i2c-mux@75 { /* u60 */
 223                 compatible = "nxp,pca9544";
 224                 #address-cells = <1>;
 225                 #size-cells = <0>;
 226                 reg = <0x75>;
 227                 i2c@0 { /* i2c mw 75 0 1 */
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230                         reg = <0>;
 231                         /* PS_PMBUS */
 232                         ina226@40 { /* u76 */
 233                                 compatible = "ti,ina226";
 234                                 reg = <0x40>;
 235                                 shunt-resistor = <5000>;
 236                         };
 237                         ina226@41 { /* u77 */
 238                                 compatible = "ti,ina226";
 239                                 reg = <0x41>;
 240                                 shunt-resistor = <5000>;
 241                         };
 242                         ina226@42 { /* u78 */
 243                                 compatible = "ti,ina226";
 244                                 reg = <0x42>;
 245                                 shunt-resistor = <5000>;
 246                         };
 247                         ina226@43 { /* u87 */
 248                                 compatible = "ti,ina226";
 249                                 reg = <0x43>;
 250                                 shunt-resistor = <5000>;
 251                         };
 252                         ina226@44 { /* u85 */
 253                                 compatible = "ti,ina226";
 254                                 reg = <0x44>;
 255                                 shunt-resistor = <5000>;
 256                         };
 257                         ina226@45 { /* u86 */
 258                                 compatible = "ti,ina226";
 259                                 reg = <0x45>;
 260                                 shunt-resistor = <5000>;
 261                         };
 262                         ina226@46 { /* u93 */
 263                                 compatible = "ti,ina226";
 264                                 reg = <0x46>;
 265                                 shunt-resistor = <5000>;
 266                         };
 267                         ina226@47 { /* u88 */
 268                                 compatible = "ti,ina226";
 269                                 reg = <0x47>;
 270                                 shunt-resistor = <5000>;
 271                         };
 272                         ina226@4a { /* u15 */
 273                                 compatible = "ti,ina226";
 274                                 reg = <0x4a>;
 275                                 shunt-resistor = <5000>;
 276                         };
 277                         ina226@4b { /* u92 */
 278                                 compatible = "ti,ina226";
 279                                 reg = <0x4b>;
 280                                 shunt-resistor = <5000>;
 281                         };
 282                 };
 283                 i2c@1 { /* i2c mw 75 0 1 */
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                         reg = <1>;
 287                         /* PL_PMBUS */
 288                         ina226@40 { /* u79 */
 289                                 compatible = "ti,ina226";
 290                                 reg = <0x40>;
 291                                 shunt-resistor = <2000>;
 292                         };
 293                         ina226@41 { /* u81 */
 294                                 compatible = "ti,ina226";
 295                                 reg = <0x41>;
 296                                 shunt-resistor = <5000>;
 297                         };
 298                         ina226@42 { /* u80 */
 299                                 compatible = "ti,ina226";
 300                                 reg = <0x42>;
 301                                 shunt-resistor = <5000>;
 302                         };
 303                         ina226@43 { /* u84 */
 304                                 compatible = "ti,ina226";
 305                                 reg = <0x43>;
 306                                 shunt-resistor = <5000>;
 307                         };
 308                         ina226@44 { /* u16 */
 309                                 compatible = "ti,ina226";
 310                                 reg = <0x44>;
 311                                 shunt-resistor = <5000>;
 312                         };
 313                         ina226@45 { /* u65 */
 314                                 compatible = "ti,ina226";
 315                                 reg = <0x45>;
 316                                 shunt-resistor = <5000>;
 317                         };
 318                         ina226@46 { /* u74 */
 319                                 compatible = "ti,ina226";
 320                                 reg = <0x46>;
 321                                 shunt-resistor = <5000>;
 322                         };
 323                         ina226@47 { /* u75 */
 324                                 compatible = "ti,ina226";
 325                                 reg = <0x47>;
 326                                 shunt-resistor = <5000>;
 327                         };
 328                 };
 329                 i2c@2 { /* i2c mw 75 0 1 */
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         reg = <2>;
 333                         /* MAXIM_PMBUS - 00 */
 334                         max15301@a { /* u46 */
 335                                 compatible = "maxim,max15301";
 336                                 reg = <0xa>;
 337                         };
 338                         max15303@b { /* u4 */
 339                                 compatible = "maxim,max15303";
 340                                 reg = <0xb>;
 341                         };
 342                         max15303@10 { /* u13 */
 343                                 compatible = "maxim,max15303";
 344                                 reg = <0x10>;
 345                         };
 346                         max15301@13 { /* u47 */
 347                                 compatible = "maxim,max15301";
 348                                 reg = <0x13>;
 349                         };
 350                         max15303@14 { /* u7 */
 351                                 compatible = "maxim,max15303";
 352                                 reg = <0x14>;
 353                         };
 354                         max15303@15 { /* u6 */
 355                                 compatible = "maxim,max15303";
 356                                 reg = <0x15>;
 357                         };
 358                         max15303@16 { /* u10 */
 359                                 compatible = "maxim,max15303";
 360                                 reg = <0x16>;
 361                         };
 362                         max15303@17 { /* u9 */
 363                                 compatible = "maxim,max15303";
 364                                 reg = <0x17>;
 365                         };
 366                         max15301@18 { /* u63 */
 367                                 compatible = "maxim,max15301";
 368                                 reg = <0x18>;
 369                         };
 370                         max15303@1a { /* u49 */
 371                                 compatible = "maxim,max15303";
 372                                 reg = <0x1a>;
 373                         };
 374                         max15303@1d { /* u18 */
 375                                 compatible = "maxim,max15303";
 376                                 reg = <0x1d>;
 377                         };
 378                         max15303@20 { /* u8 */
 379                                 compatible = "maxim,max15303";
 380                                 status = "disabled"; /* unreachable */
 381                                 reg = <0x20>;
 382                         };
 383
 384                         max20751@72 { /* u95 */
 385                                 compatible = "maxim,max20751";
 386                                 reg = <0x72>;
 387                         };
 388                         max20751@73 { /* u96 */
 389                                 compatible = "maxim,max20751";
 390                                 reg = <0x73>;
 391                         };
 392                 };
 393                 /* Bus 3 is not connected */
 394         };
 395 };
 396
 397 &i2c1 {
 398         status = "okay";
 399         clock-frequency = <400000>;
 400         pinctrl-names = "default", "gpio";
 401         pinctrl-0 = <&pinctrl_i2c1_default>;
 402         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 403         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 404         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 405
 406         /* PL i2c via PCA9306 - u45 */
 407         i2c-mux@74 { /* u34 */
 408                 compatible = "nxp,pca9548";
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 reg = <0x74>;
 412                 i2c@0 { /* i2c mw 74 0 1 */
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         reg = <0>;
 416                         /*
 417                          * IIC_EEPROM 1kB memory which uses 256B blocks
 418                          * where every block has different address.
 419                          *    0 - 256B address 0x54
 420                          * 256B - 512B address 0x55
 421                          * 512B - 768B address 0x56
 422                          * 768B - 1024B address 0x57
 423                          */
 424                         eeprom: eeprom@54 { /* u23 */
 425                                 compatible = "at,24c08";
 426                                 reg = <0x54>;
 427                         };
 428                 };
 429                 i2c@1 { /* i2c mw 74 0 2 */
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432                         reg = <1>;
 433                         si5341: clock-generator1@36 { /* SI5341 - u69 */
 434                                 compatible = "si5341";
 435                                 reg = <0x36>;
 436                         };
 437
 438                 };
 439                 i2c@2 { /* i2c mw 74 0 4 */
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         reg = <2>;
 443                         si570_1: clock-generator2@5d { /* USER SI570 - u42 */
 444                                 #clock-cells = <0>;
 445                                 compatible = "silabs,si570";
 446                                 reg = <0x5d>;
 447                                 temperature-stability = <50>;
 448                                 factory-fout = <300000000>;
 449                                 clock-frequency = <300000000>;
 450                         };
 451                 };
 452                 i2c@3 { /* i2c mw 74 0 8 */
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                         reg = <3>;
 456                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
 457                                 #clock-cells = <0>;
 458                                 compatible = "silabs,si570";
 459                                 reg = <0x5d>;
 460                                 temperature-stability = <50>; /* copy from zc702 */
 461                                 factory-fout = <156250000>;
 462                                 clock-frequency = <148500000>;
 463                         };
 464                 };
 465                 i2c@4 { /* i2c mw 74 0 10 */
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         reg = <4>;
 469                         si5328: clock-generator4@69 {/* SI5328 - u20 */
 470                                 compatible = "silabs,si5328";
 471                                 reg = <0x69>;
 472                                 /*
 473                                  * Chip has interrupt present connected to PL
 474                                  * interrupt-parent = <&>;
 475                                  * interrupts = <>;
 476                                  */
 477                         };
 478                 };
 479                 /* 5 - 7 unconnected */
 480         };
 481
 482         i2c-mux@75 {
 483                 compatible = "nxp,pca9548"; /* u135 */
 484                 #address-cells = <1>;
 485                 #size-cells = <0>;
 486                 reg = <0x75>;
 487
 488                 i2c@0 {
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491                         reg = <0>;
 492                         /* HPC0_IIC */
 493                 };
 494                 i2c@1 {
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497                         reg = <1>;
 498                         /* HPC1_IIC */
 499                 };
 500                 i2c@2 {
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         reg = <2>;
 504                         /* SYSMON */
 505                 };
 506                 i2c@3 { /* i2c mw 75 0 8 */
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         reg = <3>;
 510                         /* DDR4 SODIMM */
 511                         dev@19 {
 512                                 reg = <0x19>;
 513                         };
 514                         dev@30 {
 515                                 reg = <0x30>;
 516                         };
 517                         dev@35 {
 518                                 reg = <0x35>;
 519                         };
 520                         dev@36 {
 521                                 reg = <0x36>;
 522                         };
 523                         dev@51 {
 524                                 reg = <0x51>;
 525                         };
 526                 };
 527                 i2c@4 {
 528                         #address-cells = <1>;
 529                         #size-cells = <0>;
 530                         reg = <4>;
 531                         /* SEP 3 */
 532                 };
 533                 i2c@5 {
 534                         #address-cells = <1>;
 535                         #size-cells = <0>;
 536                         reg = <5>;
 537                         /* SEP 2 */
 538                 };
 539                 i2c@6 {
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         reg = <6>;
 543                         /* SEP 1 */
 544                 };
 545                 i2c@7 {
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                         reg = <7>;
 549                         /* SEP 0 */
 550                 };
 551         };
 552 };
 553
 554 &pinctrl0 {
 555         status = "okay";
 556         pinctrl_i2c0_default: i2c0-default {
 557                 mux {
 558                         groups = "i2c0_3_grp";
 559                         function = "i2c0";
 560                 };
 561
 562                 conf {
 563                         groups = "i2c0_3_grp";
 564                         bias-pull-up;
 565                         slew-rate = <SLEW_RATE_SLOW>;
 566                         io-standard = <IO_STANDARD_LVCMOS18>;
 567                 };
 568         };
 569
 570         pinctrl_i2c0_gpio: i2c0-gpio {
 571                 mux {
 572                         groups = "gpio0_14_grp", "gpio0_15_grp";
 573                         function = "gpio0";
 574                 };
 575
 576                 conf {
 577                         groups = "gpio0_14_grp", "gpio0_15_grp";
 578                         slew-rate = <SLEW_RATE_SLOW>;
 579                         io-standard = <IO_STANDARD_LVCMOS18>;
 580                 };
 581         };
 582
 583         pinctrl_i2c1_default: i2c1-default {
 584                 mux {
 585                         groups = "i2c1_4_grp";
 586                         function = "i2c1";
 587                 };
 588
 589                 conf {
 590                         groups = "i2c1_4_grp";
 591                         bias-pull-up;
 592                         slew-rate = <SLEW_RATE_SLOW>;
 593                         io-standard = <IO_STANDARD_LVCMOS18>;
 594                 };
 595         };
 596
 597         pinctrl_i2c1_gpio: i2c1-gpio {
 598                 mux {
 599                         groups = "gpio0_16_grp", "gpio0_17_grp";
 600                         function = "gpio0";
 601                 };
 602
 603                 conf {
 604                         groups = "gpio0_16_grp", "gpio0_17_grp";
 605                         slew-rate = <SLEW_RATE_SLOW>;
 606                         io-standard = <IO_STANDARD_LVCMOS18>;
 607                 };
 608         };
 609
 610         pinctrl_uart0_default: uart0-default {
 611                 mux {
 612                         groups = "uart0_4_grp";
 613                         function = "uart0";
 614                 };
 615
 616                 conf {
 617                         groups = "uart0_4_grp";
 618                         slew-rate = <SLEW_RATE_SLOW>;
 619                         io-standard = <IO_STANDARD_LVCMOS18>;
 620                 };
 621
 622                 conf-rx {
 623                         pins = "MIO18";
 624                         bias-high-impedance;
 625                 };
 626
 627                 conf-tx {
 628                         pins = "MIO19";
 629                         bias-disable;
 630                 };
 631         };
 632
 633         pinctrl_uart1_default: uart1-default {
 634                 mux {
 635                         groups = "uart1_5_grp";
 636                         function = "uart1";
 637                 };
 638
 639                 conf {
 640                         groups = "uart1_5_grp";
 641                         slew-rate = <SLEW_RATE_SLOW>;
 642                         io-standard = <IO_STANDARD_LVCMOS18>;
 643                 };
 644
 645                 conf-rx {
 646                         pins = "MIO21";
 647                         bias-high-impedance;
 648                 };
 649
 650                 conf-tx {
 651                         pins = "MIO20";
 652                         bias-disable;
 653                 };
 654         };
 655
 656         pinctrl_usb0_default: usb0-default {
 657                 mux {
 658                         groups = "usb0_0_grp";
 659                         function = "usb0";
 660                 };
 661
 662                 conf {
 663                         groups = "usb0_0_grp";
 664                         slew-rate = <SLEW_RATE_SLOW>;
 665                         io-standard = <IO_STANDARD_LVCMOS18>;
 666                 };
 667
 668                 conf-rx {
 669                         pins = "MIO52", "MIO53", "MIO55";
 670                         bias-high-impedance;
 671                 };
 672
 673                 conf-tx {
 674                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 675                                "MIO60", "MIO61", "MIO62", "MIO63";
 676                         bias-disable;
 677                 };
 678         };
 679
 680         pinctrl_gem3_default: gem3-default {
 681                 mux {
 682                         function = "ethernet3";
 683                         groups = "ethernet3_0_grp";
 684                 };
 685
 686                 conf {
 687                         groups = "ethernet3_0_grp";
 688                         slew-rate = <SLEW_RATE_SLOW>;
 689                         io-standard = <IO_STANDARD_LVCMOS18>;
 690                 };
 691
 692                 conf-rx {
 693                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 694                                                                         "MIO75";
 695                         bias-high-impedance;
 696                         low-power-disable;
 697                 };
 698
 699                 conf-tx {
 700                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 701                                                                         "MIO69";
 702                         bias-disable;
 703                         low-power-enable;
 704                 };
 705
 706                 mux-mdio {
 707                         function = "mdio3";
 708                         groups = "mdio3_0_grp";
 709                 };
 710
 711                 conf-mdio {
 712                         groups = "mdio3_0_grp";
 713                         slew-rate = <SLEW_RATE_SLOW>;
 714                         io-standard = <IO_STANDARD_LVCMOS18>;
 715                         bias-disable;
 716                 };
 717         };
 718
 719         pinctrl_can1_default: can1-default {
 720                 mux {
 721                         function = "can1";
 722                         groups = "can1_6_grp";
 723                 };
 724
 725                 conf {
 726                         groups = "can1_6_grp";
 727                         slew-rate = <SLEW_RATE_SLOW>;
 728                         io-standard = <IO_STANDARD_LVCMOS18>;
 729                 };
 730
 731                 conf-rx {
 732                         pins = "MIO25";
 733                         bias-high-impedance;
 734                 };
 735
 736                 conf-tx {
 737                         pins = "MIO24";
 738                         bias-disable;
 739                 };
 740         };
 741
 742         pinctrl_sdhci1_default: sdhci1-default {
 743                 mux {
 744                         groups = "sdio1_0_grp";
 745                         function = "sdio1";
 746                 };
 747
 748                 conf {
 749                         groups = "sdio1_0_grp";
 750                         slew-rate = <SLEW_RATE_SLOW>;
 751                         io-standard = <IO_STANDARD_LVCMOS18>;
 752                         bias-disable;
 753                 };
 754
 755                 mux-cd {
 756                         groups = "sdio1_0_cd_grp";
 757                         function = "sdio1_cd";
 758                 };
 759
 760                 conf-cd {
 761                         groups = "sdio1_0_cd_grp";
 762                         bias-high-impedance;
 763                         bias-pull-up;
 764                         slew-rate = <SLEW_RATE_SLOW>;
 765                         io-standard = <IO_STANDARD_LVCMOS18>;
 766                 };
 767
 768                 mux-wp {
 769                         groups = "sdio1_0_wp_grp";
 770                         function = "sdio1_wp";
 771                 };
 772
 773                 conf-wp {
 774                         groups = "sdio1_0_wp_grp";
 775                         bias-high-impedance;
 776                         bias-pull-up;
 777                         slew-rate = <SLEW_RATE_SLOW>;
 778                         io-standard = <IO_STANDARD_LVCMOS18>;
 779                 };
 780         };
 781
 782         pinctrl_gpio_default: gpio-default {
 783                 mux-sw {
 784                         function = "gpio0";
 785                         groups = "gpio0_22_grp", "gpio0_23_grp";
 786                 };
 787
 788                 conf-sw {
 789                         groups = "gpio0_22_grp", "gpio0_23_grp";
 790                         slew-rate = <SLEW_RATE_SLOW>;
 791                         io-standard = <IO_STANDARD_LVCMOS18>;
 792                 };
 793
 794                 mux-msp {
 795                         function = "gpio0";
 796                         groups = "gpio0_13_grp", "gpio0_38_grp";
 797                 };
 798
 799                 conf-msp {
 800                         groups = "gpio0_13_grp", "gpio0_38_grp";
 801                         slew-rate = <SLEW_RATE_SLOW>;
 802                         io-standard = <IO_STANDARD_LVCMOS18>;
 803                 };
 804
 805                 conf-pull-up {
 806                         pins = "MIO22", "MIO23";
 807                         bias-pull-up;
 808                 };
 809
 810                 conf-pull-none {
 811                         pins = "MIO13", "MIO38";
 812                         bias-disable;
 813                 };
 814         };
 815 };
 816
 817 &pcie {
 818         status = "okay";
 819 };
 820
 821 &qspi {
 822         status = "okay";
 823         is-dual = <1>;
 824         flash@0 {
 825                 compatible = "m25p80"; /* 32MB */
 826                 #address-cells = <1>;
 827                 #size-cells = <1>;
 828                 reg = <0x0>;
 829                 spi-tx-bus-width = <1>;
 830                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 831                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 832                 partition@qspi-fsbl-uboot { /* for testing purpose */
 833                         label = "qspi-fsbl-uboot";
 834                         reg = <0x0 0x100000>;
 835                 };
 836                 partition@qspi-linux { /* for testing purpose */
 837                         label = "qspi-linux";
 838                         reg = <0x100000 0x500000>;
 839                 };
 840                 partition@qspi-device-tree { /* for testing purpose */
 841                         label = "qspi-device-tree";
 842                         reg = <0x600000 0x20000>;
 843                 };
 844                 partition@qspi-rootfs { /* for testing purpose */
 845                         label = "qspi-rootfs";
 846                         reg = <0x620000 0x5E0000>;
 847                 };
 848         };
 849 };
 850
 851 &rtc {
 852         status = "okay";
 853 };
 854
 855 &sata {
 856         status = "okay";
 857         /* SATA OOB timing settings */
 858         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 859         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 860         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 861         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 862         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 863         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 864         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 865         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 866         phy-names = "sata-phy";
 867         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 868 };
 869
 870 /* SD1 with level shifter */
 871 &sdhci1 {
 872         status = "okay";
 873         pinctrl-names = "default";
 874         pinctrl-0 = <&pinctrl_sdhci1_default>;
 875         no-1-8-v;       /* for 1.0 silicon */
 876         xlnx,mio_bank = <1>;
 877 };
 878
 879 &serdes {
 880         status = "okay";
 881 };
 882
 883 &uart0 {
 884         status = "okay";
 885         pinctrl-names = "default";
 886         pinctrl-0 = <&pinctrl_uart0_default>;
 887 };
 888
 889 &uart1 {
 890         status = "okay";
 891         pinctrl-names = "default";
 892         pinctrl-0 = <&pinctrl_uart1_default>;
 893 };
 894
 895 /* ULPI SMSC USB3320 */
 896 &usb0 {
 897         status = "okay";
 898         pinctrl-names = "default";
 899         pinctrl-0 = <&pinctrl_usb0_default>;
 900 };
 901
 902 &dwc3_0 {
 903         status = "okay";
 904         dr_mode = "host";
 905         snps,usb3_lpm_capable;
 906         phy-names = "usb3-phy";
 907         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 908         maximum-speed = "super-speed";
 909 };
 910
 911 &watchdog0 {
 912         status = "okay";
 913 };
 914
 915 &xilinx_ams {
 916         status = "okay";
 917 };
 918
 919 &ams_ps {
 920         status = "okay";
 921 };
 922
 923 &ams_pl {
 924         status = "okay";
 925 };
 926
 927 &xilinx_drm {
 928         status = "okay";
 929         clocks = <&si570_1>;
 930 };
 931
 932 &xlnx_dp {
 933         status = "okay";
 934 };
 935
 936 &xlnx_dp_sub {
 937         status = "okay";
 938         xlnx,vid-clk-pl;
 939 };
 940
 941 &xlnx_dp_snd_pcm0 {
 942         status = "okay";
 943 };
 944
 945 &xlnx_dp_snd_pcm1 {
 946         status = "okay";
 947 };
 948
 949 &xlnx_dp_snd_card {
 950         status = "okay";
 951 };
 952
 953 &xlnx_dp_snd_codec0 {
 954         status = "okay";
 955 };
 956
 957 &xlnx_dpdma {
 958         status = "okay";
 959 };