git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-rockchip/grf_rk3188.h

   1 /*
   2  * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #ifndef _ASM_ARCH_GRF_RK3188_H
   8 #define _ASM_ARCH_GRF_RK3188_H
   9
  10 struct rk3188_grf_gpio_lh {
  11         u32 l;
  12         u32 h;
  13 };
  14
  15 struct rk3188_grf {
  16         struct rk3188_grf_gpio_lh gpio_dir[4];
  17         struct rk3188_grf_gpio_lh gpio_do[4];
  18         struct rk3188_grf_gpio_lh gpio_en[4];
  19
  20         u32 reserved[2];
  21         u32 gpio0c_iomux;
  22         u32 gpio0d_iomux;
  23
  24         u32 gpio1a_iomux;
  25         u32 gpio1b_iomux;
  26         u32 gpio1c_iomux;
  27         u32 gpio1d_iomux;
  28
  29         u32 gpio2a_iomux;
  30         u32 gpio2b_iomux;
  31         u32 gpio2c_iomux;
  32         u32 gpio2d_iomux;
  33
  34         u32 gpio3a_iomux;
  35         u32 gpio3b_iomux;
  36         u32 gpio3c_iomux;
  37         u32 gpio3d_iomux;
  38
  39         u32 soc_con0;
  40         u32 soc_con1;
  41         u32 soc_con2;
  42         u32 soc_status0;
  43
  44         u32 busdmac_con[3];
  45         u32 peridmac_con[4];
  46
  47         u32 cpu_con[6];
  48         u32 reserved0[2];
  49
  50         u32 ddrc_con0;
  51         u32 ddrc_stat;
  52
  53         u32 io_con[5];
  54         u32 soc_status1;
  55
  56         u32 uoc0_con[4];
  57         u32 uoc1_con[4];
  58         u32 uoc2_con[2];
  59         u32 reserved1;
  60         u32 uoc3_con[2];
  61         u32 hsic_stat;
  62         u32 os_reg[8];
  63
  64         u32 gpio0_p[3];
  65         u32 gpio1_p[3][4];
  66
  67         u32 flash_data_p;
  68         u32 flash_cmd_p;
  69 };
  70 check_member(rk3188_grf, flash_cmd_p, 0x01a4);
  71
  72 /* GRF_SOC_CON0 */
  73 enum {
  74         HSADC_CLK_DIR_SHIFT     = 15,
  75         HSADC_CLK_DIR_MASK      = 1,
  76
  77         HSADC_SEL_SHIFT         = 14,
  78         HSADC_SEL_MASK          = 1,
  79
  80         NOC_REMAP_SHIFT         = 12,
  81         NOC_REMAP_MASK          = 1,
  82
  83         EMMC_FLASH_SEL_SHIFT    = 11,
  84         EMMC_FLASH_SEL_MASK     = 1,
  85
  86         TZPC_REVISION_SHIFT     = 7,
  87         TZPC_REVISION_MASK      = 0xf,
  88
  89         L2CACHE_ACC_SHIFT       = 5,
  90         L2CACHE_ACC_MASK        = 3,
  91
  92         L2RD_WAIT_SHIFT         = 3,
  93         L2RD_WAIT_MASK          = 3,
  94
  95         IMEMRD_WAIT_SHIFT       = 1,
  96         IMEMRD_WAIT_MASK        = 3,
  97 };
  98
  99 /* GRF_SOC_CON1 */
 100 enum {
 101         RKI2C4_SEL_SHIFT        = 15,
 102         RKI2C4_SEL_MASK         = 1,
 103
 104         RKI2C3_SEL_SHIFT        = 14,
 105         RKI2C3_SEL_MASK         = 1,
 106
 107         RKI2C2_SEL_SHIFT        = 13,
 108         RKI2C2_SEL_MASK         = 1,
 109
 110         RKI2C1_SEL_SHIFT        = 12,
 111         RKI2C1_SEL_MASK         = 1,
 112
 113         RKI2C0_SEL_SHIFT        = 11,
 114         RKI2C0_SEL_MASK         = 1,
 115
 116         VCODEC_SEL_SHIFT        = 10,
 117         VCODEC_SEL_MASK         = 1,
 118
 119         PERI_EMEM_PAUSE_SHIFT   = 9,
 120         PERI_EMEM_PAUSE_MASK    = 1,
 121
 122         PERI_USB_PAUSE_SHIFT    = 8,
 123         PERI_USB_PAUSE_MASK     = 1,
 124
 125         SMC_MUX_MODE_0_SHIFT    = 6,
 126         SMC_MUX_MODE_0_MASK     = 1,
 127
 128         SMC_SRAM_MW_0_SHIFT     = 4,
 129         SMC_SRAM_MW_0_MASK      = 3,
 130
 131         SMC_REMAP_0_SHIFT       = 3,
 132         SMC_REMAP_0_MASK        = 1,
 133
 134         SMC_A_GT_M0_SYNC_SHIFT  = 2,
 135         SMC_A_GT_M0_SYNC_MASK   = 1,
 136
 137         EMAC_SPEED_SHIFT        = 1,
 138         EMAC_SPEEC_MASK         = 1,
 139
 140         EMAC_MODE_SHIFT         = 0,
 141         EMAC_MODE_MASK          = 1,
 142 };
 143
 144 /* GRF_SOC_CON2 */
 145 enum {
 146         SDIO_CLK_OUT_SR_SHIFT   = 15,
 147         SDIO_CLK_OUT_SR_MASK    = 1,
 148
 149         MEM_EMA_L2C_SHIFT       = 11,
 150         MEM_EMA_L2C_MASK        = 7,
 151
 152         MEM_EMA_A9_SHIFT        = 8,
 153         MEM_EMA_A9_MASK         = 7,
 154
 155         MSCH4_MAINDDR3_SHIFT    = 7,
 156         MSCH4_MAINDDR3_MASK     = 1,
 157         MSCH4_MAINDDR3_DDR3     = 1,
 158
 159         EMAC_NEWRCV_EN_SHIFT    = 6,
 160         EMAC_NEWRCV_EN_MASK     = 1,
 161
 162         SW_ADDR15_EN_SHIFT      = 5,
 163         SW_ADDR15_EN_MASK       = 1,
 164
 165         SW_ADDR16_EN_SHIFT      = 4,
 166         SW_ADDR16_EN_MASK       = 1,
 167
 168         SW_ADDR17_EN_SHIFT      = 3,
 169         SW_ADDR17_EN_MASK       = 1,
 170
 171         BANK2_TO_RANK_EN_SHIFT  = 2,
 172         BANK2_TO_RANK_EN_MASK   = 1,
 173
 174         RANK_TO_ROW15_EN_SHIFT  = 1,
 175         RANK_TO_ROW15_EN_MASK   = 1,
 176
 177         UPCTL_C_ACTIVE_IN_SHIFT = 0,
 178         UPCTL_C_ACTIVE_IN_MASK  = 1,
 179         UPCTL_C_ACTIVE_IN_MAY   = 0,
 180         UPCTL_C_ACTIVE_IN_WILL,
 181 };
 182
 183 /* GRF_DDRC_CON0 */
 184 enum {
 185         DDR_16BIT_EN_SHIFT      = 15,
 186         DDR_16BIT_EN_MASK       = 1,
 187
 188         DTO_LB_SHIFT            = 11,
 189         DTO_LB_MASK             = 3,
 190
 191         DTO_TE_SHIFT            = 9,
 192         DTO_TE_MASK             = 3,
 193
 194         DTO_PDR_SHIFT           = 7,
 195         DTO_PDR_MASK            = 3,
 196
 197         DTO_PDD_SHIFT           = 5,
 198         DTO_PDD_MASK            = 3,
 199
 200         DTO_IOM_SHIFT           = 3,
 201         DTO_IOM_MASK            = 3,
 202
 203         DTO_OE_SHIFT            = 1,
 204         DTO_OE_MASK             = 3,
 205
 206         ATO_AE_SHIFT            = 0,
 207         ATO_AE_MASK             = 1,
 208 };
 209 #endif