git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-rockchip/grf_rk3188.h

   1 /*
   2  * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #ifndef _ASM_ARCH_GRF_RK3188_H
   8 #define _ASM_ARCH_GRF_RK3188_H
   9
  10 struct rk3188_grf_gpio_lh {
  11         u32 l;
  12         u32 h;
  13 };
  14
  15 struct rk3188_grf {
  16         struct rk3188_grf_gpio_lh gpio_dir[4];
  17         struct rk3188_grf_gpio_lh gpio_do[4];
  18         struct rk3188_grf_gpio_lh gpio_en[4];
  19
  20         u32 reserved[2];
  21         u32 gpio0c_iomux;
  22         u32 gpio0d_iomux;
  23
  24         u32 gpio1a_iomux;
  25         u32 gpio1b_iomux;
  26         u32 gpio1c_iomux;
  27         u32 gpio1d_iomux;
  28
  29         u32 gpio2a_iomux;
  30         u32 gpio2b_iomux;
  31         u32 gpio2c_iomux;
  32         u32 gpio2d_iomux;
  33
  34         u32 gpio3a_iomux;
  35         u32 gpio3b_iomux;
  36         u32 gpio3c_iomux;
  37         u32 gpio3d_iomux;
  38
  39         u32 soc_con0;
  40         u32 soc_con1;
  41         u32 soc_con2;
  42         u32 soc_status0;
  43
  44         u32 busdmac_con[3];
  45         u32 peridmac_con[4];
  46
  47         u32 cpu_con[6];
  48         u32 reserved0[2];
  49
  50         u32 ddrc_con0;
  51         u32 ddrc_stat;
  52
  53         u32 io_con[5];
  54         u32 soc_status1;
  55
  56         u32 uoc0_con[4];
  57         u32 uoc1_con[4];
  58         u32 uoc2_con[2];
  59         u32 reserved1;
  60         u32 uoc3_con[2];
  61         u32 hsic_stat;
  62         u32 os_reg[8];
  63
  64         u32 gpio0_p[3];
  65         u32 gpio1_p[3][4];
  66
  67         u32 flash_data_p;
  68         u32 flash_cmd_p;
  69 };
  70 check_member(rk3188_grf, flash_cmd_p, 0x01a4);
  71
  72 /* GRF_GPIO0D_IOMUX */
  73 enum {
  74         GPIO0D7_SHIFT           = 14,
  75         GPIO0D7_MASK            = 1,
  76         GPIO0D7_GPIO            = 0,
  77         GPIO0D7_SPI1_CSN0,
  78
  79         GPIO0D6_SHIFT           = 12,
  80         GPIO0D6_MASK            = 1,
  81         GPIO0D6_GPIO            = 0,
  82         GPIO0D6_SPI1_CLK,
  83
  84         GPIO0D5_SHIFT           = 10,
  85         GPIO0D5_MASK            = 1,
  86         GPIO0D5_GPIO            = 0,
  87         GPIO0D5_SPI1_TXD,
  88
  89         GPIO0D4_SHIFT           = 8,
  90         GPIO0D4_MASK            = 1,
  91         GPIO0D4_GPIO            = 0,
  92         GPIO0D4_SPI0_RXD,
  93
  94         GPIO0D3_SHIFT           = 6,
  95         GPIO0D3_MASK            = 3,
  96         GPIO0D3_GPIO            = 0,
  97         GPIO0D3_FLASH_CSN3,
  98         GPIO0D3_EMMC_RSTN_OUT,
  99
 100         GPIO0D2_SHIFT           = 4,
 101         GPIO0D2_MASK            = 3,
 102         GPIO0D2_GPIO            = 0,
 103         GPIO0D2_FLASH_CSN2,
 104         GPIO0D2_EMMC_CMD,
 105
 106         GPIO0D1_SHIFT           = 2,
 107         GPIO0D1_MASK            = 1,
 108         GPIO0D1_GPIO            = 0,
 109         GPIO0D1_FLASH_CSN1,
 110
 111         GPIO0D0_SHIFT           = 0,
 112         GPIO0D0_MASK            = 3,
 113         GPIO0D0_GPIO            = 0,
 114         GPIO0D0_FLASH_DQS,
 115         GPIO0D0_EMMC_CLKOUT
 116 };
 117
 118 /* GRF_GPIO1A_IOMUX */
 119 enum {
 120         GPIO1A7_SHIFT           = 14,
 121         GPIO1A7_MASK            = 3,
 122         GPIO1A7_GPIO            = 0,
 123         GPIO1A7_UART1_RTS_N,
 124         GPIO1A7_SPI0_CSN0,
 125
 126         GPIO1A6_SHIFT           = 12,
 127         GPIO1A6_MASK            = 3,
 128         GPIO1A6_GPIO            = 0,
 129         GPIO1A6_UART1_CTS_N,
 130         GPIO1A6_SPI0_CLK,
 131
 132         GPIO1A5_SHIFT           = 10,
 133         GPIO1A5_MASK            = 3,
 134         GPIO1A5_GPIO            = 0,
 135         GPIO1A5_UART1_SOUT,
 136         GPIO1A5_SPI0_TXD,
 137
 138         GPIO1A4_SHIFT           = 8,
 139         GPIO1A4_MASK            = 3,
 140         GPIO1A4_GPIO            = 0,
 141         GPIO1A4_UART1_SIN,
 142         GPIO1A4_SPI0_RXD,
 143
 144         GPIO1A3_SHIFT           = 6,
 145         GPIO1A3_MASK            = 1,
 146         GPIO1A3_GPIO            = 0,
 147         GPIO1A3_UART0_RTS_N,
 148
 149         GPIO1A2_SHIFT           = 4,
 150         GPIO1A2_MASK            = 1,
 151         GPIO1A2_GPIO            = 0,
 152         GPIO1A2_UART0_CTS_N,
 153
 154         GPIO1A1_SHIFT           = 2,
 155         GPIO1A1_MASK            = 1,
 156         GPIO1A1_GPIO            = 0,
 157         GPIO1A1_UART0_SOUT,
 158
 159         GPIO1A0_SHIFT           = 0,
 160         GPIO1A0_MASK            = 1,
 161         GPIO1A0_GPIO            = 0,
 162         GPIO1A0_UART0_SIN,
 163 };
 164
 165 /* GRF_GPIO1B_IOMUX */
 166 enum {
 167         GPIO1B7_SHIFT           = 14,
 168         GPIO1B7_MASK            = 1,
 169         GPIO1B7_GPIO            = 0,
 170         GPIO1B7_SPI0_CSN1,
 171
 172         GPIO1B6_SHIFT           = 12,
 173         GPIO1B6_MASK            = 3,
 174         GPIO1B6_GPIO            = 0,
 175         GPIO1B6_SPDIF_TX,
 176         GPIO1B6_SPI1_CSN1,
 177
 178         GPIO1B5_SHIFT           = 10,
 179         GPIO1B5_MASK            = 3,
 180         GPIO1B5_GPIO            = 0,
 181         GPIO1B5_UART3_RTS_N,
 182         GPIO1B5_RESERVED,
 183
 184         GPIO1B4_SHIFT           = 8,
 185         GPIO1B4_MASK            = 3,
 186         GPIO1B4_GPIO            = 0,
 187         GPIO1B4_UART3_CTS_N,
 188         GPIO1B4_GPS_RFCLK,
 189
 190         GPIO1B3_SHIFT           = 6,
 191         GPIO1B3_MASK            = 3,
 192         GPIO1B3_GPIO            = 0,
 193         GPIO1B3_UART3_SOUT,
 194         GPIO1B3_GPS_SIG,
 195
 196         GPIO1B2_SHIFT           = 4,
 197         GPIO1B2_MASK            = 3,
 198         GPIO1B2_GPIO            = 0,
 199         GPIO1B2_UART3_SIN,
 200         GPIO1B2_GPS_MAG,
 201
 202         GPIO1B1_SHIFT           = 2,
 203         GPIO1B1_MASK            = 3,
 204         GPIO1B1_GPIO            = 0,
 205         GPIO1B1_UART2_SOUT,
 206         GPIO1B1_JTAG_TDO,
 207
 208         GPIO1B0_SHIFT           = 0,
 209         GPIO1B0_MASK            = 3,
 210         GPIO1B0_GPIO            = 0,
 211         GPIO1B0_UART2_SIN,
 212         GPIO1B0_JTAG_TDI,
 213 };
 214
 215 /* GRF_GPIO1D_IOMUX */
 216 enum {
 217         GPIO1D7_SHIFT           = 14,
 218         GPIO1D7_MASK            = 1,
 219         GPIO1D7_GPIO            = 0,
 220         GPIO1D7_I2C4_SCL,
 221
 222         GPIO1D6_SHIFT           = 12,
 223         GPIO1D6_MASK            = 1,
 224         GPIO1D6_GPIO            = 0,
 225         GPIO1D6_I2C4_SDA,
 226
 227         GPIO1D5_SHIFT           = 10,
 228         GPIO1D5_MASK            = 1,
 229         GPIO1D5_GPIO            = 0,
 230         GPIO1D5_I2C2_SCL,
 231
 232         GPIO1D4_SHIFT           = 8,
 233         GPIO1D4_MASK            = 1,
 234         GPIO1D4_GPIO            = 0,
 235         GPIO1D4_I2C2_SDA,
 236
 237         GPIO1D3_SHIFT           = 6,
 238         GPIO1D3_MASK            = 1,
 239         GPIO1D3_GPIO            = 0,
 240         GPIO1D3_I2C1_SCL,
 241
 242         GPIO1D2_SHIFT           = 4,
 243         GPIO1D2_MASK            = 1,
 244         GPIO1D2_GPIO            = 0,
 245         GPIO1D2_I2C1_SDA,
 246
 247         GPIO1D1_SHIFT           = 2,
 248         GPIO1D1_MASK            = 1,
 249         GPIO1D1_GPIO            = 0,
 250         GPIO1D1_I2C0_SCL,
 251
 252         GPIO1D0_SHIFT           = 0,
 253         GPIO1D0_MASK            = 1,
 254         GPIO1D0_GPIO            = 0,
 255         GPIO1D0_I2C0_SDA,
 256 };
 257
 258 /* GRF_GPIO3A_IOMUX */
 259 enum {
 260         GPIO3A7_SHIFT           = 14,
 261         GPIO3A7_MASK            = 1,
 262         GPIO3A7_GPIO            = 0,
 263         GPIO3A7_SDMMC0_DATA3,
 264
 265         GPIO3A6_SHIFT           = 12,
 266         GPIO3A6_MASK            = 1,
 267         GPIO3A6_GPIO            = 0,
 268         GPIO3A6_SDMMC0_DATA2,
 269
 270         GPIO3A5_SHIFT           = 10,
 271         GPIO3A5_MASK            = 1,
 272         GPIO3A5_GPIO            = 0,
 273         GPIO3A5_SDMMC0_DATA1,
 274
 275         GPIO3A4_SHIFT           = 8,
 276         GPIO3A4_MASK            = 1,
 277         GPIO3A4_GPIO            = 0,
 278         GPIO3A4_SDMMC0_DATA0,
 279
 280         GPIO3A3_SHIFT           = 6,
 281         GPIO3A3_MASK            = 1,
 282         GPIO3A3_GPIO            = 0,
 283         GPIO3A3_SDMMC0_CMD,
 284
 285         GPIO3A2_SHIFT           = 4,
 286         GPIO3A2_MASK            = 1,
 287         GPIO3A2_GPIO            = 0,
 288         GPIO3A2_SDMMC0_CLKOUT,
 289
 290         GPIO3A1_SHIFT           = 2,
 291         GPIO3A1_MASK            = 1,
 292         GPIO3A1_GPIO            = 0,
 293         GPIO3A1_SDMMC0_PWREN,
 294
 295         GPIO3A0_SHIFT           = 0,
 296         GPIO3A0_MASK            = 1,
 297         GPIO3A0_GPIO            = 0,
 298         GPIO3A0_SDMMC0_RSTN,
 299 };
 300
 301 /* GRF_GPIO3B_IOMUX */
 302 enum {
 303         GPIO3B7_SHIFT           = 14,
 304         GPIO3B7_MASK            = 3,
 305         GPIO3B7_GPIO            = 0,
 306         GPIO3B7_CIF_DATA11,
 307         GPIO3B7_I2C3_SCL,
 308
 309         GPIO3B6_SHIFT           = 12,
 310         GPIO3B6_MASK            = 3,
 311         GPIO3B6_GPIO            = 0,
 312         GPIO3B6_CIF_DATA10,
 313         GPIO3B6_I2C3_SDA,
 314
 315         GPIO3B5_SHIFT           = 10,
 316         GPIO3B5_MASK            = 3,
 317         GPIO3B5_GPIO            = 0,
 318         GPIO3B5_CIF_DATA1,
 319         GPIO3B5_HSADC_DATA9,
 320
 321         GPIO3B4_SHIFT           = 8,
 322         GPIO3B4_MASK            = 3,
 323         GPIO3B4_GPIO            = 0,
 324         GPIO3B4_CIF_DATA0,
 325         GPIO3B4_HSADC_DATA8,
 326
 327         GPIO3B3_SHIFT           = 6,
 328         GPIO3B3_MASK            = 1,
 329         GPIO3B3_GPIO            = 0,
 330         GPIO3B3_CIF_CLKOUT,
 331
 332         GPIO3B2_SHIFT           = 4,
 333         GPIO3B2_MASK            = 1,
 334         GPIO3B2_GPIO            = 0,
 335         /* no muxes */
 336
 337         GPIO3B1_SHIFT           = 2,
 338         GPIO3B1_MASK            = 1,
 339         GPIO3B1_GPIO            = 0,
 340         GPIO3B1_SDMMC0_WRITE_PRT,
 341
 342         GPIO3B0_SHIFT           = 0,
 343         GPIO3B0_MASK            = 1,
 344         GPIO3B0_GPIO            = 0,
 345         GPIO3B0_SDMMC_DETECT_N,
 346 };
 347
 348 /* GRF_GPIO3C_IOMUX */
 349 enum {
 350         GPIO3C7_SHIFT           = 14,
 351         GPIO3C7_MASK            = 3,
 352         GPIO3C7_GPIO            = 0,
 353         GPIO3C7_SDMMC1_WRITE_PRT,
 354         GPIO3C7_RMII_CRS_DVALID,
 355         GPIO3C7_RESERVED,
 356
 357         GPIO3C6_SHIFT           = 12,
 358         GPIO3C6_MASK            = 3,
 359         GPIO3C6_GPIO            = 0,
 360         GPIO3C6_SDMMC1_DECTN,
 361         GPIO3C6_RMII_RX_ERR,
 362         GPIO3C6_RESERVED,
 363
 364         GPIO3C5_SHIFT           = 10,
 365         GPIO3C5_MASK            = 3,
 366         GPIO3C5_GPIO            = 0,
 367         GPIO3C5_SDMMC1_CLKOUT,
 368         GPIO3C5_RMII_CLKOUT,
 369         GPIO3C5_RMII_CLKIN,
 370
 371         GPIO3C4_SHIFT           = 8,
 372         GPIO3C4_MASK            = 3,
 373         GPIO3C4_GPIO            = 0,
 374         GPIO3C4_SDMMC1_DATA3,
 375         GPIO3C4_RMII_RXD1,
 376         GPIO3C4_RESERVED,
 377
 378         GPIO3C3_SHIFT           = 6,
 379         GPIO3C3_MASK            = 3,
 380         GPIO3C3_GPIO            = 0,
 381         GPIO3C3_SDMMC1_DATA2,
 382         GPIO3C3_RMII_RXD0,
 383         GPIO3C3_RESERVED,
 384
 385         GPIO3C2_SHIFT           = 4,
 386         GPIO3C2_MASK            = 3,
 387         GPIO3C2_GPIO            = 0,
 388         GPIO3C2_SDMMC1_DATA1,
 389         GPIO3C2_RMII_TXD0,
 390         GPIO3C2_RESERVED,
 391
 392         GPIO3C1_SHIFT           = 2,
 393         GPIO3C1_MASK            = 3,
 394         GPIO3C1_GPIO            = 0,
 395         GPIO3C1_SDMMC1_DATA0,
 396         GPIO3C1_RMII_TXD1,
 397         GPIO3C1_RESERVED,
 398
 399         GPIO3C0_SHIFT           = 0,
 400         GPIO3C0_MASK            = 3,
 401         GPIO3C0_GPIO            = 0,
 402         GPIO3C0_SDMMC1_CMD,
 403         GPIO3C0_RMII_TX_EN,
 404         GPIO3C0_RESERVED,
 405 };
 406
 407 /* GRF_GPIO3D_IOMUX */
 408 enum {
 409         GPIO3D6_SHIFT           = 12,
 410         GPIO3D6_MASK            = 3,
 411         GPIO3D6_GPIO            = 0,
 412         GPIO3D6_PWM_3,
 413         GPIO3D6_JTAG_TMS,
 414         GPIO3D6_HOST_DRV_VBUS,
 415
 416         GPIO3D5_SHIFT           = 10,
 417         GPIO3D5_MASK            = 3,
 418         GPIO3D5_GPIO            = 0,
 419         GPIO3D5_PWM_2,
 420         GPIO3D5_JTAG_TCK,
 421         GPIO3D5_OTG_DRV_VBUS,
 422
 423         GPIO3D4_SHIFT           = 8,
 424         GPIO3D4_MASK            = 3,
 425         GPIO3D4_GPIO            = 0,
 426         GPIO3D4_PWM_1,
 427         GPIO3D4_JTAG_TRSTN,
 428
 429         GPIO3D3_SHIFT           = 6,
 430         GPIO3D3_MASK            = 3,
 431         GPIO3D3_GPIO            = 0,
 432         GPIO3D3_PWM_0,
 433
 434         GPIO3D2_SHIFT           = 4,
 435         GPIO3D2_MASK            = 3,
 436         GPIO3D2_GPIO            = 0,
 437         GPIO3D2_SDMMC1_INT_N,
 438
 439         GPIO3D1_SHIFT           = 2,
 440         GPIO3D1_MASK            = 3,
 441         GPIO3D1_GPIO            = 0,
 442         GPIO3D1_SDMMC1_BACKEND_PWR,
 443         GPIO3D1_MII_MDCLK,
 444
 445         GPIO3D0_SHIFT           = 0,
 446         GPIO3D0_MASK            = 3,
 447         GPIO3D0_GPIO            = 0,
 448         GPIO3D0_SDMMC1_PWR_EN,
 449         GPIO3D0_MII_MD,
 450 };
 451
 452 /* GRF_SOC_CON0 */
 453 enum {
 454         HSADC_CLK_DIR_SHIFT     = 15,
 455         HSADC_CLK_DIR_MASK      = 1,
 456
 457         HSADC_SEL_SHIFT         = 14,
 458         HSADC_SEL_MASK          = 1,
 459
 460         NOC_REMAP_SHIFT         = 12,
 461         NOC_REMAP_MASK          = 1,
 462
 463         EMMC_FLASH_SEL_SHIFT    = 11,
 464         EMMC_FLASH_SEL_MASK     = 1,
 465
 466         TZPC_REVISION_SHIFT     = 7,
 467         TZPC_REVISION_MASK      = 0xf,
 468
 469         L2CACHE_ACC_SHIFT       = 5,
 470         L2CACHE_ACC_MASK        = 3,
 471
 472         L2RD_WAIT_SHIFT         = 3,
 473         L2RD_WAIT_MASK          = 3,
 474
 475         IMEMRD_WAIT_SHIFT       = 1,
 476         IMEMRD_WAIT_MASK        = 3,
 477 };
 478
 479 /* GRF_SOC_CON1 */
 480 enum {
 481         RKI2C4_SEL_SHIFT        = 15,
 482         RKI2C4_SEL_MASK         = 1,
 483
 484         RKI2C3_SEL_SHIFT        = 14,
 485         RKI2C3_SEL_MASK         = 1,
 486
 487         RKI2C2_SEL_SHIFT        = 13,
 488         RKI2C2_SEL_MASK         = 1,
 489
 490         RKI2C1_SEL_SHIFT        = 12,
 491         RKI2C1_SEL_MASK         = 1,
 492
 493         RKI2C0_SEL_SHIFT        = 11,
 494         RKI2C0_SEL_MASK         = 1,
 495
 496         VCODEC_SEL_SHIFT        = 10,
 497         VCODEC_SEL_MASK         = 1,
 498
 499         PERI_EMEM_PAUSE_SHIFT   = 9,
 500         PERI_EMEM_PAUSE_MASK    = 1,
 501
 502         PERI_USB_PAUSE_SHIFT    = 8,
 503         PERI_USB_PAUSE_MASK     = 1,
 504
 505         SMC_MUX_MODE_0_SHIFT    = 6,
 506         SMC_MUX_MODE_0_MASK     = 1,
 507
 508         SMC_SRAM_MW_0_SHIFT     = 4,
 509         SMC_SRAM_MW_0_MASK      = 3,
 510
 511         SMC_REMAP_0_SHIFT       = 3,
 512         SMC_REMAP_0_MASK        = 1,
 513
 514         SMC_A_GT_M0_SYNC_SHIFT  = 2,
 515         SMC_A_GT_M0_SYNC_MASK   = 1,
 516
 517         EMAC_SPEED_SHIFT        = 1,
 518         EMAC_SPEEC_MASK         = 1,
 519
 520         EMAC_MODE_SHIFT         = 0,
 521         EMAC_MODE_MASK          = 1,
 522 };
 523
 524 /* GRF_SOC_CON2 */
 525 enum {
 526         SDIO_CLK_OUT_SR_SHIFT   = 15,
 527         SDIO_CLK_OUT_SR_MASK    = 1,
 528
 529         MEM_EMA_L2C_SHIFT       = 11,
 530         MEM_EMA_L2C_MASK        = 7,
 531
 532         MEM_EMA_A9_SHIFT        = 8,
 533         MEM_EMA_A9_MASK         = 7,
 534
 535         MSCH4_MAINDDR3_SHIFT    = 7,
 536         MSCH4_MAINDDR3_MASK     = 1,
 537         MSCH4_MAINDDR3_DDR3     = 1,
 538
 539         EMAC_NEWRCV_EN_SHIFT    = 6,
 540         EMAC_NEWRCV_EN_MASK     = 1,
 541
 542         SW_ADDR15_EN_SHIFT      = 5,
 543         SW_ADDR15_EN_MASK       = 1,
 544
 545         SW_ADDR16_EN_SHIFT      = 4,
 546         SW_ADDR16_EN_MASK       = 1,
 547
 548         SW_ADDR17_EN_SHIFT      = 3,
 549         SW_ADDR17_EN_MASK       = 1,
 550
 551         BANK2_TO_RANK_EN_SHIFT  = 2,
 552         BANK2_TO_RANK_EN_MASK   = 1,
 553
 554         RANK_TO_ROW15_EN_SHIFT  = 1,
 555         RANK_TO_ROW15_EN_MASK   = 1,
 556
 557         UPCTL_C_ACTIVE_IN_SHIFT = 0,
 558         UPCTL_C_ACTIVE_IN_MASK  = 1,
 559         UPCTL_C_ACTIVE_IN_MAY   = 0,
 560         UPCTL_C_ACTIVE_IN_WILL,
 561 };
 562
 563 /* GRF_DDRC_CON0 */
 564 enum {
 565         DDR_16BIT_EN_SHIFT      = 15,
 566         DDR_16BIT_EN_MASK       = 1,
 567
 568         DTO_LB_SHIFT            = 11,
 569         DTO_LB_MASK             = 3,
 570
 571         DTO_TE_SHIFT            = 9,
 572         DTO_TE_MASK             = 3,
 573
 574         DTO_PDR_SHIFT           = 7,
 575         DTO_PDR_MASK            = 3,
 576
 577         DTO_PDD_SHIFT           = 5,
 578         DTO_PDD_MASK            = 3,
 579
 580         DTO_IOM_SHIFT           = 3,
 581         DTO_IOM_MASK            = 3,
 582
 583         DTO_OE_SHIFT            = 1,
 584         DTO_OE_MASK             = 3,
 585
 586         ATO_AE_SHIFT            = 0,
 587         ATO_AE_MASK             = 1,
 588 };
 589 #endif