]> git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
f39e81bfbae6ade3dcc0bccdc0f8494c2b992b5c
[u-boot] / arch / arm / include / asm / arch-s32v234 / mc_rgm_regs.h
1 /*
2  * (C) Copyright 2015, Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
8 #define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
9
10 #define MC_RGM_DES                      (MC_RGM_BASE_ADDR)
11 #define MC_RGM_FES                      (MC_RGM_BASE_ADDR + 0x300)
12 #define MC_RGM_FERD                     (MC_RGM_BASE_ADDR + 0x310)
13 #define MC_RGM_FBRE                     (MC_RGM_BASE_ADDR + 0x330)
14 #define MC_RGM_FESS                     (MC_RGM_BASE_ADDR + 0x340)
15 #define MC_RGM_DDR_HE                   (MC_RGM_BASE_ADDR + 0x350)
16 #define MC_RGM_DDR_HS                   (MC_RGM_BASE_ADDR + 0x354)
17 #define MC_RGM_FRHE                     (MC_RGM_BASE_ADDR + 0x358)
18 #define MC_RGM_FREC                     (MC_RGM_BASE_ADDR + 0x600)
19 #define MC_RGM_FRET                     (MC_RGM_BASE_ADDR + 0x607)
20 #define MC_RGM_DRET                     (MC_RGM_BASE_ADDR + 0x60B)
21
22 /* function reset sources mask */
23 #define F_SWT4                          0x8000
24 #define F_JTAG                          0x400
25 #define F_FCCU_SOFT                     0x40
26 #define F_FCCU_HARD                     0x20
27 #define F_SOFT_FUNC                     0x8
28 #define F_ST_DONE                       0x4
29 #define F_EXT_RST                       0x1
30
31 #endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */