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   1 /*
   2  * NVIDIA Tegra I2C controller
   3  *
   4  * Copyright 2010-2011 NVIDIA Corporation
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0
   7  */
   8
   9 #ifndef _TEGRA_I2C_H_
  10 #define _TEGRA_I2C_H_
  11
  12 #include <asm/types.h>
  13
  14 enum {
  15         I2C_TIMEOUT_USEC = 10000,       /* Wait time for completion */
  16         I2C_FIFO_DEPTH = 8,             /* I2C fifo depth */
  17 };
  18
  19 enum i2c_transaction_flags {
  20         I2C_IS_WRITE = 0x1,             /* for I2C write operation */
  21         I2C_IS_10_BIT_ADDRESS = 0x2,    /* for 10-bit I2C slave address */
  22         I2C_USE_REPEATED_START = 0x4,   /* for repeat start */
  23         I2C_NO_ACK = 0x8,               /* for slave that won't generate ACK */
  24         I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */
  25         I2C_NO_STOP = 0x20,
  26 };
  27
  28 /* Contians the I2C transaction details */
  29 struct i2c_trans_info {
  30         /* flags to indicate the transaction details */
  31         enum i2c_transaction_flags flags;
  32         u32 address;    /* I2C slave device address */
  33         u32 num_bytes;  /* number of bytes to be transferred */
  34         /*
  35          * Send/receive buffer. For the I2C send operation this buffer should
  36          * be filled with the data to be sent to the slave device. For the I2C
  37          * receive operation this buffer is filled with the data received from
  38          * the slave device.
  39          */
  40         u8 *buf;
  41         int is_10bit_address;
  42 };
  43
  44 struct i2c_control {
  45         u32 tx_fifo;
  46         u32 rx_fifo;
  47         u32 packet_status;
  48         u32 fifo_control;
  49         u32 fifo_status;
  50         u32 int_mask;
  51         u32 int_status;
  52 };
  53
  54 struct dvc_ctlr {
  55         u32 ctrl1;                      /* 00: DVC_CTRL_REG1 */
  56         u32 ctrl2;                      /* 04: DVC_CTRL_REG2 */
  57         u32 ctrl3;                      /* 08: DVC_CTRL_REG3 */
  58         u32 status;                     /* 0C: DVC_STATUS_REG */
  59         u32 ctrl;                       /* 10: DVC_I2C_CTRL_REG */
  60         u32 addr_data;                  /* 14: DVC_I2C_ADDR_DATA_REG */
  61         u32 reserved_0[2];              /* 18: */
  62         u32 req;                        /* 20: DVC_REQ_REGISTER */
  63         u32 addr_data3;                 /* 24: DVC_I2C_ADDR_DATA_REG_3 */
  64         u32 reserved_1[6];              /* 28: */
  65         u32 cnfg;                       /* 40: DVC_I2C_CNFG */
  66         u32 cmd_addr0;                  /* 44: DVC_I2C_CMD_ADDR0 */
  67         u32 cmd_addr1;                  /* 48: DVC_I2C_CMD_ADDR1 */
  68         u32 cmd_data1;                  /* 4C: DVC_I2C_CMD_DATA1 */
  69         u32 cmd_data2;                  /* 50: DVC_I2C_CMD_DATA2 */
  70         u32 reserved_2[2];              /* 54: */
  71         u32 i2c_status;                 /* 5C: DVC_I2C_STATUS */
  72         struct i2c_control control;     /* 60 ~ 78 */
  73 };
  74
  75 struct i2c_ctlr {
  76         u32 cnfg;                       /* 00: I2C_I2C_CNFG */
  77         u32 cmd_addr0;                  /* 04: I2C_I2C_CMD_ADDR0 */
  78         u32 cmd_addr1;                  /* 08: I2C_I2C_CMD_DATA1 */
  79         u32 cmd_data1;                  /* 0C: I2C_I2C_CMD_DATA2 */
  80         u32 cmd_data2;                  /* 10: DVC_I2C_CMD_DATA2 */
  81         u32 reserved_0[2];              /* 14: */
  82         u32 status;                     /* 1C: I2C_I2C_STATUS */
  83         u32 sl_cnfg;                    /* 20: I2C_I2C_SL_CNFG */
  84         u32 sl_rcvd;                    /* 24: I2C_I2C_SL_RCVD */
  85         u32 sl_status;                  /* 28: I2C_I2C_SL_STATUS */
  86         u32 sl_addr1;                   /* 2C: I2C_I2C_SL_ADDR1 */
  87         u32 sl_addr2;                   /* 30: I2C_I2C_SL_ADDR2 */
  88         u32 reserved_1[2];              /* 34: */
  89         u32 sl_delay_count;             /* 3C: I2C_I2C_SL_DELAY_COUNT */
  90         u32 reserved_2[4];              /* 40: */
  91         struct i2c_control control;     /* 50 ~ 68 */
  92         u32 clk_div;                    /* 6C: I2C_I2C_CLOCK_DIVISOR */
  93 };
  94
  95 /* bit fields definitions for IO Packet Header 1 format */
  96 #define PKT_HDR1_PROTOCOL_SHIFT         4
  97 #define PKT_HDR1_PROTOCOL_MASK          (0xf << PKT_HDR1_PROTOCOL_SHIFT)
  98 #define PKT_HDR1_CTLR_ID_SHIFT          12
  99 #define PKT_HDR1_CTLR_ID_MASK           (0xf << PKT_HDR1_CTLR_ID_SHIFT)
 100 #define PKT_HDR1_PKT_ID_SHIFT           16
 101 #define PKT_HDR1_PKT_ID_MASK            (0xff << PKT_HDR1_PKT_ID_SHIFT)
 102 #define PROTOCOL_TYPE_I2C               1
 103
 104 /* bit fields definitions for IO Packet Header 2 format */
 105 #define PKT_HDR2_PAYLOAD_SIZE_SHIFT     0
 106 #define PKT_HDR2_PAYLOAD_SIZE_MASK      (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
 107
 108 /* bit fields definitions for IO Packet Header 3 format */
 109 #define PKT_HDR3_READ_MODE_SHIFT        19
 110 #define PKT_HDR3_READ_MODE_MASK         (1 << PKT_HDR3_READ_MODE_SHIFT)
 111 #define PKT_HDR3_REPEAT_START_SHIFT     16
 112 #define PKT_HDR3_REPEAT_START_MASK      (1 << PKT_HDR3_REPEAT_START_SHIFT)
 113 #define PKT_HDR3_SLAVE_ADDR_SHIFT       0
 114 #define PKT_HDR3_SLAVE_ADDR_MASK        (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
 115
 116 #define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT      26
 117 #define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK       \
 118                                 (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
 119
 120 /* I2C_CNFG */
 121 #define I2C_CNFG_NEW_MASTER_FSM_SHIFT   11
 122 #define I2C_CNFG_NEW_MASTER_FSM_MASK    (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
 123 #define I2C_CNFG_PACKET_MODE_SHIFT      10
 124 #define I2C_CNFG_PACKET_MODE_MASK       (1 << I2C_CNFG_PACKET_MODE_SHIFT)
 125
 126 /* I2C_SL_CNFG */
 127 #define I2C_SL_CNFG_NEWSL_SHIFT         2
 128 #define I2C_SL_CNFG_NEWSL_MASK          (1 << I2C_SL_CNFG_NEWSL_SHIFT)
 129
 130 /* I2C_FIFO_STATUS */
 131 #define TX_FIFO_FULL_CNT_SHIFT          0
 132 #define TX_FIFO_FULL_CNT_MASK           (0xf << TX_FIFO_FULL_CNT_SHIFT)
 133 #define TX_FIFO_EMPTY_CNT_SHIFT         4
 134 #define TX_FIFO_EMPTY_CNT_MASK          (0xf << TX_FIFO_EMPTY_CNT_SHIFT)
 135
 136 /* I2C_INTERRUPT_STATUS */
 137 #define I2C_INT_XFER_COMPLETE_SHIFT     7
 138 #define I2C_INT_XFER_COMPLETE_MASK      (1 << I2C_INT_XFER_COMPLETE_SHIFT)
 139 #define I2C_INT_NO_ACK_SHIFT            3
 140 #define I2C_INT_NO_ACK_MASK             (1 << I2C_INT_NO_ACK_SHIFT)
 141 #define I2C_INT_ARBITRATION_LOST_SHIFT  2
 142 #define I2C_INT_ARBITRATION_LOST_MASK   (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
 143
 144 /* I2C_CLK_DIVISOR_REGISTER */
 145 #define CLK_DIV_STD_FAST_MODE           0x19
 146 #define CLK_DIV_HS_MODE                 1
 147 #define CLK_MULT_STD_FAST_MODE          8
 148
 149 /**
 150  * Returns the bus number of the DVC controller
 151  *
 152  * @return number of bus, or -1 if there is no DVC active
 153  */
 154 int tegra_i2c_get_dvc_bus(struct udevice **busp);
 155
 156 #endif  /* _TEGRA_I2C_H_ */