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   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
   8 #define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
   9
  10 #ifndef __ASSEMBLY__
  11
  12 #include <linux/types.h>
  13
  14 /* Clock Controller Module (CCM) */
  15 struct ccm_reg {
  16         u32 ccr;
  17         u32 csr;
  18         u32 ccsr;
  19         u32 cacrr;
  20         u32 cscmr1;
  21         u32 cscdr1;
  22         u32 cscdr2;
  23         u32 cscdr3;
  24         u32 cscmr2;
  25         u32 cscdr4;
  26         u32 ctor;
  27         u32 clpcr;
  28         u32 cisr;
  29         u32 cimr;
  30         u32 ccosr;
  31         u32 cgpr;
  32         u32 ccgr0;
  33         u32 ccgr1;
  34         u32 ccgr2;
  35         u32 ccgr3;
  36         u32 ccgr4;
  37         u32 ccgr5;
  38         u32 ccgr6;
  39         u32 ccgr7;
  40         u32 ccgr8;
  41         u32 ccgr9;
  42         u32 ccgr10;
  43         u32 ccgr11;
  44         u32 cmeor0;
  45         u32 cmeor1;
  46         u32 cmeor2;
  47         u32 cmeor3;
  48         u32 cmeor4;
  49         u32 cmeor5;
  50         u32 cppdsr;
  51         u32 ccowr;
  52         u32 ccpgr0;
  53         u32 ccpgr1;
  54         u32 ccpgr2;
  55         u32 ccpgr3;
  56 };
  57
  58 /* Analog components control digital interface (ANADIG) */
  59 struct anadig_reg {
  60         u32 reserved_0x000[4];
  61         u32 pll3_ctrl;
  62         u32 reserved_0x014[3];
  63         u32 pll7_ctrl;
  64         u32 reserved_0x024[3];
  65         u32 pll2_ctrl;
  66         u32 reserved_0x034[3];
  67         u32 pll2_ss;
  68         u32 reserved_0x044[3];
  69         u32 pll2_num;
  70         u32 reserved_0x054[3];
  71         u32 pll2_denom;
  72         u32 reserved_0x064[3];
  73         u32 pll4_ctrl;
  74         u32 reserved_0x074[3];
  75         u32 pll4_num;
  76         u32 reserved_0x084[3];
  77         u32 pll4_denom;
  78         u32 reserved_0x094[3];
  79         u32 pll6_ctrl;
  80         u32 reserved_0x0A4[3];
  81         u32 pll6_num;
  82         u32 reserved_0x0B4[3];
  83         u32 pll6_denom;
  84         u32 reserved_0x0C4[7];
  85         u32 pll5_ctrl;
  86         u32 reserved_0x0E4[3];
  87         u32 pll3_pfd;
  88         u32 reserved_0x0F4[3];
  89         u32 pll2_pfd;
  90         u32 reserved_0x104[3];
  91         u32 reg_1p1;
  92         u32 reserved_0x114[3];
  93         u32 reg_3p0;
  94         u32 reserved_0x124[3];
  95         u32 reg_2p5;
  96         u32 reserved_0x134[7];
  97         u32 ana_misc0;
  98         u32 reserved_0x154[3];
  99         u32 ana_misc1;
 100         u32 reserved_0x164[63];
 101         u32 anadig_digprog;
 102         u32 reserved_0x264[3];
 103         u32 pll1_ctrl;
 104         u32 reserved_0x274[3];
 105         u32 pll1_ss;
 106         u32 reserved_0x284[3];
 107         u32 pll1_num;
 108         u32 reserved_0x294[3];
 109         u32 pll1_denom;
 110         u32 reserved_0x2A4[3];
 111         u32 pll1_pdf;
 112         u32 reserved_0x2B4[3];
 113         u32 pll_lock;
 114 };
 115 #endif
 116
 117 #define CCM_CCR_FIRC_EN                         (1 << 16)
 118 #define CCM_CCR_OSCNT_MASK                      0xff
 119 #define CCM_CCR_OSCNT(v)                        ((v) & 0xff)
 120
 121 #define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET        19
 122 #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK          (0x7 << 19)
 123 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v)            (((v) & 0x7) << 19)
 124
 125 #define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET        16
 126 #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK          (0x7 << 16)
 127 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v)            (((v) & 0x7) << 16)
 128
 129 #define CCM_CCSR_PLL2_PFD4_EN                   (1 << 15)
 130 #define CCM_CCSR_PLL2_PFD3_EN                   (1 << 14)
 131 #define CCM_CCSR_PLL2_PFD2_EN                   (1 << 13)
 132 #define CCM_CCSR_PLL2_PFD1_EN                   (1 << 12)
 133 #define CCM_CCSR_PLL1_PFD4_EN                   (1 << 11)
 134 #define CCM_CCSR_PLL1_PFD3_EN                   (1 << 10)
 135 #define CCM_CCSR_PLL1_PFD2_EN                   (1 << 9)
 136 #define CCM_CCSR_PLL1_PFD1_EN                   (1 << 8)
 137
 138 #define CCM_CCSR_DDRC_CLK_SEL(v)                ((v) << 6)
 139 #define CCM_CCSR_FAST_CLK_SEL(v)                ((v) << 5)
 140
 141 #define CCM_CCSR_SYS_CLK_SEL_OFFSET             0
 142 #define CCM_CCSR_SYS_CLK_SEL_MASK               0x7
 143 #define CCM_CCSR_SYS_CLK_SEL(v)                 ((v) & 0x7)
 144
 145 #define CCM_CACRR_IPG_CLK_DIV_OFFSET            11
 146 #define CCM_CACRR_IPG_CLK_DIV_MASK              (0x3 << 11)
 147 #define CCM_CACRR_IPG_CLK_DIV(v)                (((v) & 0x3) << 11)
 148 #define CCM_CACRR_BUS_CLK_DIV_OFFSET            3
 149 #define CCM_CACRR_BUS_CLK_DIV_MASK              (0x7 << 3)
 150 #define CCM_CACRR_BUS_CLK_DIV(v)                (((v) & 0x7) << 3)
 151 #define CCM_CACRR_ARM_CLK_DIV_OFFSET            0
 152 #define CCM_CACRR_ARM_CLK_DIV_MASK              0x7
 153 #define CCM_CACRR_ARM_CLK_DIV(v)                ((v) & 0x7)
 154
 155 #define CCM_CSCMR1_DCU1_CLK_SEL                 (1 << 29)
 156 #define CCM_CSCMR1_DCU0_CLK_SEL                 (1 << 28)
 157
 158 #define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET         22
 159 #define CCM_CSCMR1_QSPI0_CLK_SEL_MASK           (0x3 << 22)
 160 #define CCM_CSCMR1_QSPI0_CLK_SEL(v)             (((v) & 0x3) << 22)
 161 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET        18
 162 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK          (0x3 << 18)
 163 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v)            (((v) & 0x3) << 18)
 164 #define CCM_CSCMR1_NFC_CLK_SEL_OFFSET           12
 165 #define CCM_CSCMR1_NFC_CLK_SEL_MASK             (0x3 << 12)
 166 #define CCM_CSCMR1_NFC_CLK_SEL(v)               (((v) & 0x3) << 12)
 167
 168 #define CCM_CSCDR1_RMII_CLK_EN                  (1 << 24)
 169
 170 #define CCM_CSCDR2_NFC_EN                       (1 << 9)
 171 #define CCM_CSCDR2_NFC_FRAC_DIV_EN              (1 << 13)
 172 #define CCM_CSCDR2_NFC_CLK_INV                  (1 << 14)
 173 #define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET          4
 174 #define CCM_CSCDR2_NFC_FRAC_DIV_MASK            (0xf << 4)
 175 #define CCM_CSCDR2_NFC_FRAC_DIV(v)              (((v) & 0xf) << 4)
 176
 177 #define CCM_CSCDR2_ESDHC1_EN                    (1 << 29)
 178 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET        20
 179 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK          (0xf << 20)
 180 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)            (((v) & 0xf) << 20)
 181
 182 #define CCM_CSCDR3_DCU1_EN                      (1 << 23)
 183 #define CCM_CSCDR3_DCU1_DIV_MASK                (0x7 << 20)
 184 #define CCM_CSCDR3_DCU1_DIV(v)                  (((v) & 0x7) << 20)
 185 #define CCM_CSCDR3_DCU0_EN                      (1 << 19)
 186 #define CCM_CSCDR3_DCU0_DIV_MASK                (0x7 << 16)
 187 #define CCM_CSCDR3_DCU0_DIV(v)                  (((v) & 0x7) << 16)
 188
 189 #define CCM_CSCDR3_NFC_PRE_DIV_OFFSET           13
 190 #define CCM_CSCDR3_NFC_PRE_DIV_MASK             (0x7 << 13)
 191 #define CCM_CSCDR3_NFC_PRE_DIV(v)               (((v) & 0x7) << 13)
 192 #define CCM_CSCDR3_QSPI0_EN                     (1 << 4)
 193 #define CCM_CSCDR3_QSPI0_DIV(v)                 ((v) << 3)
 194 #define CCM_CSCDR3_QSPI0_X2_DIV(v)              ((v) << 2)
 195 #define CCM_CSCDR3_QSPI0_X4_DIV(v)              ((v) & 0x3)
 196
 197 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET          4
 198 #define CCM_CSCMR2_RMII_CLK_SEL_MASK            (0x3 << 4)
 199 #define CCM_CSCMR2_RMII_CLK_SEL(v)              (((v) & 0x3) << 4)
 200
 201 #define CCM_REG_CTRL_MASK                       0xffffffff
 202 #define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 203 #define CCM_CCGR0_UART1_CTRL_MASK               (0x3 << 16)
 204 #define CCM_CCGR0_DSPI0_CTRL_MASK               (0x3 << 24)
 205 #define CCM_CCGR0_DSPI1_CTRL_MASK               (0x3 << 26)
 206 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 207 #define CCM_CCGR1_PIT_CTRL_MASK                 (0x3 << 14)
 208 #define CCM_CCGR1_TCON0_CTRL_MASK               (0x3 << 26)
 209 #define CCM_CCGR1_WDOGA5_CTRL_MASK              (0x3 << 28)
 210 #define CCM_CCGR2_QSPI0_CTRL_MASK               (0x3 << 8)
 211 #define CCM_CCGR2_IOMUXC_CTRL_MASK              (0x3 << 16)
 212 #define CCM_CCGR2_PORTA_CTRL_MASK               (0x3 << 18)
 213 #define CCM_CCGR2_PORTB_CTRL_MASK               (0x3 << 20)
 214 #define CCM_CCGR2_PORTC_CTRL_MASK               (0x3 << 22)
 215 #define CCM_CCGR2_PORTD_CTRL_MASK               (0x3 << 24)
 216 #define CCM_CCGR2_PORTE_CTRL_MASK               (0x3 << 26)
 217 #define CCM_CCGR3_ANADIG_CTRL_MASK              0x3
 218 #define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
 219 #define CCM_CCGR3_DCU0_CTRL_MASK                (0x3 << 16)
 220 #define CCM_CCGR4_WKUP_CTRL_MASK                (0x3 << 20)
 221 #define CCM_CCGR4_CCM_CTRL_MASK                 (0x3 << 22)
 222 #define CCM_CCGR4_GPC_CTRL_MASK                 (0x3 << 24)
 223 #define CCM_CCGR4_I2C0_CTRL_MASK                (0x3 << 12)
 224 #define CCM_CCGR4_I2C1_CTRL_MASK                (0x3 << 14)
 225 #define CCM_CCGR6_OCOTP_CTRL_MASK               (0x3 << 10)
 226 #define CCM_CCGR6_DSPI2_CTRL_MASK               (0x3 << 24)
 227 #define CCM_CCGR6_DSPI3_CTRL_MASK               (0x3 << 26)
 228 #define CCM_CCGR6_DDRMC_CTRL_MASK               (0x3 << 28)
 229 #define CCM_CCGR7_SDHC1_CTRL_MASK               (0x3 << 4)
 230 #define CCM_CCGR7_USBC1_CTRL_MASK       (0x3 << 8)
 231 #define CCM_CCGR9_FEC0_CTRL_MASK                0x3
 232 #define CCM_CCGR9_FEC1_CTRL_MASK                (0x3 << 2)
 233 #define CCM_CCGR10_NFC_CTRL_MASK                0x3
 234 #define CCM_CCGR10_I2C2_CTRL_MASK               (0x3 << 12)
 235 #define CCM_CCGR10_I2C3_CTRL_MASK               (0x3 << 14)
 236
 237 #define ANADIG_PLL7_CTRL_BYPASS         (1 << 16)
 238 #define ANADIG_PLL7_CTRL_ENABLE         (1 << 13)
 239 #define ANADIG_PLL7_CTRL_POWERDOWN      (1 << 12)
 240 #define ANADIG_PLL7_CTRL_DIV_SELECT     (1 << 1)
 241 #define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
 242 #define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)
 243 #define ANADIG_PLL5_CTRL_POWERDOWN              (1 << 12)
 244 #define ANADIG_PLL5_CTRL_DIV_SELECT             1
 245 #define ANADIG_PLL3_CTRL_BYPASS         (1 << 16)
 246 #define ANADIG_PLL3_CTRL_ENABLE         (1 << 13)
 247 #define ANADIG_PLL3_CTRL_POWERDOWN      (1 << 12)
 248 #define ANADIG_PLL3_CTRL_DIV_SELECT     (1 << 1)
 249 #define ANADIG_PLL2_CTRL_ENABLE                 (1 << 13)
 250 #define ANADIG_PLL2_CTRL_POWERDOWN              (1 << 12)
 251 #define ANADIG_PLL2_CTRL_DIV_SELECT             1
 252 #define ANADIG_PLL1_CTRL_ENABLE                 (1 << 13)
 253 #define ANADIG_PLL1_CTRL_POWERDOWN              (1 << 12)
 254 #define ANADIG_PLL1_CTRL_DIV_SELECT             1
 255
 256 #define FASE_CLK_FREQ           24000000
 257 #define SLOW_CLK_FREQ           32000
 258 #define PLL1_PFD1_FREQ          500000000
 259 #define PLL1_PFD2_FREQ          452000000
 260 #define PLL1_PFD3_FREQ          396000000
 261 #define PLL1_PFD4_FREQ          528000000
 262 #define PLL1_MAIN_FREQ          528000000
 263 #define PLL2_PFD1_FREQ          500000000
 264 #define PLL2_PFD2_FREQ          396000000
 265 #define PLL2_PFD3_FREQ          339000000
 266 #define PLL2_PFD4_FREQ          413000000
 267 #define PLL2_MAIN_FREQ          528000000
 268 #define PLL3_MAIN_FREQ          480000000
 269 #define PLL3_PFD3_FREQ          298000000
 270 #define PLL5_MAIN_FREQ          500000000
 271
 272 #define ENET_EXTERNAL_CLK       50000000
 273 #define AUDIO_EXTERNAL_CLK      24576000
 274
 275 #endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */